Semiconductor device

Abstract

Provided is a semiconductor device that has a large storage capacity per unit area. The semiconductor device has: a first insulating body having a first opening; a first conductor upon the first insulating body and having a second opening; a second insulating body upon the first conductor and having a third opening; a third insulating body provided along a first side surface of the first opening, a second side surface of the second opening, and a third side surface of a third opening; an oxide provided along the first side surface, the second side surface, and the third side surface, via the third insulating body; a second conductor provided on the first side surface, via the third insulating body and the oxide; and a third conductor provided on the third side surface, via the third insulating body and the oxide. The oxide has a first region inside the first opening, a second region inside the second opening, and a third region inside the third opening. The second region has higher resistance than the first region and the third region.

Description

Technical Field

[0001] The present invention relates to, for example, a memory device and a semiconductor device. Or, the present invention relates to, for example, a method for manufacturing a memory device and a semiconductor device. Or, it relates to a memory transistor included in a memory device and a method for manufacturing the memory transistor. Or, the present invention relates to, for example, a processor and an electronic device. Or, it relates to a method for manufacturing a processor and an electronic device. Or, it relates to a driving method for a memory device, a processor, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification or the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Note that in this specification or the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a memory device, a semiconductor circuit, and an electronic device may include a semiconductor device.

Background Art

[0004] In recent years, with the increase in the amount of data to be handled, semiconductor devices having a larger storage capacity have been demanded. In order to increase the storage capacity per unit area, it is effective to stack and form memory cells (see Patent Document 1 and Patent Document 2). By stacking and providing memory cells, the storage capacity per unit area can be increased according to the number of stacked memory cells.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] In Patent Document 1 and Patent Document 2, a plurality of memory elements (also referred to as memory cells) are stacked, and by connecting them in series, a memory cell array (also referred to as a memory string) having a three-dimensional structure is configured. On the other hand, in such a memory cell array having a three-dimensional structure, as the number of stacked memory elements increases, the series resistance between the memory cells increases, and the resistance of the memory cell array increases. When the resistance of the memory cell array increases, there are problems such as loss of current flowing through the memory cell array and heat generation of the memory cell array.

[0007] Further, in Patent Document 1, a semiconductor pattern provided in a columnar shape is in contact with an insulator having a charge storage layer. Further, in Patent Document 2, a semiconductor pattern provided in a columnar shape is in contact with an insulator that functions as a tunnel dielectric. When a semiconductor and an insulator are in contact, trap centers may be formed at these interfaces. Trap centers formed at the interface between a semiconductor and an insulator capture electrons and change the threshold voltage of the transistor in the positive direction, so there is a risk of adversely affecting the current driving force in the on state of the transistor, that is, the on current, the field-effect mobility, and the reliability.

[0008] In view of the above problems, one aspect of the present invention is to provide a semiconductor device having good electrical characteristics and in which the formation of trap centers is suppressed as one of the problems.

[0009] Another object is to provide a semiconductor device having a large memory capacity per unit area. Another object is to provide a semiconductor device having a novel structure in which memory cells are stacked. Another object is to provide a highly productive semiconductor device.

[0010] Another object is to provide a module having the semiconductor device. Another object is to provide an electronic device having the semiconductor device or the module. Another object is to provide a novel semiconductor device. Another object is to provide a novel module. Another object is to provide a novel electronic device.

[0011] Another object is to provide a semiconductor device with reduced power consumption in circuit operation. Another object is to provide a module having the semiconductor device with reduced power consumption in circuit operation. Another object is to provide an electronic device having the semiconductor device or the module with reduced power consumption in circuit operation.

[0012] Note that the description of these objects does not preclude the existence of other objects. Note that one aspect of the present invention does not need to solve all of these objects. Other objects will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other objects from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0013] One aspect of the present invention includes a first insulator having a first opening, a first conductor having a second opening on the first insulator, a second insulator having a third opening on the first conductor, a third insulator provided along a first side surface of the first opening, a second side surface of the second opening, and a third side surface of the third opening, an oxide provided along the first side surface, the second side surface, and the third side surface via the third insulator, a second conductor provided on the first side surface via the third insulator and the oxide, and a third conductor provided on the third side surface via the third insulator and the oxide. The oxide has a first region in the first opening, a second region in the second opening, and a third region in the third opening, and the second region is a semiconductor device having a higher resistance than the first region and the third region.

[0014] One aspect of the present invention includes a first insulator having a first opening, a first conductor having a second opening on the first insulator, a second insulator having a third opening on the first conductor, a third insulator provided along a first side surface of the first opening, a second side surface of the second opening, and a third side surface of the third opening, an oxide provided along the first side surface, the second side surface, and the third side surface via the third insulator, a second conductor provided on the first side surface via the third insulator and the oxide, a third conductor provided on the third side surface via the third insulator and the oxide, a fourth insulator in contact with the oxide, the second conductor, and the third conductor, and a fourth conductor in contact with the fourth insulator. The oxide is provided between the first conductor and the fourth insulator, the fourth insulator is provided between the oxide and the fourth conductor, the oxide has a first region within the first opening, a second region within the second opening, and a third region within the third opening, and the second region has a higher resistance than the first region and the third region. A semiconductor device.

[0015] In the above, it is preferable that the first conductor functions as a first gate and the fourth conductor functions as a second gate.

[0016] In the above, it is preferable that the oxide has indium, an element M (M is one or more selected from aluminum, gallium, yttrium, and tin), and zinc.

[0017] In the above, it is preferable that the oxide has a first layer, a second layer provided in contact with the inside of the first layer, and a third layer provided in contact with the inside of the second layer, and the energy gap of the second layer is narrower than the energy gap of the first layer, and the energy gap of the second layer is narrower than the energy gap of the third layer.

[0018] In the above, it is preferable that the second conductor and the third conductor have a function of shielding microwaves.

[0019] In the above, it is preferable that the second region contains more oxygen than the first region and the third region.

[0020] In the above, it is preferable that the second region contains less hydrogen than the first region and the third region.

[0021] In the above, it is preferable that the second region has a lower carrier concentration than the first region and the third region.

[0022] In the above, it is preferable that the third insulator has a gate insulating layer, a charge storage layer, and a tunnel insulating layer.

[0023] In the above, it is preferable that the diameter of the first opening and the diameter of the third opening are larger than the diameter of the second opening.

[0024] One aspect of the present invention is to form a first insulating film, form a first conductive film on the first insulating film, form a second insulating film on the first conductive film, process the second insulating film, the first conductive film, and the first insulating film to form a first insulator having a first opening, a first conductor having a second opening on the first insulator, and a second insulator having a third opening on the first conductor, process the first insulator and the second insulator to make the diameter of the first opening and the diameter of the third opening larger than the diameter of the second opening, form a third insulator in contact with the first insulator, the first conductor, and the second insulator in the first opening, the second opening, and the third opening, form an oxide in contact with the third insulator, form a second conductor and a third conductor in contact with the oxide in the first opening and the third opening respectively, and irradiate the oxide with microwaves using the second conductor and the third conductor as masks, which is a method for manufacturing a semiconductor device.

[0025] In the above, after forming the second conductor and the third conductor, it is preferable to perform a heat treatment.

Effects of the Invention

[0026] According to one aspect of the present invention, it is possible to provide a semiconductor device having good electrical characteristics and suppressing the formation of trap centers.

[0027] In addition, a semiconductor device having a large memory capacity per unit area can be provided. Or, a semiconductor device having a novel structure in which memory cells (also referred to as memory transistors) are stacked can be provided. Or, a highly productive semiconductor device can be provided.

[0028] Or, a module having the semiconductor device can be provided. Or, an electronic device having the semiconductor device or the module can be provided. Or, a novel semiconductor device can be provided. Or, a novel module can be provided. Or, a novel electronic device can be provided.

[0029] In addition, in circuit operation, a semiconductor device with reduced power consumption can be provided. Or, a module having a semiconductor device with reduced power consumption in circuit operation can be provided. Or, an electronic device having a semiconductor device or a module with reduced power consumption in circuit operation can be provided.

[0030] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be naturally apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0031] FIG. 1 is a cross-sectional view for explaining a semiconductor device according to one aspect of the present invention. FIG. 2A is a top view for explaining a semiconductor device according to one aspect of the present invention. FIG. 2B is a cross-sectional view for explaining a semiconductor device according to one aspect of the present invention. Figures 3A and 3B are cross-sectional views illustrating a semiconductor device according to an aspect of the present invention. Figure 4 is a top view illustrating a semiconductor device according to an aspect of the present invention. Figure 5 is a cross-sectional view illustrating a semiconductor device according to an aspect of the present invention. Figure 6 is a cross-sectional view illustrating a semiconductor device according to an aspect of the present invention. Figures 7A to 7C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figures 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figures 9A to 9C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figures 10A and 10B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figure 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figures 12A and 12B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figures 13A to 13C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figures 14A to 14C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figures 15A to 15C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figure 16A is a top view illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figures 16B and 16C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figure 17A is a top view illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figures 17B and 17C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figure 18A is a top view illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. Figures 18B and 18C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 19A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 19B and 19C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 20A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 20B and 20C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 21A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 21B and 21C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 22A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 22B and 22C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 23A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 23B and 23C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 24A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 24B and 24C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 25A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 25B and 25C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 26A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 26B to 26D are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 27A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 27B and 27C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 28A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 28B and 28C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 29A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 29B to 29D are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 30A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 30B and 30C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 31A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 31B and 31C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 32A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 32B and 32C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 33A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 33B and 33C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 34A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 34B and 34C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 35A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 35B and 35C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 36A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 36B and 36C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 37A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 37B and 37C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 38A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 38B and 38C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 39A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 39B and 39C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 40A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 40B and 40C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 41A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 41B and 41C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 42A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 42B and 42C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 43A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 43B and 43C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 44A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 44B and 44C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 45A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 45B and 45C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 46A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 46B and 46C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 47A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 47B and 47C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 48A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 48B and 48C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 49A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 49B and 49C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 50A is a top view for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIGS. 50B and 50C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. FIG. 51 is a top view for explaining a microwave processing device according to an aspect of the present invention. FIG. 52 is a cross-sectional view for explaining a microwave processing device according to an aspect of the present invention. FIG. 53 is a cross-sectional view for explaining a microwave processing device according to an aspect of the present invention. FIG. 54 is a cross-sectional view for explaining a microwave processing device according to an aspect of the present invention. FIG. 55A is a functional block diagram showing a configuration example of a storage device according to an aspect of the present invention. FIG. 55B is a circuit diagram showing a configuration example of a memory string according to an aspect of the present invention. FIG. 56 is a functional block diagram showing a configuration example of a storage device according to an aspect of the present invention. FIG. 57 is a diagram showing a three-dimensional structure example of a memory cell array according to an aspect of the present invention. FIG. 58 is a diagram showing a three-dimensional structure example of a memory cell array according to an aspect of the present invention. FIG. 59 is a diagram showing a three-dimensional structure example of a memory cell array according to an aspect of the present invention. FIGS. 60A to 60C are circuit diagrams for explaining the operation of a storage device according to an aspect of the present invention. FIGS. 61A to 61E are schematic diagrams of a storage device according to an aspect of the present invention. FIG. 62 is a block diagram showing a configuration example of an AI system according to an aspect of the present invention. FIGS. 63A and 63B are block diagrams for explaining application examples of an AI system according to an aspect of the present invention. FIG. 64 is a perspective schematic diagram showing a configuration example of an IC incorporating an AI system according to an aspect of the present invention. FIG. 65A is a diagram showing an electronic device according to an aspect of the present invention. FIG. 65B is a block diagram showing a configuration example of the electronic device according to an aspect of the present invention. FIGS. 66A to 66F are diagrams showing an electronic device according to an aspect of the present invention.

Mode for Carrying Out the Invention

[0032] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it will be easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0033] In the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. In the drawings, the same reference numerals are commonly used among different drawings for the same part or parts having the same function, and the repeated description thereof is omitted. Also, when referring to the same function, the hatch patterns may be the same and may not be particularly labeled.

[0034] In this specification and the like, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, "first" can be appropriately replaced with "second" or "third" and so on for explanation. Also, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to identify an aspect of the present invention.

[0035] In this specification, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0036] In addition, in this specification and the like, "electrically connected" includes cases where it is connected via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the exchange of electrical signals between the connection targets. For example, "something having some electrical effect" includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

[0037] Note that in this specification and the like, nitride oxide refers to a compound having a higher nitrogen content than oxygen. Also, oxynitride refers to a compound having a higher oxygen content than nitrogen. Note that the content of each element can be measured using, for example, the Rutherford Backscattering Spectrometry (RBS).

[0038] In addition, in this specification and the like, the term "film" and the term "layer" can be interchanged with each other. For example, in some cases, the term "conductive layer" can be changed to the term "conductive film". Or, for example, in some cases, the term "insulating film" can be changed to the term "insulating layer".

[0039] In addition, in this specification and the like, "parallel" refers to a state where two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "substantially parallel" refers to a state where two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" refers to a state where two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included. Also, "substantially perpendicular" refers to a state where two straight lines are arranged at an angle of 60° or more and 120° or less.

[0040] In addition, in this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

[0041] In this specification, the barrier film is a film having a function of suppressing the permeation of impurities such as hydrogen and oxygen. When the barrier film has conductivity, it may be referred to as a conductive barrier film.

[0042] In this specification and the like, the metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS FET, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0043] Also, regarding this specification and the like, In:Ga:Zn = 4:2:3 or in the vicinity thereof means that when In is 4 with respect to the total number of atoms, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, In:Ga:Zn = 5:1:6 or in the vicinity thereof means that when In is 5 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also, In:Ga:Zn = 1:1:1 or in the vicinity thereof means that when In is 1 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2).

[0044] (Embodiment 1) In this embodiment, the configuration, manufacturing method, circuit configuration, and operation of a semiconductor device according to one aspect of the disclosed invention will be described with reference to FIGS. 1 to 60C.

[0045] (Memory Transistor MT, Memory Cell Array 700) First, the configuration of the memory transistor MT of the semiconductor device and the memory cell array 700 will be described with reference to FIGS. 1 to 3B. FIG. 1 is a cross-sectional view of the memory cell array 700. FIG. 2A is a top view of the memory cell array 700. Note that FIG. 2A is a top view of the plane indicated by the dashed line A5 - A6 in FIG. 1, and some components are omitted. Also, FIG. 1 is a cross-sectional view of the part indicated by the dashed line A1 - A2 in FIG. 2A. Further, FIG. 2B is a cross-sectional view of the part indicated by the dashed line A3 - A4 in FIG. 2A, and is a cross-sectional view for explaining an example of a memory string. Also, FIG. 3A is an enlarged cross-sectional view of the part surrounded by the dashed line 791 in FIG. 1, and is a diagram for explaining an example of the memory transistor MT that functions as a memory cell. Also, FIG. 3B is an enlarged cross-sectional view of the part surrounded by the dashed line 792 in FIG. 1, and is a diagram for explaining an example of a transistor that functions as a selection transistor. Hereinafter, as shown in FIGS. 1 and 2, a rectangular coordinate system composed of the x-axis, y-axis, and z-axis will be set for convenience of explanation. Here, the x-axis and y-axis are parallel to the upper surface of the substrate 720 on which the memory cell array 700 is provided, and the z-axis is perpendicular to the upper surface of the substrate 720.

[0046] The memory cell array 700 has a conductor 706 (conductors 706_1 to 706_4) and an insulator 721 on the substrate 720, and has a stacked body in which a conductor 701 (conductors 701_1 to 701_m: m is a natural number of 2 or more) and an insulator 722 (insulators 722_1 to 722_m) are alternately stacked on the insulator 721. Also, the memory cell array 700 has a conductor 702 on the stacked body, and has an insulator 724 on the conductor 702 and the stacked body.

[0047] In addition, the memory cell array 700 has a plurality of openings formed so as to penetrate the insulator 724, the conductor 702, the laminate, and the insulator 721. In FIG. 1, four openings are shown. The openings are provided at positions overlapping the conductor 706. Further, the memory cell array 700 has an insulator 703 (insulators 703_1 to 703_4) inside each opening, an oxide 704 (oxides 704_1 to 704_4) inside the insulator 703, and an insulator 711 (insulators 711_1 to 711_4) inside the oxide 704. Also, the memory cell array 700 has a conductor 719 between the oxide 704 and the insulator 711. As will be described later, the conductor 719 has a function of shielding microwaves. Further, the memory cell array 700 has a conductor 712 (conductors 712_1 to 712_4) inside the insulator 711.

[0048] In addition, the memory cell array 700 has a conductor 705 (conductors 705_1 to 705_4) on the insulator 724. In FIG. 1, each of the conductors 705_1 to 705_4 is electrically connected to each of the oxides 704_1 to 704_4. Also, each of the conductors 706_1 to 706_4 is electrically connected to each of the oxides 704_1 to 704_4.

[0049] In addition, the memory cell array 700 has a conductor 710 and conductors 708 (conductors 708_1 to 708_m) on the insulator 724. The conductor 710 is electrically connected to the conductor 702 via the conductor 709. Also, an insulator 717 is provided on the insulator 724, the conductor 705, the conductor 708, and the conductor 710. Also, a plurality of insulators 713 and a plurality of conductors 714 are provided so as to be embedded in the insulator 717 in a region overlapping the conductor 712 and its vicinity. In the x-axis direction, the conductor 714 has a region overlapping the insulator 717 via the insulator 713.

[0050] Further, the memory cell array 700 has a plurality of conductors 715 on an insulator 717. The conductor 715 is electrically connected to the conductor 712 via the conductor 714.

[0051] Also, in the memory cell array 700 shown in FIG. 1, conductors 707 (conductors 707_1 to 707_m) are provided so as to be embedded in the insulator 724. Each of the conductors 708_1 to 708_m is electrically connected to each of the conductors 701_1 to 701_m via each of the conductors 707_1 to 707_m. Note that in FIGS. 1 and 2, in order to represent a plurality of conductors 701, the conductors 701 are shown in four or more stages. However, the present embodiment is not limited to FIG. 1, and it is sufficient to have at least two or more stages of the conductors 701.

[0052] Here, as shown in FIGS. 1 and 2A, the conductor 701 is provided to extend in the x-axis direction. Also, as shown in FIGS. 1 and 2B, the insulator 703 and the oxide 704 are provided to extend in the z-axis direction along the side surfaces of openings formed so as to penetrate the insulator 724, the conductor 702, the laminate, and the insulator 721. That is, it is preferable that the conductor 701 and the insulator 703 and the oxide 704 are provided to intersect each other perpendicularly. Also, as shown in FIG. 1, the conductor 707 is provided to extend in the z-axis direction. Further, the conductor 708 may be provided to extend in the y-axis direction. Also, a conductor that functions as a bit line BL connected to the conductor 705 may be provided to extend in the y-axis direction. Note that a part of the conductor 705 may function as a bit line BL, and the conductor 705 may be provided to extend in the y-axis direction.

[0053] The conductor 712 is formed in a columnar shape and is provided so as to extend in the z-axis direction. Further, an insulator 711 is provided so as to surround the conductor 712, and an oxide 704 is provided so as to surround the insulator 711, and each is provided so as to extend in the z-axis direction. In other words, inside the columnar oxide 704 provided so as to extend in the z-axis direction, the conductor 712 is provided like a core, and an insulator 711 is provided between the oxide 704 and the conductor 712. Further, the insulator 703 is provided so as to surround the side periphery of the columnar oxide 704. Further, the conductor 707 is formed in a columnar shape and is provided so as to extend in the z-axis direction.

[0054] The diameters of the openings formed in the insulator 721, the insulator 722, and the insulator 724 are larger than the diameters of the openings formed in the conductor 701 and the conductor 702, and it can be said that the insulator has a concave portion with respect to the side surface of the conductor. The conductor 719 is provided on the side surfaces of the insulator 721, the insulator 722, and the insulator 724 via the insulator 703 and the oxide 704. That is, the insulator 703 and the oxide 704 are provided on the side surfaces of the insulator 721, the conductor 701, the insulator 722, the conductor 702, and the insulator 724 along the concave portion, and the conductor 719 is provided inside the concave portion via the insulator 703 and the oxide 704. The conductor 719 comes into contact with a part of the oxide 704, thereby reducing the resistance of the region and forming a low-resistance region. This low-resistance region may be referred to as an N-type region. Further, the conductor 719 preferably has an effect of suppressing the transmission of microwaves. By irradiating the oxide 704 with microwaves, the carrier concentration of the oxide 704 can be reduced, and a high-resistance region, that is, an I-type region can be formed in the oxide 704. The carrier concentration of the I-type region irradiated with microwaves is preferably less than 1×10 18 / cm 3 and more preferably less than 1×10 17 / cm 3 and even more preferably less than 1×10 16 / cm 3The following is more preferable. When the conductor 719 functions as a shield during microwave irradiation, the N-type region can be maintained at a low resistance. Therefore, in the oxide 704, N-type regions and I-type regions are alternately provided in the z-axis direction. Such a structure may be referred to as an N-I-N junction. Further, since the oxide 704 has a low-resistance region, the series resistance between memory cells can be reduced in a memory string in which memory cells are stacked or a memory cell array.

[0055] When the oxide 704 is irradiated with microwaves in an atmosphere containing oxygen and argon, the hydrogen concentration and the carrier concentration of the oxide 704 are reduced. This is presumably because hydrogen in the oxide 704 combines with oxygen to form water molecules or hydroxide ions and is released from the oxide 704. Further, oxygen in the atmosphere is supplied to the oxygen vacancies generated in the oxide 704 due to the release of water molecules or hydroxide ions, and it is considered that the oxide 704 becomes highly resistive, i.e., an I-type.

[0056] In microwave treatment, thermal energy may be directly transferred to the oxide 704 due to the electromagnetic interaction between the microwaves and the molecules in the oxide 704. The oxide 704 may be heated by this thermal energy. Such a heat treatment may be referred to as microwave annealing. By performing the microwave treatment in an atmosphere containing oxygen, an effect equivalent to oxygen annealing may be obtained. Further, when the oxide 704 contains hydrogen, it is considered that this thermal energy is transferred to the hydrogen in the oxide 704, and the activated hydrogen is released from the oxide 704.

[0057] On the other hand, in the oxide 704 covered with the conductor 719, the microwaves are shielded, the reduction of the hydrogen concentration and the carrier concentration does not occur, and the N-type region can maintain a low resistance value. At this time, the carrier concentration of the N-type region is 1×10 18 / cm 3 or more, preferably 1×10 19 / cm 3 or more, more preferably 1×10 20 / cm 3 It is preferably as described above.

[0058] The columnar oxide 704 is electrically connected to the conductor 706 at the lower end in the z-axis direction and electrically connected to the conductor 705 at the upper end. Further, as shown in FIG. 2B, the conductor 706 is electrically connected to the lower ends of two adjacent columnar oxides 704, and the upper ends of the two columnar oxides 704 are electrically connected to the conductors 705 that are electrically separated from each other, respectively. In the present embodiment, a U-shaped memory string in which two columnar oxides 704 are electrically connected by a conductor 706 will be described, but the present invention is not limited thereto. For example, the conductor 706 may be one of the bit line BL and the source line SL, and the conductor 705 may be the other of the bit line BL and the source line SL. In this case, the conductor 706 may be electrically connected to a plurality of columnar oxides 704 or may be electrically connected to one columnar oxide 704. Further, the conductor 705 may be electrically connected to a plurality of columnar oxides 704 or may be electrically connected to one columnar oxide 704.

[0059] When the lower end of the columnar oxide 704 is electrically connected to one of the bit line BL and the source line SL and the upper end is electrically connected to the other, it is preferable to provide selection transistors near the lower end and near the upper end of the columnar oxide 704. For example, when the conductor 706 is a part of the bit line BL and the conductor 705 is a part of the source line SL, a selection transistor SST is provided between the conductor 706 and the memory transistor MT, and a selection transistor SDT is provided between the conductor 705 and the memory transistor MT.

[0060] Here, the region where the conductor 701 intersects with the insulator 703 and the oxide 704 and its vicinity function as the memory transistor MT. Also, the region where the conductor 702 intersects with the insulator 703 and the oxide 704 and its vicinity function as the selection transistor. The channel length directions of these memory transistors MT and selection transistors are parallel to the z-axis. The memory transistor MT and the selection transistor are electrically connected in series, and they constitute a memory string.

[0061] FIG. 3A is an enlarged cross-sectional view of the portion surrounded by the dashed-dotted line 791 in FIG. 1, and shows a cross-section of the memory transistor MT at the k-th stage (k is an integer from 2 to m - 1). The memory transistor MT includes a conductor 701_k, an insulator 703 (insulator 703a, insulator 703b, and insulator 703c), and an oxide 704 (oxide 704a, oxide 704b, and oxide 704c). It may also include a conductor 712 and an insulator 711.

[0062] The conductor 701_k functions as the gate of the memory transistor MT, the insulator 703a functions as the gate insulating layer, the insulator 703b functions as the charge storage layer, and the insulator 703c functions as the tunnel insulating layer.

[0063] Although details will be described later, the oxide 704 includes oxide 704a, oxide 704b, and oxide 704c. Oxide 704a has a relatively wider energy gap compared to oxide 704b, and oxide 704c has a relatively wider energy gap compared to oxide 704b. In other words, oxide 704b has a relatively narrower energy gap compared to oxide 704a and oxide 704c.

[0064] Also, among the oxide 704, the region 734 that overlaps with the conductor 701_k in the x-axis direction functions as a channel formation region. Also, among the oxide 704, the regions 731 (region 731a, region 731b) that overlap with the conductor 719 in the x-axis direction function as low-resistance regions. Also, among the oxide 704, the region located between the region 734 and the region 731 functions as a junction region. It is preferable that this region has a lower resistance than the region 734. Also, this region may have a resistance value similar to that of the region 731, or may have a higher resistance than the region 731. This region may function as a channel formation region similar to the region 734, or may function as a low-resistance region similar to the region 731.

[0065] The memory transistor MT at the k-th stage shares a low-resistance region with the memory transistor MT at the (k - 1)-th stage or the memory transistor MT at the (k + 1)-th stage. The oxide 704 has a structure in which channel formation regions and low-resistance regions are alternately formed. By having a low-resistance region in the oxide 704, the series resistance between memory cells can be reduced in a memory string or a memory cell array in which memory cells are stacked.

[0066] When the conductor 712 is provided, the conductor 701_k functions as a first gate, and the conductor 712 functions as a second gate. Note that the first gate may be simply referred to as a gate or a control gate, and the second gate may be referred to as a back gate. Also, an insulator 711 is provided between the oxide 704 and the conductor 712 and functions as a second gate insulating layer. At this time, the insulator 703a functions as a first gate insulating layer. In the circuit operation of the memory transistor MT, the power consumption of the memory transistor MT can be reduced by controlling the potential of the conductor 712 that functions as the second gate.

[0067] FIG. 3B is an enlarged cross-sectional view of the portion surrounded by the dashed-dotted line 792 in FIG. 1, and shows the cross-section of the selection transistors (bit-line side transistor SDT and source-line side transistor SST). The selection transistors include a conductor 702, an insulator 703 (insulators 703a, 703b, and 703c), and an oxide 704 (oxides 704a, 704b, and 704c). Further, a conductor 712 and an insulator 711 may be included.

[0068] The conductor 702 functions as the gate of the selection transistor, and the insulator 703a functions as the gate insulating layer. The gate insulating layer only needs to have at least the insulator 703a, and the insulators 703b and 703c may not be provided. Alternatively, after providing the insulators 703a, 703b, and 703c, the insulators 703b and 703c may be partially removed.

[0069] The oxide 704 includes oxides 704a, 704b, and 704c. The oxide 704a has a relatively wider energy gap than the oxide 704b, and the oxide 704c has a relatively wider energy gap than the oxide 704b. In other words, the oxide 704b has a relatively narrower energy gap than the oxides 704a and 704c.

[0070] Also, among the oxides 704, a region 734 located in the same layer as the conductor 702 functions as a channel formation region. Also, among the oxides 704, regions 731 (regions 731a and 731b) covered by the conductor 719 function as low-resistance regions.

[0071] When providing the conductor 712, the conductor 702 functions as the first gate, and the conductor 712 functions as the second gate. Note that the first gate may be simply referred to as the gate or the top gate, and the second gate may be referred to as the back gate. Also, an insulator 711 is provided between the oxide 704 and the conductor 712, which functions as the second gate insulating layer. At this time, the insulator 703a functions as the first gate insulating layer. The threshold value of the selection transistor can be controlled by the conductor 712 that functions as the second gate.

[0072] Note that the configuration of the semiconductor device shown in this embodiment is an example, and the present invention is not limited to the number and arrangement of circuit elements, wirings, etc. shown in the drawings and the like according to this embodiment. The number and arrangement of circuit elements, wirings, etc. of the semiconductor device according to this embodiment can be appropriately set according to the circuit configuration and driving method.

[0073] The substrate 720 provided with the memory cell array 700 preferably has an insulating surface. As the substrate having an insulating surface, a semiconductor substrate with an insulator formed on its surface, an insulator substrate, a conductor substrate with an insulator formed on its surface, etc. may be used. As the semiconductor substrate, for example, a semiconductor substrate containing silicon, germanium, etc., or a semiconductor substrate containing silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. may be used. Also, as the insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate, etc. may be used. Further, as the substrate having an insulator region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate may be used. Also, as the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. may be used.

[0074] The conductor 701 functions as the gate of the memory transistor MT and is electrically connected to the word line. That is, the conductor 701, the conductor 707, and the conductor 708 also function as part of the word line. Here, as shown in FIG. 1, the conductor 701 is preferably provided in a stepped shape in which the lower conductor 701 extends to the A2 side from the upper conductor 701. By providing the conductor 701 in this way, a partial region of the upper surface of the lower conductor 701 does not overlap with the upper conductor 701, so that the regions of each layer of the conductor 701 and each conductor 707 can be connected.

[0075] As the conductor 701, a conductive material such as silicon doped with impurities or a metal can be used. When silicon is used as the conductor 701, amorphous silicon or polysilicon can be used. Further, in order to impart conductivity to silicon, p-type impurities or n-type impurities may be added. Further, as the conductive material containing silicon, a silicide containing titanium, cobalt, or nickel can be used as the conductor 701. When a metal material is used for the conductor 701, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used.

[0076] The conductor 702 is provided on the conductor 701. The conductor 702 functions as the gate of the selection transistors (bit line side selection transistor SDT and source line side selection transistor SST) and is electrically connected to the wiring DGL or the wiring SGL. That is, the conductor 702, the conductor 709, and the conductor 710 also function as part of the wiring DGL or the wiring SGL. Further, the conductor 702 can use the same material as the conductor 701. Also, the conductor 702 may use the same material as the conductor 701 or a different material. The materials of the conductor 701 and the conductor 702 may be determined in consideration of the work function, etc., according to the application.

[0077] As insulators such as insulator 721, insulator 722, and insulator 724, which are provided on the upper and lower layers of conductor 701 and conductor 702, oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having insulating properties can be used. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores or resin are suitable for use in the insulator because of their low relative permittivity.

[0078] On the other hand, as the insulator, aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium or nitrides having silicon and hafnium, etc. can also be used. However, since their relative permittivity is high, parasitic capacitance may occur between conductors 701 or between conductor 701 and conductor 702. The material used for the insulator can be determined according to the design and application of the device.

[0079] Insulator 703 has insulator 703a, insulator 703b, and insulator 703c. Insulator 703a is provided on the side of conductor 701, insulator 703c is provided on the side of oxide 704, and insulator 703b is provided between insulator 703a and insulator 703c. Insulator 703a functions as a gate insulating layer, insulator 703b functions as a charge storage layer, and insulator 703c functions as a tunnel insulating layer.

[0080] Note that the selection transistor may have the same structure as the memory transistor MT. On the other hand, as shown in FIG. 3B, the selection transistor may not be provided with a charge storage layer and a tunnel insulating layer. In the bit line side transistor SDT and the source line side transistor SST, the insulators 703b and 703c may be removed, and only the insulator 703a may be provided as the insulator 703. Further, a conductor 712 may be provided as the second gate electrode. In this case, the conductor 702 functions as the first gate electrode, the insulator 703a functions as the first gate insulating film, and the insulator 711 functions as the second gate insulating film. The threshold value of the selection transistor can be controlled by the conductor 712.

[0081] As the insulator 703a, it is preferable to use silicon oxide or silicon oxynitride. Further, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Further, these may be laminated to form the insulator 703a.

[0082] It is preferable to use a material that functions as a charge storage layer for the insulator 703b, and it is preferable to use silicon nitride or silicon oxynitride. Further, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used.

[0083] As the insulator 703c, it is preferable to use silicon oxide or silicon oxynitride. Further, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Further, these may be laminated to form the insulator 703c. Also, the insulator 703c is preferably thinner than the insulator 703a. Although details will be described later, in writing or erasing data to the memory transistor MT, charge transfer occurs between the oxide 704 and the insulator 703b through the insulator 703c. That is, the insulator 703c functions as a tunnel insulating layer.

[0084] In particular, when forming the insulator 703 in the opening provided in the laminate having the conductor 701, the conductor 702, and the insulating film, the insulator 703 formed at the bottom of the opening needs to be removed by anisotropic etching using dry etching or the like. During anisotropic etching, the insulator 703c is exposed to plasma, radicals, gas, chemical solutions, etc. also on the side surfaces. When the side surfaces of the insulator 703c are damaged by these, trap centers may occur in the insulator 703c, which may affect the electrical characteristics of the transistor. In order to suppress the generation of trap centers, it is required that the side surfaces of the insulator 703c have high resistance to damage caused by etching. In this case, it is preferable to use aluminum oxide, a laminate of silicon oxide and aluminum oxide, or a laminate of silicon oxynitride and aluminum oxide as the insulator 703c.

[0085] The insulator 703a, the insulator 703b, and the insulator 703c can be formed using the ALD (Atomic Layer Deposition) method or the CVD (Chemical Vapor Deposition) method. Further, in order to prevent contamination of the interfaces of the insulator 703a, the insulator 703b, and the insulator 703c, it is preferable to form the films continuously without exposure to the atmosphere using a film forming apparatus of a multi-chamber system having the same chamber or a plurality of chambers.

[0086] As the oxide 704, it is preferable to use a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). The oxide semiconductor is preferable because it has good on characteristics of the transistor and can obtain high mobility as compared with a semiconductor made of silicon or the like.

[0087] For example, as the oxide 704, a metal oxide such as an In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. Further, as the oxide 704, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used. For example, as the oxide 704, an oxide containing indium, gallium, and zinc (which may be denoted as In-Ga-Zn oxide), an In-Ga-Zn oxide containing tin, etc. can be used.

[0088] In addition, a semiconductor device using the above metal oxide, particularly an In-Ga-Zn oxide, has a very good heat resistance with an operating temperature of -40°C or higher and 190°C or lower. By using such a metal oxide in a memory device, a memory device having good characteristics over a wide temperature range and high reliability can be realized. That is, a memory device having good heat resistance can be realized. This shows good heat resistance even when compared with the heat resistance of a phase change memory (PCM: Phase Change Memory) (-40°C or higher and 150°C or lower), a resistance change type memory (ReRAM: Resistance Random Access Memory) (-40°C or higher and 125°C or lower), a magnetoresistive random access memory (MRAM: Magnetoresistive Random Access Memory) (-40°C or higher and 105°C or lower), etc.

[0089] The oxide 704 preferably has an oxide 704a provided on the insulator 703c side, an oxide 704b provided inside the oxide 704a, and an oxide 704c provided inside the oxide 704b. At this time, it is preferable to use an oxide having a relatively wide energy gap for the oxide 704a with respect to the oxide 704b. Also, it is preferable to use an oxide having a relatively wide energy gap for the oxide 704c with respect to the oxide 704b. Here, an oxide with a wide energy gap may be called a wide-gap oxide, and an oxide with a narrow energy gap may be called a narrow-gap oxide.

[0090] Note that in FIGS. 3A and 3B, the oxide 704 has a three-layer structure of the oxide 704a, the oxide 704b, and the oxide 704c, but it is not limited thereto. The oxide 704 may have a single-layer structure consisting of any one of the oxide 704a, the oxide 704b, and the oxide 704c, may have a two-layer structure of the oxide 704a and the oxide 704b, or may have a laminated structure of four or more layers.

[0091] When the oxide 704a and the oxide 704c are wide-gap oxides and the oxide 704b is a narrow-gap oxide, it is preferable that the energy of the lower end of the conduction band of the oxide 704a and the oxide 704c is higher than the energy of the lower end of the conduction band of the oxide 704b. In other words, it is preferable that the electron affinity of the oxide 704a and the oxide 704c is smaller than the electron affinity of the oxide 704b.

[0092] In addition, it is preferable that the oxide 704a, the oxide 704b, and the oxide 704c have different combinations of the atomic ratios of the respective metal atoms. Specifically, in the metal oxides used for the oxide 704a and the oxide 704c, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 704b. Further, in the metal oxides used for the oxide 704a and the oxide 704c, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 704b. Also, in the metal oxide used for the oxide 704b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxides used for the oxide 704a and the oxide 704c.

[0093] For the oxide 704a and the oxide 704c, for example, metal oxides having a composition of In:Ga:Zn = 1:3:4, In:Ga:Zn = 1:3:2, or In:Ga:Zn = 1:1:1 and compositions in the vicinity thereof can be used. For the oxide 704b, for example, metal oxides having a composition of In:Ga:Zn = 4:2:3 to 4.1, In:Ga:Zn = 1:1:1, or In:Ga:Zn = 5:1:6 and compositions in the vicinity thereof can be used. It is preferable to combine these oxide 704a, oxide 704b, and oxide 704c so as to satisfy the above relationship of the atomic ratios. For example, it is preferable that the oxide 704a and the oxide 704c are metal oxides having a composition of In:Ga:Zn = 1:3:4 and compositions in the vicinity thereof, and the oxide 704b is a metal oxide having a composition of In:Ga:Zn = 4:2:3 to 4.1 and compositions in the vicinity thereof. Note that the above compositions indicate the atomic ratios in the oxide formed on the substrate or the atomic ratios in the sputtering target.

[0094] Also, as the oxide 704a and the oxide 704c, it is preferable to use CAAC-OS described later, and as the oxide 704b, it is preferable to use CAC-OS. When using CAAC-OS as the oxide 704a and the oxide 704c, the c-axis is preferably parallel to the x-y plane shown in FIGS. 1 and 2, etc., that is, perpendicular to the z-axis, and oriented from the side surface of the opening toward the center.

[0095] Here, at the junction between the oxide 704a and the oxide 704b and at the junction between the oxide 704c and the oxide 704b, the lower end of the conduction band changes smoothly. In other words, it can also be said that the lower end of the conduction band at the junction between the oxide 704a and the oxide 704b and at the junction between the oxide 704c and the oxide 704b changes continuously or is continuously joined. To achieve this, it is preferable to lower the density of defect levels in the mixed layer formed at the interface between the oxide 704a and the oxide 704b and at the interface between the oxide 704c and the oxide 704b.

[0096] Specifically, by having a common element other than oxygen (as the main component) in the oxide 704a, the oxide 704b, and the oxide 704c, a mixed layer with a low density of defect levels can be formed. For example, when the oxide 704b is an In-Ga-Zn oxide, it is preferable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, etc. as the oxide 704a and the oxide 704c. Thereby, the density of defect levels at the interface between the oxide 704a and the oxide 704b and at the interface between the oxide 704c and the oxide 704b can be lowered. Therefore, the influence of interface scattering on carrier conduction is reduced, and the memory transistor MT can obtain a high on-current.

[0097] For a more detailed description of the metal oxide that can be used as the oxide 704, it will be described later.

[0098] FIG. 3A is an enlarged view of the memory transistor MT surrounded by the dashed-dotted line 791 in FIG. 1. As shown in FIG. 3A, the oxide 704b is provided so as to be sandwiched between the oxide 704a and the oxide 704c. In such a configuration, when carriers flow through the oxide 704 in the direction from the conductor 705 to the conductor 706 or in the direction from the conductor 706 to the conductor 705, the carriers mainly flow in the component having a narrow gap. Therefore, when the above configuration is used, by sandwiching the oxide 704b having a narrow gap with the oxides 704a and 704c having a wide gap, the carriers flowing through the oxide 704 can be confined in the oxide 704b, and a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0099] Further, by providing the oxide 704a between the oxide 704b and the insulator 703c, the oxide 704b serving as a carrier path and the insulator 703c do not directly contact each other, and the formation of trap centers can be suppressed. Trap centers formed at the interface between a semiconductor (oxide semiconductor) and an insulator capture electrons and cause the threshold voltage of the transistor to vary in the positive direction, which may adversely affect the reliability of the transistor and its on / off characteristics. Therefore, the transistor using the oxide is not affected by the electrical characteristics of the trap centers, and thus a higher current driving force, that is, a larger on-current, and a high field-effect mobility can be obtained in the on-state. Further, the transistor and the semiconductor device using the transistor can obtain high reliability.

[0100] In order to provide a low-resistance region in the oxide 704, it is preferable to provide a conductor 719 so as to be in contact with a part of the oxide 704. The conductor 719 is provided via the insulator 703 and the oxide 704 on the side surfaces of the insulator 721, the insulator 722, and the insulator 724. Although details will be described later, the diameter of the openings formed in the insulator 721, the insulator 722, and the insulator 724 is larger than the diameter of the openings formed in the conductor 701 and the conductor 702, and the conductor 719 exists only in the same layer as the insulator 721, the insulator 722, and the insulator 724. Therefore, the oxide 704 has a region that is partially in contact with the conductor 719.

[0101] The conductor 719 preferably has at least one of a function of supplying hydrogen to the oxide 704, a function of supplying nitrogen to the oxide 704, and a function of extracting oxygen from the oxide 704. When the conductor 719 having such a function is in contact with the oxide 704, carriers are generated in the oxide 704.

[0102] Specifically, when oxygen is extracted from the oxide 704, oxygen deficiency occurs in the oxide 704. When hydrogen is trapped by this oxygen deficiency, carriers are generated. Or, when nitrogen is trapped by the generated oxygen deficiency, oxygen and nitrogen that were bonded to two indiums are replaced. When nitrogen is bonded to these two indiums, nitrogen has unpaired electrons and is considered to function as a carrier.

[0103] As the conductor 719 having a function of extracting oxygen from the oxide 704, a material containing one or more of tantalum, tungsten, titanium, and aluminum can be used. Alternatively, a nitride or an oxide containing one or more of tantalum, tungsten, titanium, and aluminum can be used. Specifically, tantalum nitride, tungsten nitride, titanium nitride, aluminum nitride, a nitride containing aluminum and tantalum, a nitride containing aluminum and titanium, aluminum oxide, tantalum oxide, etc. can be used. By using a metal nitride as the conductor 719, it is possible to extract oxygen from the oxide 704 and supply nitrogen to the oxide 704.

[0104] Also, hydrogen contained in the insulator 703, insulator 721, insulator 722, and insulator 724 may be supplied to the oxide 704. Alternatively, as the conductor 719, a material formed using a gas containing hydrogen during formation can be used, and silicon, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, etc. formed using monosilane, disilane, ammonia, etc. can be used. Such a material preferably has a function of shielding microwaves.

[0105] After providing the oxide 704 and the conductor 719 in contact with each other, it is preferable to perform heat treatment. By performing heat treatment, the extraction of oxygen, the supply of hydrogen, or the supply of nitrogen is promoted, and the oxide 704 can be efficiently partially made to have a lower resistance. Thus, by providing a low-resistance region in the oxide 704, in a memory string or a memory cell array in which memory cells are stacked, the series resistance between the memory cells can be reduced.

[0106] Further, the region 731 and a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be heat-treated in an atmosphere containing nitrogen while being in contact with each other. By this heat treatment, the metal element diffuses from the metal film, the nitride film containing a metal element, or the oxide film containing a metal element into the region 731 of the oxide 704, and the metal element can be added to the region 731. At this time, the region 731 of the oxide 704 and the metal element may be alloyed. When the region 731 of the oxide 704 and the metal element are alloyed, the metal element added to the oxide semiconductor becomes in a relatively stable state, so that a highly reliable semiconductor device can be provided.

[0107] Further, in order to provide a type I region in the oxide 704, the conductor 719 preferably shields microwaves and functions as a mask for the oxide 704.

[0108] By performing a high-resistance treatment on the oxide 704 not covered by the conductor 719, a region 734 that becomes a high-resistance region is formed in the oxide 704. Examples of the high-resistance treatment include a method of supplying oxygen to the oxide 704 and a method of extracting hydrogen from the oxide 704.

[0109] By performing microwave treatment on the oxide 704 in an atmosphere containing at least oxygen, the carrier concentration of the oxide 704 can be reduced, and a high-resistance region can be formed. The atmosphere for performing the microwave treatment may be an atmosphere containing oxygen and argon. By the microwave treatment, the carrier concentration of the oxide 704 is preferably less than 1×10 18 / cm 3 , preferably less than 1×10 17 / cm 3 , more preferably less than 1×10 16 / cm 3 .

[0110] By microwave treatment, hydrogen in the oxide 704 combines with oxygen to form water molecules or hydroxide ions and is released from the oxide 704. Also, oxygen in the atmosphere is supplied to the oxygen vacancies generated in the oxide 704 due to the release of water molecules or hydroxide ions, and it is considered that the oxide 704 becomes highly resistive and the region 734 becomes a high-resistance region, that is, a type-I region.

[0111] In microwave treatment, thermal energy may be directly transmitted to the oxide 704 by the electromagnetic interaction between the microwave and the molecules in the oxide 704. The oxide 704 may be heated by this thermal energy. Such a heat treatment may be called microwave annealing. By performing the microwave treatment in an atmosphere containing oxygen, an effect equivalent to oxygen annealing may be obtained. Also, when the oxide 704 contains hydrogen, it is considered that this thermal energy is transmitted to the hydrogen in the oxide 704, and the activated hydrogen is released from the oxide 704.

[0112] Here, in a memory transistor or a selection transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in the region where the channel in the oxide semiconductor is formed, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, if the region where the channel in the oxide semiconductor is formed contains oxygen vacancies, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen vacancies in the region 734 where the channel is formed are reduced as much as possible. Since oxygen can be supplied to the oxide 704 by microwave treatment, it is possible to repair the oxygen vacancies in the region 734, which is preferable.

[0113] On the other hand, in the region 731 covered with the conductor 719, the microwave is shielded, and the reduction of the hydrogen concentration and the carrier concentration does not occur, and a low-resistance region, that is, an N-type region can be maintained. At this time, the carrier concentration in the region 731 is 1×10 18 / cm 3 or more, preferably 1×10 19 / cm 3 or more, more preferably 1×10 20 / cm3 It is preferably as described above.

[0114] In addition, when hydrogen in the oxide 704 diffuses into the region 731 and enters the oxygen vacancies existing in the region 731, it becomes a relatively stable state. Also, hydrogen in the oxygen vacancies existing in the region 734 escapes from the oxygen vacancies by heat treatment at 250 °C or higher, diffuses into the region 731, and enters the oxygen vacancies existing in the region 731, becoming a relatively stable state. Therefore, by heat treatment, the region 731 has lower resistance, and the region 734 is purified (reduction of impurities such as water and hydrogen) and has higher resistance.

[0115] When providing the conductor 712, as the conductor 712, the same material as the conductor 701 can be used. Since the conductor 712 needs to be formed inside an opening with a large aspect ratio (in other words, the recesses of the oxide 704 and the insulator 711), it is preferably formed by a CVD method, an ALD method, or a plating method. At this time, the insulator 711 can use the same material as the insulator 703.

[0116] In addition, when providing the insulator 711 inside the oxide 704c, the insulator 711 is preferably a material that can supply oxygen to the oxide 704 or a material that can supply impurities such as hydrogen and nitrogen. By using an oxide that contains as little hydrogen and nitrogen as possible as the insulator 711, it may be possible to supply oxygen to the oxide 704. By supplying oxygen to the oxide 704, impurities such as hydrogen and water contained in the oxide 704 can be removed, and the oxide 704 is purified. By using an oxide with extremely reduced impurities as the oxide 704, the memory transistor MT and the semiconductor device using the memory transistor MT can obtain high reliability.

[0117] Also, when using an oxide containing hydrogen or nitrogen as the insulator 711, hydrogen or nitrogen may be supplied to the oxide 704. By supplying hydrogen or nitrogen to the oxide 704, the resistance value of the oxide 704 may decrease. By reducing the resistance value of the oxide 704 to such an extent that it does not cause adverse effects on circuit operation, the memory transistor MT can be operated at a lower drive voltage. Also, a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the memory transistor MT.

[0118] Note that the opening formed in the laminate where the memory transistor MT is provided has a circular upper surface in FIG. 2A and the like, but is not limited thereto. For example, the upper surface may be elliptical, or may be polygonal such as triangular or quadrangular. Also, when it is polygonal, it may have a shape with rounded corners. Also, the upper surface shapes of the insulator 703 and the oxide 704 may change according to the upper surface shape of the opening. Also, the opening may have a shape in which the cross-sectional area of the lower opening (on the side of the conductor 706) is narrower than the cross-sectional area of the upper opening (on the side of the conductor 705).

[0119] The memory transistor MT is composed of the oxide 704, the insulator 703, and the conductor 701 (any one of the conductors 701_1 to 701_m). FIGS. 1 and 2 show an example in which the memory transistors MT are stacked in m stages (m is a natural number of 2 or more). In FIGS. 1 and 2, in order to represent a plurality of conductors 701, the conductor 701 is displayed in 4 or more stages, but the present embodiment is not limited to FIG. 1, and it is sufficient to have at least 2 or more stages of the conductor 701.

[0120] The conductor 705 is electrically connected to the oxide 704 and functions as part of the source line SL or the bit line BL. As the conductor 705, it is preferable to use a conductive material containing a metal element. Alternatively, as the conductor 705, a conductive material among those that can be used for the conductor 719 can be used. In this case, as described above, a part of the oxide 704 has a reduced resistance. Also, at the interface between the conductor 705 and the oxide 704, it is preferable that a metal compound layer containing the metal element of the conductor 705 and the components of the oxide 704 is formed. The formation of the metal compound layer is preferable because it reduces the contact resistance between the conductor 705 and the oxide 704. Alternatively, the oxygen contained in the oxide 704 is absorbed by the conductor 705, and the contact resistance between the conductor 705 and the oxide 704 can be reduced by reducing the resistance in the vicinity of the interface between the conductor 705 and the oxide 704.

[0121] As the conductor 705, it is preferable to use a conductive material containing one or more metal elements selected from aluminum, ruthenium, titanium, tantalum, chromium, tungsten, and copper.

[0122] As shown in FIG. 2B, the conductor 706 electrically connects the oxide 704 that is electrically connected to the conductor 705 functioning as part of the bit line BL and the oxide 704 that is electrically connected to the conductor 705 functioning as part of the source line SL, thereby constituting a memory string. The region surrounded by the dotted line in FIG. 2A represents the memory string. That is, FIG. 2A shows a memory cell array 700 having four memory strings.

[0123] As the conductor 706, the same material as that of the conductor 705 can be used. Alternatively, as the conductor 706, a conductive material among those that can be used for the conductor 719 can be used. In this case, as described above, a part of the oxide 704 has a reduced resistance. Also, the conductor 706 may use the same material as that of the conductor 705 or a different material.

[0124] In addition, it is preferable that a metal compound layer containing a metal element included in the conductor 706 and components of the oxide 704 is formed at the interface between the conductor 706 and the oxide 704. The formation of the metal compound layer is preferable because it reduces the contact resistance between the conductor 706 and the oxide 704. Alternatively, the oxygen contained in the oxide 704 is absorbed by the conductor 706, and the contact resistance between the conductor 706 and the oxide 704 can be reduced by reducing the resistance in the vicinity of the interface between the conductor 706 and the oxide 704 of the oxide 704.

[0125] The conductors 707, 708, 709, 710, 714, and 715 can be similarly made of materials that can be used for the conductor 701, the conductor 702, or the conductor 712. Each conductor may use the same material or different materials.

[0126] (Memory cell array 700A) FIG. 4 is a top view for explaining a memory cell array 700A in which a plurality of memory cell arrays 700 each having six-stage memory transistors MT are combined. In FIG. 4, some components are omitted for ease of explanation. For example, the selection transistors (bit line side transistors SDT and source line side transistors SST) provided on the conductor 701 and the conductor 702 which is one of their components are omitted. Also, the conductor 705 that functions as part of the bit line BL and the source line SL, the conductor 708 that functions as part of the word line WL, and the conductor 715 that functions as part of the wiring BG electrically connected to the conductor 712 that functions as the second gate are shown by solid lines.

[0127] In the memory cell array 700A, each memory cell array 700 has four memory strings each having six-stage memory transistors MT.

[0128] The ends of the memory string on the bit line side are electrically connected to different bit lines BL (bit lines BL_1 to BL_4), respectively. On the other hand, the ends of the memory string on the source line side are electrically connected to the source line SL, and a common potential is applied. The source line SL may be grounded or a certain potential may be applied. Also, the potential may be varied according to the operation of the circuit.

[0129] Conductors 701_1 to 701_6 are electrically connected to different word lines WL, respectively. The conductors 701_1 to 701_6 on the bit line side are electrically connected to word lines WLa_1 to WLa_6, respectively, and the conductors 701_1 to 701_6 on the source line side are electrically connected to word lines WLb_1 to WLb_6, respectively.

[0130] Conductor 712 is electrically connected to wiring BG. FIG. 4 shows an example in which conductors 712 arranged in the column direction are electrically connected to a common wiring BG, but the present invention is not limited thereto. Conductors 712 arranged in the row direction may be electrically connected to a common wiring BG. Also, different potentials may be applied to each wiring BG. Also, the same potential may be applied to a plurality of wirings BG. When the same potential is applied to a plurality of wirings BG, it is preferable that the plurality of wirings BG are electrically connected to each other. The plurality of wirings BG may refer to all the wirings BG that the memory cell array 700A has.

[0131] Also, in order to apply an arbitrary potential to the wiring BG, it is preferable that the wiring BG is electrically connected to a circuit for controlling the potential of the wiring BG (for example, a BG driver, or sometimes called a BG driver circuit. Also, sometimes simply called a driver, or a driver circuit). The BG driver circuit may be provided for each wiring BG, or a plurality of wirings BG may be electrically connected to one BG driver circuit. For example, the memory cell array 700A may have one BG driver circuit, and all the wirings BG that the memory cell array 700A has may be electrically connected to the BG driver circuit.

[0132] By appropriately selecting bit lines BL (bit lines BL_1 to BL_4) and word lines WL (word lines WLa_1 to WLa_6 and word lines WLb_1 to WLb_6), any memory transistor MT in the memory cell array 700 can be selected. Further, writing, reading, erasing, etc. can be performed on the selected memory transistor MT.

[0133] In addition, since each memory string is provided with a selection transistor (not shown), any memory cell array 700 in the memory cell array 700A can be selected, and writing, reading, erasing, etc. can be performed on any memory transistor MT in the selected memory cell array 700.

[0134] (Configuration example of the storage device 750) FIG. 5 shows a configuration example of a storage device 750 in which a memory cell array 700A is stacked on a circuit 300. As shown in FIG. 5, the memory cell array 700A is provided by being stacked on a region where the circuit 300 having the transistor 301, the transistor 302, and the transistor 303 is formed. Note that the transistor 301 and the transistor 302 constitute a sense amplifier 304, and the transistor 303 functions as a column selection switch. Specifically, the bit line BL of the memory cell array 700A is electrically connected to one of the source and drain of the transistor 301, the gate of the transistor 301 is electrically connected to one of the source and drain of the transistor 302, and the gate of the transistor 302 is electrically connected to the other of the source and drain of the transistor 301. Further, one of the source and drain of the transistor 301 and the other of the source and drain of the transistor 302 are electrically connected to one of the source and drain of the transistor 303 that functions as a column selection switch. Thereby, the layout area of the storage device 750 can be reduced. Note that FIG. 5 shows an example in which ten stages of memory transistors MT are provided and 20 memory transistors MT are provided per memory string. However, the number of stages in which the memory transistors MT are stacked is not limited to this. For example, 32 stages, 64 stages, or 128 stages may be stacked, or 200 or more stages may be stacked.

[0135] The bit line BL of the memory cell array 700A is electrically connected to the sense amplifier 304 and the transistor 303 that functions as a column selection switch via a conductor 752 formed so as to be embedded in insulators 726, 722, and the like. Note that the circuits and transistors included in the circuit 300 are merely examples, and one aspect of the present invention is not limited to the circuit configuration and the transistor structure. In addition to the above, appropriate circuits and transistors can be provided according to the configuration of the storage device 750, such as a control circuit, a row decoder, a row driver, a source line driver, and an input / output circuit, and its driving method.

[0136] Transistors 301, 302, and 303 are provided on substrate 311 and each have a conductor 316, an insulator 315, a semiconductor region 313 which is part of substrate 311, and low-resistance regions 314a and 314b that function as a source region or a drain region. Note that, as shown in FIG. 5, one low-resistance region may be shared as one of the source regions or drain regions of transistors 301 and 302 and the other source region or drain region of transistors 301 and 302.

[0137] Transistors 301, 302, and 303 have a semiconductor region 313 (a part of substrate 311) where a channel is formed and has a convex shape. Also, the side surface and the upper surface of semiconductor region 313 are covered with conductor 316 via insulator 315. Note that conductor 316 may use a material for adjusting the work function. Since transistors 301, 302, and 303 of such a structure utilize the convex portions of the semiconductor substrate, they are also called FIN-type transistors. Note that an insulator that functions as a mask for forming the convex portions may be provided in contact with the upper portions of the convex portions. Here, the case where a part of the semiconductor substrate is processed to form the convex portions has been described, but an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0138] Transistors 301, 302, and 303 may each be either a p-channel type or an n-channel type, but it is preferable that transistors 301 and 302 are transistors having different polarities.

[0139] In regions where channels of the semiconductor region 313 are formed, regions in the vicinity thereof, source regions, or drain regions, such as the low-resistance regions 314a and 314b, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is more preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice spacing may also be used. Alternatively, by using GaAs, GaAlAs, etc., the transistors 301, 302, and 303 may be HEMTs (High Electron Mobility Transistors).

[0140] The low-resistance regions 314a and 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity such as arsenic and phosphorus, or elements that impart p-type conductivity such as boron.

[0141] The insulator 315 functions as a gate insulating film for the transistors 301, 302, and 303.

[0142] The conductor 316 that functions as a gate electrode can be made of a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic and phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material.

[0143] Note that since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embedding properties, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0144] Also, it is preferable that an insulator 317 that functions as an etch stopper is provided above the conductor 316. Further, it is preferable that an insulator 318 that functions as a spacer is provided on the side surface of the insulator 315. By providing the insulator 317 and the insulator 318, the low-resistance regions 314a and 314b and the region where the conductor 328 is electrically connected can be self-alignedly determined. Therefore, even if an alignment deviation occurs when forming an opening for exposing a part of the low-resistance region 314a and the low-resistance region 314b, an opening for exposing the intended region can be formed. By forming the conductor 328 in the opening thus formed, a good contact with reduced contact resistance can be obtained between the low-resistance region 314a, the low-resistance region 314b, and the conductor 328. The contact between the low-resistance region 314a and the low-resistance region 314b and the conductor 328 thus formed may be referred to as a self-aligned contact. Further, a conductor 329 electrically connected to the conductor 316 may be provided so as to be embedded in the insulator 317 and the insulator 322.

[0145] The insulators 320, 322, 324, 326, and 327 are sequentially laminated and provided so as to cover the transistors 301, 302, and 303.

[0146] As the insulators 320, 322, 324, 326, and 327, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0147] The insulator 322 may have a function as a planarization film that planarizes the step formed by the transistor 301 or the like provided therebelow. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like in order to enhance flatness.

[0148] In addition, for the insulator 324, it is preferable to use a film having a barrier property such that hydrogen and impurities do not diffuse into the region where the memory cell array 700A is provided, such as the substrate 311 or the transistor 301.

[0149] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor device having an oxide semiconductor such as a memory transistor MT, the characteristics of the semiconductor device may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the memory transistor MT and the transistor 301 or the like. Specifically, the film that suppresses the diffusion of hydrogen is a film having a small amount of hydrogen desorption.

[0150] The amount of hydrogen desorption can be analyzed using, for example, temperature-programmed desorption gas analysis (TDS). For example, the amount of hydrogen desorption of the insulator 324 is such that in the TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, when converted per unit area of the insulator 324, is 10×10 15 atoms / cm 2 or less, preferably 5×10 15 atoms / cm 2 or less.

[0151] Note that the insulators 326 and 327 preferably have a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulators 326 and 327 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulators 326 and 327 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0152] In addition, conductors 328, 329, and 330, etc., which are electrically connected to the memory cell array 700A, are embedded in the insulators 320, 322, 324, 326, and 327. Note that the conductors 328, 329, and 330 have functions as plugs or wirings. Also, conductors having functions as plugs or wirings may be given the same reference numeral collectively for a plurality of structures. Further, in this specification etc., a wiring and a plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0153] As materials for each plug and wiring (conductors 328, 329, 330, etc.), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used singly or in a stacked manner. It is preferable to use high melting point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity, and particularly preferably to use tungsten. Alternatively, it is preferable to form with a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0154] A wiring layer may be provided on the insulator 327 and the conductor 330. For example, in FIG. 5, the insulators 350, 352, and 354 are sequentially stacked and provided. Also, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 has functions as a plug or a wiring. Note that the conductor 356 can be provided using the same material as the conductors 328, 329, and 330.

[0155] Note that, for example, as with the insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 350. Further, the conductor 356 preferably includes a conductor having a barrier property against hydrogen. That is, it is preferable that the conductor 356 having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 301 etc. and the memory transistor MT can be separated by the barrier layer, and the diffusion of hydrogen from the transistor 301 etc. to the memory transistor MT can be suppressed.

[0156] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride etc. may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, the diffusion of hydrogen from the transistor 301 etc. can be suppressed while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0157] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 5, the insulator 360, the insulator 362, and the insulator 364 are laminated and provided in this order. Further, the conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has the function of a plug or wiring. Note that the conductor 366 can be provided using the same materials as the conductor 328, the conductor 329, and the conductor 330.

[0158] Note that, for example, as with insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for insulator 360. Further, conductor 366 preferably includes a conductor having a barrier property against hydrogen. That is, it is preferable that conductor 366 having a barrier property against hydrogen is formed in the opening of insulator 360 having a barrier property against hydrogen. With this configuration, the transistor 301 etc. and the memory transistor MT can be separated by a barrier layer, and diffusion of hydrogen from the transistor 301 etc. to the memory transistor MT can be suppressed.

[0159] An insulator 722 is provided on insulator 364 and conductor 366, and a memory cell array 700A is provided above insulator 722. A barrier film using the same material as insulator 324 may be provided between insulator 364 and insulator 722.

[0160] In FIG. 5, an example of a memory cell array 700A having a U-shaped memory string in which two columnar oxides 704 are electrically connected by a conductor 706 is shown, but the present invention is not limited to this. FIG. 6 shows an example in which, in a columnar oxide 704 having eight-stage memory transistors MT and two selection transistors (SDT, SST), the lower end of one columnar oxide 704 is electrically connected to a conductor 705B functioning as a bit line BL, and the upper end is electrically connected to a conductor 705S functioning as a source line SL. That is, one memory string is configured by one columnar oxide 704. In FIG. 6, conductor 705B is electrically connected to the lower ends of four columnar oxides, but the present invention is not limited to this. One conductor 705B may be electrically connected to one columnar oxide 704, or one conductor 705B may be electrically connected to two or more columnar oxides 704. Further, conductor 705S is electrically connected to the upper ends of two columnar oxides, but the present invention is not limited to this. One conductor 705S may be electrically connected to one columnar oxide 704, or one conductor 705S may be electrically connected to two or more columnar oxides 704.

[0161] A selection transistor SDT is provided between the conductor 705B and the memory transistor MT, and a selection transistor SST is provided between the conductor 705S and the memory transistor MT. Since the conductor 705B functioning as the bit line BL is electrically connected to the circuit 300 provided below, the number of wirings (routing wirings) and plugs for electrically connecting the memory cell array 700A and the circuit 300 can be reduced, and the layout area of the storage device 750 can be further reduced, which is preferable. In FIG. 6, eight stages of memory transistors MT to be stacked are shown, but the present invention is not limited to this. It may be two or more and seven or less stages, or nine or more stages. For example, 32 stages, 64 stages, or 128 stages may be stacked, or 200 or more stages may be stacked.

[0162] <<Metal Oxide>> Hereinafter, metal oxides applicable to the oxide 704 according to the present invention will be described.

[0163] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that one or more selected from aluminum, gallium, yttrium, and tin are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be contained.

[0164] For example, the metal oxide preferably contains indium, gallium, and zinc. Or, the metal oxide preferably contains indium and gallium. Or, the metal oxide preferably contains indium and zinc. Or, the metal oxide preferably contains indium. Or, the metal oxide preferably contains indium, gallium, zinc, and tin.

[0165] Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is one or more elements selected from aluminum, gallium, yttrium, and tin. Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like. However, there may be cases where a plurality of the aforementioned elements are combined as element M.

[0166] In this specification and the like, a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0167] [Configuration of Metal Oxide] Hereinafter, the configuration of the CAC (Cloud-Aligned Composite)-OS that can be used in the transistor disclosed in one aspect of the present invention will be described.

[0168] In this specification and the like, there may be cases where CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite) are described. Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material configuration.

[0169] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is the function of flowing electrons (or holes) serving as carriers, and the insulating function is the function of not flowing electrons serving as carriers. By causing the conductive function and the insulating function to act complementarily, respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximally enhanced.

[0170] In addition, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material, respectively. Also, the conductive region may be observed to be blurred at the periphery and connected in a cloud shape.

[0171] In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively.

[0172] In addition, CAC-OS or CAC-metal oxide is composed of components having different bandgaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide bandgap due to an insulating region and a component having a narrow bandgap due to a conductive region. In such a configuration, when carriers flow, carriers mainly flow in the component having a narrow bandgap. Further, the component having a narrow bandgap acts complementarily to the component having a wide bandgap, and carriers also flow in the component having a wide bandgap in conjunction with the component having a narrow bandgap. Therefore, when the above CAC-OS or CAC-metal oxide is used for the channel formation region of a transistor, a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0173] That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0174] [Structure of Metal Oxide] Oxide semiconductors (metal oxides) can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0175] CAAC-OS has a c-axis orientation, and in the a-b plane direction, a plurality of nanocrystals are connected to form a crystal structure with strain. The strain refers to a location where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.

[0176] The nanocrystals are based on a hexagon, but are not necessarily regular hexagons and may be non-regular hexagons. Also, in the strain, there may be lattice arrangements such as pentagons and heptagons. In CAAC-OS, it is difficult to confirm a clear grain boundary (also referred to as a grain boundary) even in the vicinity of the strain. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements.

[0177] Also, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M,Zn) layer) are laminated. Indium and element M are mutually substitutable, and when element M in the (M,Zn) layer is substituted with indium, it can also be represented as an (In,M,Zn) layer. Also, when indium in the In layer is substituted with element M, it can also be represented as an (In,M) layer.

[0178] CAAC-OS is a highly crystalline metal oxide. On the other hand, since it is difficult to confirm a clear grain boundary in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur. Also, since the crystallinity of metal oxides may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS has impurities and defects (oxygen vacancies (V O: It can also be said to be a metal oxide with few (such as oxygen vacancies). Therefore, the metal oxide having CAAC-OS has stable physical properties. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0179] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed in the whole film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor.

[0180] a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity compared with nc-OS and CAAC-OS.

[0181] An oxide semiconductor (metal oxide) has various structures and each has different characteristics. The oxide semiconductor according to one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0182] [Transistor having a metal oxide] Subsequently, the case where the above metal oxide is used for the channel formation region of a transistor will be described.

[0183] Note that by using the above metal oxide for the channel formation region of a transistor, a transistor with high field-effect mobility can be realized. Further, a highly reliable transistor can be realized.

[0184] Here, an example of a hypothesis of the electrical conduction of a metal oxide will be described.

[0185] Electrical conduction in a solid is inhibited by scattering sources called scattering centers. For example, in the case of single-crystal silicon, lattice scattering and ionized impurity scattering are known to be the main scattering centers. In other words, in an essential state with few lattice defects and impurities, there are no factors inhibiting electrical conduction in the solid, and the carrier mobility is high.

[0186] The above is presumed to apply to metal oxides as well. For example, in a metal oxide containing less oxygen than the stoichiometric composition, it is considered that there are many oxygen vacancies V O present. The atoms existing around this oxygen vacancy are located in a distorted place rather than in an essential state. There is a possibility that the distortion caused by this oxygen vacancy serves as a scattering center.

[0187] Also, for example, in a metal compound containing more oxygen than the stoichiometric composition, there is excess oxygen. The excess oxygen existing in a free state in the metal compound accepts electrons to become O - or O 2- . There is a possibility that the excess oxygen that has become O - or O 2- becomes a scattering center.

[0188] From the above, when a metal oxide has an essential state containing oxygen that satisfies the stoichiometric composition, the carrier mobility is considered to be high.

[0189] Indium-gallium-zinc oxide (hereinafter, IGZO), which is a kind of metal oxide having indium, gallium, and zinc, particularly tends to be difficult to grow crystals in the air. Therefore, a crystal smaller than a large crystal (here, a crystal of several mm or several cm), for example, the above-described nanocrystal, may be structurally more stable. This is considered to be because the strain energy is relaxed when small crystals are connected to each other rather than forming a large crystal.

[0190] In the region where small crystals are connected to each other, defects may be formed in order to relax the strain energy in the region. Therefore, by relaxing the strain energy without forming defects in the region, the mobility of carriers can be increased.

[0191] In addition, for the transistor, it is preferable to use a metal oxide with a low carrier density. When reducing the carrier density of the metal oxide film, the impurity concentration in the metal oxide film may be reduced and the density of defect levels may be reduced. In this specification and the like, the fact that the impurity concentration is low and the density of defect levels is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, the metal oxide has a carrier density of less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 , and may be 1×10 -9 / cm 3 or more.

[0192] In addition, since the metal oxide film having high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0193] In addition, the charge trapped in the trap levels of the metal oxide may take a long time to disappear and may behave like a fixed charge. Therefore, a transistor having a metal oxide with a high trap level density in the channel formation region may have unstable electrical characteristics.

[0194] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In addition, in order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of the impurity include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0195] [Impurity] Here, the effects of various impurities in the metal oxide will be described.

[0196] In the metal oxide, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the metal oxide. For this reason, the concentration of silicon or carbon in the metal oxide and the concentration of silicon or carbon near the interface with the metal oxide (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Hereinafter, preferably 2×10 17 atoms / cm 3 or less.

[0197] In addition, when an alkali metal or an alkaline earth metal is contained in the metal oxide, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal in the channel formation region tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or the alkaline earth metal in the metal oxide obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0198] In addition, in the metal oxide, when nitrogen is contained, carriers, i.e., electrons, are generated, the carrier density increases, and it tends to be n-type. As a result, a transistor using a metal oxide containing nitrogen in the channel formation region tends to have normally-on characteristics. Therefore, in the metal oxide, it is preferable that the nitrogen in the channel formation region is reduced as much as possible. For example, the nitrogen concentration in the metal oxide is less than 5×10 19 atoms / cm 3 preferably 5×10 18 atoms / cm 3 or less, more preferably 1×1018 atoms / cm 3 Next, more preferably, it is 5×10 17 atoms / cm 3 or less.

[0199] In addition, since hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to form water, oxygen deficiency may be formed. When hydrogen enters the oxygen deficiency, carriers, electrons, may be generated. Also, a part of hydrogen may bond to oxygen bonded to the metal atom to generate carriers, electrons. Therefore, a transistor using a metal oxide containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, preferably 1×10 19 atoms / cm 3 less than, more preferably 5×10 18 atoms / cm 3 less than, even more preferably 1×10 18 atoms / cm 3 or less.

[0200] By using a metal oxide with sufficiently reduced impurities in the channel formation region of the transistor, the off-current of the transistor can be reduced and stable electrical characteristics can be imparted.

[0201] (Fabrication Method 1 of Memory Cell) Next, one embodiment of a method for creating a memory transistor MT that functions as the memory cell of the present invention will be described with reference to FIGS. 7A to 12B. FIGS. 7A to 12B are diagrams showing cross-sections of the manufacturing process of the memory transistor MT.

[0202] First, as shown in FIG. 7A, a conductor 701 and an insulator 722 are alternately laminated in the z-axis direction.

[0203] Next, as shown in FIG. 7B, the conductor 701 and the insulator 722 are processed to form openings having a diameter of φ1 in the conductor 701 and the insulator 722.

[0204] Next, isotropic etching is performed under processing conditions in which the insulator 722 is etched while the conductor 701 is not etched, or under processing conditions in which the etching rate of the insulator 722 is sufficiently faster than that of the conductor 701. Then, as shown in FIG. 7C, the side surface of the insulator 722 retreats in a direction perpendicular and / or substantially perpendicular to the z-axis direction, and irregularities are formed on the side surface of the opening. When the opening diameter generated by the etching is φ2, the relationship φ1 < φ2 holds between φ1 and φ2.

[0205] Next, as shown in FIGS. 8A and 8B, an insulator 703 and an oxide 704 are formed inside the opening. FIG. 8B is an enlarged view of the region surrounded by the dashed-dotted line in FIG. 8A, and shows cross-sections of the conductor 701_k-1 and the insulator 722_k-1 at the k-1th stage, the conductor 701_k and the insulator 722_k at the kth stage, and the conductor 701_k+1 at the k+1th stage (k is an integer from 2 to m-1). The insulator 703 is formed by sequentially laminating an insulator 703a, an insulator 703b, and an insulator 703c. The oxide 704 is formed by sequentially laminating an oxide 704a, an oxide 704b, and an oxide 704c. Although not shown, it is preferable to remove the insulator 703 at the bottom of the opening before forming the oxide 704. The insulator 703 and the oxide 704 are well formed even in the recess of the insulator 722, and the insulator 703a is formed so as to be in contact with the side surface of the insulator 722, the side surface of the conductor 701, a part of the upper surface, and a part of the lower surface.

[0206] Next, as shown in FIG. 9A, a conductive film 719A is formed inside the opening. FIG. 9B is an enlarged view of the portion surrounded by the dashed-dotted line in FIG. 9A. As shown in FIG. 9B, the conductive film 719A may be formed so as to sandwich the insulator 703 and the oxide 704 and fill the inside of the recess. However, the present invention is not limited to this. As shown in FIG. 9C, the conductive film 719A may be formed so as to fill not only the recess but also the entire opening.

[0207] Next, the conductive film 719A is processed to form the conductor 719 (see FIG. 10A). Isotropic etching or anisotropic etching can be used for processing the conductive film 719A. In the formation of the conductive film 719A, as shown in FIG. 9A, when the conductive film 719A fills the concave portion and the opening is not completely filled, it is preferable to use isotropic etching for processing the conductive film 719A. On the other hand, as shown in FIG. 9C, when the conductive film 719A is formed so as to fill the concave portion and the opening, it is preferable to use anisotropic etching. By the above-described processing, the conductor 719 can be formed inside the concave portion.

[0208] After the formation of the conductor 719, heat treatment may be performed to reduce the resistance of the oxide 704 in the region in contact with the conductor 719. Further, the timing of performing the heat treatment is not limited to this step. It may be performed after the microwave treatment, after the formation of the insulator 711, or after the formation of the conductor 712, which will be described later.

[0209] Next, as shown in FIG. 10B, microwave treatment is performed on the oxide 704. The microwave treatment is preferably performed in an atmosphere containing oxygen, and particularly preferably performed in an atmosphere containing oxygen and argon. The microwave 744 irradiated from above the substrate (sometimes referred to as a wafer) on which the conductor 701, the insulator 722, the insulator 703, the oxide 704, and the conductor 719 are formed irradiates the region 734 of the oxide 704 and the conductor 719 inside the opening. Here, since the conductor 719 has a function of shielding the microwave 744, the region 731 of the oxide 704 covered with the conductor 719 is not irradiated with the microwave 744.

[0210] Upon irradiation with microwave 744, the hydrogen concentration in region 734 decreases. In region 734, hydrogen combines with oxygen to form water molecules or hydroxide ions and is considered to be released outside region 734. Also, oxygen in the atmosphere is supplied to the oxygen deficiency formed by the release of water molecules or hydroxide ions. Therefore, it is considered that the carrier concentration in region 734 decreases and region 734 becomes highly resistive. Thus, region 734 can be made into a high-resistance region, that is, a type-I region (see Fig. 11). At this time, by microwave treatment, the carrier concentration of oxide 704 is 1×10 18 / cm 3 less than, preferably, 1×10 17 / cm 3 or less, more preferably, 1×10 16 / cm 3 or less. Also, region 731 not irradiated with microwave 744 maintains low resistance. At this time, the carrier concentration of region 731 is 1×10 18 / cm 3 or more, preferably, 1×10 19 / cm 3 or more, more preferably, 1×10 20 / cm 3 or more.

[0211] In microwave treatment, thermal energy may be directly transferred to oxide 704 due to the electromagnetic interaction between the microwave and the molecules in oxide 704. Oxide 704 may be heated by this thermal energy. Such a heat treatment may be called microwave annealing. By performing microwave treatment in an atmosphere containing oxygen, an effect equivalent to oxygen annealing may be obtained. Also, when oxide 704 contains hydrogen, it is considered that this thermal energy is transferred to the hydrogen in oxide 704 and the activated hydrogen is released from oxide 704.

[0212] Next, an insulator 711 is formed inside the oxide 704 and the conductor 719, and a conductor 712 is formed inside the insulator 711 (see FIG. 12A). Note that the conductor 712 is not necessarily provided, and the inside of the oxide 704 and the conductor 719 may be filled with the insulator 711.

[0213] Here, heat treatment may be performed to reduce the resistance of the oxide 704 in contact with the conductor 719. Since the regions 731 (regions 731a and 731b) of the oxide 704 are in contact with the conductor 719, their resistance is reduced, forming low-resistance regions. On the other hand, the resistance of the region 734 not in contact with the conductor 719 remains high (see FIG. 12B). On the other hand, the above microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. When the oxide 704 etc. are sufficiently heated by microwave annealing, the heat treatment may not be necessary.

[0214] The region 734 of the oxide 704 functions as the channel formation region of the memory transistor MT. Also, the region 731a functions as one of the source and drain of the memory transistor MT, and the region 731b functions as the other of the source and drain. The conductor 701_k functions as the first gate of the memory transistor MT, the conductor 712 functions as the second gate, the insulator 703a functions as the first gate insulating layer, the insulator 703b functions as the charge storage layer, the insulator 703c functions as the tunnel insulating layer, and the insulator 711 functions as the second gate insulating layer. Note that the source or drain of the memory transistor MT with the conductor 701_k as the gate may function as the drain or source in the transistors located above and below. For example, when the region 731b functions as the source of the transistor with the conductor 701_k as the gate, the region 731b may function as the drain of the transistor with the conductor 701_k+1 as the gate.

[0215] Through the above steps, a memory transistor MT that functions as a memory cell can be formed. By the above method, memory transistors MT of multiple layers can be fabricated in one batch without performing pattern formation for fabricating the memory transistor MT for each layer. Further, when fabricating a memory cell array by the above method, even if the number of layers of the memory transistor MT is increased, the number of steps for pattern formation and etching process of the memory transistor MT does not increase. Thus, the process of fabricating the memory cell array can be shortened, and a highly productive semiconductor device can be provided.

[0216] (Method of fabricating memory cell 2) Next, a method of fabricating a memory cell different from the above method will be described with reference to FIGS. 13A to 15C. Here, a method of fabricating a memory cell using different formation methods of the conductor 701 is shown. Note that the same reference numerals are given to the components similar to those shown in the method of fabricating the memory cell 1, and the description thereof and the description of the fabrication method may be omitted.

[0217] First, as shown in FIG. 13A, an insulator 722 and a layer 716 capable of selective etching with respect to the insulator 722 are alternately laminated. The layer 716 is used as a sacrificial layer and removed in a later process, and thus, an insulator, a conductor, a semiconductor, or the like can be used as the material thereof. For example, silicon nitride can be used as the layer 716.

[0218] Next, as shown in FIG. 13B, the layer 716 and the insulator 722 are processed to form first openings having a diameter of φ1 in the layer 716 and the insulator 722.

[0219] Next, as shown in FIG. 13C, a layer 740 is formed inside the first opening. The layer 740 is preferably formed to fill the inside of the first opening. For the formation of the layer 740, one or both of the CVD method and the ALD method can be used. Also, it is preferable that the layer 740 can be selectively etched with respect to the conductor 701 formed in a subsequent process. Further, since the layer 740 is used as a sacrificial layer and removed in a subsequent process, an insulator, a conductor, a semiconductor, or the like can be used as its material. As the layer 740, the same material as the insulator 722 can be used.

[0220] Next, as shown in FIG. 14A, the layer 716 and the insulator 722 are processed to form a second opening in the layer 716 and the insulator 722. The second opening has a slit shape, and a plurality of second openings are formed so as to sandwich the first opening therebetween. The second openings are provided such that their major axes are parallel to each other.

[0221] Next, as shown in FIG. 14B, the layer 716 is etched and removed. For the etching of the layer 716, it is preferable to use isotropic etching such as wet etching, plasma etching, or gas etching. An etchant is introduced from the second opening to remove the layer 716.

[0222] Next, as shown in FIG. 14C, a conductor 810A is formed so as to fill the inside of the second opening and the region where the layer 716 has been removed. For the formation of the conductor 810A, the ALD method or the CVD method can be used. The conductor 810A can use the same material as the conductor 701.

[0223] Next, as shown in FIG. 15A, a part of the conductor 810A is processed to be removed to form a conductor 810. In this processing, at least the conductor 810A inside the second opening is removed. It is preferable to use anisotropic etching for the removal of the conductor 810A. For example, it is preferable to self-aligningly process the conductor 810A using the uppermost layer of the insulator 722 as a mask. By this processing, the second opening is formed again.

[0224] Next, as shown in FIG. 15B, an insulator 742 is formed to fill the second opening. For the formation of the insulator 742, an ALD method or a CVD method can be used. It is preferable that the insulator 742 can be selectively etched with respect to the layer 740 in a subsequent process. As the insulator 742, for example, silicon nitride, silicon oxynitride, silicon nitride oxide, silicon oxide, etc. can be used.

[0225] Next, as shown in FIG. 15C, the layer 740 is processed to form the first opening again. For the processing of the layer 740, it is preferable to use anisotropic etching. Also, isotropic etching is performed on the insulator 722 to expand the opening diameter of the insulator 722. Let the diameter of the opening at this time be φ2 (φ2 > φ1). Here, it can be said that the insulator 722 has a recess with respect to the side surfaces of the conductors 810 sandwiched therebetween vertically. The processing of the insulator 722 may be performed in the same process as the anisotropic etching of the layer 740. For example, it may be performed during the over-etching of the anisotropic etching of the layer 740. Or, after removing the layer 740, isotropic etching may be performed to process the insulator 722.

[0226] Next, although not shown, an insulator 703 and an oxide 704 are formed, a conductor 719 is formed, microwave treatment is performed, an insulator 711 is formed, and a conductor 712 is formed inside the insulator 711, whereby a memory cell can be created. These steps can be implemented in the same manner as the method shown in Fabrication Method 1 of the memory cell.

[0227] (Fabrication Method 1 of Memory Cell Array) Next, an aspect of the method for manufacturing the memory cell array of the present invention will be described with reference to FIGS. 16A to 34C. In each of FIGS. 16A to 34C, A is a top view seen from the z-axis direction, B is a cross-sectional view of the part indicated by the one-dot chain line A1 - A2 in A, and C is a cross-sectional view of the part indicated by the one-dot chain line A3 - A4 in A. Also, FIGS. 26D and 29D are cross-sectional views in which the portions surrounded by the one-dot chain line in FIGS. 26B and 29B are enlarged, respectively. Also, the same components as those shown in the manufacturing method 1 of the memory cell are denoted by the same reference numerals, and the description thereof and the description of the manufacturing method may be omitted.

[0228] First, a conductor 706 is formed on a substrate 720 having an insulating surface, and an insulator 721 is formed so as to cover the conductor 706 (see FIGS. 16A to 16C).

[0229] First, a conductive film is formed, and the conductive film is processed using a lithography method to form the conductor 706. However, the formation methods of the conductor 706 and the insulator 721 are not limited to this. The insulator 721 may be formed on the substrate 720, and grooves and openings may be formed by removing unnecessary portions of the insulator 721, and the conductor 706 may be formed so as to be embedded in the grooves and the openings. Such a method of forming a conductor may be called a damascene method (single damascene method, dual damascene method). By further forming an insulating film on the conductor 706 and the insulator 721 formed by the damascene method, the structure shown in FIGS. 16A to 16C can be obtained.

[0230] The formation of the conductor 706 and the insulator 721 can be performed using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0231] Note that the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, a photo CVD method that uses light, and so on. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method according to the raw material gas used.

[0232] In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Also, since the thermal CVD method does not use plasma, it is a film-forming method capable of reducing plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0233] Also, the ALD method is also a film-forming method capable of reducing plasma damage to the object to be processed. Since the ALD method also does not cause plasma damage during film formation, a film with few defects can be obtained.

[0234] The CVD method and the ALD method are film-forming methods in which a film is formed by a reaction on the surface of the object to be processed, different from a film-forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film-forming method that is less affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method is suitable for covering the surface of an opening with a high aspect ratio because it has excellent step coverage and excellent thickness uniformity. However, since the ALD method has a relatively slow film-forming rate, it may be preferable to use it in combination with other film-forming methods such as the CVD method with a high film-forming rate.

[0235] In the CVD method and the ALD method, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film with an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Also, for example, in the CVD method and the ALD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened by the time required for transfer and pressure adjustment compared to the case of using a plurality of film formation chambers. Therefore, the productivity of semiconductor devices may be increased.

[0236] In the lithography method, first, a resist is exposed through a photomask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Next, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when using an electron beam or an ion beam, a photomask is not required. Note that for removing the resist mask, a dry etching process such as ashing, a wet etching process, a wet etching process after a dry etching process, or a dry etching process after a wet etching process can be performed.

[0237] Also, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed on the conductive film, a resist mask is formed thereon, and a hard mask with a desired shape can be formed by etching the hard mask material.

[0238] This processing can use a dry etching method or a wet etching method. Processing by the dry etching method is suitable for microfabrication.

[0239] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency power source to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high-frequency power sources to one of the parallel plate electrodes. Or it may be configured to apply high-frequency power sources of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high-frequency power sources of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0240] When using a hard mask for etching the conductive film, the etching process may be performed after removing the resist mask used for forming the hard mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the etching of the conductive film. On the other hand, when the material of the hard mask has no influence on the subsequent process or can be used in the subsequent process, it is not necessarily required to remove the hard mask.

[0241] The conductive film serving as the conductor 706 is preferably formed by a sputtering method to form a conductive film containing a metal element. It can also be formed using the CVD method.

[0242] The surface of the insulator 721 is preferably subjected to a planarization process as required. For the planarization process, a chemical mechanical polishing (CMP) method or a reflow method can be used.

[0243] A conductive film 701A and an insulating film 722A are alternately laminated on a conductor 706 and an insulator 721. In the present embodiment, an example is shown in which the conductive film 701A is formed on the insulator 721 and the insulating film 722A is formed on the conductive film 701A, but the order of formation is not limited to this. The insulating film 722A may be formed on the insulator 721 and the conductive film 701A may be formed on the insulating film 722A. For the formation of the conductive film 701A and the insulating film 722A, a CVD method can be used. Also, a sputtering method may be used.

[0244] As the conductor 706 and the conductive film 701A, a conductive material such as silicon doped with impurities or a metal can be used. The conductor 706 and the conductive film 701A may be made of the same material or different materials. When silicon is used as the conductor 706 or the conductive film 701A, amorphous silicon or polysilicon can be used. Also, in order to make silicon conductive, a p-type impurity or an n-type impurity may be added. Also, as a conductive material containing silicon, a silicide containing titanium, cobalt, or nickel can be used as the conductor 706 or the conductive film 701A. When a metal material is used for the conductor 706 or the conductive film 701A, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used.

[0245] As the insulator 721 and the insulating film 722A, oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having insulating properties can be used. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores or resin, aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, or nitrides having silicon and hafnium, etc. can be used.

[0246] In addition, in this embodiment, an example in which four layers of the conductive film 701A and the insulating film 722A are formed respectively is shown, but the number of stacked layers is not limited to this. Depending on the required performance of the semiconductor device, five or more layers may be formed respectively. For example, the conductive film 701A and the insulating film 722A may be formed in 32 layers, 64 layers, 128 layers respectively, or 200 or more layers may be formed.

[0247] The conductive film 702A is formed on the uppermost insulating film 722A. A mask 723 is formed on the conductive film 702A (see FIGS. 17A to 17C). The conductive film 702A can be formed using the same method and the same materials as the conductive film 701A. Note that the conductive film 702A may be formed by the same method as the conductive film 701A or by a different method. Also, the conductive film 702A may be made of the same material as the conductive film 701A or a different material.

[0248] Next, the conductive film 702A, the conductive film 701A, and the insulating film 722A are processed to form stepped conductors 701B, 702B, and insulator 722B as shown in FIG. 18B. In the processing of the conductive film 702A, the conductive film 701A, and the insulating film 722A, by alternately performing etching of the conductive film 702A, the conductive film 701A, and the insulating film 722A and slimming of the mask 723, stepped conductors 701B, 702B, and insulator 722B can be formed. By processing the conductive film 702A, the conductive film 701A, and the insulating film 722A, the mask 723 is reduced in both width and thickness to become the mask 723A (see FIGS. 18A to 18C).

[0249] Next, the mask 723A is removed and the insulator 724 is formed. The insulator 724 can be formed using the CVD method. The insulator 724 is preferably planarized using the CMP method or the reflow method. A mask 725 is formed on the insulator 724. By forming the mask 725 on the planarized insulator 724, the lithography accuracy is improved (see FIGS. 19A to 19C).

[0250] Next, using the mask 725, the insulator 724, the conductor 702B, the conductor 701B, the insulator 722B, and the insulator 721 are processed. By this processing, a conductor 701 that functions as the gate of the memory transistor MT and is electrically connected to the word line and a conductor 702 that functions as the gate of the selection transistor are formed. Also, the insulator 722B becomes the insulator 722 by this processing (see FIGS. 20A to 20C).

[0251] Next, the mask 725 is removed. Next, an insulator 726 is formed so as to fill the portions of the insulator 724, the conductor 702B, the conductor 701B, the insulator 722B, and the insulator 721 that have been removed by the above processing. The insulator 726 can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Alternatively, the insulator 726 may be formed by combining the ALD method and the CVD method. The insulator 726 is preferably planarized using a CMP method or a reflow method. When performing planarization using the CMP method, the insulator 726 may be polished until the surface of the insulator 724 is exposed. Also, the insulator 724 and the insulator 726 may be polished together. In this case, the film thickness of the insulator 724 becomes thinner.

[0252] Next, the insulator 724 is processed using a lithography method to form a first opening so as to expose the conductor 701 and the conductor 702. The first opening is formed for each of the conductors 701 formed in a stepped shape (see FIGS. 21A to 21C).

[0253] Next, a conductor 707 electrically connected to the conductor 701 and a conductor 709 electrically connected to the conductor 702 are formed so as to be embedded in the first opening (see FIGS. 22A to 22C). The conductor 707 and the conductor 709 can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Alternatively, the conductor 707 and the conductor 709 may be formed by combining the ALD method and the CVD method. Also, the conductor 707 and the conductor 709 may have a laminated structure composed of a plurality of layers. The conductor 707 and the conductor 709 can be formed by forming a conductive film that becomes the conductor 707 and the conductor 709 on the insulator 724 and inside the first opening, and removing the unnecessary conductive film using CMP or the like.

[0254] Next, a mask 729 is formed on the insulator 724 and the insulator 726, and the insulator 724, the conductor 702, the conductor 701, the insulator 722, and the insulator 721 are processed using a lithography method to form a second opening so as to expose the conductor 706 (see FIGS. 23A to 23C).

[0255] Next, isotropic etching is performed on the insulator 721, the insulator 722, and the insulator 724 to expand the diameters of the openings of the insulator 721, the insulator 722, and the insulator 724 (see FIGS. 24A to 24C). By this process, the diameter of the opening of the insulator becomes larger than the diameters of the openings of the conductor 701 and the conductor 702. Also, it can be said that the insulator has a concave portion with respect to the side surface of the conductor (the conductor 701 or the conductor 702) located at the upper or lower part. For such processing, isotropic etching by dry etching using a gas, radical, plasma, etc., or isotropic etching by wet etching using a liquid can be used. The liquid used for wet etching is sometimes called an etchant. When performing isotropic etching using dry etching, a gas, radical, plasma, etc. containing at least one of chlorine, bromine, and fluorine can be used. It is preferable to perform isotropic etching without removing the mask 729.

[0256] Next, an insulating film 703A that becomes the insulator 703 is formed on the insulator 724, the conductor 707, the conductor 709, and the mask 729, and inside the second opening (see FIGS. 25A to 25C). Although not shown, the insulating film 703A may be formed by sequentially laminating an insulating film that becomes the insulator 703a, an insulating film that becomes the insulator 703b, and an insulating film that becomes the insulator 703c. The insulating film 703A can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Alternatively, the insulating film 703A may be formed by combining the ALD method and the CVD method. The insulating film that becomes the insulator 703a, the insulating film that becomes the insulator 703b, and the insulating film that becomes the insulator 703c may be formed by the same film-forming apparatus or different film-forming apparatuses. Note that the insulating film that becomes the insulator 703c is preferably formed thinner than the insulating film that becomes the insulator 703a so that the insulator 703c is thinner than the insulator 703a.

[0257] The insulating film 703A formed by the above method has good coverage, and the insulating film 703A can be formed even for the recesses of the insulator 721, the insulator 722, and the insulator 724. That is, the insulating film 703A can be formed so as to be in contact with not only the side surfaces of the insulator 721, the insulator 722, and the insulator 724, but also the side surfaces of the conductor 701 and the conductor 702, and a part of the upper surface and a part of the lower surface of the conductor 701 and the conductor 702.

[0258] Next, the insulating film 703A formed at the bottom of the second opening is removed to obtain the insulator 703. It is preferable to use anisotropic etching to remove the insulating film 703A. At this time, since the insulating film 703A on the mask 729 is also removed, the insulator 703 is provided only on the sidewall of the second opening (see FIGS. 26A to 26D). By removing the insulating film 703A at the bottom of the second opening, the conductor 706 is exposed again.

[0259] Here, as shown in FIG. 26D, the insulator 703b and the insulator 703c of the insulator 703 located at the upper part of the second opening may be removed. FIG. 26D is an enlarged view of the portion surrounded by the dashed-dotted line in FIG. 26B. First, a material 727 (also called a sacrificial layer) that can be easily removed in a later process is formed so as to fill the inside of the second opening, and is removed by etching or the like to a desired depth inside the second opening. By sequentially removing the insulator 703c and the insulator 703b exposed by the etching, the insulator 703 located in the horizontal direction (x-y direction) of the conductor 702 can be made only the insulator 703a. In this case, the gate insulating films of the selection transistors SST and SDT are composed of the insulator 703a. After removing the insulator 703c and the insulator 703b, the material 727 is removed.

[0260] Next, an oxide film 704A that becomes the oxide 704 is formed inside the second opening. The oxide film 704A can be formed by sequentially forming an oxide film that becomes the oxide 704a, an oxide film that becomes the oxide 704b, and an oxide film that becomes the oxide 704c on the insulator 724, the conductor 707, the conductor 709, the insulator 703, and the mask 729, and inside the second opening. A part of the oxide 704 is formed so as to be in contact with the conductor 706.

[0261] The oxide film that becomes the oxide 704a, the oxide film that becomes the oxide 704b, and the oxide film that becomes the oxide 704c can be formed using the CVD method or the ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Alternatively, the ALD method and the CVD method may be combined to form the oxide film. Also, different film formation methods and film formation apparatuses may be used for each oxide film.

[0262] Next, a conductive film 719A is formed inside the second opening (see FIGS. 27A to 27C). The conductive film 719A only needs to be formed so as to fill the recesses of the insulator 721, the insulator 722, and the insulator 724 via at least the insulator 703 and the oxide film 704A, and it is not necessarily required to fill the entire inside of the second opening. The conductive film 719A can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Alternatively, the conductive film 719A may be formed by combining the ALD method and the CVD method.

[0263] Next, the conductive film 719A is processed to form a conductor 719 (see FIGS. 28A to 28C). Isotropic etching or anisotropic etching can be used for processing the conductive film 719A. In the formation of the conductive film 719A, as shown in FIGS. 27A to 27C, when the conductive film 719A fills the recess and the opening is not completely filled, it is preferable to use isotropic etching for processing the conductive film 719A. On the other hand, when the conductive film 719A is formed so as to fill the recess and the opening, it is preferable to use anisotropic etching. By the above-described processing, the conductor 719 can be formed inside the recess.

[0264] Next, using the conductor 719 as a mask, a part of the oxide film 704A is made to have a high resistance to form a high-resistance region (type I region). As a method for forming the high-resistance region, the oxide film 704A may be irradiated with microwaves 744 to remove hydrogen contained in the oxide 704. Further, it is preferable to perform the irradiation of the microwaves 744 in an atmosphere containing oxygen because oxygen is supplied to the oxide film 704A. In the present embodiment, the region 734 of the oxide film 704A is made to have a high resistance in an atmosphere containing oxygen and argon (see FIGS. 29A to 29D).

[0265] Here, heat treatment may be performed. The heat treatment is carried out in an atmosphere containing nitrogen, preferably at 200°C or higher and 500°C or lower, more preferably at 300°C or higher and 400°C or lower. The atmosphere for performing the heat treatment is not limited to the above, and it may be carried out in an atmosphere containing at least one of nitrogen, oxygen, and argon. Further, the heat treatment may be carried out in a reduced-pressure atmosphere or in an atmospheric-pressure atmosphere. On the other hand, the above microwave treatment, that is, microwave annealing, may also serve as the heat treatment. When the oxide 704 and the like are sufficiently heated by microwave annealing, the heat treatment may not be performed.

[0266] By the heat treatment, the oxide film 704A in contact with the conductor 719 can be made to have a lower resistance, and a low-resistance region (N-type region) can be formed in the region 731. By performing the heat treatment in a state where the oxide film 704A and the conductor 719 are in contact, a metal compound layer containing the metal element of the conductor 719 and the components of the oxide film 704A may be formed at the interface between the conductor 719 and the oxide film 704A. The formation of the metal compound layer is preferable because the resistance of the oxide film 704A is reduced in the region in contact with the conductor 719. Further, the conductor 719 may absorb the oxygen contained in the oxide film 704A. By performing the heat treatment in a state where the oxide film 704A and the conductor 719 are in contact, the oxide film 704A has a lower resistance. The heat treatment may be performed before the microwave treatment. Since the region 731 with a reduced resistance by the heat treatment is covered by the conductor 719, it is not affected by the microwave 744 and can maintain a low resistance value even after the microwave treatment.

[0267] Also, by performing heat treatment with the oxide film 704A in contact with the conductor 706, the oxide film 704A may have a reduced resistance. By performing heat treatment with the oxide film 704A in contact with the conductor 706, a metal compound layer containing the metal elements of the conductor 706 and the components of the oxide film 704A may be formed at the interface between the conductor 706 and the oxide film 704A. The formation of the metal compound layer is preferable because it reduces the contact resistance between the conductor 706 and the oxide film 704A. Also, the conductor 706 may absorb the oxygen contained in the oxide film 704A. At this time, it is preferable because the resistance of the oxide film 704A near the interface between the conductor 706 and the oxide film 704A is reduced, and the contact resistance between the conductor 706 and the oxide film 704A is reduced. By performing heat treatment with the oxide film 704A in contact with the conductor 706, the oxide film 704A has a lower resistance, and the contact resistance between the conductor 706 and the oxide film 704A is further reduced.

[0268] The carrier concentration of the region 734 after the microwave treatment and the heat treatment is 1×10 18 / cm 3 less than, preferably, 1×10 17 / cm 3 or less, more preferably, 1×10 16 / cm 3 or less. Also, the carrier concentration of the region 731 is 1×10 18 / cm 3 or more, preferably, 1×10 19 / cm 3 or more, more preferably, 1×10 20 / cm 3 or more.

[0269] Next, an insulating film 711A is formed inside the oxide film 704A and the conductor 719, and a conductive film 712A is formed inside the insulating film 711A. The insulating film 711A and the conductive film 712A can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Alternatively, they may be formed by combining the ALD method and the CVD method (see FIGS. 30A to 30C).

[0270] The insulator 711 can use a material that supplies oxygen to the oxide 704 or a material that supplies hydrogen, according to the characteristics required for the memory transistor MT and the semiconductor device having the memory transistor MT.

[0271] Next, a heat treatment is performed. The heat treatment is preferably performed at 200°C or higher and 500°C or lower, more preferably 300°C or higher and 400°C or lower, in an atmosphere containing nitrogen. The atmosphere for performing the heat treatment is not limited to the above, and may be an atmosphere containing at least one of nitrogen, oxygen, and argon. Also, the heat treatment may be performed in a reduced-pressure atmosphere or in an atmospheric-pressure atmosphere.

[0272] Next, the conductive film 712A, the insulating film 711A, the oxide film 704A, the insulator 703, etc. above the mask 729 and the portions indicated by dotted lines in FIGS. 30B and 30C are removed using a CMP method or the like to obtain the oxide 704, the insulator 711, and the conductor 712 (see FIGS. 31A to 31C). Note that the above-described heat treatment may be performed after removing the unnecessary conductive film 712A, insulating film 711A, and oxide film 704A. Also, if the mask 729 has been removed after the formation of the first opening and before the formation of the insulating film 703A, there is no need to remove the mask 729 in this step.

[0273] Next, as shown in FIGS. 32A to 32C, a conductor 705 that functions as part of a bit line BL or a source line SL, a conductor 708 that functions as part of a word line WL, and a conductor 710 that functions as part of a wiring DGL or a wiring SGL are formed. The conductor 705 is provided so as to be electrically connected to the oxide 704. Also, the conductor 708 is provided so as to be electrically connected to the conductor 707. Also, the conductor 710 is provided so as to be electrically connected to the conductor 709. Further, when a conductor 712 is provided inside the oxide 704, it is preferable to provide an opening in the conductor 705 that exposes at least the conductor 712 and electrically isolate the conductor 705 from the conductor 712. At this time, the opening may be provided so that the insulator 711 is exposed. Also, a part of the oxide 704 may be exposed.

[0274] Next, as shown in FIGS. 33A to 33C, an insulator 717 is formed so as to cover the conductor 705, the conductor 708, and the conductor 710. The insulator 717 is provided with an opening that exposes a part of the conductor 705 (the conductor 705 that is electrically connected to the oxide 704 on the bit line side) and the conductor 712. When forming the opening that exposes the conductor 712, the diameter of the opening may be larger than the diameter of the opening provided in the conductor 705. Since the opening is provided in the conductor 705, the opening that exposes the conductor 712 is formed self-alignedly, and it is possible to suppress problems such as the diameter of the bottom of the opening being formed to an unintended size or the opening being displaced from the conductor 712, which is preferable.

[0275] Next, as shown in FIGS. 34A to 34C, an insulator 713 is formed on the side surface of the opening provided in the insulator 717 that exposes the conductor 712. An insulating film that becomes the insulator 713 is formed on the insulator 717 using a CVD method or an ALD method, and anisotropic etching is performed to remove the insulating film formed at the bottom of the opening. At this time, the insulating film on the insulator 717 is also removed, and the insulator 713 is formed. Also, the insulating film may be processed using a lithography method. At this time, the formed insulator 713 may also exist on the insulator 717.

[0276] Next, a conductor 714 and a conductor 715 that function as bit lines BL and wiring BG are formed. In FIGS. 34A to 34C, the conductor 714 and the conductor 715 are illustrated as different layers, but the present invention is not limited thereto. The conductor 714 and the conductor 715 may be formed together as one conductor. When the conductor 714 and the conductor 715 are formed separately, a conductive film that becomes the conductor 714 is formed on the insulator 717 and fills an opening formed in the insulator 717, and the unnecessary conductive film is removed using a CMP method or the like to form the conductor 714. Thereafter, the conductor 715 may be formed. For forming the conductor 715, a lithography method or a damascene method may be used. At this time, since the insulator 713 is provided on the side surfaces of the insulator 717 and the opening formed in the conductor 705, the conductor 715 that is electrically connected to the conductor 712 is not electrically connected to the conductor 705. When the conductor 714 and the conductor 715 are formed together, a conductive film is formed on the insulator 717 and fills an opening formed in the insulator 717, and processed using a lithography method to form conductors that become the conductor 714 and the conductor 715.

[0277] Through the above steps, a memory cell array can be fabricated. In the description of this fabrication process, the memory cell array includes four-layer memory transistors MT and four memory strings, but is not limited thereto. It may include five or more layers of memory transistors MT or five or more memory strings. For example, a memory cell array having 32-layer, 64-layer, or 128-layer memory transistors MT can be fabricated. Also, a memory cell array having 200 or more layers of memory transistors MT can be fabricated.

[0278] By fabricating the memory cell array as described above, it is possible to fabricate a plurality of layers of memory transistors MT in one batch without performing patterning for fabricating the memory transistors MT for each layer. Further, when fabricating the memory cell array by the above method, even if the number of layers of the memory transistors MT is increased, the number of steps for patterning and etching the memory transistors MT does not increase. Thus, since the process for fabricating the memory cell array can be shortened, a highly productive semiconductor device can be provided.

[0279] (Method for fabricating a memory cell array 2) Next, a method for fabricating a memory cell array different from the above method will be described with reference to FIGS. 35A to 50C. In each of FIGS. 35A to 50C, A is a top view seen from the z-axis direction, B is a cross-sectional view of the part indicated by the one-dot chain line A1-A2 in A, and C is a cross-sectional view of the part indicated by the one-dot chain line A3-A4 in A. Also, the same components as those shown in the manufacturing method 1 of the memory cell, the manufacturing method 2 of the memory cell, and the manufacturing method 1 of the memory cell array are denoted by the same reference numerals, and the description thereof and the description of the manufacturing method may be omitted.

[0280] Similar to the method shown in the manufacturing method 1 of the memory cell array, a conductor 706 and an insulator 721 are formed on the substrate 720 (see FIGS. 35A to 35C).

[0281] Next, a layer 716 and an insulating film 722A are alternately formed on the conductor 706 and the insulator 721 to form a laminate. In the present embodiment, an example is shown in which the layer 716 is formed on the insulator 721 and the insulating film 722A is formed on the layer 716, but the order of formation is not limited to this. The insulating film 722A may be formed on the insulator 721 and the layer 716 may be formed on the insulating film 722A. For the formation of the layer 716 and the insulating film 722A, a CVD method can be used. Also, a sputtering method may be used.

[0282] In addition, the number of stacked layers of the layer 716 and the insulating film 722A may be determined according to the required performance of the semiconductor device. For example, the layer 716 and the insulating film 722A may be formed in 32 layers, 64 layers, 128 layers respectively, or may be formed in 200 layers or more.

[0283] In addition, the top layer of the layer 716 and the top layer of the insulating film 722A function as a hard mask in a subsequent process. A mask 801 is formed on the top layer of the layer 716 (see FIGS. 35A to 35C).

[0284] Next, using the mask 801, a laminate including the layer 716 and the insulating film 722A is processed to form a first opening (see FIGS. 36A to 36C). By this processing, a part of the conductor 706 is exposed at the bottom of the first opening.

[0285] Next, a layer 740 is formed on the top layer of the layer 716 so as to fill the first opening (see FIGS. 37A to 37C).

[0286] Next, a laminate including the layer 740, the layer 716, and the insulating film 722A is processed to form a second opening (see FIGS. 38A to 38C). The second opening has a slit shape, and a plurality of second openings are formed so as to sandwich the first opening therebetween. In the present embodiment, as shown in FIG. 38A, the second opening is formed such that its major axis extends in the x-axis direction. Also, as shown in FIG. 38C, the first opening and the second opening are alternately arranged in the y-axis direction. By this processing, a part of the substrate 720 is exposed at the bottom of the second opening.

[0287] Next, the layer 716 is etched and removed (see FIGS. 39A to 39C). It is preferable to use isotropic etching such as wet etching, plasma etching, or gas etching for etching the layer 716. An etchant is introduced from the second opening to remove the layer 716. By this etching, the side surface of the layer 740 that was in contact with the layer 716 is exposed.

[0288] Next, a conductor 810A is formed on the layer 740 and the substrate 720 so as to fill the inside of the second opening and the region where the layer 716 has been removed (see FIGS. 40A to 40C). The conductor 810A can be made of a material that can be used for the conductive film 701A shown in the manufacturing method 1 of the memory cell array. For forming the conductor 810A, an ALD method or a CVD method can be used.

[0289] Next, a part of the conductor 810A is removed so that the surface of the layer 740 is exposed (see FIGS. 41A to 41C). The conductor 810A is preferably removed by polishing. For polishing, a CMP method or the like can be used.

[0290] Next, using the layer 740 as a mask, a process is performed to remove a part of the conductor 810A to form a conductor 810B, a conductor 812A, and a conductor 803 (see FIGS. 42A to 42C). In this process, at least the conductor 810A inside the second opening is removed. It is preferable to use anisotropic etching to remove the conductor 810A. It is preferable to self-aligningly process the conductor 810A using the layer 740 as a mask. By this process, the second opening is formed again. Also, by this process, the conductors 810B, 812A, and 803 that are electrically separated from each other are formed. The conductor 810B is used as the gate of the memory transistor MT after subsequent processes. The conductor 812A is used as the gate of the selection transistor after subsequent processes. The conductor 803 is used as a hard mask in subsequent processes.

[0291] Next, an insulator 742 is formed on the layer 740 and the substrate 720 so as to fill the second opening (see FIGS. 43A to 43C).

[0292] Next, a part of the insulator 742 and the layer 740 is removed so that the surface of the conductor 803 is exposed (see FIGS. 44A to 44C). The insulator 742 and the layer 740 are preferably removed by polishing. For polishing, a CMP method or the like can be used.

[0293] Next, using the conductor 803 and the insulator 742 as masks, the layer 740 is removed (see FIGS. 45A to 45C). It is preferable to use anisotropic etching for removing the layer 740. By the anisotropic etching, the first opening is formed again. Further, isotropic etching is performed on the insulating film 722A to expand its opening diameter and form the insulator 722B. Here, it can be said that the insulator 722B has recesses with respect to the side surfaces of the conductor 810B sandwiched therebetween vertically. The processing of the insulating film 722A may be performed in the same step as the anisotropic etching of the layer 740. For example, it may be performed during the over-etching of the anisotropic etching of the layer 740. Or, after removing the layer 740, isotropic etching may be performed to process the insulating film 722A.

[0294] Next, the insulator 703, the oxide film 704A, the conductor 719, the insulating film 711A, and the conductive film 712A are formed (see FIGS. 46A to 46C). Further, after forming the conductor 719 and before forming the insulating film 711A, microwave treatment is performed on the region 734 of the oxide film 704A to form a high-resistance region. Also, a region 731 that becomes a low-resistance region is formed in the oxide film 704A in contact with the conductor 719. For forming the low-resistance region, it is preferable to perform heat treatment as appropriate. On the other hand, the above-mentioned microwave treatment, that is, microwave annealing may also serve as the heat treatment. When the oxide 704 and the like are sufficiently heated by the microwave annealing, the heat treatment may not be performed. These steps can be implemented in the same manner as the method shown in the manufacturing method 1 of the memory cell array.

[0295] Next, the conductor 803, and the upper portions of the conductive film 712A, the insulating film 711A, the oxide film 704A, the insulator 703, etc. indicated by the dotted lines in FIGS. 46B and 46C are removed using the CMP method or the like to obtain the oxide 704, the insulator 711, and the conductor 712 (see FIGS. 47A to 47C). Note that the above-mentioned heat treatment may be performed after removing the unnecessary conductive film 712A, insulating film 711A, and oxide film 704A.

[0296] Next, a mask 805 is formed over the insulator 703, the oxide 704, the insulator 711, the conductor 712, the conductor 719, and the insulator 722B (see FIGS. 47A to 47C).

[0297] Next, the conductor 812A, the conductor 810B, the insulator 722B, and the insulator 742 are processed to form the stepped conductors 810, 812, and the insulator 722 as shown in FIG. 48B. In processing the conductor 812A, the conductor 810B, the insulator 722B, and the insulator 742, by alternately performing etching of the conductor 812A, the conductor 810B, the insulator 722B, and the insulator 742 and slimming of the mask 805, the stepped conductors 810, 812, and the insulator 722 can be formed. By processing the conductor 812A, the conductor 810B, the insulator 722B, and the insulator 742, the mask 805 is reduced in both width and thickness and becomes the mask 805A (see FIGS. 48A to 48C).

[0298] Next, the mask 805A is removed, and an insulator 807 is formed so as to cover the conductors 810, 812, and the insulator 722, etc. (see FIGS. 49A to 49C). The insulator 807 can be made of a material that can be used for the insulator 721 or the insulating film 722A. Also, for forming the insulator 807, a CVD method or an ALD method can be used. An opening reaching the conductor 810 is formed in the insulator 807. Also, openings reaching the conductor 812 are formed in the insulator 722 and the insulator 807.

[0299] Next, conductors 707 that are electrically connected to conductor 810 and conductors 709 that are electrically connected to conductor 812 are formed in the openings formed in insulator 722 and insulator 807 (see FIGS. 50A to 50C). A conductor is formed on insulator 807 so as to fill the above openings, and the conductor located above insulator 807 is polished and removed using a CMP method or the like, whereby conductors 707 and conductors 709 can be formed inside the openings. Conductors 707 and conductors 709 can use materials that can be used for conductor 810A. Also, a CVD method or an ALD method can be used to form the conductors that become conductors 707 and conductors 709.

[0300] Thereafter, using the materials and manufacturing methods shown in manufacturing method 1 of the memory cell array, a conductor 705 that functions as part of a bit line BL or a source line SL, a conductor 708 that functions as part of a word line WL, a conductor 710 that functions as part of a wiring DGL or a wiring SGL, an insulator 717, an insulator 713, a bit line BL, and a conductor 714 and a conductor 715 that function as a wiring BG are formed.

[0301] Through the above steps, a memory cell array can be manufactured. In the description of this manufacturing process, the memory cell array includes, but is not limited to, four-layer memory transistors MT and four memory strings. It may include five or more layers of memory transistors MT or five or more memory strings. For example, a memory cell array having 32 layers, 64 layers, or 128 layers of memory transistors MT can be manufactured. Also, a memory cell array having 200 or more layers of memory transistors MT can be manufactured.

[0302] By fabricating the memory cell array as described above, it is possible to fabricate a plurality of layers of memory transistors MT all at once without performing patterning for fabricating the memory transistors MT for each layer. Further, when fabricating the memory cell array by the above method, even if the number of layers of the memory transistors MT is increased, the number of steps of the patterning and etching processes of the memory transistors MT does not increase. Thus, since the process of fabricating the memory cell array can be shortened, a highly productive semiconductor device can be provided.

[0303] <Microwave processing apparatus> Hereinafter, a microwave processing apparatus that can be used in the method for fabricating the semiconductor device will be described.

[0304] First, the configuration of a manufacturing apparatus with less impurity contamination during the manufacture of a semiconductor device or the like will be described with reference to FIGS. 51, 52, and 53.

[0305] FIG. 51 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric-side substrate supply chamber 2701 having a cassette port 2761 for accommodating a substrate and an alignment port 2762 for aligning the substrate, an atmospheric-side substrate transfer chamber 2702 for transferring the substrate from the atmospheric-side substrate supply chamber 2701, a load lock chamber 2703a for loading the substrate and switching the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading the substrate and switching the pressure in the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring the substrate in a vacuum, and chambers 2706a, 2706b, 2706c, and 2706d.

[0306] In addition, the atmospheric-side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b. The load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the chambers 2706a, 2706b, 2706c, and 2706d.

[0307] Note that gate valves GV are provided at the connection parts of each chamber, and except for the atmospheric-side substrate supply chamber 2701 and the atmospheric-side substrate transfer chamber 2702, each chamber can be independently maintained in a vacuum state. Further, a transfer robot 2763a is provided in the atmospheric-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robot 2763a and the transfer robot 2763b.

[0308] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, and more preferably 1×10 -5 Pa or less. Also, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, and more preferably 3×10 -6 Pa or less. Also, the partial pressure of gas molecules (atoms) with an m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, and more preferably 3×10 -6 Pa or less. Also, the partial pressure of gas molecules (atoms) with an m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, and more preferably 3×10 -6 Pa or less.

[0309] Incidentally, the total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also referred to as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.

[0310] In addition, it is desirable that the transfer chamber 2704 and each chamber have a configuration with little external leakage or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. Also, for example, the leak rate of gas molecules (atoms) with m / z = 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. Also, for example, the leak rate of gas molecules (atoms) with m / z = 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. Also, for example, the leak rate of gas molecules (atoms) with m / z = 44 is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0311] Incidentally, regarding the leak rate, it may be derived from the total pressure and partial pressure measured using the aforementioned mass spectrometer. The leak rate depends on external leakage and internal leakage. External leakage is the inflow of gas from outside the vacuum system due to minute holes, seal failures, etc. Internal leakage is caused by leakage from partitions such as valves within the vacuum system and the release gas from internal members. In order to make the leak rate equal to or less than the above-mentioned numerical values, it is necessary to take measures against both external leakage and internal leakage.

[0312] For example, the transfer chamber 2704 and the opening / closing parts of each chamber may be sealed with a metal gasket. It is preferable to use a metal gasket made of a metal coated with iron fluoride, aluminum oxide, or chromium oxide. The metal gasket has higher adhesion compared to an O-ring and can reduce external leakage. Also, by using the passivation of a metal coated with iron fluoride, aluminum oxide, chromium oxide, etc., the emission gas containing impurities emitted from the metal gasket can be suppressed, and internal leakage can be reduced.

[0313] Also, as a member constituting the manufacturing apparatus 2700, use aluminum, chromium, titanium, zirconium, nickel, or vanadium that emits less emission gas containing impurities. Further, the aforementioned member may be used after being coated with an alloy containing iron, chromium, nickel, etc. Alloys containing iron, chromium, nickel, etc. are rigid, heat-resistant, and suitable for processing. Here, if the surface unevenness of the member is reduced by polishing or the like in order to reduce the surface area, the emission gas can be reduced.

[0314] Alternatively, the members of the aforementioned manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, etc.

[0315] The members of the manufacturing apparatus 2700 are preferably composed of only metal as much as possible. For example, even when installing a viewing window composed of quartz or the like, the surface may be thinly coated with iron fluoride, aluminum oxide, chromium oxide, etc. to suppress the emission gas.

[0316] The adsorbed substances present in the transfer chamber 2704 and each chamber do not affect the pressure in the transfer chamber 2704 and each chamber because they are adsorbed on the inner wall or the like, but they cause gas release when the transfer chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with a high evacuation capacity to desorb the adsorbed substances present in the transfer chamber 2704 and each chamber as much as possible and evacuate them in advance. In addition, in order to promote the desorption of the adsorbed substances, the transfer chamber 2704 and each chamber may be baked. By baking, the desorption rate of the adsorbed substances can be increased by about 10 times. Baking may be performed at 100 °C or higher and 450 °C or lower. At this time, if the adsorbed substances are removed while introducing an inert gas into the transfer chamber 2704 and each chamber, the desorption rate of water or the like that is difficult to desorb by simply evacuating can be further increased. In addition, by heating the introduced inert gas to about the same temperature as the baking temperature, the desorption rate of the adsorbed substances can be further increased. Here, it is preferable to use a noble gas as the inert gas.

[0317] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as heated noble gas or oxygen, etc., and then perform a process of evacuating the transfer chamber 2704 and each chamber again after a certain period of time. By introducing the heated gas, the adsorbed substances in the transfer chamber 2704 and each chamber can be desorbed, and the impurities present in the transfer chamber 2704 and each chamber can be reduced. In addition, this process is effectively repeated in the range of 2 to 30 times, preferably 5 to 15 times. Specifically, by introducing an inert gas or oxygen etc. whose temperature is 40 °C or higher and 400 °C or lower, preferably 50 °C or higher and 200 °C or lower, the pressure in the transfer chamber 2704 and each chamber is set to 0.1 Pa or higher and 10 kPa or lower, preferably 1 Pa or higher and 1 kPa or lower, more preferably 5 Pa or higher and 100 Pa or lower, and the period for maintaining the pressure is set to 1 minute or longer and 300 minutes or shorter, preferably 5 minutes or longer and 120 minutes or shorter. Then, the transfer chamber 2704 and each chamber are evacuated for a period of 5 minutes or longer and 300 minutes or shorter, preferably 10 minutes or longer and 120 minutes or shorter.

[0318] Next, the chambers 2706b and 2706c will be described with reference to the schematic cross-sectional view shown in FIG. 52.

[0319] The chambers 2706b and 2706c are chambers capable of performing microwave treatment on an object to be processed, for example. Note that the chambers 2706b and 2706c differ only in the atmosphere during microwave treatment. Since the other configurations are common, they will be described together below.

[0320] The chambers 2706b and 2706c include a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. In addition, outside the chambers 2706b and 2706c, etc., there are provided a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0321] The high-frequency generator 2803 is connected to the mode converter 2805 via the waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is disposed in contact with the dielectric plate 2809. Also, the gas supply source 2801 is connected to the mode converter 2805 via the valve 2802. Then, gas is sent into the chambers 2706b and 2706c by the mode converter 2805, the waveguide 2807, and the gas pipe 2806 passing through the dielectric plate 2809. Further, the vacuum pump 2817 has a function of exhausting gas and the like from the chambers 2706b and 2706c via the valve 2818 and the exhaust port 2819. Also, the high-frequency power supply 2816 is connected to the substrate holder 2812 via the matching box 2815.

[0322] The substrate holder 2812 has the function of holding the substrate 2811. For example, it has the function of electrostatically or mechanically chucking the substrate 2811. It also has the function as an electrode to which power is supplied from the high-frequency power supply 2816. Further, it has a heating mechanism 2813 inside and has the function of heating the substrate 2811.

[0323] As the vacuum pump 2817, for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used. Further, in addition to the vacuum pump 2817, a cryotrap may be used. It is particularly preferable to use a cryopump and a cryotrap because water can be efficiently exhausted.

[0324] As the heating mechanism 2813, for example, a heating mechanism that heats using a resistance heating element or the like may be used. Alternatively, it may be a heating mechanism that heats by heat conduction or heat radiation from a medium such as heated gas. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs a heat treatment using high-temperature gas. As the gas, an inert gas is used.

[0325] The gas supply source 2801 may be connected to the purifier via a mass flow controller. It is preferable to use a gas having a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and noble gas (such as argon gas) may be used.

[0326] As the dielectric plate 2809, for example, silicon oxide (quartz), aluminum oxide (alumina), yttrium oxide (yttria), etc. may be used. Further, another protective layer may be formed on the surface of the dielectric plate 2809. As the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, yttrium oxide, etc. may be used. Since the dielectric plate 2809 is to be exposed to the particularly high-density region of the high-density plasma 2810 described later, damage can be mitigated by providing a protective layer. As a result, an increase in particles during processing can be suppressed.

[0327] The high-frequency generator 2803 has a function of generating microwaves, for example, in the range of 0.3 GHz or more and 6.0 GHz or less. For example, microwaves in the range of 0.7 GHz or more and 1.1 GHz or less, or 2.2 GHz or more and 2.8 GHz or less, or 5.0 GHz or more and 6.0 GHz or less can be generated. The microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as the TE mode are converted to the TEM mode. Then, the microwaves are transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with a plurality of slot holes, and the microwaves pass through the slot holes and the dielectric plate 2809. Then, an electric field can be generated below the dielectric plate 2809 to generate the high-density plasma 2810. In the high-density plasma 2810, ions and radicals corresponding to the gas species supplied from the gas supply source 2801 are present. For example, oxygen radicals, etc. are present.

[0328] At this time, the substrate 2811 can be modified, such as the film on the substrate 2811, by ions and radicals generated by the high-density plasma 2810. In addition, it may be preferable to apply a bias to the substrate 2811 side using the high-frequency power supply 2816. For the high-frequency power supply 2816, for example, an RF (Radio Frequency) power supply with a frequency such as 13.56 MHz or 27.12 MHz may be used. By applying a bias to the substrate side, ions in the high-density plasma 2810 can efficiently reach the depth of the openings of the film on the substrate 2811 and the like.

[0329] For example, in the chamber 2706b or the chamber 2706c, oxygen radical treatment using the high-density plasma 2810 can be performed by introducing oxygen from the gas supply source 2801.

[0330] Next, the chambers 2706a and 2706d will be described using the cross-sectional schematic diagrams shown in FIG. 53.

[0331] The chambers 2706a and 2706d are, for example, chambers capable of irradiating an object to be processed with electromagnetic waves. Note that the chambers 2706a and 2706d differ only in the type of electromagnetic waves. Since there are many common parts in other configurations, the following will be described together.

[0332] The chambers 2706a and 2706d include one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. In addition, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the chambers 2706a and 2706d.

[0333] The gas supply source 2821 is connected to the gas inlet 2823 via the valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 via the valve 2829. The lamp 2820 is arranged facing the substrate holder 2825. The substrate holder 2825 has the function of holding the substrate 2824. Further, the substrate holder 2825 has a heating mechanism 2826 inside and has the function of heating the substrate 2824.

[0334] As the lamp 2820, for example, a light source having a function of emitting electromagnetic waves such as visible light or ultraviolet light may be used. For example, a light source having a function of emitting electromagnetic waves having a peak at a wavelength of 10 nm or more and 2500 nm or less, 500 nm or more and 2000 nm or less, or 40 nm or more and 340 nm or less may be used.

[0335] For example, as the lamp 2820, a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp or a high-pressure mercury lamp may be used.

[0336] For example, part or all of the electromagnetic waves radiated from the lamp 2820 can be absorbed by the substrate 2824 to modify a film or the like on the substrate 2824. For example, generation or reduction of defects, or removal of impurities can be performed. Note that when the substrate 2824 is heated, generation or reduction of defects, or removal of impurities can be efficiently performed.

[0337] Alternatively, for example, the electromagnetic waves radiated from the lamp 2820 may heat the substrate holder 2825 to heat the substrate 2824. In that case, the heating mechanism 2826 does not have to be provided inside the substrate holder 2825.

[0338] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. Also, for the heating mechanism 2826, refer to the description of the heating mechanism 2813. Also, for the gas supply source 2821, refer to the description of the gas supply source 2801.

[0339] The microwave processing apparatus that can be used in this embodiment is not limited to the above. The microwave processing apparatus 2900 shown in FIG. 54 can be used. The microwave processing apparatus 2900 includes a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas tube 2806, a vacuum pump 2817, and a valve 2818. Further, the microwave processing apparatus 2900 has a substrate holder 2902 that holds a plurality of substrates 2811 (substrates 2811_1 to 2811_n, where n is an integer of 2 or more) inside the quartz tube 2901. Further, the microwave processing apparatus 2900 may have heating means 2903 outside the quartz tube 2901.

[0340] The microwave generated by the high-frequency generator 2803 is irradiated onto the substrate provided in the quartz tube 2901 through the waveguide 2804. The vacuum pump 2817 is connected to the exhaust port 2819 via the valve 2818, and can adjust the pressure inside the quartz tube 2901. Further, the gas supply source 2801 is connected to the gas tube 2806 via the valve 2802, and can introduce a desired gas into the quartz tube 2901. Further, the substrate 2811 inside the quartz tube 2901 can be heated to a desired temperature by the heating means 2903. Alternatively, the gas supplied from the gas supply source 2801 may be heated by the heating means 2903. With the microwave processing apparatus 2900, heat treatment and microwave treatment can be performed on the substrate 2811 simultaneously. Further, microwave treatment can be performed after heating the substrate 2811. Further, heat treatment can be performed after performing microwave treatment on the substrate 2811.

[0341] The substrates 2811_1 to 2811_n may all be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, substrates 2811_1 and 2811_n may be dummy substrates, and substrates 2811_2 to 2811_n-1 may be processing substrates. Also, substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and substrates 2811_3 to 2811_n-2 may be processing substrates. Using dummy substrates is preferable because when performing microwave processing or heat treatment, a plurality of processing substrates are uniformly processed, and variations between the processing substrates can be reduced. For example, it is preferable to arrange a dummy substrate on the processing substrate closest to the high-frequency generator 2803 and the waveguide 2804, because this can prevent the processing substrate from being directly exposed to microwaves.

[0342] By using the above manufacturing apparatus, it is possible to suppress the contamination of impurities into the object to be processed and to perform film modification and the like.

[0343] (Configuration example of 3D NAND) FIG. 55A shows a configuration example of a three-dimensional structure NAND type nonvolatile memory device (3D NAND). The memory device 100 shown in FIG. 55A includes a control circuit 105, a memory cell array 110, and peripheral circuits.

[0344] The control circuit 105 comprehensively controls the entire memory device 100 and performs data writing and data reading. The control circuit 105 processes external command signals and generates control signals for the peripheral circuits. As the peripheral circuits, a row decoder 121, a row driver 122, a sense amplifier 123, a source line driver 124, and an input / output circuit 125 are provided.

[0345] The memory cell array 110 has a plurality of memory strings 112. FIG. 55B shows a circuit configuration example of the memory string 112. In the memory string 112, a selection transistor SST, memory transistors MT1 to MT2k (k is an integer of 1 or more), and a selection transistor SDT are electrically connected in series between the bit line BL and the source line SL.

[0346] When the memory transistors MT1 to MT2k are not distinguished, they are referred to as memory transistor MT. The same applies to other elements. For example, when the word lines WL1 to WL2k are not distinguished, they are referred to as word line WL.

[0347] The selection transistors SST, SDT, and the memory transistors MT1 to MT2k are each a transistor having a channel formed of a metal oxide as described above. The memory transistor MT includes a charge storage layer and constitutes a nonvolatile memory cell.

[0348] The gates of the selection transistors SST and SDT are electrically connected to wirings SGL and DGL that function as selection gate lines, respectively. The gates of the memory transistors MT1 to MT2k are electrically connected to the word lines WL1 to WL2k, respectively. The bit line BL extends in the column direction, and the wirings SGL, DGL, and the word lines WL extend in the row direction.

[0349] Further, as shown in FIG. 55B, the selection transistors SST, SDT, and the memory transistor MT may each have a second gate. The second gate is electrically connected to the wiring BG. FIG. 55B shows the wiring BG that is electrically connected to the second gates of the selection transistor SST and the memory transistors MT1 to MTk, and the wiring BG that is electrically connected to the second gates of the selection transistor SDT and the memory transistors MTk+1 to MT2k. Different potentials may be applied to the wirings BG, or they may be at the same potential. Also, the wirings BG may be electrically connected to each other.

[0350] The wiring BG preferably extends in the column direction parallel to the bit line BL, but may be arranged to extend in the row direction.

[0351] The threshold values of the selection transistors SST and SDT can be controlled by the wiring BG. Also, the potential of the wiring BG may be controlled in accordance with the circuit operation of the memory cell array.

[0352] The input / output circuit 125 temporarily holds the write data to the memory cell array 110, temporarily holds the data read from the memory cell array 110, and so on.

[0353] The source line driver 124 drives the source line SL.

[0354] The bit line BL is electrically connected to the sense amplifier 123. The sense amplifier 123 detects and amplifies the voltage read from the memory string 112 to the bit line BL during data reading. Also, during data writing, a voltage corresponding to the write data is input to the bit line BL.

[0355] The row decoder 121 decodes the address data input from the outside and selects the accessed row. The row driver 122 inputs the voltages necessary for data writing, reading, and erasing to the wirings DGL, SGL, and the word line WL according to the decoding result of the row decoder 121.

[0356] Also, the memory cell array 110 may be provided in a layer different from the peripheral circuits such as the control circuit 105 and the sense amplifier 123. In particular, it is preferable to stack and provide the memory cell array 110 so as to overlap the sense amplifier 123, as this can simplify the wiring routed from the memory cell array 110 to the sense amplifier 123. FIG. 56 is a block diagram showing a three-dimensional structure of the storage device 100 in which the memory cell array 110 is provided so as to overlap the sense amplifier 123 on the control circuit 105, row decoder 121, row driver 122, sense amplifier 123, source line driver 124, and input / output circuit 125 shown in FIG. 55A.

[0357] Figures 57 to 59 show examples of the three-dimensional stacked structure of the memory cell array 110. FIG. 57 is a diagram schematically showing an example of the three-dimensional structure of the memory cell array 110 in a circuit diagram. For ease of explanation, some circuits (memory strings) are omitted. FIG. 58 is a perspective view showing an example of the three-dimensional structure of the memory cell array 110. FIG. 59 is a perspective view showing an example of the three-dimensional structure of the connection portion between the word line WL and the conductor 701. As shown in FIG. 57, the memory cell array 110 is provided by being stacked in a region where the sense amplifier 123 is formed. Thereby, the layout area of the storage device 100 can be reduced. As shown in FIGS. 58 and 59, even for the conductors 701 in the same stage, the conductor 701a on the bit line BL side is connected to the word line WLa, and the conductor 701b on the source line SL side is connected to the word line WLb. The wiring BG electrically connected to the conductor 712 is provided in the same layer as the bit line BL and extends in the column direction in the same manner as the bit line BL, but the present invention is not limited thereto. An insulator may be provided on the bit line BL, and the wiring BG may be provided on the insulator. Further, the wiring BG may be provided so as to extend not only in the column direction but also in the row direction. Note that FIGS. 57 to 59 show an example in which eight memory transistors MT1 to MT8 are provided per one memory string 112.

[0358] (Description of the circuit operation of the storage device) Next, the writing and reading operations of data to and from the memory string 112 will be described with reference to FIGS. 60A to 60C. Hereinafter, a group of memory transistors MT sharing the word lines WL1 to WL2k will be referred to as a page.

[0359] In FIGS. 60A to 60C, as an example, an example in which the memory string 112 has the memory transistors MT1 to MT8 is shown, but the number of the memory transistors MT is not limited thereto.

[0360] <Erase operation> When writing data to the memory transistor MT, it is preferable to erase the data before the write operation. Note that the operation of erasing data is sometimes also referred to as a reset operation. The erasing operation is performed for each memory string 112 (also referred to as a block). For example, to select a block for which data is to be erased, as shown in FIG. 60A, a low potential (a potential at which the memory transistors MT1 to MT8 become non-conductive, for example, 0 V) is applied to the word lines WL1 to WL8, an erasing potential VE is applied to the source line SL and the bit line BL, and the selection transistors SDT and SST are turned on. By the reset operation, electrons accumulated in the charge storage layers of the memory transistors MT1 to MT8 can be extracted. As a result, the memory transistors MT1 to MT8 are in a state of holding the data "1".

[0361] Also, the erasing operation can be executed by applying an erasing potential to the wiring BG. For example, an erasing potential of 15 V is applied to the wiring BG, a low potential (a potential at which the memory transistors MT1 to MT8 become non-conductive, for example, 0 V) is applied to the word lines WL1 to the word line WL8, and the selection transistors SDT and SST are turned on.

[0362] Alternatively, the selection transistors SDT and SST are turned off, the oxide including the channel formation region of the memory transistor MT is made floating, and a positive charge (for example, 15 V) is applied as the erasing potential to the wiring BG, whereby the data of the memory transistor MT can be erased. At this time, since the selection transistors SDT and SST are non-conductive, the potentials of the bit line BL and the source line SL may be arbitrary. For example, a low potential (a potential at which the memory transistors MT1 to MT8 become non-conductive, for example, 0 V) is applied to the word lines WL1 to the word line WL8. As a result, since the oxide including the channel formation region is floating, as the potential of the wiring BG increases, the potential of the oxide also increases, and the electrons accumulated in the charge storage layer can be extracted to the oxide side.

[0363] As another different erasing operation, for example, a low potential (a potential at which memory transistors MT1 to MT8 become non-conductive, for example, 0V) is applied to word lines WL1 to WL8. Then, the selection transistor SDT and the selection transistor SST are made conductive, and the potentials of the bit line BL and the source line SL are raised. At this time, the potentials of the bit line BL and the source line SL are made lower than the potential of the wiring BG. For example, the potentials of the bit line BL and the source line SL are set to 10V, and the potential of the wiring BG is set to 12V. At this time, the memory transistor MT is turned on by the potential of the wiring BG, and the oxide of the memory transistor MT also becomes 10V. As a result, the electrons accumulated in the charge storage layer can be drawn out to the oxide side.

[0364] Also, the erasing operation is not limited to the above method. The erasing operation may be performed, for example, by sequentially selecting the memory transistors MT for which data is to be erased. In that case, the erasing operation does not necessarily have to be performed on all the memory transistors MT, and only the memory transistors MT for which data erasure is necessary may be selected to erase the data. For example, the erasing operation may be performed only on the memory transistors MT in which the data “0” is written.

[0365] Note that it is preferable to store the data of the memory transistors MT for which data rewriting is not performed in another memory area before the block erasing operation.

[0366] <Writing operation> Next, the data writing operation will be described with reference to FIG. 60B.

[0367] The data writing operation can be performed page by page as described above. First, a write potential (e.g., 15V) is applied to the word line of the page to be written, and a positive potential (the potential at which the transistor conducts, e.g., 3V) is applied to the word lines of the pages where writing is not to be performed. Here, as shown in FIG. 60B, first, a write potential is applied to the word line WL1, and a positive potential is applied to the word lines WL2 to WL8. Then, the selection transistor SST is set to the non-conducting state, and a positive potential is applied to the selection transistor SDT to make it conductive. By doing so, data corresponding to the potential of the bit line BL is written into the memory transistor MT1. Specifically, when the potential of the bit line BL is a low potential (e.g., 0V), electrons are injected into the charge storage layer of the memory transistor MT1 due to the large potential difference from the write potential applied to the word line WL1. Also, when both the potential of the selection transistor SDT and the potential of the bit line BL are positive, the selection transistor SDT becomes non-conductive. At this time, since the memory transistor MT is in an electrically floating state, no electrons are injected into the charge storage layer of the memory transistor MT1. That is, when a low potential is applied to the bit line BL, data "0" is written into the memory transistor MT1, and when a positive potential is applied, the data in the memory transistor MT1 remains "1".

[0368] Here, by applying different potentials to each memory string 112 of the bit line BL, data can be written page by page.

[0369] Note that multi-valued data can also be written into the memory transistor MT. For example, the amount of charge injected into the charge storage layer of the memory transistor MT can be controlled by the potential of the bit line BL or the like and the time for applying the potential.

[0370] <Read operation> Next, the data read operation will be described with reference to FIG. 60C.

[0371] The data reading operation can also be performed page by page. First, a low potential (e.g., 0 V) is applied to the word lines of the page to be read, and a positive potential (the potential at which the transistor conducts, e.g., 3 V) is applied to the word lines of the pages not to be read. Here, as shown in FIG. 60C, first, a low potential is applied to the word line WL1, and positive potentials are applied to the word lines WL2 to WL8. Then, the selection transistors SDT and SST are set to the conductive state. Also, a read potential (e.g., 1 V) is applied to the bit line BL, and a low potential (e.g., 0 V) is applied to the source line SL. At this time, if the data stored in the memory transistor MT is "1", a current flows through the memory string 112, and the potential of the bit line BL drops. If the data stored in the memory transistor MT1 is "0", no current flows through the memory string 112, and the potential of the bit line BL does not change. The sense amplifier 123 detects and amplifies the potential of the bit line BL. Thus, the data in the memory string 112 can be read out.

[0372] At this time, by applying a positive potential to the wiring BG, the threshold voltage (Vth) of the memory transistor MT may be shifted negatively. The potential applied to the wiring BG is adjusted so that the memory transistor MT in which writing is not performed becomes normally on. By doing so, incorrect reading can be prevented. Also, the potential applied to the word line WL can be reduced, and the power consumption of the storage device can be reduced, which is preferable.

[0373] Here, by reading the data of each memory string 112 to the bit line BL, data can be read out in page units.

[0374] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0375] (Embodiment 2) In this embodiment, an application example of a memory device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the previous embodiment can be applied to, for example, memory devices of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), recording and playback devices, navigation systems, etc.). Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers, but also large-scale computers such as server systems. Alternatively, the semiconductor device shown in the previous embodiment is applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, and SSDs (solid state drives). Some configuration examples of the removable storage device are schematically shown in FIGS. 61A to 61E. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0376] FIG. 61A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 etc. of the substrate 1104.

[0377] FIG. 61B is a schematic diagram of the appearance of an SD card, and FIG. 61C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing a memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thereby, data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1114 and the like on the substrate 1113.

[0378] FIG. 61D is a schematic diagram of the appearance of an SSD, and FIG. 61E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DRAM chip may be used. By providing a memory chip 1154 also on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1154 and the like on the substrate 1153.

[0379] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0380] (Embodiment 3) In this embodiment, with reference to FIG. 62, an AI system to which the semiconductor device shown in the above embodiment is applied will be described.

[0381] FIG. 62 is a block diagram showing a configuration example of the AI system 4041. The AI system 4041 includes an arithmetic unit 4010, a control unit 4020, and an input / output unit 4030.

[0382] The arithmetic unit 4010 includes an analog arithmetic circuit 4011, a DOSRAM 4012, a NOSRAM 4013, an FPGA 4014, and a 3D-NAND 4015.

[0383] Here, DOSRAM (registered trademark) is an abbreviation of "Dynamic Oxide Semiconductor RAM" and refers to a RAM having a 1T (transistor) 1C (capacitance) type memory cell.

[0384] Also, NOSRAM (registered trademark) is an abbreviation of "Nonvolatile Oxide Semiconductor RAM" and refers to a RAM having a gain cell type (2T type, 3T type) memory cell. DOSRAM and NOSRAM are memories that utilize the low off-current of transistors using oxide as a semiconductor (hereinafter referred to as OS transistors). In the following, a memory device using OS transistors such as NOSRAM may be referred to as an OS memory.

[0385] The control unit 4020 includes a CPU (Central Processing Unit) 4021, a GPU (Graphics Processing Unit) 4022, a PLL (Phase Locked Loop) 4023, an SRAM (Static Random Access Memory) 4024, a PROM (Programmable Read Only Memory) 4025, a memory controller 4026, a power supply circuit 4027, and a PMU (Power Management Unit) 4028.

[0386] The input / output unit 4030 includes an external memory control circuit 4031, an audio codec 4032, a video codec 4033, a general-purpose input / output module 4034, and a communication module 4035.

[0387] The arithmetic unit 4010 can perform learning or inference by a neural network.

[0388] The analog arithmetic circuit 4011 has an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a sum-of-products arithmetic circuit.

[0389] The analog arithmetic circuit 4011 is preferably formed using OS transistors. The analog arithmetic circuit 4011 using OS transistors has an analog memory and can perform the sum-of-products arithmetic necessary for learning or inference with low power consumption.

[0390] The DOSRAM 4012 is a DRAM formed using OS transistors. The DOSRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021. The DOSRAM 4012 has a memory cell including an OS transistor and a read circuit section including an Si transistor. Since the memory cell and the read circuit section can be provided in different stacked layers, the DOSRAM 4012 can reduce the overall circuit area.

[0391] In the calculation using a neural network, the input data may exceed 1000. When storing the input data in the SRAM, since the SRAM has a limit on the circuit area and a small storage capacity, the input data has to be stored in small portions. The DOSRAM 4012 can arrange the memory cells with high integration even with a limited circuit area and has a larger storage capacity than the SRAM. Therefore, the DOSRAM 4012 can store the input data efficiently.

[0392] NOSRAM4013 is a non-volatile memory using an OS transistor. Compared with other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory), and MRAM (Magnetoresistive Random Access Memory), NOSRAM4013 has low power consumption when writing data. Also, unlike flash memory and ReRAM, the elements do not deteriorate when writing data, and there is no limit to the number of times data can be written.

[0393] In addition to 1-bit binary data, NOSRAM4013 can store multi-valued data of 2 bits or more. By storing multi-valued data, NOSRAM4013 can reduce the memory cell area per bit.

[0394] Furthermore, NOSRAM4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 can also use NOSRAM4013 as an analog memory. Since NOSRAM4013 can store analog data as it is, a D / A conversion circuit and an A / D conversion circuit are not required. Therefore, NOSRAM4013 can reduce the area of peripheral circuits. In this specification, analog data refers to data having a resolution of 3 bits (8 values) or more. The above-mentioned multi-valued data may be included in the analog data.

[0395] The data and parameters used in the calculation of the neural network can be stored in NOSRAM4013 once. The above data and parameters may be stored in a memory provided outside the AI system 4041 via the CPU4021, but NOSRAM4013 provided inside can store the above data and parameters faster and with lower power consumption. Also, since NOSRAM4013 can make the bit lines longer than DOSRAM4012, the storage capacity can be increased.

[0396] FPGA4014 is an FPGA using OS transistors. By using FPGA4014, the AI system 4041 can configure, in hardware, the connections of neural networks such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), which will be described later. By configuring the above-mentioned connections of neural networks in hardware, it can be executed at a higher speed.

[0397] FPGA4014 is an FPGA having OS transistors (OS-FPGA). The OS-FPGA can reduce the memory area compared to an FPGA composed of SRAM. Therefore, even if a context switching function is added, the increase in area is small. In addition, the OS-FPGA can transmit data and parameters at high speed by boosting.

[0398] 3D-NAND4015 is a non-volatile memory using an oxide semiconductor. 3D-NAND4015 is a highly integrated memory with a large storage capacity per unit area.

[0399] In addition to 1-bit binary data, 3D-NAND4015 can store multi-valued data of 2 bits or more. By storing multi-valued data in 3D-NAND4015, the memory cell area per bit can be further reduced.

[0400] Also, as 3D-NAND4015, for example, the semiconductor device shown in the above embodiment can be used. Thereby, since the occupied area in the memory cell can be reduced, 3D-NAND4015 can be further highly integrated. Therefore, the storage capacity per unit area of 3D-NAND4015 can be increased.

[0401] The AI system 4041 can be provided with an analog arithmetic circuit 4011, a DOSRAM 4012, a NOSRAM 4013, and an FPGA 4014 on one die (chip). Therefore, the AI system 4041 can execute neural network calculations at high speed and with low power consumption. In addition, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be fabricated using the same manufacturing process. Therefore, the AI system 4041 can be fabricated at low cost.

[0402] Note that the arithmetic unit 4010 does not necessarily have to have all of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014. One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selectively provided according to the problem to be solved by the AI system 4041.

[0403] The AI system 4041 can execute methods such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), and a deep belief network (DBN) according to the problem to be solved. The PROM 4025 can store a program for executing at least one of these methods. Also, part or all of the program may be stored in the NOSRAM 4013 or the 3D-NAND 4015. The 3D-NAND 4015 is a highly integrated memory and has a large storage capacity per unit area, so a large-capacity program can be stored.

[0404] Many existing programs that exist as libraries assume GPU processing. Therefore, it is preferable for the AI system 4041 to have a GPU 4022. The AI system 4041 can execute the bottleneck multiply-accumulate operation in the arithmetic unit 4010 and execute other multiply-accumulate operations on the GPU 4022 among the multiply-accumulate operations used in learning and inference. By doing so, learning and inference can be executed at high speed.

[0405] The power supply circuit 4027 not only generates a low power supply potential for the logic circuit but also generates a potential for analog operations. The power supply circuit 4027 may use an OS memory. The power supply circuit 4027 can reduce power consumption by storing a reference potential in the OS memory.

[0406] The PMU 4028 has a function of temporarily turning off the power supply to the AI system 4041.

[0407] The CPU 4021 and the GPU 4022 preferably have an OS memory as a register. By having the OS memory, the CPU 4021 and the GPU 4022 can continue to hold data (logical values) in the OS memory even when the power supply is turned off. As a result, the AI system 4041 can save power.

[0408] The PLL 4023 has a function of generating a clock. The AI system 4041 operates based on the clock generated by the PLL 4023. The PLL 4023 preferably has an OS memory. By having the OS memory, the PLL 4023 can hold an analog potential for controlling the oscillation period of the clock.

[0409] The AI system 4041 may store data in an external memory such as a DRAM. Therefore, the AI system 4041 preferably has a memory controller 4026 that functions as an interface to the external DRAM. Also, the memory controller 4026 is preferably arranged near the CPU 4021 or the GPU 4022. By doing so, data can be exchanged at high speed.

[0410] Part or all of the circuits shown in the control unit 4020 can be formed on the same die as the arithmetic unit 4010. By doing so, the AI system 4041 can execute neural network calculations at high speed and with low power consumption.

[0411] Data used in neural network calculations is often stored in an external storage device (such as an HDD (Hard Disk Drive) or an SSD (Solid State Drive)). Therefore, it is preferable that the AI system 4041 has an external memory control circuit 4031 that functions as an interface with the external storage device.

[0412] Learning and inference using neural networks often involve handling audio and video. Therefore, the AI system 4041 has an audio codec 4032 and a video codec 4033. The audio codec 4032 encodes (encrypts) and decodes (decrypts) audio data, and the video codec 4033 encodes and decodes video data.

[0413] The AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general-purpose input / output module 4034. The general-purpose input / output module 4034 includes, for example, USB (Universal Serial Bus) and I2C (Inter-Integrated Circuit).

[0414] The AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, it is preferable that the AI system 4041 has a communication module 4035.

[0415] The analog arithmetic circuit 4011 may use a multi-value flash memory as an analog memory. However, the flash memory has a limit on the number of rewritable times. Also, it is very difficult to form a multi-value flash memory embedded (form the arithmetic circuit and the memory on the same die).

[0416] In addition, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limited number of rewritable times and also has problems in terms of storage accuracy. Furthermore, since it is a two-terminal element, the circuit design for separating data writing and reading becomes complicated.

[0417] Also, the analog arithmetic circuit 4011 may use MRAM as an analog memory. However, MRAM has a low resistance change rate and has problems in terms of storage accuracy.

[0418] In view of the above, it is preferable that the analog arithmetic circuit 4011 uses the OS memory as an analog memory.

[0419] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments.

[0420] (Embodiment 4) (Application Examples of AI System) In this embodiment, the application examples of the AI system shown in the above embodiment will be described with reference to FIGS. 63A and 63B.

[0421] FIG. 63A shows an AI system 4041A in which the AI systems 4041 described in FIG. 62 are arranged in parallel and signals can be transmitted and received between the systems via a bus line.

[0422] The AI system 4041A shown in FIG. 63A includes a plurality of AI systems 4041_1 to AI systems 4041_n (n is a natural number). The AI systems 4041_1 to AI systems 4041_n are connected to each other via a bus line 4098.

[0423] Also, FIG. 63B shows an AI system 4041B in which the AI systems 4041 described in FIG. 62 are arranged in parallel in the same manner as in FIG. 63A and signals can be transmitted and received between the systems via a network.

[0424] The AI system 4041B shown in FIG. 63B has a plurality of AI systems 4041_1 to AI systems 4041_n. The AI systems 4041_1 to AI systems 4041_n are connected to each other via a network 4099.

[0425] The network 4099 may be configured to provide a communication module for each of the AI systems 4041_1 to AI systems 4041_n to perform wireless or wired communication. The communication module can communicate via an antenna. For example, each electronic device can be connected to a computer network such as the Internet, which is the basis of the World Wide Web (WWW), an intranet, an extranet, a PAN (Personal Area Network), a LAN (Local Area Network), a CAN (Campus Area Network), a MAN (Metropolitan Area Network), a WAN (Wide Area Network), a GAN (Global Area Network), etc. to perform communication. When performing wireless communication, as a communication protocol or communication technology, communication standards such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), W-CDMA (registered trademark), etc., or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark), etc. can be used.

[0426] By adopting the configurations shown in FIGS. 63A and 63B, analog signals obtained by an external sensor or the like can be processed by separate AI systems. For example, information such as electroencephalogram, pulse, blood pressure, body temperature, etc., like biological information, can be acquired by various sensors such as an electroencephalogram sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor, and the analog signals can be processed by separate AI systems. By performing signal processing or learning in each of the separate AI systems, the amount of information processing per AI system can be reduced. Therefore, signal processing or learning can be performed with a smaller amount of computation. As a result, the recognition accuracy can be improved. It is expected that the changes in the complexly changing biological information can be instantaneously and integrally grasped from the information obtained by each AI system.

[0427] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0428] (Embodiment 5) This embodiment shows an example of an IC in which the AI system shown in the above embodiment is incorporated.

[0429] The AI system shown in the above embodiment can integrate a digital processing circuit composed of Si transistors such as a CPU, an analog arithmetic circuit using OS transistors, 3D-NAND, OS-FPGA, and OS memories such as DOSRAM and NOSRAM on one die.

[0430] FIG. 64 shows an example of an IC incorporating an AI system. The AI system IC 7000 shown in FIG. 64 has leads 7001 and a circuit section 7003. The AI system IC 7000 is mounted on, for example, a printed circuit board 7002. A plurality of such IC chips are combined, and each is electrically connected on the printed circuit board 7002 to complete a substrate (mounting substrate 7004) on which electronic components are mounted. In the circuit section 7003, various circuits shown in the above-described embodiments are provided on one die. The circuit section 7003 has a stacked structure and is roughly classified into an Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033, as shown in the previous embodiment. Since the OS transistor layer 7033 can be stacked on the Si transistor layer 7031, the AI system IC 7000 can be easily miniaturized.

[0431] In FIG. 64, a QFP (Quad Flat Package) is applied to the package of the AI system IC 7000, but the package form is not limited to this.

[0432] A digital processing circuit such as a CPU, an analog arithmetic circuit using an OS transistor, 3D-NAND, an OS-FPGA, and OS memories such as DOSRAM and NOSRAM can all be formed in the Si transistor layer 7031, the wiring layer 7032, and the OS transistor layer 7033. That is, the elements constituting the above AI system can be formed by the same manufacturing process. Therefore, for the IC shown in this embodiment, even if the number of constituent elements increases, it is not necessary to increase the manufacturing process, and the above AI system can be incorporated at low cost.

[0433] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0434] (Embodiment 6) <Electronic device> The semiconductor device according to one aspect of the present invention can be used in various electronic devices. FIGS. 65A to 66F show specific examples of electronic devices using the semiconductor device according to one aspect of the present invention.

[0435] The robot 2100 shown in FIG. 65A includes an arithmetic unit 2001, a sensor 2002, a light 2003, a lift 2004, a drive unit 2005, and a moving mechanism 2012, and can capture still images and moving images while moving. Such a robot can be used as a security system or a monitoring system.

[0436] The robot 2100 may further include a communication means 2006, a speaker 2007, a microphone 2008, a display unit 2009, a light emitting unit 2010, and the like.

[0437] The arithmetic unit 2001 can use a semiconductor device according to an aspect of the present invention. Further, for the arithmetic unit 2001, an IC incorporating an AI system according to an aspect of the present invention can be used. The sensor 2002 has a function as a camera that captures the surroundings of the robot 2100. The light 2003 can be used as a light when the sensor 2002 captures the surroundings of the robot 2100. When the sensor 2002 captures a still image, the light 2003 preferably functions as a flash light. The sensor 2002 is connected to the robot main body via the lift 2004. The height of the sensor 2002 can be adjusted by the lift 2004. The lift 2004 is preferably a telescopic type. Further, the lift 2004 may be a foldable type constituted by a plurality of booms. Further, since the robot 2100 is provided with a drive unit 2005 and a moving mechanism 2012 connected to the drive unit 2005, the imaging range by the sensor 2002, that is, the monitoring range is widened, which is preferable.

[0438] The communication means 2006 can transmit the information captured by the sensor 2002 to the administrator or the server owned by the administrator. Also, when the information captured by the sensor 2002 is analyzed by the arithmetic unit 2001 and determined to be an emergency such as a crime, accident, or fire, it can contact a security company, the police, the fire department, a medical institution, or the owner of the land or building. The speaker 2007 can transmit information around the robot 2100, such as warnings to criminals, inquiries to the injured or critically ill, and evacuation guidance. The microphone 2008 can be used to acquire the sounds around the robot 2100. Also, when used in combination with the communication means 2006 and the speaker 2007, the robot 2100 can have the function of a telephone. People around the robot 2100 can talk to the administrator or any person. The display unit 2009 can display any information. In case of an emergency, it can display disaster information and evacuation routes. Also, when used in combination with the communication means 2006, the speaker 2007, and the microphone 2008, the robot 2100 can have the function of a videophone. People around the robot 2100 can talk to the administrator or any person while looking at the display unit 2009.

[0439] The light emitting unit 2010 can indicate the traveling direction and stop state of the robot 2100 in characters or light. It may also indicate an emergency.

[0440] FIG. 65B is a block diagram showing the configuration of the robot 2100. The arithmetic unit 2001 controls the lighting, extinguishing, and brightness adjustment of the light 2003 based on information such as images obtained by the sensor 2002. It also adjusts the height of the lift 2004 or controls the drive unit 2005 to align the positions of the robot 2100 and the sensor 2002. In addition, the operating status of the drive unit 2005 can be indicated using the light emitting unit 2010. Further, using the communication means 2006, the information around the robot 2100 obtained from the sensor 2002 and the microphone 2008 can be transmitted to the administrator or a server owned by the administrator. Also, depending on the judgment of the arithmetic unit 2001 or the administrator, information can be transmitted around the robot 2100 using the speaker 2007 and the display unit 2009.

[0441] When using a sensor that can perform imaging even in a dark environment as the sensor 2002, the light 2003 may not be provided. As such a sensor, an image sensor using selenium (Se) in the light receiving part can be used.

[0442] Such a robot 2100 can be used for security in commercial facilities and offices. The information obtained from the sensor 2002 and the microphone 2008 is stored in the arithmetic unit 2001 and the server. The stored information is analyzed by an AI system to determine the presence or absence of abnormalities such as loss or damage of articles, intrusion of suspicious persons, and disasters such as fires. Deep learning may be used for information analysis. When it is determined that an abnormality has occurred, the robot 2100 contacts the administrator, transmits information around, and records the surrounding situation.

[0443] In addition, the robot 2100 may be used to monitor the growth status of crops. The robot 2100 installed in a paddy field or a field monitors the leaves of the crops, or the shape, size, and color of the fruits by means of the sensor 2002, and determines whether the crops are diseased or have no pest attachment. Since the robot 2100 is provided with a moving mechanism 2012, the growth status of a wide range of crops can be monitored. In addition, since the robot 2100 is provided with a lift 2004, it is possible to monitor the leaves and fruits at any height regardless of the type of crops and their growth status. The monitoring results are sent to the producer using the communication means 2006, and the producer can determine the type, amount, and spraying time of fertilizers and pesticides required for the crops. Alternatively, the monitoring results may be analyzed by an AI system using the arithmetic unit 2001 to determine the type, amount, and spraying time of fertilizers and pesticides required for the crops, and notify the producer. Deep learning may be used for the analysis of the monitoring results.

[0444] FIG. 66A shows a sorting system 3000 using a robot 3001. The robot 3001 includes an arithmetic unit 3002, a boom 3003, and an arm 3004. The robot 3001 may also include wired or wireless communication means 3011. The sorting system 3000 includes a housing 3008 having a sensor 3009. The housing 3008 has communication means 3010. The housing 3008 is provided on the sorting system 3000, or on the ceiling, wall, or beam (all not shown) of the sorting work area. The housing 3008 may also be provided on the robot 3001. For example, it may be provided on the boom 3003 or the arm 3004. When the housing 3008 is provided on the robot 3001, the information obtained by the sensor 3009 may be sent to the arithmetic unit 3002 and processed without passing through the communication means 3010 and the communication means 3011.

[0445] The boom 3003 is movable and can position the arm 3004 at a desired position. Also, the arm 3004 may be telescopic. After extending the arm 3004 placed on the desired article 3007, grasping the desired article 3007, and retracting the arm 3004, the arm 3004 may be moved by the boom 3003.

[0446] The sorting system 3000 can move the article 3007 in the container 3005 to the container 3006. The containers 3005 and 3006 may have the same shape or different shapes. Also, a plurality of articles 3007 contained in one container 3005 may be sorted and moved to a plurality of containers 3006.

[0447] As the containers 3005 and 3006, a container, a cardboard box, a box for packing goods, a case, a film, or a bag, a vat for storing food, a lunch box, etc. are used. Also, at least one of the containers 3005 and 3006 may be a cooking utensil such as a pot or a frying pan.

[0448] For the arithmetic unit 3002, a semiconductor device according to one aspect of the present invention can be used. Also, for the arithmetic unit 3002, an IC incorporating an AI system according to one aspect of the present invention can be used.

[0449] The sensor 3009 reads the position and number of the container 3005, the position and number of the container 3006, the inside of the container 3005, and the state of the article 3007 inside the container 3005, and transmits information to the arithmetic unit 3002 using the communication means 3010. The information can be transmitted wirelessly or by wire. Also, the information may be transmitted by wire without using the communication means 3010. The arithmetic unit 3002 analyzes the transmitted information. Here, the state of the article 3007 refers to the shape, number, overlap between the articles 3007, and the like. The arithmetic unit 3002 performs analysis based on the information from the sensor 3009 and derives detailed information about the article 3007. The arithmetic unit 3002 compares with the data stored in the server that can communicate with the arithmetic unit 3002 or the robot 3001, and derives the three-dimensional shape and hardness (softness) of the article 3007. Further, the shape of the arm 3004 can be changed based on the three-dimensional shape and hardness (softness) of the article 3007. Also, depending on the shape and size of the article 3007, the placement location inside the container 3006 may be changed for sorting, or it may be sorted by placing it in a plurality of different containers 3006.

[0450] To derive the detailed information of the article 3007, analysis using an AI system can be utilized. Deep learning may be used for the analysis of the information.

[0451] Figure 66B shows an arm where a pair of plates 3021 can move horizontally to clamp an article 3007. By moving the pair of plates 3021 horizontally towards the center, the article 3007 can be clamped. Such an arm can capture the article 3007 by its surface and is suitable for grasping an article 3007 having a columnar shape such as a cube or a rectangular parallelepiped. Figure 66C shows an arm where a plurality of bars 3022 can move horizontally to clamp an article 3007. By moving the plurality of bars 3022 horizontally towards the center, the article 3007 can be clamped. Such an arm can capture the article 3007 at points and is suitable for grasping an article 3007 having a spherical shape or an article 3007 with an irregular shape, that is, an amorphous article 3007. In Figure 66C, the number of bars 3022 is four, but the present embodiment is not limited to this. The number of bars 3022 may be three or five or more. Figure 66D shows an arm where a pair of plates 3023 can rotate around a common axis so as to approach each other to clamp an article 3007. Such an arm can capture the article 3007 by its surface and is suitable for grasping an article 3007 having a thin film shape such as paper or a film. Figure 66E shows an arm where a pair of claw-shaped plates 3024 can rotate around a common axis so that the tips of each other approach each other to clamp an article 3007. Such an arm can capture the article 3007 at points or lines and is suitable for grasping an article 3007 having a thin film shape such as paper or a film or an article 3007 having a smaller granular shape. Also, as shown in Figure 66F, a spatula 3025 may be attached to the tip of the arm to scoop up an article 3007 having a smaller granular shape.

[0452] The arms shown in Figures 66A to 66F are examples, and one aspect of the present invention is not limited to these shapes. Also, the description of the use of each arm is an example, and one aspect of the present invention is not limited to these descriptions.

[0453] Based on the signal from the arithmetic unit 3002, the robot 3001 moves the boom 3003 and moves the arm 3004 onto the desired article 3007 in the container 3005. In the case of the telescopic arm 3004, the arm 3004 is extended and the tip of the arm 3004 is lowered to the height of the article 3007. The tip of the arm is moved to grasp the desired article 3007. While grasping the article 3007, the arm is retracted. The boom 3003 is moved again, and the arm 3004 is moved to the desired position in the container 3006. At this time, the arm 3004 may be rotated to adjust the angle of the article 3007 with respect to the container 3006. The arm 3004 is extended, the article 3007 is placed in the container 3006, and the arm 3004 releases the article 3007. By repeating the above operations, the robot 3001 can move the article 3007 from the container 3005 to the container 3006.

[0454] Since the position information of the containers 3005 and 3006 and the state of the article 3007 are analyzed using the AI system, the article 3007 can be surely moved regardless of the shape and hardness of the article 3007. Examples of the article 3007 include not only articles packed in a cube, a rectangular parallelepiped box, or a box or case of any shape, but also eggs, processed foods such as hamburgers and croquettes, foods such as irregular vegetables such as potatoes and tomatoes, machine parts such as screws and nuts, and thin films such as paper and film. Since the sorting system 3000 shown in the present embodiment can change the shape of the arm in consideration of the shape and hardness of the article 3007, the article 3007 exemplified above can be moved from the container 3005 to the container 3006 regardless of the shape and hardness.

[0455] For example, a storage device using the semiconductor device according to one aspect of the present invention can store the control information of the above-described electronic device, control programs, etc. for a long period of time. By using the semiconductor device according to one aspect of the present invention, a highly reliable electronic device can be realized.

[0456] Also, for example, an IC incorporating the above AI system can be used in the arithmetic unit of the electronic device described above. As a result, the electronic device shown in this embodiment can perform accurate operations according to the situation with low power consumption by the AI system.

[0457] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

Explanation of Reference Numerals

[0458] 700: Memory cell array, 700A: Memory cell array, 701: Conductor, 702: Conductor, 702A: Conductive film, 703: Insulator, 704: Oxide, 705: Conductor, 706: Conductor, 707: Conductor, 708: Conductor, 709: Conductor, 710: Conductor, 711: Insulator, 712: Conductor, 713: Insulator, 714: Conductor, 715: Conductor, 716: Layer, 717: Insulator, 719: Conductor, 720: Substrate, 721: Insulator, 722: Insulator, 723: Mask, 724: Insulator, 725: Mask, 726: Insulator, 727: Material, 729: Mask, 731: Region, 734: Region, 740: Layer, 742: Insulator, 744: Microwave, 750: Memory device, 752: Conductor, 801: Mask, 803: Conductor, 805: Mask, 807: Insulator, 810: Conductor, 812: Conductor

Claims

1. A first insulator having a first opening; A first conductor having a second opening on the first insulator; A second insulator having a third opening on the first conductor; A third insulator provided along a first side surface of the first opening, a second side surface of the second opening, and a third side surface of the third opening; An oxide provided along the first side surface, the second side surface, and the third side surface via the third insulator; A second conductor provided on the first side surface via the third insulator and the oxide; A third conductor provided on the third side surface via the third insulator and the oxide; A fourth insulator in contact with the oxide, the second conductor, and the third conductor; A fourth conductor in contact with the fourth insulator; and having the oxide is provided between the first conductor and the fourth insulator; the fourth insulator is provided between the oxide and the fourth conductor; the oxide has a first region in the first opening, a second region in the second opening, and a third region in the third opening; the second region has a higher resistance than the first region and the third region; the second conductor and the third conductor have a function of shielding microwaves; the first conductor functions as a first gate; the fourth conductor functions as a second gate; A semiconductor device.

2. In claim 1, the oxide has indium, an element M (M is one or more selected from aluminum, gallium, yttrium, and tin), and zinc; Semiconductor device.

3. In claim 1, the oxide has indium oxide, Semiconductor device.

4. In any one of claims 1 to 3, the oxide has a first layer, a second layer provided in contact with the inside of the first layer, a third layer provided in contact with the inside of the second layer, and has the energy gap of the second layer is narrower than the energy gap of the first layer, a semiconductor device in which the energy gap of the second layer is narrower than the energy gap of the third layer.

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