Pixel Circuit, Image Sensor, Imaging Module, and Electronic Device

Abstract

The pixel circuit includes a photoelectric conversion device, a charge storage device, a first transfer transistor, a second transfer transistor, and an exposure control signal memory.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims the priority of Chinese Patent Application No. 202011587897.4, filed in China on December 28, 2020, and all of its contents are incorporated herein by reference.

[0002] This application relates to the technical field of image processing, and specifically, to pixel circuits, image sensors, imaging modules, and electronic devices.

Background Art

[0003] In a Complementary Metal - Oxide Semiconductor (CMOS) image sensor, the dynamic range is generally gain - adjusted by changing the exposure time and pixel signal of all pixels. In High Dynamic Range (HDR) or Wide Dynamic Range (WDR) technology, in any of the multi - frame, line - interleaved, or dual - gain methods, all pixels adopt the same exposure time. The modulation effect of HDR is changed by adjusting the length of the exposure time and the gain of the output signal. In related HDR technologies, since the exposure time of each pixel is the same, in the use of HDR, depending on the scene, some pixels may be locally over - exposed, or some pixels may be under - exposed.

[0004] In related technologies, through pixel-wise exposure time control technology, for pixels in overexposed areas, individual encoding is performed for each pixel to control the exposure time, thereby realizing dynamic range modulation at the pixel level and avoiding problems of overexposure or underexposure. However, when practicing the pixel-wise HDR modulation method using off-chip technology, it is necessary to adopt a complex optical encoding exposure control system. This system not only has a large volume but also requires precise calibration between different devices, has high power consumption, and is not suitable for practical use in mobile terminal devices such as mobile phones. When practicing the pixel-wise HDR modulation method using on-chip technology, the pixel circuit requires two or more exposure control signal storage units to control two or more charge storage devices, which is disadvantageous for pixel miniaturization and may reduce pixel performance such as the fill factor of the pixel. Also, when using multiple exposure control signal storage units, the output exposure control signals may all be the same. For example, there is a probability that all high-level signals will be output. As a result, the charges generated by the photoelectric conversion device will flow into multiple charge storage areas simultaneously, and ultimately the encoded exposure will fail.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Embodiments of the present application provide a pixel circuit, an image sensor, an imaging module, and an electronic device that can simplify the pixel architecture, effectively reduce the volume of the pixel, and avoid the problem that the structure of the pixel circuit is complex and huge.

Means for Solving the Problems

[0006] In a first aspect, embodiments of the present application include a photoelectric conversion device for generating charges based on the photoelectric effect in response to incident light, and a charge storage device connected to the photoelectric conversion device for storing the charges generated by the photoelectric conversion device after exposure. A first transfer transistor connected to a photoelectric conversion device and a charge storage device for transferring charges to the charge storage device, A second transfer transistor connected to the photoelectric conversion device for transferring charges to a predetermined node to discard the charges, An exposure control signal memory connected to the first transfer transistor and the second transfer transistor, generating a charge control signal based on an exposure control signal, and controlling the on-states of the first transfer transistor and the second transfer transistor, is provided.

[0007] On a second aspect, embodiments of the present application provide An image sensor including the pixel circuit provided in the first aspect.

[0008] On a third aspect, embodiments of the present application provide A circuit board, The image sensor provided in the second aspect electrically connected to the circuit board, A lens provided on a side away from the circuit board of the image sensor, is provided.

[0009] On a fourth aspect, embodiments of the present application provide An electronic device including the imaging module provided in the third aspect.

Advantages of the Invention

[0010] In an embodiment of the present application, the pixel circuit includes a photoelectric conversion device for generating charges based on the photoelectric effect in response to incident light, a charge storage device connected to the photoelectric conversion device for storing the charges generated by the photoelectric conversion device after exposure, a first transfer transistor connected to the photoelectric conversion device and the charge storage device for transferring the charges to the charge storage device, a second transfer transistor connected to the photoelectric conversion device for transferring the charges to a predetermined node to discard the charges, and an exposure control signal memory connected to the first transfer transistor and the second transfer transistor for generating a charge control signal based on an exposure control signal to control the on states of the first transfer transistor and the second transfer transistor. Thereby, in the exposure process, only one exposure control signal memory of a binary signal (1 or 0) is required, and within the exposure time of one frame, by continuously changing and updating the exposure control signals of each pixel, the first transfer transistor and the second transfer transistor are controlled. When the pixel is instructed to be exposed, the generated charges flow to the charge storage device, and when the pixel is instructed not to be exposed, the generated charges flow to a predetermined node and are discarded. Thereby, the effective exposure time of each pixel is programmed by the pre-written exposure control signal, and the HDR modulation function for each pixel of the image sensor can be realized. On the other hand, there is no need to adopt a complex optical encoding exposure control system, and the problems of volume and power consumption in practicing the HDR modulation method for each pixel by Off-Chip technology can be avoided. On the other hand, when practicing the HDR modulation method for each pixel by On-Chip technology, by reducing the number of exposure control signal memories for receiving and analyzing the exposure control signals, while simplifying the pixel circuit structure, the volume of the pixel is effectively reduced, which is advantageous for the miniaturization of the pixel, the performance of the pixel is improved, and the charge flow disturbance caused by the same exposure control signals of multiple exposure control signal memories is avoided, and the stability and gain effect of the HDR modulation for each pixel are guaranteed.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Mode for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present application will be described in detail. Exemplary examples of the embodiments are shown in the drawings. In the drawings, the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only and are intended only to interpret the present application and should not be construed as limiting the present application. Based on the embodiments of the present application, all other embodiments obtained without creative effort by those skilled in the art belong to the protection scope of the present application.

[0013] In the description and claims of the present application, the terms "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "a plurality" means two or more. Also, in the description and claims, "and / or" represents at least one of the connected objects, and the symbol " / " generally represents that the related objects before and after are in an "or" relationship.

[0014] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "upper", "lower", "front", "rear", "left", "right", etc. is based on the drawings and is only for facilitating the description of the present application and simplifying the description, and does not explicitly or implicitly imply that the described device or element must have a specific orientation or be configured and operated in a specific orientation. Therefore, it should not be construed as limiting the present application.

[0015] In the description of this application, unless otherwise clearly defined or limited, the terms "attach", "connect", and "couple" should be understood in a broad sense. For example, they may be fixedly connected, removably connected, integrally connected, mechanically connected, electrically connected, directly connected, or indirectly connected through an intermediate medium, and the interiors of two elements may be in communication. A person skilled in the art can understand the specific meaning of these terms in this application according to the specific situation.

[0016] Hereinafter, with reference to FIGS. 1 to 5, a pixel circuit, an image sensor, an imaging module, and an electronic device provided in an embodiment of this application will be described.

[0017] As shown in FIG. 1, which is a schematic diagram of a pixel circuit provided in an embodiment of this application, the pixel circuit 100 provided in the embodiment of this application includes a photoelectric conversion device 102 for generating charges based on the photoelectric effect in response to incident light, a charge storage device 104 connected to the photoelectric conversion device 102 for storing the charges generated by the photoelectric conversion device 102 after exposure, a first transfer transistor 1062 connected to the photoelectric conversion device 102 and the charge storage device 104 for transferring charges to the charge storage device 104, a second transfer transistor 1064 connected to the photoelectric conversion device 102 for transferring charges to a predetermined node to discard the charges, and an exposure control signal memory 108 connected to the first transfer transistor 1062 and the second transfer transistor 1064 for generating a charge control signal based on an exposure control signal and controlling the on states of the first transfer transistor 1062 and the second transfer transistor 1064.

[0018] Specifically, within the pixel circuit 100 architecture, there is one exposure control signal memory 108 (unit), one photoelectric conversion region based on the photoelectric conversion device 102, the first transfer transistor 1062, and the second transfer transistor 1064, and the charge storage device 104. In the exposure process, a binary exposure control signal (1 or 0) enters the exposure control signal memory 108 to generate charge control signals Q and Q', where Q' is the inverse of Q, i.e., Q' = Q × (-1), and controls the on states of the first transfer transistor 1062 and the second transfer transistor 1064 respectively. Thereby, part of the charges generated in the photoelectric conversion region during exposure flows through the first transfer transistor 1062 to the corresponding charge storage device 104 according to the exposure control signal, and the effective exposure of the pixel can be realized. After the exposure is completed, the charges in the charge storage device 104 can be read by the readout circuit 110 to output an image, and the other part flows to a predetermined node through the second transfer transistor 1064 and is discarded. Thereby, by updating the exposure control signal, the length of the effective exposure time of each pixel can be changed, that is, only the charges generated and accumulated when the pixel is instructed to be exposed are read, and the HDR modulation function for each pixel of the image sensor is realized.

[0019] In this embodiment, the HDR modulation function for each pixel of the image sensor can be realized without adopting a complex optical encoding exposure control system, and the problems of volume and power consumption in practicing the HDR modulation method for each pixel with Off-Chip technology can be avoided. Also, by reducing the number of exposure control signal memories 108 for receiving and analyzing the exposure control signals, while simplifying the structure of the pixel circuit 100, the volume of the pixel can be effectively reduced, which is beneficial to the miniaturization of the pixel, the performance of the pixel is improved, and the disturbance of the charge flow caused by the same exposure control signals of multiple exposure control signal memories 108 is avoided, and the stability and gain effect of the HDR modulation for each pixel are guaranteed.

[0020] Here, the predetermined node may be a memory, and the internal charge can be deleted by resetting the memory. The predetermined node may also be a voltage source and directly receives the charge.

[0021] Specifically, for example, as shown in FIG. 2 which is a schematic diagram of a pixel circuit provided in another embodiment of the present application, a predetermined node is a voltage source V DD3 . One charge storage device C1 is provided in the pixel circuit 100. When the first transfer transistor 1062 is turned off and the second transfer transistor 1064 is turned on, the charges generated by the photoelectric conversion device 102 directly flow to the voltage source V DD3 and are discarded. Thereby, when two charge storage devices are provided, it is possible to avoid the charges being stored in one of the charge storage devices and then discarded, further simplifying the pixel circuit. In a specific application, the photoelectric conversion device 102 is a photodiode, and the transistor can control the output current based on the input voltage, including a bipolar transistor (BJT) and a field effect transistor (FET). Here, the field effect transistor may be a metal oxide semiconductor field effect transistor (MOSFET). The charge storage device 104 may be a capacitive charge storage device or another type of charge storage device, such as an operational transconductance amplifier.

[0022] It should be noted that during the exposure time of one pixel frame, the exposure control signal is obtained from an analysis based on the situation of overexposure or underexposure of the pixels in the image within the exposure time, and each pixel can receive one or more binary exposure control signals. The sequence of these exposure control signals may be the same signal, such as all 1 (high level) or all 0 (low level), or different signals, such as 100101100....

[0023] Also, in one image sensor, the sequence of exposure control signals received by each pixel within the exposure time of one pixel frame may be the same or different. Similarly, the effective exposure time of each pixel in one pixel frame may be different or the same, and the effective exposure may be continuous or intermittent.

[0024] Furthermore, the first transfer transistor 1062 and the second transfer transistor 1064 are turned on alternately, that is, the first transfer transistor 1062 and the second transfer transistor 1064 are not turned on simultaneously, thereby preventing charge from flowing into a plurality of charge storage devices 104 at the same time and ultimately preventing the failure of encoded exposure.

[0025] Specifically, for example, when the sequence of exposure control signals for one pixel is all 1 and the output charge control signals are Q = 1 and Q’ = 0, within the exposure time of one pixel frame, the first transfer transistor 1062 is turned on and the second transfer transistor 1064 is turned off. When the sequence of exposure control signals for one pixel is 1001, the first output charge control signal is Q = 1, Q’ = 0, the second and third charge control signals are Q = 0, Q’ = 1, and the fourth charge control signal is Q = 1, Q’ = 0. First, the first transfer transistor 1062 is turned on and the second transfer transistor 1064 is turned off and maintained for a predetermined time length. Subsequently, the first transfer transistor 1062 is turned off and the second transfer transistor 1064 is turned on and maintained for two predetermined time lengths. Finally, it returns to the state where the first transfer transistor 1062 is turned on and the second transfer transistor 1064 is turned off and is maintained for a predetermined time length. Here, when the first transfer transistor 1062 is turned on, the charges generated during the exposure of the photoelectric conversion device 102 are transferred to and stored in the charge storage device 104. When the second transfer transistor 1064 is turned on, the charges generated during the exposure of the photoelectric conversion device 102 are transferred to a predetermined node and discarded. Thereby, when individually modulating the effective exposure time length of each pixel to achieve pixel-level HDR modulation, the sense of protrusion of the region edges in the output image can be avoided, not only can the problems of overexposure or underexposure be compensated, but also the pixel architecture can be simplified and the volume of the pixel can be effectively reduced.

[0026] In one embodiment of the present application, further, the exposure control signal memory 108 is a unit-bit static random access memory or a unit-bit dynamic random access memory.

[0027] In this embodiment, a Static Random Access Memory (SRAM) is a storage device with a static access function, capable of storing the data stored internally without the need for a refresh circuit, improving the read / write speed, reducing power consumption, and the SRAM process can be widely applied to the cache modules of various processor chips, reducing the manufacturing difficulty. A Dynamic Random Access Memory (DRAM) has the characteristics of a large storage capacity and low cost, and has a simpler circuit structure than the SRAM, and can further reduce the pixel size. Similarly, the DRAM process can be widely applied to mainstream memory chips, facilitating production and manufacturing.

[0028] Also, since both the unit-bit SRAM and the unit-bit DRAM use an information amount of 1 bit (bit), even if the exposure control signal memory 108 receives a plurality of exposure control signals, it sequentially stores 1-bit binary signals. This avoids generating different charge control signals at the same time, and avoids the charge generated by the photoelectric conversion device 102 flowing to different elements simultaneously, ultimately resulting in the failure of the encoded exposure. Thereby, only one exposure control signal memory 108 can achieve HDR modulation for each pixel, not only simplifying the pixel architecture, but also ensuring the stability and gain effect of HDR modulation for each pixel.

[0029] As shown in FIG. 3, which is a schematic diagram of a pixel circuit provided in a further embodiment of the present application, the unit-bit static random access memory includes a signal receiving device 1084 for receiving an exposure control signal according to a control command of a control terminal of the unit-bit static random access memory, and a signal processing device 1082 connected to the signal receiving device 1084 for generating a charge control signal based on the exposure control signal.

[0030] Specifically, the signal receiving device 1084 includes a first transistor M1 and a second transistor M2. The drains of the first transistor M1 and the second transistor M2 are connected to the output terminal of the exposure control signal. The gates of the first transistor M1 and the second transistor M2 are connected to the control terminals of the unit bit static random access memory.

[0031] The signal processing device 1082 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The sources of the third transistor M3 and the fourth transistor M4 are connected to the first voltage source VDD1 of the pixel circuit 100. The gate of the third transistor M3 is connected to the gate of the fifth transistor M5, the drain of the fourth transistor M4, the drain of the sixth transistor M6, the source of the first transistor M1, and the first transfer transistor 1062, respectively. The gate of the fourth transistor M4 is connected to the gate of the sixth transistor M6, the drain of the third transistor M3, the drain of the fifth transistor M5, the source of the second transistor M2, and the second transfer transistor 1064, respectively. The sources of the fifth transistor M5 and the sixth transistor M6 are grounded.

[0032] In this embodiment, the control terminal of the unit bit static random access memory outputs and receives a control command rs, controls the on states of the first transistor M1 and the second transistor M2, and can further control the signal receiving device 1084 to receive an exposure control signal res. Here, the first transistor M1 and the second transistor M2 are respectively used to receive opposite exposure control signals res, that is, the exposure control signal res received by the second transistor M2 is the inverted signal of the exposure control signal res received by the first transistor M1. Each bit is stored in two cross-coupled inverters composed of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6. That is, the output of the first inverter is connected to the input of the second inverter, the output of the second inverter is connected to the input of the first inverter, and when the outputs of the two inverters are completed, the storage of one bit is completed.

[0033] In a specific application, the first voltage source VDD1 may be a variable voltage source.

[0034] As shown in FIG. 4, which is a schematic diagram of a pixel circuit provided in a further embodiment of the present application, the unit-bit dynamic random access memory includes a seventh transistor M7 whose drain is connected to the output terminal of the exposure control signal, whose gate is connected to the control terminal of the unit-bit dynamic random access memory, and which receives the exposure control signal res based on the control command rs of the control terminal; a first capacitor C3 whose first end is connected to the source of the seventh transistor M7 and the first transfer transistor 1062 respectively, and whose second end is grounded; and an inverter P whose first end is connected to the first end of the first capacitor C3 and whose second end is connected to the second transfer transistor 1064, for inverting the phase of the input signal by 180 degrees.

[0035] In this embodiment, within the exposure time of one pixel frame, the exposure control signal res reaches the first capacitor C3 through the seventh transistor M7 and directly serves as the charge control signal Q of the first transfer transistor 1062. At the same time, the charge control signal Q generates the charge control signal Q' of the second transfer transistor 1064 through an inverter P (NOT gate).

[0036] It should be noted that due to the characteristics of the semiconductor, the first capacitor of the DRAM has an inevitable leakage effect, and the DRAM exposure control signal memory needs to perform signal refresh periodically so that the exposure control signal can be stored continuously and effectively in the DRAM exposure control signal memory.

[0037] In a specific application, the first capacitor C3 may be a parasitic capacitor of the node, a Poly capacitor, a MIM (metal isolator metal) capacitor, a MOM (metal oxide metal) capacitor, or a MOS (metal oxide semiconductor) capacitor.

[0038] As shown in FIG. 1, in one embodiment of the present application, further, the pixel circuit 100 is connected to the charge storage device 104 and further includes a read circuit 110 for reading the charge in the charge storage device 104 and outputting an exposed image.

[0039] In this embodiment, after the exposure is completed, the read circuit 110 can read the charge in the modulated charge storage device 104 through the column data line and output an image after exposure.

[0040] As shown in FIGS. 3 and 4, in one embodiment of the present application, further, the charge storage device is connected to a first transfer transistor 1062 and includes a first charge storage device 1042 for outputting charge according to a read command of the read circuit 110, and a second charge storage device 1044 that is connected to a second transfer transistor 1064 and is reset according to a read command of the read circuit 110.

[0041] In this embodiment, the number of charge storage devices is one or more, and the plurality of charge storage devices includes a first charge storage device 1042 and a second charge storage device 1044. Here, the first charge storage device 1042 is connected to the first transfer transistor 1062. When the pixel is instructed to be exposed, charges can be accumulated in the first charge storage device 1042 via the first transfer transistor 1062. After the exposure ends, the reading circuit 110 can read the charges in the first charge storage device 1042 to generate an exposure image. The second charge storage device 1044 is connected to the second transfer transistor 1064. When the pixel is instructed not to be exposed, charges can be accumulated in the second charge storage device 1044 via the second transfer transistor 1064. After the reading circuit 110 reads the charges in the second charge storage device 1044, it can discard them. At the same time, the second charge storage device 1044 is reset to ensure sufficient space to accumulate the charges generated by the next exposure. The accumulated charges are deleted, or the second charge storage device 1044 is directly reset without reading the charges in the second charge storage device 1044. Thereby, the first charge storage device 1042 and the second charge storage device 1044 output two types of pixel output signals, only one of which is used for image output, and the other is finally ignored and reset. Since the charges to be discarded are pre-accumulated in the second charge storage device 1044, the processor can read the pixel output signal generated by the discarded charges, which facilitates the analysis of image HDR modulation.

[0042] It should be noted that the number of charge storage devices is N, and N is a multiple of 2. Therefore, the number of exposure control signal memories 108 is N / 2 so that each exposure control signal memory 108 can control two charge storage devices.

[0043] As shown in FIGS. 3 and 4, in one embodiment of the present application, further, the first charge storage device 1042 or the second charge storage device 1044 includes a second capacitor (capacitors C1, C2) connected to the photoelectric conversion device 102, and a storage transistor (transistors M8, M9) connected to the second capacitor and the reading circuit 110 for transferring the charge in the second capacitor to the reading circuit 110.

[0044] In this embodiment, the charges generated when the photoelectric conversion device 102 is exposed can flow to the corresponding second capacitor through the first transfer transistor 1062 and the second transfer transistor 1064 in the on state. After the exposure is completed, in the signal reading stage of the pixel, the charge in the second capacitor is read by the reading circuit 110 through the corresponding storage transistor.

[0045] Specifically, for example, after the exposure is completed, the charge in the second capacitor C1 reaches the floating diffusion node FD1 through the turned-on storage transistor M8 and is read by the reading circuit 110 to output the exposure image. The charge in the second capacitor C2 reaches the floating diffusion node FD2 through the turned-on storage transistor M9 and is read by the reading circuit 110 and then ignored and reset.

[0046] As shown in FIGS. 2 to 4, in one embodiment of the present application, further, the pixel circuit 100 includes floating diffusion nodes (FD1, FD2) located between the storage transistor (transistors M8, M9) and the reading circuit 110, and a second voltage source V DD2 and a reset transistor (RST1, RST2) connected between the second voltage source and the floating diffusion node for resetting the floating diffusion node voltage based on a reset control signal, and a gate connected to the floating diffusion node and a drain connected to the second voltage source V DD2Source follower transistors (SF1, SF2) connected to [[ID=]], and row selection transistors (RS1, RS2) with their drains connected to the sources of the source follower transistors and their sources and gates connected to the read circuit 110.

[0047] In this embodiment, due to the on-state of the reset transistor and the storage transistor in the charge storage device 104, the floating diffusion node is coupled to the second capacitor in the charge storage device 104 during the charge integration period to receive the charge stored in the second capacitor, or to the second voltage source V DD2 during the reset period to determine whether to reset the floating diffusion node voltage. The voltage signal of the floating diffusion node is amplified by the source follower transistors and the row selection transistors and output to the column data line.

[0048] Specifically, for example, as shown in FIGS. 3 and 4, in the read step, the row selection transistors RS1 and RS2 are turned on, the reset transistors RST1 and RST2 are turned on, and the floating diffusion nodes FD1 and FD2 are reset to the voltage of the second voltage source V DD2 The charges stored in the second capacitors C1 and C2 are transferred to the floating diffusion nodes FD1 and FD2 respectively, and the charges are read by SF1, RS1 and SF2, RS2.

[0049] In an embodiment of the present application, an image sensor is provided. The image sensor includes the pixel circuit provided in any one of the above-described embodiments. Therefore, the image sensor simultaneously includes all the beneficial effects of the pixel circuit in any one of the above-described embodiments, and detailed description is omitted here.

[0050] Furthermore, the image sensor is a complementary metal-oxide semiconductor image sensor (CMOS Image Sensor, CIS) having a high dynamic range (HDR) mode. The CMOS image sensor has advantages such as simple process, easy integration with other devices, small size, light weight, low power consumption, and low cost. For example, it can be widely applied to various electronic devices such as digital cameras, mobile phones with cameras, digital video cameras, medical imaging devices (endoscopes), and vehicle imaging devices.

[0051] In one embodiment of the present application, an imaging module is provided. The imaging module includes a circuit board, the image sensor provided in the above embodiment electrically connected to the circuit board, and a lens provided on a side away from the circuit board of the image sensor. Therefore, the imaging module simultaneously includes all the beneficial effects of the image sensor in any one of the above-described embodiments, and detailed description thereof is omitted here.

[0052] In one embodiment of the present application, an electronic device is provided. The electronic device includes the imaging module provided in the above embodiment. Therefore, the electronic device simultaneously includes all the beneficial effects of the imaging module in the above embodiment, and detailed description thereof is omitted here.

[0053] The electronic device in the embodiments of the present application may be a device, or may be a member, integrated circuit or chip in a terminal. The device may be a portable electronic device or a non-portable electronic device. By way of example, the portable electronic device may be a mobile phone, tablet computer, notebook computer, portable information terminal, in-vehicle electronic device, wearable device, ultra-mobile personal computer (UMPC), netbook or personal digital assistant (PDA), etc., and the non-portable electronic device may be a server, network attached storage (NAS), personal computer (PC), television (TV), automated teller machine or kiosk, etc., which is not specifically limited in the embodiments of the present application.

[0054] The electronic device in the embodiments of the present application may be a device having an operating system. The operating system may be an Android (registered trademark) operating system, an iOS operating system, or other possible operating systems, which is not specifically limited in the embodiments of the present application.

[0055] FIG. 5 is a hardware structure block diagram of the electronic device provided in the embodiments of the present application. As shown in FIG. 5, the electronic device 500 includes members such as a high-frequency unit 502, a network module 504, an audio output unit 506, an input unit 508, a sensor 510, a display unit 512, a user input unit 514, an interface unit 516, a memory 518, a processor 520, etc., but is not limited thereto.

[0056] A person skilled in the art will understand that the electronic device 500 may further include a power source (e.g., a battery) for supplying electricity to each component. The power source is logically connected to the processor 520 by a power management system, and the power management system can realize functions such as charge and discharge management and power consumption management. It is understandable that the structure of the electronic device shown in FIG. 5 does not limit the electronic device, and the electronic device may include more or fewer components than shown in the figure, or a combination of some components, or different component arrangements. In the embodiments of the present application, the electronic device includes, but is not limited to, mobile phones, tablet computers, notebook computers, personal digital assistants, in-vehicle electronic devices, wearable devices, and pedometers (registered trademarks), etc.

[0057] It should be understood that in the embodiments of the present application, the high-frequency unit 502 can be used for receiving and transmitting information or receiving and transmitting signals in the call process. Specifically, it can receive downlink data from the base station or transmit uplink data to the base station. The high-frequency unit 502 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier, a duplexer, etc.

[0058] The network module 504 provides the user with wireless broadband Internet access, for example, to assist in sending and receiving emails, browsing web pages, and accessing streaming media.

[0059] The audio output unit 506 can convert the audio data received by the high-frequency unit 502 or the network module 504 or stored in the memory 518 into an audio signal and output it as sound. In addition, the audio output unit 506 can also provide audio output related to specific functions executed by the electronic device 500 (e.g., call signal reception sound, message reception sound, etc.). The audio output unit 506 includes a speaker, a buzzer, a receiver, etc.

[0060] The input unit 508 is used to receive audio or video signals. The input unit 508 may include a Graphics Processing Unit (GPU) 5082 that processes still image or video image data acquired by an image capture device (e.g., a camera) in video capture mode or image capture mode, and a microphone 5084. The processed image frames can be displayed on the display unit 512, stored in the memory 518 (or other storage media), or transmitted by the high-frequency unit 502 or the network module 504. The microphone 5084 can receive sound and process such sound as audio data. The processed audio data can be converted into a format that can be transmitted by the high-frequency unit 502 to a mobile communication base station in a telephone call mode and output.

[0061] The electronic device 500 further includes at least one sensor 510 such as a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, an optical sensor, a motion sensor, and other sensors.

[0062] The display unit 512 is used to display information input by the user or information provided to the user. The display unit 512 may include a display panel 5122, and the display panel 5122 can be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like.

[0063] The user input unit 514 can be used to receive input numerical or character information and generate key signal inputs for user settings and function control in the electronic device. Specifically, the user input unit 514 includes a touch panel 5142 and other input devices 5144. The touch panel 5142 is also called a touch screen and can detect the user's touch operation thereon or in its vicinity. The touch panel 5142 may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch orientation, detects the signal caused by the touch operation, and transmits it to the touch controller. The touch controller receives the touch information from the touch detection device, converts it into touch point coordinates and transmits it to the processor 520, and receives and executes the command transmitted from the processor 520. The other input devices 5144 may include a physical keyboard, function buttons (such as volume control buttons, switch buttons, etc.), trackballs, mice, operation levers, but are not limited thereto, and detailed descriptions are omitted here.

[0064] Furthermore, the touch panel 5142 may cover the display panel 5122. When the touch panel 5142 detects a touch operation thereon or in its vicinity, it transmits it to the processor 520 to identify the type of touch event. Then, the processor 520 provides a corresponding visual output on the display panel 5122 according to the type of touch event. The touch panel 5142 and the display panel 5122 may be two separate members or integrated as one member.

[0065] The interface unit 516 is an interface for connecting an external device and the electronic device 500. For example, the external device may include a wired or wireless headphone port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device equipped with a recognition module, an audio input / output (I / O) port, a video I / O port, an earphone port, etc. The interface unit 516 can receive an input (e.g., data information, power, etc.) from the external device and transmit the received input to one or more members within the electronic device 500, or be used to transmit data between the electronic device 500 and the external device.

[0066] The memory 518 can be used to store applications and various data. The memory 518 may mainly include a program storage area capable of storing an operating system, applications required for at least one function (e.g., a voice playback function, an image playback function, etc.), etc., and a data storage area capable of storing data created according to the use of the mobile terminal (e.g., audio data, phone book, etc.). Further, the memory 518 may include a high-speed random access memory, and may further include a non-volatile memory, for example, at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0067] The processor 520 operates or executes the applications and / or modules stored in the memory 518, and calls the data stored in the memory 518, thereby executing various functions and data processing of the electronic device 500, and thereby monitoring the electronic device 500 as a whole. The processor 520 may include one or more processing units, and the processor 520 can integrate an application processor mainly processing an operating system, a user interface, an application, etc., and a modem processor mainly processing image processing operations.

[0068] In the description of this specification, references to terms such as "one embodiment", "several embodiments", "exemplary embodiments", "examples", "specific examples", or "several examples" mean that the specific features, structures, materials, or characteristics described based on the embodiment or example are included in at least one embodiment or example of this application. In this specification, exemplary descriptions of the above terms are not necessarily for the same embodiment or example. And the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0069] As described above, the embodiments of this application have been described with reference to the drawings. However, this application is not limited to the above specific embodiments. The above specific embodiments are merely exemplary and not restrictive. Based on the suggestions of this application, many forms that those skilled in the art can achieve without departing from the spirit and scope of protection of this application's claims all belong to the protection scope of this application.

[0070] The above are merely preferred embodiments of this application and are not for controlling this application. For those skilled in the art, this application may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application all fall within the protection scope of this application.

Description of Reference Signs

[0071] 100 Pixel Circuit 102 Photoelectric Conversion Device 104 Charge Storage Device 1062 First Transfer Transistor 1064 Second Transfer Transistor 108 Exposure Control Signal Memory 1082 Signal Processing Device 1084 Signal Receiving Device 110 Reading Circuit 500 Electronic Device 502 High-Frequency Unit 504 Network Module 506 Audio output unit 508 Input unit 510 Sensor 512 Display unit 514 User input unit 516 Interface unit 518 Memory 520 Processor

Claims

1. A photoelectric conversion device for generating charges based on the photoelectric effect in response to incident light, A charge storage device connected to the photoelectric conversion device for storing the charges generated by the photoelectric conversion device, A first transfer transistor connected to the photoelectric conversion device and the charge storage device for transferring the charges to the charge storage device, A second transfer transistor connected to the photoelectric conversion device for transferring the charges to a predetermined node to discard the charges, An exposure control signal memory connected to the first transfer transistor and the second transfer transistor for generating a charge control signal based on an exposure control signal and controlling the on states of the first transfer transistor and the second transfer transistor, A reading circuit connected to the charge storage device for reading the charges in the charge storage device and outputting an exposure image, The charge storage device is A second charge storage device connected to the second transfer transistor for resetting according to a read command of the reading circuit, A pixel circuit.

2. The pixel circuit according to claim 1, wherein the exposure control signal memory is a unit-bit static random access memory or a unit-bit dynamic random access memory.

3. The unit-bit static random access memory A signal receiving device for receiving the exposure control signal according to a control command of a control terminal of the unit-bit static random access memory, A signal processing device connected to the signal receiving device for generating the charge control signal based on the exposure control signal, The signal receiving device includes a first transistor and a second transistor. The drains of the first transistor and the second transistor are connected to the output terminal of the exposure control signal. The gates of the first transistor and the second transistor are connected to the control terminal of the unit bit static random access memory. The signal processing device includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The sources of the third transistor and the fourth transistor are connected to the first voltage source of the pixel circuit. The gate of the third transistor is connected to the gate of the fifth transistor, the drain of the fourth transistor, the drain of the sixth transistor, the source of the first transistor, and the first transfer transistor, respectively. The gate of the fourth transistor is connected to the gate of the sixth transistor, the drain of the third transistor, the drain of the fifth transistor, the source of the second transistor, and the second transfer transistor, respectively. The sources of the fifth transistor and the sixth transistor are grounded. The pixel circuit according to claim 2.

4. The unit bit dynamic random access memory includes a seventh transistor having a drain connected to the output terminal of the exposure control signal, a gate connected to the control terminal of the unit bit dynamic random access memory, and receiving the exposure control signal according to the control command of the control terminal. a first capacitor having a first end connected to the source of the seventh transistor and the first transfer transistor, respectively, and a second end grounded. an inverter having a first end connected to the first end of the first capacitor and a second end connected to the second transfer transistor. The pixel circuit according to claim 3.

5. The charge storage device further includes a first charge storage device connected to the first transfer transistor and outputting the charge according to the read command of the read circuit. The pixel circuit according to claim 1.

6. The first charge storage device or the second charge storage device is a second capacitor connected to the photoelectric conversion device, and a storage transistor connected to the second capacitor and the reading circuit for transferring the charge in the second capacitor to the reading circuit. The pixel circuit according to claim 5 includes **Claim 7** a floating diffusion node located between the storage transistor and the reading circuit, a reset transistor connected between a second voltage source and the floating diffusion node for resetting the voltage of the floating diffusion node based on a reset control signal, a source follower transistor having a gate connected to the floating diffusion node and a drain connected to the second voltage source, and a row selection transistor having a drain connected to the source of the source follower transistor and a source and a gate connected to the reading circuit. The pixel circuit according to claim 6 further includes **Claim 8** In the pixel circuit according to any one of claims 1 to 4, the first transfer transistor and the second transfer transistor are alternately turned on. **Claim 9** An image sensor including the pixel circuit according to any one of claims 1 to 8. **Claim 10** A circuit board, the image sensor according to claim 9 electrically connected to the circuit board, and a lens provided on a side of the image sensor away from the circuit board. The imaging module includes **Claim 11** An electronic device including the imaging module according to claim 10. ​​​

Images