Method and apparatus for voltage buffering

Abstract

In the illustrated device 108, a first transistor 202 includes a base terminal 208, a first current terminal 206, and a second current terminal 210. The base terminal 208 is coupled to the input voltage node 106. A second transistor 220 has a control terminal 226, a third current terminal 224, and a fourth current terminal 228. The third current terminal 224 is coupled to the second current terminal 210. The fourth current terminal 228 is coupled to a first resistor 236. A second resistor 402 is coupled to the control terminal 226. An inductor 406 is coupled between the first resistor 236 and a ground terminal.

Description

Technical Field

[0001] This application generally relates to buffering, and more particularly to voltage buffering.

Background Art

[0002] A first voltage amplifier stage can be used as a buffer between a voltage input and a second voltage amplifier stage. The voltage gain of an amplifier is the ratio of the amplifier output voltage to the amplifier input voltage. When the amplifier is used as a buffer, the voltage gain of the amplifier is typically 1, which can also be called unity gain. The voltage amplifier can be single-stage or multi-stage. A multi-stage voltage amplifier includes a plurality of cascaded single-stage voltage amplifiers. A single-stage voltage amplifier can have many topologies such as an inverting voltage amplifier, a current follower amplifier, a voltage follower amplifier, etc.

[0003] In an exemplary voltage follower amplifier, the voltage at the output generally follows the voltage at the input. One exemplary voltage follower topology includes a bipolar junction transistor (BJT) connected in an emitter follower configuration. Another exemplary voltage follower topology includes a metal oxide semiconductor field effect transistor (MOSFET) connected in a common drain configuration.

Summary of the Invention

[0004] In an exemplary apparatus, a first transistor has a base terminal, a first current terminal, and a second current terminal. The base terminal is coupled to an input voltage node. A second transistor has a control terminal, a third current terminal, and a fourth current terminal. The third current terminal is coupled to the second current terminal. The fourth current terminal is coupled to a first resistor. A second resistor is coupled to the control terminal. An inductor is coupled between the first resistor and a ground terminal.

Brief Description of the Drawings

[0005]

Figure 1

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Figure 2

[0007]

Figure 3

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Figure 4

[0009]

Figure 5

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Figure 6

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Figure 7

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Figure 8

Mode for Carrying Out the Invention

[0013] The drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and the present specification indicate the same or similar parts. The drawings show each layer and region using clear lines and boundaries, but some or all of these lines and / or boundaries may be idealized. In reality, these lines and / or boundaries may be unobservable, mixed, and / or irregular.

[0014] In at least one example, a buffering circuit is used to transfer a voltage from a first circuit having a high output impedance to a second circuit having a low input impedance. As used herein, impedance is the effective resistance of an electrical circuit or component to alternating current. Impedance represents the combined effect of ohmic resistance (e.g., resistance due to resistive components) and reactance (e.g., resistance due to inductive and capacitive components). Examples of buffering circuits include emitter follower amplifiers, voltage buffers, common collector amplifiers, common source amplifiers, buffer amplifiers, and the like. In some examples, the buffering circuit is used for impedance matching between the output of the first circuit and the input of the second circuit. For example, an emitter follower can be used when any input signal, such as an audio signal, is reproduced by a speaker in the audible frequency range.

[0015] In other examples, the buffering circuit drives the load with a high operating voltage (e.g., the high voltage can vary depending on the application, such as 5 volts, 50 volts, 80 volts, etc.) rather than a low operating current (e.g., tens of milliamperes). In an exemplary operation, the buffering circuit is useful for generating an output voltage that matches the input voltage of the buffering circuit at the load. Thereby, the buffering circuit maintains the output voltage independent of the current load drawn from the output terminal, which is also known as buffering of the input. Some buffering circuits include a current source at the output of the buffering circuit.

[0016] In operation and implementation, the emitter follower includes a first transistor such as a BJT, which causes the voltage at the emitter terminal of the BJT to follow the voltage at the base terminal of the BJT. The base terminal of the BJT is coupled to an input node and is configured to receive an input signal at the input node. The input signal can be an audio or radio frequency signal, an output voltage from a previous amplifier stage, etc. The emitter terminal of the first transistor is coupled to a second transistor (BJT, MOSFET, etc.). The second transistor is coupled between the emitter terminal of the first transistor and ground. In such a configuration, the second transistor operates as a current source. For example, the second transistor provides a high impedance at the emitter terminal of the first transistor while setting the bias current of the first transistor. The second transistor allows a constant DC current to flow through the collector terminal of the first transistor when the collector terminal of the first transistor is coupled to a supply voltage node and does not receive an incoming input signal.

[0017] In an exemplary operation of an emitter follower with a current source, the base terminal of the first transistor receives an input signal. In some examples, the input signal swings (e.g., varies between a relatively high voltage and a relatively low voltage). Under certain conditions (e.g., when the manufacturing specifications of the second transistor are met), the second transistor, functioning as a current source, causes the output signal of the first transistor to swing in response to the input signal. As used herein, "output swing," "signal swing," "voltage swing," and "current swing" are terms used to refer to the offset of the input signal value and time. For example, if the input signal is a sine wave with an amplitude of 1, the signal "swings" from 1 to -1. The units for signal swing can be voltage, current, frequency, etc. (1 volt, 1 ampere, 1 kHz, etc.). In other examples, under conditions where the manufacturing specifications of the second transistor are not met, the second transistor does not allow the output signal to swing in response to the input signal.

[0018] The emitter follower is designed to faithfully represent the input signal at the output. Therefore, the emitter follower will always follow the swing of the input signal. Under conditions where the manufacturing specifications are not met (for example, when the input voltage is too high for types such as BJTs, transistors, MOSFETs, etc.), the output will not faithfully follow the swing of the input. For example, a MOSFET of the type that functions as a current source has specifications corresponding to the amount of input voltage that the MOSFET should receive. Such MOSFET specifications are based on the physical size of the MOSFET. The physical size of the MOSFET is related to the voltage limit that can pass through the MOSFET before its reliability is affected. The voltage limit includes the limit on how much voltage (Vds) the drain terminal and source terminal of the MOSFET can generate. For example, the Vds (of a MOSFET that functions as a current source) is a limit value, and the MOSFET is specified to handle values that do not exceed the threshold above or below the limit value. When the input signal swings to a voltage value below the threshold value of the MOSFET, the Vds of the MOSFET greatly decreases, and as a result, output clipping occurs at the output (for example, the emitter terminal) of the emitter follower. Clipping is a form of waveform distortion that occurs when an amplifier (such as an emitter follower amplifier, a voltage buffer amplifier, etc.) is overdriven (for example, does not meet the manufacturing specifications) and attempts to supply an output voltage or current that exceeds its maximum capacity. In hard clipping, the amplitude of the signal is limited to the maximum amplitude, so the waveform does not have a round top and bottom but becomes flat or cutoff. In soft clipping, the amplitude of the signal saturates along a smooth curve rather than the sharp shape of hard clipping. Also, soft clipping is also known as voltage compression because the amplitude of the waveform is smaller (compressed) than the amplitude of the input signal. As a result of clipping, the output signal does not faithfully follow the input signal.

[0019] Output clipping is a serious problem because it introduces non-linearity to the emitter follower. When a system such as an emitter follower is non-linear, the output of the system is not equal to the input. For example, when the non-linearity of the emitter follower increases due to the decrease in Vds of the current source MOSFET, the output signal of the emitter follower is likely not to follow the input signal (e.g., the output signal is distorted when the input voltage exceeds the manufacturing specifications). Since the emitter follower is designed and implemented for a specific use as a buffer to maintain the input voltage at the output for the load, non-linearity is an undesirable effect.

[0020] The exemplary devices and systems described herein minimize and / or eliminate the non-linearity of an emitter follower with a current source MOSFET by including an inductor coupled to the output of the current source MOSFET. For example, the devices described herein eliminate output signal clipping by including an inductor. Also, the examples described herein reduce the voltage compression of the emitter follower resulting from clipping of the output signal swing.

[0021] Due to the reduction of voltage compression in the emitter follower, the non-linearity of the emitter follower is eliminated. Also, the devices described herein reduce the modulation in the emitter follower when the voltage swing exceeds the threshold value. In this way, the linearity of the emitter follower is improved, the 1 decibel (1 dB) compression point is extended to a new value, and the noise generated between high-frequency input signals is reduced.

[0022] Generally, when the linearity of a device is improved, the 1 dB compression point of the device is also improved (e.g., extended). For example, the 1 dB compression point (e.g., OP1dB, P1dB) is the point at which the current of the input signal reduces the gain of the device at the output by 1 dB from the normal linear gain of the output. Many linear amplifiers have a fixed gain for a specific frequency range. When the output signal versus the input signal is plotted on a graph, a linear relationship is illustrated. The slope of the line is the gain. As the frequency of the input signal continues to increase, at some point the gain begins to decrease. The amplifier enters compression and the output no longer increases in response to an increase in the input. Extending P1dB includes increasing the amount of the input signal (e.g., the voltage of the signal) to the device before the output signal compresses.

[0023] FIG. 1 is a schematic diagram of an exemplary amplification system 100. In some examples, the amplification system uses a voltage buffer, an emitter follower, a source follower, etc. to buffer the signal provided by the input terminal. The amplification system 100 includes an exemplary first-stage amplifier 102 that includes a first-stage input 104 and a first-stage output 106. The amplification system 100 includes a buffer 108 coupled to the first-stage output 106, a bias voltage terminal (Vbias) 110, and a voltage supply (Vsupply) 112. The output 114 of the buffer 108 is coupled to a second-stage amplifier 118 that includes a load output 120.

[0024] In FIG. 1, the amplification system 100 includes a first-stage amplifier 102 that receives the first-stage input 104 and adjusts the amplitude of the first-stage input 104 based on each load. For example, the first-stage input 104 can be a sine wave with a negligible value for a load such as a speaker. The first-stage amplifier 102 can operate to increase and / or boost the amplitude of the first-stage input 104 and reproduce an amplitude such as that of the first-stage input 104. The first-stage amplifier 102 provides the adjusted input signal to the buffer 108 via the first-stage output 106. The first-stage amplifier 102 can be a voltage amplifier, a current amplifier, an operational amplifier, a MOSFET, a BJT, or any other electrical device suitable for adjusting the amplitude of the first-stage input 104.

[0025] In FIG. 1, the amplification system 100 includes a buffer 108 for buffering the received first-stage output 106 for the second-stage amplifier 118. As used herein, the first-stage output 106 is referred to as the input 106 such that the voltage and current on the "first-stage output" 106 and the "input" 106 are equal. The buffer 108 is configured to receive a supply voltage 112 via a supply voltage terminal and a bias voltage via Vbias110 for a particular operation of the buffer 108. In some examples, the buffer 108 can be an emitter follower, a source follower, a common collector amplifier, and / or any other device that can buffer an input voltage. In the example described herein, the buffer 108 includes a single-ended output (e.g., 114) with a single-ended input 106. Alternatively, the buffer 108 can be a differential buffer amplifier configured to receive two inputs and include two outputs for a non-differential buffer amplifier with a single-ended input and a single-ended output.

[0026] In some examples, the buffer 108 receives the input 106 as a sine wave and reproduces (e.g., buffers) that sine wave at the output 114. The buffer 108 will be described in further detail hereinafter in connection with FIGS. 2 and 3.

[0027] In FIG. 1, the amplification system 100 includes a second-stage amplifier 118 for increasing the gain applied to the input 106 in addition to the gain applied to the first-stage input 104 by the first-stage amplifier 102. For example, when multiple amplifier stages are used in series, the overall voltage gain can be increased. For example, if the first-stage amplifier 102 has a gain of 10 and the second-stage amplifier 118 also has a gain of 10, the total gain applied to the original first-stage input 104 is 20, so the first-stage input 104 receives twice the amount of gain compared to what the first-stage input 104 would receive if only one amplifier were present.

[0028] In some examples, the second stage amplifier 118 increases the overall gain applied to the first stage input 104 for the load. For example, the load is a speaker and the first stage input 104 is an audio signal. The second stage amplifier 118 increases the audio signal to a value that meets the threshold of that speaker in order to generate an audible frequency (e.g., audio that can be heard by a user). In this way, the amount of gain generated by the second stage amplifier 118 can be determined by the load.

[0029] In some examples, there is no buffer (e.g., buffer 108) between the first stage amplifier 102 and the second stage amplifier 118. In the case of no buffer, the impedance on the first stage amplifier 102 is the input resistance (e.g., impedance) of the second stage amplifier 118. When the first stage amplifier 102 directly controls the second stage amplifier 118, the "low" input impedance of the second stage amplifier 118 "loads down" the first stage amplifier 102, thus reducing the voltage swing. Therefore, in order to increase the impedance at the load, it is desirable to include a voltage amplifier / buffer (e.g., an emitter follower, a source follower, etc.) between the two amplifier stages (e.g., 102, 118). By inserting the buffer 108, the impedance between the first stage amplifier 102 and the load becomes high impedance. As a result of the high impedance, the swing from the first stage amplifier 102 is not loaded down. The buffer 108 then reproduces the output swing on the buffer output 114 in order to drive the second stage amplifier 118.

[0030] The second stage amplifier 118 can be a current amplifier, an operational amplifier, a MOSFET, a BJT, or any other electrical device suitable for adjusting the amplitude of the signal on the output 114.

[0031] Figure 2 is a schematic diagram showing additional details of the implementation of the buffer of Figure 1. The buffer includes a first transistor 202, a second transistor 204, a first resistor 218, a first current source 220, and a second current source 222. In the buffer, since the buffer of Figure 2 is a differential implementation, the right side of the schematic diagram (e.g., the second transistor 204 and the second current source 222) can be identified as a replica of the left side of the schematic diagram (e.g., the first transistor 202 and the first current source 220). The differential implementation can be referred to as an implementation including a non-inverting input (106), an inverting input (the dashed line coupled to the second base terminal 214), a non-inverting output (114), and an inverting output (the dashed line coupled to the emitter node 217). The buffer of Figure 2 exhibits undesirable characteristics such as clipping, unintentional modulation, reduction of the compression point (OP1dB), and increase of intermodulation distortion (IMD3) when operating in a large signal operation (e.g., the large signal is with respect to the sizes of the transistors and resistors).

[0032] As used herein, when referring to the "first transistor 202", it should be understood that the description and / or drawings apply to both the first transistor 202 and the second transistor 204. Similarly, when referring to the "first current source 220", it should be understood that the description and / or drawings apply to both the first current source 220 and the second current source 222. In this way, the second transistor 204 and the second current source 222 are replicas of the first transistor 202 and the first current source 220, and can be understood to operate in the same manner as each other. However, the second transistor 204 receives an input signal that is 180 degrees out of phase with the input signal applied to the first transistor 202 from the input 106.

[0033] In FIG. 2, the buffer includes a first transistor 202 and a second transistor 204 for flowing current from the collector terminal to the emitter terminal. The first transistor 202 includes a first collector terminal 206 coupled to a first resistor 218 at a collector node 207, a first base terminal 208 coupled to input 106 and configured to receive an input signal via input 106, and a first emitter terminal 210 coupled to output 114 at an emitter node 211. The second transistor 204 includes a second collector terminal 212 coupled to the first resistor 218 and the first collector terminal 206 at the collector node 207, a second base terminal 214 coupled to the inverting input and configured to receive an inverting input signal (-Vin), which is the inverse of the input signal at input 106, via the inverting input, and a second emitter terminal 216 coupled to the output at an emitter node 217. The output has an inverted output signal (-Vout), which is the inverse of the output signal at output 114.

[0034] In FIG. 2, the first transistor 202 and the second transistor 204 are N-type (NPN) BJTs. The first transistor 202 and the second transistor 204 can be either on (e.g., conducting) or off (e.g., non-conducting). When transistors 202 and 204 are on, the base terminals 208 and 214 may vary the amount of current conducting through the collector terminals 206, 212, or may not vary the amount of current conducting through the collector terminals 206, 212. In FIG. 2, transistors 202, 204 are normally always on so that transistors 202, 204 reproduce the input signal 106. In this way, the voltage at the collector node 207 (e.g., provided by Vsupply 112 and the resistance of R1 218) sets the collector voltage.

[0035] Also, in FIG. 2, the first resistor 218 is included in the buffer to shift the DC voltage provided to the first collector terminal 206 and the second collector terminal 212. The supply voltage 112 can be greater than the input voltage on input 106 and the output voltage on output 114. The first transistor 202 generates a voltage at output 114 in response to the voltage at input 106. Thus, when the input voltage of the first transistor 202 decreases, the voltage at output 114 also decreases. When the voltage on output 114 decreases, the voltage (Vce) from the collector to the emitter of the first transistor 202 increases. If the supply voltage 112 is greater than the threshold value of the collector-emitter voltage (Vce) of the transistor 202, the first transistor 202 can be damaged. Therefore, the first resistor 218 is introduced to bias the Vce of the first transistor 202 within the operating conditions of the first transistor 202.

[0036] In FIG. 2, the buffer includes a first current source 220 and a second current source 222 to bias the currents at the first emitter terminal 210 and the second emitter terminal 216. The first current source 220 includes a first drain terminal 224 coupled to the first emitter terminal 210 at emitter node 211, a first control terminal 226 (e.g., gate) coupled to Vbias110, and a first source terminal 228 coupled to the second resistor (R2) 236. The second current source 222 includes a second drain terminal 230 coupled to the second emitter terminal 216 at emitter node 217, a second control terminal 232 (e.g., gate) coupled to Vbias110, and a second source terminal 234 coupled to the third resistor (R3) 238.

[0037] In FIG. 2, the first current source 220 operates as a current mirror and is an n-channel MOSFET (NFET) that essentially biases the current at the emitter node 211. Alternatively, the first current source 220 can be an NPN BJT, a PNP BJT, a p-channel MOSFET (PFET), or the like. By controlling the current conducting through different active devices while keeping the current constant, the current mirror copies the current conducting through a certain active device. For example, the first current source 220 sets the current flowing into the emitter terminal 210 of the first transistor 202.

[0038] The NFET includes two current terminals and a control terminal (e.g., gate) where the first current terminal is the drain terminal and the second current terminal is the source terminal. The control terminal of the NFET controls the current conducting from the drain terminal to the source terminal. The NFET operates in the saturation mode when the gate-source voltage (Vgs) > the threshold voltage (Vth), and when the drain-source voltage (Vds) is greater than Vgs minus Vth (e.g., Vgs > Vth; Vds > Vgs - Vth). When the NFET is in the saturation mode, the drain terminal and the source terminal operate as a current source. After the voltage exceeds the threshold for saturation, the current conducting through the two terminals does not change significantly in response to the increase in the Vds voltage. After Vds exceeds Vth, the transistor operates as a current source and the current does not change when Vds increases beyond the saturation voltage.

[0039] The first current source 220 operates in the saturation mode as a current source for the first transistor 202. Thus, the voltage at Vbias110 is a constant bias voltage, and therefore, the current conducting from the first drain terminal 224 to the first source terminal 228 is constant. The voltage at Vbias110 is set to a certain value with respect to the voltage signal on the input 106.

[0040] In FIG. 2, the first source terminal 228 is coupled to R2 236. R2 236 is a degeneration resistor. A degeneration resistor is useful in current source designs, as it "degenerates" or reduces the gain of the current source transistor, while improving other aspects such as linearity and output impedance. The degeneration resistor R2 236 minimizes the noise generated at the first source terminal 228. Also, R2 236 sets the voltage at the first source terminal 228. The voltage at the source terminal 228 is determined by multiplying the resistance (e.g., ohms) by the current flowing through R2 236. The current flowing through R2 236 can be the current from the first drain terminal 224.

[0041] In the operation of the buffer, an incoming voltage signal is applied to input 106. As used herein, the voltage signal on input 106 is Vin. Typically, Vin swings. When Vin swings, output 114 swings. Vin is applied to the first base terminal 208, and when Vin swings, the voltage at the first emitter terminal 210 begins to swing.

[0042] Also, since the voltage at the first emitter terminal 210 is swinging, the voltage at the first collector terminal 206 can swing. However, the buffer is differentially implemented, which means that the second transistor 204 receives an input 106 that is adjusted to have a 180-degree phase difference with respect to the Vin signal. Due to this differential implementation, the voltage at the second collector terminal 212 cancels out the voltage swing at the first collector terminal 206 when Vin swings. In this way, the voltage at the first collector terminal 206 and the voltage at the second collector terminal 212 have opposite polarities, opposite phases, etc. Also, node 207 is a quiescent node because the two voltages at the first collector terminal 206 and the second collector terminal 212 cancel each other out. In this way, the only variations in the voltage generated in the buffer occur at input 106 and output 114.

[0043] The voltage on output 114 swings in the positive or negative direction. When Vin increases, since Ic decreases, the voltage on output 114 swings in the positive direction. The voltage on output 114 can increase until the voltage reaches the voltage of Vsupply112. When the voltage on output 114 reaches Vsupply112, there is zero voltage drop across the resistor of the first collector terminal 206, which indicates zero Ic. When Ic is zero, the first transistor 202 does not conduct current, and in response, the first transistor 202 enters the cut-off mode (e.g., is turned off).

[0044] When Vin decreases, since Ic increases, the voltage on output 114 swings in the negative direction. The voltage on output 114 can decrease until the voltage on output 114 equals the drain-source voltage (Vds) of the current source 220 that does not meet the threshold for keeping the MOSFET on. For the current source 220 to operate in the linear mode (e.g., is turned on and conducting), the Vds of the current source 220 needs to be greater than the voltage obtained by subtracting the threshold voltage (Vth) from the gate-source voltage (Vgs) (e.g., Vgs > Vth; Vds > Vgs - Vth). When the voltage on output 114 swings in the negative direction, Vds can drop below the voltage obtained by subtracting Vth from Vgs, and thus, the current source 220 can be turned off.

[0045] The operation of the current source is determined by the bias voltage at Vbias110. The voltage at Vbias110 is a constant voltage that determines the DC current conducting through the current source 220. The voltage at Vbias110 sets Vgs. Vgs determines the current conducting through the current source 220. The current conducting through the current source 220 is equal to the current Ic conducting at the first collector terminal 206. In the operation of the buffer in FIG. 2, when the input voltage signal Vinp is swinging, the voltage at the first emitter terminal 210 swings, while the voltage at the first collector terminal 206 remains unchanged. The voltage at the first collector terminal 206 does not change (modulate, wiggle, swing, etc.) because the node 207 is a resting node and holds the voltage at the first collector terminal 206 (and the voltage at the second collector terminal 212) at zero potential. In this way, the collector-emitter voltage (Vce) fluctuates. Also, when the voltage at the emitter node 211 swings in the negative direction, the voltage at the first drain terminal 224 begins to drop. When the voltage at the first drain terminal 224 is dropping, the Vds of the current source 220 begins to modulate (change, vary in amplitude, etc.), and the current flowing through the MOSFET changes.

[0046] It is not desirable for the Vds of a current source (e.g., current source 220) to drop below Vgs - Vth. For example, when the Vds of current source 220 drops below Vgs - Vth, an ideal, specified, and / or desired current source is not specified such that the current conducted through the MOSFET varies as the Vds varies. The current source 220 of the buffer in FIG. 2 can vary due to a certain value of "headroom". Headroom is a characteristic of the MOSFET defined during the manufacture of the MOSFET. The headroom of the MOSFET determines the tolerance or threshold range of the voltage swing between the drain and source. This is the range within which the drain current (Id) does not change. For example, a manufacturer can design the MOSFET to allow a voltage swing (e.g., the voltage at the control terminal of the MOSFET) with values from -1 volt to 1 volt. When the input voltage drops below -1 volt (e.g., to -1.5 volts), the drain current begins to clip (e.g., decrease).

[0047] Referring to FIG. 3, signal plot 300 illustrates the voltage at the first control terminal 226 (e.g., the voltage provided by Vbias110), the voltage at the first source terminal 228, and the voltage at the first emitter terminal 210 (e.g., the voltage at the first emitter terminal 210 is also equal to the voltage at the emitter node 211, the voltage at output 114, and the voltage at the first drain terminal 224). The gate voltage (e.g., the voltage at Vbias110) is held and / or maintained at a constant value (e.g., 0.7 volts). In response to the gate voltage being held at a constant value, the source voltage at the first source terminal 228 is also held at a constant value (e.g., 0.2 volts).

[0048] The voltage at the first emitter terminal 210 (e.g., the voltage at the first drain terminal 224, the voltage at the emitter node 211) is illustrated as a sine wave resulting from the swing of the incoming voltage signal on input 106. The average voltage (DC) of the sine wave at the first emitter terminal 210 is equal to 0.8 volts. In operation, when the emitter voltage (e.g., the voltage at the first drain terminal 224) moves from 0.8 DC to a value obtained by subtracting the voltage swing from 0.8 DC, the Vds of the first current source 220 begins to decrease below the value obtained by subtracting the threshold voltage from the voltage at Vbias110. When the Vds of the first current source 220 decreases below the voltage at Vbias110, the drain current of the first current source 220 clips in response to the decrease in the headroom of the first current source 220.

[0049] When the emitter voltage at the first emitter terminal 210 varies significantly beyond a specified value of the operation of the current source 220, problems occur in the buffer of FIG. 2. Typically, the drain-source voltage of the current source 220 does not affect the drain current (e.g., the current at the emitter node 211) until the drain-source voltage reaches a value (e.g., a voltage value defined by the manufacturer as the threshold amount of swing that a MOSFET can encounter before compression occurs). As illustrated in FIG. 3, the emitter voltage exceeds the threshold value defined by the manufacturer, whereby the drain current (e.g., the current at the emitter node 211) is adversely affected by the drain-source voltage of the first current source 220. When the drain current begins to clip, the buffer becomes unavailable for the operation in the amplification system 100 of FIG. 1 (e.g., due to an increase in non-linearity / compression).

[0050] The example of FIG. 4 illustrates additional details of the implementation of buffer 108 of FIG. 1 that includes bias resistors and inductors. Buffer 108 of FIG. 4 overcomes the problems and issues of the buffer of FIG. 2 (e.g., one that does not include an inductor and bias resistors) as described above in connection with FIGS. 2 and 3. Buffer 108 of FIG. 4 includes an input terminal (e.g., input 106), an output terminal (e.g., output 114), a first transistor 202, a second transistor 204, a first resistor 218, a first current source 220, a second current source 222, a second resistor 236, a third resistor 238, an exemplary first bias resistor 402, an exemplary second bias resistor 404, an exemplary first inductor 406, and an exemplary second inductor 408.

[0051] FIG. 4 includes a first transistor 202 and a second transistor 204 for buffering a boosted input signal for a second stage amplifier (e.g., second stage amplifier 118 of FIG. 1). In some examples, the first transistor 202 and the second transistor 204 are differential BJTs, and the second transistor 204 may receive an adjusted input signal that is 180 degrees out of phase with the input signal on input 106 of the first transistor 202. The first transistor 202 and the second transistor 204 each have current terminals that are base terminals, collector terminals, and emitter terminals. In some examples, the second transistor 204 is a differential transistor with differential current terminals that are differential base terminals, differential collector terminals, and different emitter terminals. The first transistor 202 and the second transistor 204 are described above in connection with FIG. 2.

[0052] FIG. 4 includes a first resistor 218 coupled between a supply voltage 112 and a collector node 207. The first resistor 218 biases the Vce of the first transistor 202 and the second transistor 204 within the operating ranges of the first transistor 202 and the second transistor 204. In some examples, since Vsupply112 provides a voltage that is too large for the transistors 202, 204 to handle, the first resistor 218 is configured to reduce that voltage.

[0053] FIG. 4 includes a first current source 220 and a second current source 222 for biasing the voltages at the first emitter terminal 210 and the second emitter terminal 216 of the first and second transistors 202, 204. Also, a differential current source (e.g., the second current source 222) receives a differential input voltage with respect to the voltage at Vbias110 provided to a first control terminal 226. The first current source 220 and the second current source 222 are described above in connection with FIG. 2.

[0054] FIG. 4 includes a second resistor 236 and a third resistor 238 to minimize the noise generated at the first source terminal 228 and the second source terminal 234. Also, R2 236 and R3 238 set the voltages at the first source terminal 228 and the second source terminal 234. The second resistor 236 and the third resistor 238 are described above in connection with FIG. 2.

[0055] FIG. 4 includes an exemplary first bias resistor 402 and an exemplary second bias resistor 404. The first bias resistor 402 is coupled between Vbias110 and a first control terminal 226 of the first current source 220. The second bias resistor 404 is coupled between Vbias110 and a second control terminal 232 of the second current source 222.

[0056] FIG. 4 includes a first inductor 406 and a second inductor 408. The first inductor 406 is coupled between the second resistor 236 and a ground terminal. The second inductor 408 is coupled between the third resistor 238 and a ground terminal.

[0057] In the operation of buffer 108 of FIG. 4, when a voltage is applied to input 106, the differential of the voltage on input 106 is applied to the second base terminal 214 of the second transistor 204. For example, the voltage applied to the first base terminal 208 on input 106 is inverted and applied to the second base terminal 214. In response to the swing input voltage signal at the first base terminal 208, the first emitter terminal 210 replicates the input voltage signal. For example, when the input voltage signal is swinging from 1 volt to -1 volt, the output voltage signal at the first emitter terminal 210 is swinging from 0.7 volts below 1 volt to 0.7 volts below -1 volt. The output of emitter terminal 210 and any emitter terminal of the BJT has a voltage drop across the BJT device (e.g., the first transistor 202) when turned on, so it is lower than the voltage applied to the base terminal by the diode voltage (e.g., 0.7 volts). The voltage at the first emitter terminal 210 is also the voltage at the first drain terminal 224 of the current source 220. In this way, when the input voltage signal at the first base terminal 208 is swinging, the voltage at the first drain terminal 224 swings.

[0058] In an exemplary implementation without inductors 406, 408 and bias resistors 402, 404, if the swing of the input signal decreases below the headroom values of current sources 220 and 222, current sources 220 and 222 may fail. Also, if the swing of the input signal increases above the allowable Vds values of current sources 220, 222, there may be reliability constraints. However, buffer 108 of FIG. 4 includes a first bias resistor 402 and a first inductor 406, which is a structure that provides two main advantages. The first advantage is that when the voltage at input 106 is swinging, a voltage swing is achieved at the first source terminal 228, so that the bias resistor 402 and inductor 406 float and move the voltage at the first control terminal 226 and the voltage at the first source terminal 228 in response to the voltage swing at the first drain terminal 224, thereby maintaining the MOSFET headroom. For example, the voltage at the first control terminal 226 and the voltage at the first source terminal 228 increase and decrease in accordance with the voltage at the first drain terminal 224, and as a result, the voltages at the first control terminal 226 and the first source terminal 228 increase in response to an increase in the voltage at the first drain terminal 224 and decrease in response to a decrease in the voltage at the first drain terminal 224. The second advantage of the exemplary bias resistor / inductor configuration is that the bias resistor / inductor configuration adjusts the drain-source voltage of current source 220, thereby preventing current source 220 from "clutching" (e.g., compressing) in response to a large voltage swing. In this way, the first bias resistor 402 operating with the first inductor 406 implements the high-signal operation of the first-stage amplifier 102 of FIG. 1, so that the first-stage amplifier 102 can boost a large signal without clipping or damaging the buffer 108 of FIG. 1.

[0059] In connection with the first advantage of the exemplary bias resistor / inductor configuration, bias resistors 402 and 404 are set to a large value (e.g., 1 kiloohm or 10 kiloohms) to provide a high impedance on the first control terminal 226. The high impedance of bias resistor 402 generates a voltage swing at the first drain terminal 224 at the terminals of current source 220 (e.g., the first control terminal 226 and the first source terminal 228). For example, a MOSFET has no gate current (e.g., the control terminal of the MOSFET is isolated from the substrate of the MOSFET by a dielectric medium that does not conduct current from the control terminal to the drain and source terminals). In this way, the DC bias of the first current source 220 (biased by the voltage at Vbias110) is not affected by the first bias resistor 402. The reason is that (a) the voltage applied across the first bias resistor 402 can also be applied at the first control terminal 226 and (b) no current flows through the first bias resistor 402. In this way, the first current source 220 receives the correct gate voltage.

[0060] However, from an AC perspective, when the voltage at the first drain terminal 224 begins to swing, the voltage at the first control terminal 226 begins to swing. For example, the first bias resistor 402 does not hold the voltage at a fixed value but rather floats the voltage at the first control terminal 226. Thus, when the voltage at the first drain terminal 224 begins to swing, the first bias resistor 402 achieves a voltage swing at the first control terminal 226 while the drain voltage is swinging.

[0061] The first bias resistor 402 ensures that the Vgs of the first current source 220 remains constant. For example, the resistance set by a resistor (e.g., the first bias resistor 402) determines the voltage across the resistor. By ensuring that the Vgs of the first current source 220 is constant, the current in the first current source 220 (e.g., the current set by the Vgs and Vds of the MOSFET) is not modulated. In this way, the first bias resistor 402 and the first inductor 406 increase the linearity of the current source representing the incoming voltage on the input 106 at the output 114.

[0062] A second advantage of the exemplary bias resistor / inductor configuration is that the first current source 220 does not compress when the voltage at the input 106 approaches the threshold voltage. For example, in response to a large voltage swing at the input 106, when a large voltage swing is applied to the first drain terminal 224, the first current source 220 does not compress. For example, if the inductor is not coupled between the end of the source terminal and ground or the supply terminal (e.g., the buffer in FIG. 2), the source terminal remains constant. In such an example, the source terminal 228 of the MOSFET can be held at the ground potential or the voltage supply potential. However, by including the first inductor 406, the voltage at the first source terminal 228 can swing below the ground potential or above the supply voltage potential.

[0063] The first bias resistor 402 swings the voltage at the first control terminal 226 together with the drain voltage because the voltage across the inductor is determined by multiplying L (e.g., inductance value) by di / dt (e.g., the rate of change of current over time in the inductor). When the voltage at the input 106 to the buffer 108 is swinging down (e.g., when the voltage is decreasing), Vce increases, thereby increasing the instantaneous current at the collector terminal 206 and, similarly, at the inductor 406. This means that the voltage across the inductor 406 should be positive, which can occur when the voltage at the node between R2 236 and L1 406 swings below ground. The voltage across the inductor 406 is defined as the voltage at one terminal of the inductor (e.g., the terminal coupled to R2 236) minus the voltage at a fixed potential (e.g., ground). Subtracting a negative voltage from a fixed potential generates a positive voltage. When the voltage at the input 106 to the buffer 108 swings up (e.g., the voltage increases), the Vce of the first transistor 202 decreases, thereby decreasing the instantaneous current at the collector terminal 206 and, similarly, at the inductor 406. In response to the decrease in the instantaneous current, a negative potential is generated across the inductor 406. A negative potential is generated when the voltage at the node between R2 236 and L1 406 swings above ground. Subtracting a positive voltage from a fixed potential generates a negative voltage across the inductor 406.

[0064] The exemplary inductor has a coil with wire wound around a central core. Inductors 406, 408 can be compact low-Q inductors having a Henry value determined by the frequency of the amplifier system 100 of FIG. 1. For example, the first inductor 406 has a smaller inductance (e.g., nanohenries) for higher frequencies and a larger inductance (e.g., microhenries) for lower frequencies. The Q factor (Q) is a measure of the dissipation characteristics of the inductor. A high-Q inductor has low dissipation and is useful for creating a finely tuned narrowband circuit. A low-Q inductor has high dissipation and as a result has broadband performance. The low-Q inductor has higher resistive dissipation, which can be traded off against the resistor values of R2 236 and R3 238.

[0065] Inductor 406 causes buffer 108 to operate in a specified manner when the incoming voltage signal on input 106 is greater than the voltage that current source 220 can handle. For example, referring to FIG. 5, signal plot 500 shows the voltage at emitter node 211, the voltage at the first source terminal 228, and the voltage at the first control terminal 226. The voltage at the first control terminal 226 floats due to the first bias resistor 402. Bias resistor 402, described above in connection with FIG. 4, facilitates movement of the voltage at the first control terminal 226 in response to the voltage at emitter node 211. Also, due to the first inductor 406, the voltage at the first source terminal 228 also floats in response to the voltage at emitter node 211.

[0066] FIG. 6 is a simulated signal plot 600 illustrating the voltage through buffer 108 of FIG. 4. The simulated signal plot 600 includes the voltage at the first base terminal 208, the voltage at emitter node 211, the voltage at the first control terminal 226, and the voltage at the first source terminal 228.

[0067] As shown in FIG. 6, at time t1, the voltage at the first base terminal 208 is about 1 volt. In some examples, 1 volt represents the voltage value corresponding to the incoming input signal 106, and thus the amplifier (e.g., the first-stage amplifier 102) outputs 1 volt to the buffer 108 (e.g., or the buffer 108 including bias resistors 402, 404 and inductors 406, 408).

[0068] At time t1, the voltage at the emitter node 211 is about 0.3 volts. Since the diode drop of the first transistor 202 is 0.7 volts, the voltage at the emitter node 211 is about 0.3 volts, and thus the first transistor 202 has a 0.7-volt drop from the collector to the emitter terminal, and the output is 0.7 volts below the voltage at the base terminal 208.

[0069] In FIG. 6, the voltage at the first control terminal 226 is represented by a dashed line. At time t1, the voltage of the first control terminal 226 is equal to the voltage at the emitter node 211. For example, the bias resistor 402 is set such that the voltage at the first control terminal 226 follows / swings with the voltage at the emitter node 211. Similar to the first transistor 202, the first current source 220 has a threshold voltage of 0.7 volts. Thus, at time t1, the voltage at the first source terminal 228 is 1 threshold voltage lower than the voltage at the first control terminal 226. For example, at time t1, the voltage at the first source terminal 228 is equal to -0.3 volts.

[0070] In this way, the simulated signal plot 600 shows that the voltage at the first source terminal 228 drops below zero volts (e.g., ground potential). This is the result of the first inductor 406 accumulating a positive or negative voltage across the inductor 406 because the polarity of the voltage is determined by the rate of change of the current in the inductor 406. A decrease in the AC current means a negative voltage across the inductor 406, and an increase in the AC current means a positive voltage across the inductor 406.

[0071] At time t2, the voltage at the first base terminal 208 increases to approximately 2.8 volts. For example, since the incoming voltage signal on input 106 is swinging, the voltage at the first base terminal 208 increases and decreases. At time t2, the voltage at the emitter node increases in response to the increase in the voltage at the first base terminal 208. The increase in the voltage at emitter node 211 is less than one diode drop below the increase in the voltage at the first base terminal 208.

[0072] In response to the voltage at emitter node 211 increasing at time t2, the voltage at the first control terminal 226 and the voltage at the first source terminal 228 increase in response to the voltage at emitter node 211. For example, the voltage at the first control terminal 226 follows the voltage at emitter node 211, and the voltage at the first source terminal 228 increases less than one threshold voltage below the voltage at the first control terminal 226.

[0073] FIG. 7 is a signal plot 700 comparing the operation of buffer 108 of FIG. 4 and the buffer of FIG. 2. In FIG. 7, signal plot 700 shows the response of the voltage on emitter node 211 when the input voltage on input 106 increases and decreases. For example, three voltages are shown in FIG. 7. Input voltage 702 represents the voltage on input 106 of FIGS. 1, 2, and 4. The first voltage signal 704, shown by a dashed line, represents the voltage at emitter node 211 of a buffer without bias resistor 402 and inductor 406. The second voltage signal 706 represents the voltage at emitter node 211 of buffer 108 of FIG. 4.

[0074] In FIG. 7, the input voltage 702 is swinging. For example, the input voltage at time t1 is a value of 0.5 volts and increases to 3 volts at time t2. The increase and decrease of input voltage 702 continue with the increase in time.

[0075] The first voltage signal 704 is represented by a dashed line corresponding to the voltage at the emitter node 211 of the buffer without the bias resistor 402 and the inductor 406. At time t1, the first voltage signal 704 does not decrease beyond approximately 0.3 volts. In fact, the signal plot 700 illustrates the first voltage signal 704 that clips from time t1 to time t2. The first voltage signal 704 clips in response to an input voltage 702 that decreases beyond the headroom set by the current source 220 in FIG. 2.

[0076] The second voltage signal 706 shows an improvement over the first voltage signal 704 corresponding to the voltage at the emitter node 211 of the buffer 108 in FIG. 4. For example, from time t1 to time t2, the second voltage signal 706 decreases in response to the input voltage 702. In this way, the second voltage signal 706 does not clip when the voltage at the source terminal 228 decreases.

[0077] FIG. 8 is a noise figure plot 800 comparing the noise factors of the buffer 108 in FIG. 4 and the buffer in FIG. 2. In FIG. 8, the noise figure plot 800 shows the response of the noise factor of the buffer 108 in FIG. 4 and the noise factor of the buffer in FIG. 2 as the frequency at the input 106 increases.

[0078] The noise factor is a measure of the degradation of the signal-to-noise ratio of a circuit caused by components in the signal chain. The noise factor is a number that can specify the performance of an amplifier or a radio receiver, and a lower value indicates better performance. The noise factor is a measure expressed in decibels (dB).

[0079] In FIG. 8, a first noise factor 802, illustrated as a dashed line, corresponds to a buffer without the bias resistor 402 and the inductor 406. The first noise factor 802 is represented as a dashed line. In the illustrated example, at a frequency of about 4 gigahertz (GHz), the first noise factor 802 is equal to about 3.45 decibels. Thus, when the frequency at the input 106 of the buffer is equal to 4 gigahertz, the noise factor is equal to 3.45 decibels.

[0080] In FIG. 8, a second noise factor 804 corresponds to the buffer 108 of FIG. 4. The second noise factor 804 is represented by a solid line. In the illustrated example, when the frequency at the input 106 is equal to 4 gigahertz, the second noise factor 804 is equal to 3.3 decibels. The overall noise in the buffer 108 is reduced compared to the overall noise in a buffer without a resistor / inductor configuration. For example, the bias resistor / inductor configuration provides more voltage headroom to the current source 220, thereby reducing the noise factor of the current source 220 and further reducing the overall noise in the buffer 108. In this way, the buffer 108 shows an improvement in the noise factor compared to the buffer of FIG. 2, which does not include the bias resistor 402 and the inductor 406.

[0081] As used herein, the term "and / or" (when used in the form A, B, and / or C, etc.) refers to any combination or subset of A, B, C, such as, for example, (a) only A, (b) only B, (c) only C, (d) A and B, (e) A and C, (f) B and C, and (g) A, B, and C. Also, as used herein, the term "at least one of A or B" (or "at least one of A and B") refers to an implementation that includes any of (a) at least one A, (b) at least one B, and (c) at least one A and at least one B.

[0082] The exemplary methods, apparatuses, and products described herein improve the linearity of voltage buffers such as emitter followers, source followers, etc. In the examples described herein, the linearity of the voltage buffer is improved by floating the control terminal of a current source through a bias resistor. Also, when the input signal is larger than what a switching device (such as a MOSFET or BJT) can handle, an inductor minimizes and / or reduces the compression of the current source. Further, the bias resistor / inductor configuration protects the current source of the buffer from compression or damage when the input signal exceeds a threshold set by the manufacturer of the current source.

[0083] Within the scope of the claims, changes in the described embodiments are possible and other embodiments are possible.

Claims

1. A first transistor having a first input terminal, a first output terminal, and a current terminal, configured to receive a first input voltage at the first input terminal and buffer the first input voltage to supply a voltage to the first output terminal, the first transistor; A first current source having a first control terminal, a first current terminal coupled to the first output terminal, and a second current terminal, configured to supply a current to the first output terminal, the first current source; A first resistor coupled between the current terminal of the first transistor and a voltage supply node; A second resistor coupled to the first control terminal; A first inductor coupled between the second current terminal and a reference voltage node; Including; The first resistor and the first inductor are configured to reduce compression of the first current source when the first input voltage approaches a first threshold voltage in the first current source, the reducing including adjusting a voltage swing between the first current terminal and the second current terminal when the first input voltage is swinging, an apparatus.

2. The apparatus according to claim 1, Wherein the first threshold voltage is a voltage at which the first current terminal and the second current terminal can receive a voltage without compressing the first current source, an apparatus.

3. The apparatus according to claim 1, Wherein the second resistor is configured to generate a high impedance at the first control terminal, an apparatus.

4. The apparatus according to claim 1, Wherein the first inductor is configured to reduce the voltage at the second current terminal below a reference voltage at the reference voltage node or increase the voltage at the second current terminal above a supply voltage, an apparatus.

5. The apparatus according to claim 4, Wherein the first inductor is configured to reduce the voltage at the second current terminal below the reference voltage when the first input voltage is swinging below the reference voltage, and configured to increase the voltage at the second current terminal above the supply voltage when the first input voltage is swinging above the supply voltage, an apparatus.

6. The apparatus according to claim 1, An apparatus, wherein the second resistor and the first inductor are further configured to maintain the first threshold voltage when the first input voltage is swinging. **Claim 7** The apparatus according to claim 1, wherein the second resistor is configured to bias the voltages at the first control terminal and the second current terminal. **Claim 8** The apparatus according to claim 1, comprising a second transistor having a second input terminal and a second output terminal, a second current source having a second control terminal, a third current terminal coupled to the second output terminal, and a fourth current terminal, the second current source being configured to bias a current to the second output terminal. **Claim 9** The apparatus according to claim 8, wherein the second transistor is configured to receive a second input voltage at the second input terminal, wherein the second input voltage has a 180-degree phase difference from the first input voltage, and the voltage at the second output terminal has a 180-degree phase difference from the voltage at the first output terminal. **Claim 10** The apparatus according to claim 9, further comprising a third resistor coupled to the second control terminal, and a second inductor coupled between the fourth current terminal and the reference voltage node, wherein the third resistor and the second inductor are configured to reduce compression of the second current source when the second input voltage approaches a second threshold voltage of the second current source, the reducing including adjusting a voltage swing between the third current terminal and the fourth current terminal when the second input voltage is swinging. ​

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