Topological insulator, quantum bit, method for manufacturing a topological insulator, and method for manufacturing a quantum bit

Abstract

A topological insulator according to the present invention contains a first material, the electrical properties of which change in accordance with the width, while having a first region that extends in a first direction and a second region that is provided on the surface of the first region and contains an oxide of the first material; and the first region has such a width that the electrical properties of the first region are those of a semiconductor. A quantum bit according to the present invention is provided with a first Majorana particle carrier that contains a topological insulator and extends in a first direction, and a superconductor that is in contact with the first Majorana particle carrier; the first Majorana particle carrier contains a first material, the electrical properties of which change in accordance with the width, while having a first region that extends in the first direction and a second region that is provided on the surface of the first region and contains an oxide of the first material; and the first region has such a width that the electrical properties of the first region are those of a semiconductor.　

Description

Technical Field

[0001] The present invention relates to a topological insulator, a quantum bit, a method for manufacturing a topological insulator, and a method for manufacturing a quantum bit.

Background Art

[0002] Research on quantum computers using Majorana particles has been conducted. Various techniques have been proposed as methods for expressing Majorana particles. For example, a technique for expressing Majorana particles using a nanowire structure such as a semiconductor has been proposed (for example, Patent Documents 1-3).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] A topological superconductor is known as a substance for expressing Majorana particles. However, at present, since no good candidate for a topological superconductor has been found, research has been conducted on bringing an s-wave superconductor into contact with a topological insulator to induce superconductivity by the proximity effect. As a topological insulator, it is desired to have a property that a gapless state appears on the surface or edge while the inside is insulating or semiconducting and it is difficult to form a conduction mode.

[0005] On one side, it aims to achieve both the appearance of a gapless state and the suppression of the generation of an internal conduction mode.

Means for Solving the Problem

[0006] In one aspect, it includes a first material whose electrical properties change according to the width, a first region extending in a first direction, and a second region provided on the surface of the first region and containing an oxide of the first material. The first region is a topological insulator having a width in which the electrical properties of the first region become those of a semiconductor.

Advantages of the Invention

[0007] On one side, it is possible to achieve both the appearance of a gapless state and the suppression of the generation of an internal conduction mode.

Brief Description of the Drawings

[0008]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0009] Tungsten ditelluride (WTe2) is a substance in which the emergence of Majorana particles is strongly considered. Therefore, first, the emergence positions of the gapless state (metallic state) and the emergence positions of Majorana particles in single-layer WTe2 layers and multi-layer WTe2 layers will be described. Fig. 1(a) is a plan view showing the emergence position of the gapless state 20 of the single-layer WTe2 layer 500, and Fig. 1(b) is a perspective view showing the emergence position of the gapless state 20 of the multi-layer WTe2 layer 600. In Fig. 1(a) and Fig. 1(b), it is assumed that the length of the WTe2 layer in the horizontal direction of the paper surface is infinite. As shown in Fig. 1(a), the single-layer WTe2 layer 500 is called a two-dimensional topological insulator, and a one-dimensional gapless state 20 appears at the edge. As shown in Fig. 1(b), the multi-layer WTe2 layer 600 is called a three-dimensional second-order topological insulator, and a one-dimensional gapless state 20 appears at the ridge line.

[0010] Fig. 2(a) is a plan view showing the emergence position of the Majorana particles 22 emerging in the single-layer WTe2 layer 500, and Fig. 2(b) is a perspective view showing the emergence position of the Majorana particles 22 emerging in the multi-layer WTe2 layer 600. As shown in Fig. 2(a), when an s-wave superconductor 30 is brought into contact with the single-layer WTe2 layer 500, Majorana particles 22 appear in the vicinity of the s-wave superconductor 30 in the gapless state 20 that appears at the edge of the WTe2 layer 500. As shown in Fig. 2(b), when an s-wave superconductor 30 is brought into contact with the multi-layer WTe2 layer 600, Majorana particles 22 appear in the vicinity of the s-wave superconductor 30 in the gapless state 20 that appears at the ridge line of the WTe2 layer 600. In Fig. 2(b), in the simulation, a gapless state did not appear at the upper right ridge line, so it is not shown here.

[0011] The entire single-layer WTe2 layer is easily oxidized by natural oxidation. In this case, the gapless state 20 will not appear. In order to suppress oxidation, it is necessary to fabricate the device in an inert gas atmosphere or in a vacuum, or to protect it with a film that suppresses oxygen permeation, so the process becomes difficult and it is difficult to handle. Therefore, the multi-layer WTe2 layer will be examined below.

[0012] [Multi-layer WTe2 layers] FIG. 3(a) is a perspective view showing a bulk single-crystalline WTe2 layer 700, and FIG. 3(b) is a perspective view showing a nanowire-shaped WTe2 layer 800. As shown in FIG. 3(a), the size of the bulk single-crystalline WTe2 layer 700 is not particularly limited. For example, the width W and the length L are on the order of several tens of μm, and the thickness T is on the order of several tens of nm. As shown in FIG. 3(b), the width W of the nanowire-shaped WTe2 layer 800 is on the order of several nm. The length L and the thickness T are not particularly limited. For example, the length L is several tens of μm and the thickness T is on the order of several tens of nm.

[0013] The band structures of the bulk single-crystalline WTe2 layer 700 and the nanowire-shaped WTe2 layer 800 were calculated by simulation. The simulation was performed by the density functional method. In the density functional method, the exchange-correlation potential is treated under the generalized gradient approximation using the PBE (Perdew-Burke-Ernzerhof) exchange energy. The electron-ion interaction is described by a norm-conserving pseudopotential with partial core correction. The basis functions are pseudo-atomic orbitals centered on atomic sites, and the van der Waals interaction is described by the semi-empirical DFT-D2 method. Also, the structural optimization is performed under three-dimensional periodic boundary conditions, and the convergence condition is that the force acting on each atom is 0.01 eV / Å or less.

[0014] FIG. 4 is a diagram showing the simulation results of the band structure of the bulk single-crystalline WTe2 layer 700. The G, Y, S, X, and Z on the horizontal axis of FIG. 4 correspond to the G point, Y point, S point, X point, and Z point of the Brillouin zone, respectively. The vertical axis of FIG. 4 is the band gap. In the simulation of FIG. 4, the width W direction of the WTe2 layer 700 is the a-axis direction of the crystal, the length L direction is the b-axis direction, and the thickness T direction is the c-axis direction. The a-axis, b-axis, and c-axis directions are all models assuming periodic boundary conditions, and the width W, length L, and thickness T of the WTe2 layer 700 are assumed to be infinite. As shown in FIG. 4, it can be confirmed that the bulk single-crystalline WTe2 layer 700 has a semi-metallic electronic state. In the WTe2 layer 700 showing semi-metallic properties, in addition to the gapless state 20 appearing at the ridge line, a conduction mode also occurs inside the bulk. In this case, if an Andreev bound state occurs through the conduction mode inside the bulk, it becomes difficult to distinguish from the appearance of Majorana particles 22. That is, when some signal appears, it becomes difficult to distinguish whether it is due to Majorana particles or other quasiparticles. For these reasons, it is not preferable to use the bulk single-crystalline WTe2 layer as a topological insulator material.

[0015] FIG. 5 is a diagram showing the crystal structure in the width W direction of the nanowire-shaped WTe2 layer 800. In FIG. 5, the unit cell 40 in the width W direction of the WTe2 layer 800 is illustrated by a dotted line, and the case where the number of unit cells 40 is 9 is illustrated. As shown in FIG. 5, in the simulation, the width W direction of the nanowire-shaped WTe2 layer 800 is the a-axis direction of the crystal, the length L direction is the b-axis direction, and the thickness T direction is the c-axis direction. The lattice constant of the crystal in the a-axis direction is about 0.348 nm, the lattice constant of the crystal in the b-axis direction is about 0.625 nm, and the lattice constant of the crystal in the c-axis direction is about 1.405 nm. That is, in this specification, the direction with the smallest lattice constant in the WTe2 crystal is defined as the a-axis direction, the direction with the next smallest lattice constant is the b-axis direction, and the direction with the largest lattice constant is the c-axis direction.

[0016] Figures 6(a) to 9(b) are diagrams showing the simulation results of the band structure of the nanowire-shaped WTe2 layer 800. The G, Y, S, X, and Z on the horizontal axis of Figures 6(a) to 9(b) correspond to the G point, Y point, S point, X point, and Z point of the Brillouin zone, respectively. The vertical axis of Figures 6(a) to 9(b) is the band gap. The simulations of Figures 6(a) to 9(b) varied the number N of unit cells 40 in the width W direction (a-axis direction) between 4 and 13 to investigate the width dependence of the band structure. The b-axis and c-axis directions were modeled with periodic boundary conditions, and the length L and thickness T of the WTe2 layer 800 were assumed to be infinite.

[0017] As shown in Figures 6(a), 6(b), 7(a), 7(b), and 8(b), when the number N of unit cells 40 in the width W direction (a-axis direction) is 4, 5, 6, 7, 9, it can be confirmed that the nanowire-shaped WTe2 layer 800 has semiconductor properties. As shown in Figures 8(a), 9(a), and 9(b), when the number N of unit cells 40 in the width W direction (a-axis direction) is 8, 10, 13, it can be confirmed that the nanowire-shaped WTe2 layer 800 has semi-metal properties. The band gap was 34 meV in Figure 6(a), 10 meV in Figure 6(b), 14 meV in Figure 7(a), 17 meV in Figure 7(b), and 8 meV in Figure 8(b).

[0018] FIG. 10 is a diagram showing the relationship between the number N of unit cells 40 in the width direction and the band gap, obtained from the simulation results of FIGS. 6(a) to 9(b). As shown in FIG. 10, in the series where the number N of unit cells 40 is 3n + 1 (n is a positive integer) (i.e., N = 4, 7), the band gap tends to be large. On the other hand, in the series where the number N of unit cells 40 is 3n + 2 (n is a positive integer) (i.e., N = 5, 8), the band gap tends to be small, and when the number N is 8, the band gap is closed. Also, even in the series where the number N is 3n + 1, when the number N is 10, the band gap is closed. From these facts, it can be said that by making the number N of unit cells 40 in the a-axis direction 9 or less, the band gap can be opened to have semiconductor properties. When the number N of unit cells 40 in the a-axis direction becomes 10 or more, it can be said that the band gap is closed and it has semi-metal properties.

[0019] From this result, when using a nanowire-like multilayer WTe2 layer as a topological insulator material, by setting the width W direction of the nanowire as the a-axis direction of the WTe2 crystal and controlling the number of unit cells in the a-axis direction, it can be said that the generation of conduction modes other than the gapless state 20 appearing at the ridge line can be suppressed, and the emergence of Majorana particles 22 can be separated. Also, since natural oxidation stops at the surface several layers and the inside is not oxidized, it can be said that using a nanowire-like multilayer WTe2 layer makes it less susceptible to the influence of oxidation. Therefore, it can be said that a nanowire-like multilayer WTe2 layer is suitable as a topological insulator material. Example 1 below shows an example of a topological insulator using a nanowire-like multilayer WTe2 layer.

Example

[0020] FIG. 11(a) is a perspective view showing the topological insulator 100 according to Example 1, FIG. 11(b) is a cross-sectional view taken along line A-A of FIG. 11(a), and FIG. 11(c) is a cross-sectional view taken along line B-B of FIG. 11(a). As shown in FIGS. 11(a) to 11(c), the topological insulator 100 includes a first region 10 that is a nanowire-shaped WTe2 layer, and a second region 12 that is an oxide layer formed on the surface of the first region 10. The first region 10 extends in a first direction that is the direction of length L, and a second direction that intersects (e.g., is orthogonal to) the first direction is the direction of width W. The direction of width W of the first region 10 is the a-axis direction of the WTe2 crystal, and the direction of length L is the b-axis direction. The second region 12 is formed by natural oxidation of the surface of the first region 10. The second region 12 is formed of, for example, tungsten oxide (WO3) and / or tellurium oxide (TeO2). By using a multilayer WTe2 layer, natural oxidation remains only on the surface, and the WTe2 layer is maintained inside. Therefore, the inside becomes the first region 10 containing WTe2, and the topological insulator 100 in which the second region 12 containing an oxide of WTe2 is formed on the surface of the first region 10 is obtained. The second region 12 is not limited to being formed on all of the upper surface, lower surface, and side surfaces of the first region 10, and may not be formed on any of the surfaces.

[0021] The first region 10 containing WTe2 changes its electrical properties according to the width W, as shown in the simulation results from FIGS. 6(a) to 9(b). The width W of the first region 10 is preferably such that the number of unit cells 40 in the a-axis direction is 9 or less according to the simulation results from FIGS. 6(a) to 9(b). Since the length when the number of unit cells 40 in the a-axis direction is 9 is 3.1 nm, the width W of the first region 10 is preferably 3.1 nm or less. By having such a width W, the first region 10 comes to exhibit semiconductor properties. The thickness of the second region 12 is about 2 to 3 nm on any of the upper surface, lower surface, and side surfaces of the first region 10. Therefore, by fabricating a WTe2 layer with a width of about 7 to 9 nm or less, a topological insulator 100 is obtained, which includes a first region 10 containing WTe2 and having a width W of 3.1 nm or less, and a second region 12 provided on the surface of the first region 10, containing an oxide of WTe2 and having a thickness of about 2 to 3 nm. That is, the width of the topological insulator 100 is about 7 to 9 nm or less.

[0022] The thickness T of the first region 10 only needs to be equal to or greater than the thickness of one layer of WTe2, and may be 7.07 Å or more. Therefore, the thickness of the topological insulator 100 is about 4.1 to 6.1 nm or more when the second region 12 is formed on both the upper and lower surfaces of the first region 10, and about 2.1 to 3.1 nm or more when it is formed on only one of them. The upper limit of the thickness T of the first region 10 may be within the range where manufacturing is possible. For example, when using a film mainly composed of hydrogen silsesquioxane as a resist film for patterning as in the manufacturing method described later, the aspect ratio of patterning is about 50:1. In this case, the upper limit of the thickness T of the first region 10 is about 500 nm. The length L of the first region 10 is not particularly limited.

[0023] [Manufacturing Method] Figs. 12(a) to 12(c) are perspective views showing a method for manufacturing the topological insulator 100 according to Example 1. As shown in Fig. 12(a), in an inert atmosphere, the single crystal of WTe2 is thinned by repeating tape peeling, and is temporarily attached onto a holding substrate. Then, a WTe2 film 86 having a desired crystal is picked up from the WTe2 attached onto the holding substrate by a glass substrate 82 using, for example, a polycarbonate film 84 as an adhesive layer.

[0024] As shown in Fig. 12(b), the WTe2 film 86 picked up using the glass substrate 82 is attached onto an insulating substrate 80. At this time, the WTe2 crystal is attached so that the crystal orientation matches a desired direction by utilizing the property that the longitudinal direction easily becomes parallel to the a-axis. Note that the formation of the WTe2 film 86 on the substrate 80 may be performed using a molecular beam epitaxy method, a pulsed laser deposition method, or the like.

[0025] As shown in Fig. 12(c), the WTe2 film 86 is patterned to form a pattern 87 by a photolithography method using electron beam exposure and an etching method using reactive ion etching. The pattern 87 extends in a first direction, and the second direction is the width direction. In the photolithography method, for example, a resist film mainly composed of hydrogen silsesquioxane is used, and in the reactive ion etching, for example, a fluorocarbon-based gas is used as an etching gas. At this time, the patterning is performed so that the width of the pattern 87 becomes 7 to 9 nm or less. The surface of the pattern 87 is naturally oxidized. Thereby, as shown in Fig. 11(a), a topological insulator 100 is formed which has a nanowire shape with a width W of 3.1 nm or less, and includes a first region 10 containing WTe2 and a second region 12 formed on the surface of the first region 10 and containing an oxide of WTe2. In the attachment of the WTe2 film 86 to the substrate 80 in Fig. 12(b), the direction of the length L of the topological insulator 100 is set to be the b-axis direction of the crystal axis orientation of WTe2, and the direction of the width W is set to be the a-axis direction.

[0026] According to Example 1, the topological insulator 100 includes a material whose electrical properties change according to the width, and includes a first region 10 extending in a first direction and a second region 12 provided on the surface of the first region 10 and including an oxide of the material included in the first region 10. And the first region 10 has a width W in which the electrical properties of the first region 10 become those of a semiconductor. Thereby, the generation of conduction modes other than the gapless state appearing at the ridge line is suppressed in the first region 10. Further, since the influence of natural oxidation stops at the second region 12, the first region 10 is suppressed from being affected by oxidation. Therefore, it is possible to realize both the appearance of the gapless state and the suppression of the generation of internal conduction modes.

[0027] Further, in Example 1, the material whose electrical properties change according to the width and which is included in the first region 10 is WTe2. As shown in the simulation results from FIG. 6(a) to FIG. 9(b), the electrical properties of WTe2 change according to the width, and it exhibits semiconductor properties in the case of a predetermined width. Therefore, by using WTe2 as the material whose electrical properties change according to the width and which is included in the first region 10, it is possible to realize the appearance of the gapless state and the suppression of the generation of internal conduction modes.

[0028] Further, in Example 1, the width W of the first region 10 including WTe2 is 3.1 nm or less. At this time, the direction of the width W of the first region 10 is the a-axis direction of WTe2, and the number of unit cells 40 of WTe2 in the a-axis direction is 9 or less. Thereby, as shown in the simulation results from FIG. 6(a) to FIG. 9(b), the first region 10 showing semiconductor properties can be obtained. From the point that the first region 10 comes to show semiconductor properties, as shown in FIG. 10, the number of unit cells 40 of WTe2 in the a-axis direction, which is the direction of the width W of the first region 10, is preferably 7 or less, and more preferably 4 or less. The length when the number of unit cells 40 of WTe2 in the a-axis direction is 7 is 2.41 nm, and the length when it is 4 is 1.38 nm. Therefore, the width W of the first region 10 is preferably 2.41 nm or less, and more preferably 1.38 nm or less.

[0029] In Example 1, the thickness T of the first region 10 is equal to or greater than the thickness of one layer of WTe2 and is 7.07 Å or greater. This makes it possible to realize the emergence of a gapless state and the suppression of the generation of an internal conduction mode.

[0030] In Example 1, the direction of the length L of the first region 10 is the b-axis direction of the crystal orientation of WTe2. In nanowire-shaped WTe2, a gapless state appears at the ridge line in the b-axis direction of the crystal orientation. Therefore, by setting the direction of the length L of the first region 10 to the b-axis direction of the crystal orientation of WTe2, it becomes easier to contact the s-wave superconductor layer for expressing Majorana particles.

[0031] According to the manufacturing method of Example 1, a WTe2 film 86, which is a material whose electrical properties change according to the width, is formed on a substrate 80 (Fig. 12(b)). The WTe2 film 86 is patterned to form a pattern 87 extending in the first direction (Fig. 12(c)). The surface of the pattern 87 is oxidized to form an oxide of WTe2. When forming this oxide, the width W of the region where WTe2 is not oxidized (the first region 10 in Fig. 11(a)) is set to the width at which the electrical properties of WTe2 become semiconductor properties. As a result, a topological insulator 100 in which a gapless state appears and the generation of an internal conduction mode is suppressed can be obtained.

Example

[0032] Fig. 13 is a perspective view showing a quantum bit 200 according to Example 2. As shown in Fig. 13, the quantum bit 200 includes a nanowire-shaped Majorana particle carrier layer 50 extending in the first direction, a bulk-shaped Majorana particle carrier layer 52 having a longitudinal direction in the second direction, s-wave superconductor layers 60 to 64, and magnetic layers 70 to 76. The first direction and the second direction intersect, for example, are orthogonal. The s-wave superconductor layers 60 to 64 are, for example, aluminum (Al) layers or niobium (Nb) layers with a thickness of 30 to 50 nm. The magnetic layers 70 to 76 are, for example, iron (Fe) layers, nickel (Ni) layers, or cobalt (Co) layers with a thickness of 30 to 50 nm. Although these are provided on a substrate, the substrate is not shown in the figure for clarity.

[0033] The Majorana particle carrier layer 50 is a nanowire-shaped topological insulator, includes WTe2, and has a nanowire-shaped first region 10 extending in a first direction and a second region 12 provided on the surface of the first region 10 and containing an oxide of WTe2. The second region 12 is formed on the side surface and the upper surface of the first region 10. The first region 10 has a width exhibiting semiconductor properties as described in Example 1. That is, in the first region 10, the width direction (second direction) is the a-axis direction of the crystal orientation of WTe2, the number of unit cells 40 in the a-axis direction is 9 or less, and it has a width of 3.1 nm or less. The thickness of the first region 10 may be equal to or greater than the thickness of one layer of WTe2 and may be 7.07 Å or greater as described in Example 1. Since the first direction, which is the length direction of the Majorana particle carrier layer 50, is the b-axis direction of the crystal orientation of WTe2 and the second direction, which is the width direction, is the a-axis direction, a one-dimensional gapless state appears at the ridge line extending in the first direction of the first region 10.

[0034] The s-wave superconductor layer 60 and the magnetic layer 70 are provided in contact with the lower surface of the Majorana particle carrier layer 50. The widths of the s-wave superconductor layer 60 and the magnetic layer 70 are larger than the width of the Majorana particle carrier layer 50. As a result, as shown in FIG. 2(b), Majorana particles are generated in the vicinity of the s-wave superconductor layer 60 in the gapless state appearing at the ridge line of the first region 10. For example, the generation of Majorana particles can be controlled by turning on and off a switch connecting the s-wave superconductor layer 60 to the ground. The magnetic layer 70 is provided to suppress the influence of Majorana particles on other Majorana particles that have appeared at other positions.

[0035] The Majorana particle carrier layer 52 is a bulk topological insulator, which is a bulk single-crystalline WTe2 layer having a third region 54 with a length direction in the second direction, and a fourth region 56 provided on the surface of the third region 54 and containing an oxide of WTe2. The fourth region 56 is formed on the side surface and the upper surface of the third region 54. One end of the Majorana particle carrier layer 50 is connected to the side surface of the Majorana particle carrier layer 52 extending in the second direction. In the Majorana particle carrier layer 52, the second direction, which is the length direction, is the a-axis direction of the crystal orientation of WTe2. In bulk single-crystalline WTe2, a one-dimensional gapless state appears on the ridge line extending in the a-axis direction of the crystal orientation of WTe2. Therefore, a one-dimensional gapless state appears on the ridge line extending in the second direction of the third region 54.

[0036] The s-wave superconductor layers 62 and 64 and the magnetic layers 72 to 76 are provided in contact with the lower surface of the Majorana particle carrier layer 52. The s-wave superconductor layers 62 and 64 and the magnetic layers 72 and 74 are provided so as to protrude outside the side surface of the Majorana particle carrier layer 52. Therefore, as shown in FIG. 2(b), Majorana particles are generated in the vicinity of the s-wave superconductor layers 62 and 64 in the gapless state appearing on the ridge line extending in the second direction of the third region 54. For example, the generation of Majorana particles can be controlled by turning on and off a switch that connects the s-wave superconductor layers 62 and 64 to the ground. The s-wave superconductor layer 62 and the s-wave superconductor layer 64 are provided, for example, so as to sandwich the portion where the Majorana particle carrier layer 50 is connected to the Majorana particle carrier layer 52 in the second direction. The magnetic layers 72 to 76 are provided, like the magnetic layer 70, to suppress the influence of Majorana particles on other Majorana particles that appear at other positions.

[0037] [Manufacturing Method] FIGS. 14(a) to 15(b) are perspective views showing a method for manufacturing the quantum bit 200 according to Example 2. As shown in FIG. 14(a), the magnetic layers 70 to 76 are formed on the insulating substrate 80 using, for example, the lift-off method. As shown in FIG. 14(b), the s-wave superconductor layers 60 to 64 are formed on the substrate 80 using, for example, the lift-off method.

[0038] As shown in FIG. 14(c), in an inert atmosphere, the single crystal of WTe2 is thinned by repeatedly peeling it with tape and temporarily attached onto a holding substrate. Then, a WTe2 film 86 having a desired crystal is picked up from the WTe2 attached onto the holding substrate by a glass substrate 82 using, for example, a polycarbonate film 84 as an adhesive layer.

[0039] As shown in FIG. 15(a), the WTe2 film 86 picked up using the glass substrate 82 is attached onto a substrate 80 so as to cover the s-wave superconductor layers 60 to 64 and the magnetic layers 70 to 76. At this time, the crystal orientation is adjusted so that the b-axis direction of the WTe2 crystal is the first direction and the a-axis direction is the second direction. The WTe2 crystal utilizes the property that its longitudinal direction tends to be parallel to the a-axis.

[0040] As shown in FIG. 15(b), the WTe2 film 86 is patterned by a photolithography method using electron beam lithography and an etching method using reactive ion etching. At this time, in the Majorana particle carrier layer 50, the WTe2 film 86 is patterned so that the width becomes 7 to 9 nm or less. The surface of the patterned WTe2 film 86 is naturally oxidized. Thereby, a Majorana particle carrier layer 50 is formed which includes WTe2, has a nanowire-shaped first region 10 extending in the first direction with a width of 3.1 nm or less, and a second region 12 provided on the surface of the first region 10 and containing an oxide of WTe2 (see also FIG. 13). Further, a Majorana particle carrier layer 52 is formed which has a third region 54 that is a bulk single crystal of WTe2 having a length direction in the second direction, and a fourth region 56 provided on the surface of the third region 54 and containing an oxide of WTe2 (see also FIG. 13). The first direction is the b-axis direction of the crystal orientation of WTe2, and the second direction is the a-axis direction.

[0041] FIGS. 16(a) to 16(c) are perspective views showing another manufacturing method of the quantum bit 200 according to Example 2. As shown in FIG. 16(a), s-wave superconductor layers 60 to 64 and magnetic layers 70 to 76 are formed on an insulating substrate 80 using, for example, a lift-off method. As the substrate 80, a substrate on which epitaxial growth of WTe2 is possible, for example, a magnesium oxide (MgO) substrate, is used.

[0042] As shown in Fig. 16(b), on the substrate 80, a WTe2 film 86 covering the s-wave superconductor layers 60 to 64 and the magnetic layers 70 to 76 is formed using, for example, molecular beam epitaxy or pulsed laser deposition. Thereby, a WTe2 film 86 having a b-axis direction of the crystal orientation in the first direction and an a-axis direction in the second direction is obtained.

[0043] As shown in Fig. 16(c), the WTe2 film 86 is patterned by a photolithography method using electron beam lithography and an etching method using reactive ion etching. At this time, in the Majorana particle carrier layer 50, the WTe2 film 86 is patterned so that the width becomes 7 to 9 nm or less. The surface of the WTe2 film 86 after patterning is naturally oxidized. Thereby, a Majorana particle carrier layer 50 including WTe2 and having a nanowire-like first region 10 extending in the first direction and having a width of 3.1 nm or less, and a second region 12 provided on the surface of the first region 10 and including an oxide of WTe2 is formed (see also Fig. 13). Also, a Majorana particle carrier layer 52 including a bulk single crystal WTe2 having a length direction in the second direction and having a third region 54 and a fourth region 56 provided on the surface of the third region 54 and including an oxide of WTe2 is formed (see also Fig. 13).

[0044] According to Example 2, it includes a topological insulator and has a Majorana particle carrier layer 50 extending in a first direction and an s-wave superconductor layer 60 in contact with the Majorana particle carrier layer 50. The Majorana particle carrier layer 50 includes a material whose electrical properties vary according to the width, and includes a first region 10 extending in the first direction and a second region 12 provided on the surface of the first region 10 and including an oxide of the material contained in the first region 10. The first region 10 has a width such that the electrical properties of the first region 10 become those of a semiconductor. Thereby, the occurrence of conduction modes other than the gapless state appearing at the ridge line is suppressed in the first region 10. Further, since the influence of natural oxidation stops at the second region 12, the first region 10 is suppressed from being affected by oxidation. Therefore, in the Majorana particle carrier layer 50, a gapless state appears and the occurrence of internal conduction modes is suppressed. Thus, the appearance of the gapless state enables the expression of Majorana particles, and the occurrence of internal conduction modes being suppressed makes it possible to distinguish whether or not Majorana particles are expressed.

[0045] Also, in Example 2, it includes a bulk-like Majorana particle carrier layer 52, which is a topological insulator and is connected to the nanowire-like Majorana particle carrier layer 50, and s-wave superconductor layers 62 and 64 that are in contact with the Majorana particle carrier layer 52. The nanowire-like Majorana particle carrier layer 50 extends in a first direction, and the longitudinal direction of the bulk-like Majorana particle carrier layer 52 is a second direction that intersects (e.g., is orthogonal to) the first direction. The bulk-like Majorana particle carrier layer 52 includes a bulk-like third region 54 formed of the same material as the first region 10 of the nanowire-like Majorana particle carrier layer 50, and a fourth region 56 provided on the surface of the third region 54 and containing an oxide of the material included in the third region 54. Thereby, in addition to the nanowire-like Majorana particle carrier layer 50, it becomes possible to express Majorana particles also in the bulk-like Majorana particle carrier layer 52. For example, both the first region 10 and the third region 54 contain WTe2, the first direction in which the Majorana particle carrier layer 50 extends is the b-axis direction of the crystal orientation of WTe2, and the second direction that is the length direction of the Majorana particle carrier layer 52 is the a-axis direction. In this case, a gapless state appears on the ridge line extending in the first direction of the Majorana particle carrier layer 50, and a gapless state appears on the ridge line extending in the second direction of the Majorana particle carrier layer 52, making it easier to express Majorana particles.

[0046] Also, according to the manufacturing method of Example 2, patterned s-wave superconductor layers 60 to 62 are formed on the substrate 80 (FIGS. 14(b) and 16(a)). A WTe2 film 86, which is a material whose electrical properties change according to the width, is formed on the substrate 80 so as to cover the s-wave superconductor layers 60 to 62 (FIGS. 15(a) and 16(b)). The WTe2 film 86 is patterned to form a Majorana particle carrier layer 50, which is a topological insulator in contact with the s-wave superconductor layer 60 (FIGS. 15(b) and 16(c)). The Majorana particle carrier layer 50 includes WTe2, which is a material whose electrical properties change according to the width, has a width with semiconductor properties, and has a first region 10 extending in a first direction and a second region 12 provided on the surface of the first region 10 and containing an oxide of WTe2 (FIG. 13). As a result, a Majorana particle carrier layer 50 in which a gapless state appears and the generation of an internal conduction mode is suppressed is obtained. Therefore, it becomes possible to express Majorana particles and also to distinguish whether or not Majorana particles are expressed.

[0047] [Modification Example] FIG. 17 is a perspective view showing a quantum bit 210 according to a modification example of Example 2. As shown in FIG. 17, the quantum bit 210 includes a nanowire-shaped Majorana particle carrier layer 50 extending in a first direction, a nanowire-shaped Majorana particle carrier layer 50a extending in a third direction intersecting (for example, orthogonal to) the first direction, s-wave superconductor layers 60 to 66, and magnetic layers 70 to 76. Although these are provided on a substrate, the substrate is not shown for clarity of the figure. Also, the third direction may be the same as or different from the second direction of Example 2.

[0048] As described above, the Majorana particle carrier layer 50 is a topological insulator, contains WTe2, and has a nanowire-shaped first region 10 extending in the first direction and a second region 12 provided on the surface of the first region 10 and containing an oxide of WTe2. Similarly, the Majorana particle carrier layer 50a is also a topological insulator, contains WTe2, and has a nanowire-shaped first region 10a extending in the third direction and a second region 12a provided on the surface of the first region 10a and containing an oxide of WTe2. As described in Example 1, the first regions 10 and 10a have a width with semiconductor properties. That is, the first regions 10 and 10a have a width of 3.1 nm or less with the number of unit cells 40 in the width direction being 9 or less. The thickness of the first regions 10 and 10a may be equal to or greater than the thickness of one layer of WTe2, and may be 7.07 Å or more, as described in Example 1.

[0049] The s-wave superconductor layers 60 and 66 and the magnetic layers 70 and 76 are provided in contact with the lower surface of the Majorana particle carrier layer 50. The widths of the s-wave superconductor layers 60 and 66 and the magnetic layers 70 and 76 are larger than the width of the Majorana particle carrier layer 50. Similarly, the s-wave superconductor layers 62 and 64 and the magnetic layers 72 and 74 are provided in contact with the lower surface of the Majorana particle carrier layer 50a. The widths of the s-wave superconductor layers 62 and 64 and the magnetic layers 72 and 74 are larger than the width of the Majorana particle carrier layer 50a. Thereby, Majorana particles are generated in the vicinity of the s-wave superconductor layers 60 to 66 in the gapless state appearing at the ridge lines of the first regions 10 and 10a.

[0050] The qubit 210 of the modified example of Example 2 can be manufactured in the same manner as the qubit 200 of Example 2 described with reference to FIGS. 14(a) to 16(c).

[0051] In a modified example of Example 2, a nanowire-like Majorana particle carrier layer 50 extending in the first direction and a nanowire-like Majorana particle carrier layer 50a extending intersecting the Majorana particle carrier layer 50 in the third direction are provided. Even in this case, the Majorana particle carrier layers 50 and 50a exhibit a gapless state and suppress the generation of internal conduction modes, enabling the expression of Majorana particles and allowing discrimination of whether or not Majorana particles are expressed.

[0052] In Examples 1, 2 and their modified examples, the first regions 10, 10a may be formed of a material other than WTe2 as long as it is a material whose electrical properties change according to the width and has semiconductor properties when it has a predetermined width.

[0053] As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

Explanation of Reference Numerals

[0054] 10, 10a First region 12, 12a Second region 20 Gapless state 22 Majorana particle 30 s-wave superconductor 40 Unit lattice 50, 50a Majorana particle carrier layer 52 Majorana particle carrier layer 54 Third region 56 Fourth region 60 - 64 s-wave superconductor layer 70 - 76 Magnetic layer 80 Substrate 82 Glass substrate 84 Polycarbonate film 86 WTe2 film 100 Topological insulator 200, 210 Quantum bit 500 Single-layer WTe2 layer 600 Multilayer WTe2 layer 700 bulk single-crystalline WTe2 layers 800 nanowire-shaped WTe2 layers

Claims

1. A first region extending in a first direction, including a first material whose electrical properties change according to width; A second region provided on the surface of the first region and including an oxide of the first material; and The first region is a topological insulator having a width at which the electrical properties of the first region become semiconductor properties.

2. The topological insulator according to claim 1, wherein the first material is tungsten ditelluride.

3. The topological insulator according to claim 2, wherein the width of the first region is 3.1 nm or less.

4. The topological insulator according to claim 2 or 3, wherein the direction of the width of the first region is the a-axis direction of the crystal orientation of the tungsten ditelluride, and the number of unit cells of the tungsten ditelluride in the a-axis direction is 9 or less.

5. The topological insulator according to any one of claims 2 to 4, wherein the thickness of the first region is 7.07 Å or more.

6. The topological insulator according to any one of claims 2 to 5, wherein the first direction is the b-axis direction of the crystal orientation of the tungsten ditelluride.

7. A first Majorana particle carrier extending in a first direction, including a topological insulator; A superconductor in contact with the first Majorana particle carrier; and The first Majorana particle carrier is A first region extending in the first direction, including a first material whose electrical properties change according to width; A second region provided on the surface of the first region and including an oxide of the first material; and The first region is a qubit having a width at which the electrical properties of the first region become semiconductor properties.

8. The qubit according to claim 7, wherein the first material is tungsten ditelluride.

9. A second Majorana particle carrier including a topological insulator connected to the first Majorana particle carrier and extending in a second direction intersecting the first direction; A superconductor in contact with the second Majorana particle carrier; and The second Majorana particle carrier is A third region formed of the first material; A fourth region provided on the surface of the third region and including an oxide of the first material, the qubit according to claim 7 or 8.

10. The first material is tungsten ditelluride, The first direction is the b-axis direction of the crystal orientation of the tungsten ditelluride, The second direction is the a-axis direction of the crystal orientation of the tungsten ditelluride, the qubit according to claim 9.

11. Comprising a third Majorana particle carrier that intersects and extends across the first Majorana particle carrier in a third direction intersecting the first direction. The third Majorana particle carrier contains the first material and has a fifth region extending in the third direction, and a sixth region provided on the surface of the fifth region and containing an oxide of the first material. The fifth region has a width such that the electrical properties of the fifth region are those of a semiconductor. The quantum bit according to claim 7 or 8.

12. A step of forming a film containing a first material on a substrate, the electrical properties of which vary according to the width, a step of patterning the film to form a first pattern extending in a first direction, and a step of oxidizing the surface of the first pattern to form an oxide of the first material. In the step of forming the oxide, the width of the region where the first material is not oxidized is set to the width at which the electrical properties of the first material become those of a semiconductor. A method for manufacturing a topological insulator.

13. A method for manufacturing a quantum bit including a Majorana particle carrier that is a topological insulator extending in a first direction on a substrate, a step of forming a patterned superconductor on the substrate, a step of forming a film containing a first material on the substrate so as to cover the superconductor, the electrical properties of which vary according to the width, a step of patterning the film to form a first region that contacts the superconductor and contains the first material having a width such that the electrical properties are those of a semiconductor, and a second region provided on the surface of the first region and containing an oxide of the first material, and forming the Majorana particle carrier that is a topological insulator. A method for manufacturing a quantum bit comprising the steps.

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