Heterojunction solar cell, method for manufacturing the same, photovoltaic module, and photovoltaic power generation system

Abstract

To provide a heterojunction solar cell and a manufacturing method thereof which are able to avoid a short circuit thereby reducing the efficiency loss, ensure high current density, and minimize the loss of the fill factor.SOLUTION: A heterojunction solar cell includes: a substrate; a first intrinsic silicon layer, a first doped layer and a first transparent conductive layer 40 that are sequentially stacked on a first surface F; and a second intrinsic silicon layer, a second doped layer and a second transparent conductive layer 70 that are sequentially stacked on a second surface S. A doping type of the first doped layer is opposite to a doping type of the second doped layer. The first transparent conductive layer 40 covers at least a partial surface of the first surface F. The second transparent conductive layer 70 covers the second surface S and at least a partial surface of the plurality of lateral surfaces. An edge 41 of the first transparent conductive layer and an edge 71 of the second transparent conductive layer are spaced to define an isolation region 81 between the edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and particularly to heterojunction solar cells and their manufacturing methods, photovoltaic modules, and photovoltaic power generation systems.

Background Art

[0002] In recent years, with the rapid development of the photovoltaic industry, the domestic and international markets have put forward increasingly high requirements for the conversion efficiency and product performance of solar cells and photovoltaic modules, which also encourages manufacturers in the industry to actively research new types of batteries, module structures, and related processes. Heterojunction (HJT) solar cells have advantages such as low light attenuation and low temperature coefficient, can reduce energy consumption, and can reduce the thermal damage of silicon substrates, and have become an important direction for the development of future high-efficiency batteries. In the prior art, heterojunction solar cells mainly deposit intrinsic amorphous silicon thin films on both surfaces of a silicon substrate, and then deposit P-type and N-type amorphous or microcrystalline silicon thin films respectively to form a heterojunction. After manufacturing the corresponding transparent conductive oxide layer TCO on the surfaces of the amorphous silicon or microcrystalline silicon thin films on both sides of the silicon substrate, screen printing is performed using a low-temperature silver paste and cured to form a surface metal electrode. However, the conventional heterojunction solar cells have the problem of low efficiency.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Based on this, it is necessary to provide a heterojunction solar cell and its manufacturing method, a photovoltaic module, and a photovoltaic power generation system that can improve the efficiency of the heterojunction solar cell.

Means for Solving the Problems

[0004] The heterojunction solar cell according to the first aspect of the embodiment of the present application includes a substrate, a first intrinsic silicon layer, a first doped layer, a first transparent conductive layer, a second intrinsic silicon layer, a second doped layer, and a second transparent conductive layer. The substrate includes a first surface and a second surface provided opposite to each other, and a plurality of side surfaces adjacent between the first surface and the second surface. The first intrinsic silicon layer, the first doped layer, and the first transparent conductive layer are sequentially laminated and provided on the first surface. The second intrinsic silicon layer, the second doped layer, and the second transparent conductive layer are sequentially laminated and provided on the second surface. The doping type of the first doped layer is opposite to the doping type of the second doped layer. The first transparent conductive layer covers at least a part of the surface of the first surface. The second transparent conductive layer covers the second surface and at least a part of the surface of the plurality of side surfaces. The edges of the first transparent conductive layer and the second transparent conductive layer are provided at an interval so as to define a separation region between the edge of the first transparent conductive layer and the edge of the second transparent conductive layer.

[0005] In one embodiment, the edge of the second transparent conductive layer is located on the side surface.

[0006] In one embodiment, the edge of the first transparent conductive layer is located inside the boundary of the first surface. The minimum distance D1 between the edge of the first transparent conductive layer and the boundary of the first surface is 100 μm.

[0007] In one embodiment, the maximum distance D2 between the edge of the second transparent conductive layer and the first surface is 100 μm.

[0008] In one embodiment, the second transparent conductive layer completely covers each side surface and covers a part of the region of the first surface. The edge of the second transparent conductive layer is located outside the edge of the first transparent conductive layer.

[0009] In one embodiment, the minimum distance D3 between the edge of the first transparent conductive layer and the edge of the second transparent conductive layer is 50 μm.

[0010] In one embodiment, the maximum distance D4 between the edge of the second transparent conductive layer and the boundary of the first surface is 1000 μm.

[0011] In one embodiment, the first doped layer covers at least a part of the surface of the first surface and the plurality of side surfaces, and the edge of the second transparent conductive layer is laminated on the surface of the first doped layer away from the substrate.

[0012] In one embodiment, the heterojunction solar cell is provided by being laminated on the surface of the separation region, and further includes an insulating separation layer that covers at least the separation region.

[0013] In one embodiment, the insulating separation layer completely covers the first doped layer to cover the separation region, and at least a part of the structure of the insulating separation layer is located between the first doped layer and the second transparent conductive layer.

[0014] In one embodiment, the thickness of the insulating separation layer is 1.8 nm or more.

[0015] In one embodiment, both the second intrinsic silicon layer and the second doped layer cover at least a part of the surface of the second surface and the plurality of side surfaces. The first intrinsic silicon layer covers at least a part of the surface of the first surface and the plurality of side surfaces. A part of the structure of the second intrinsic silicon layer is laminated on the surface of the first intrinsic silicon layer away from the substrate, a part of the structure of the second doped layer is laminated on the surface of the first intrinsic silicon layer away from the substrate, and a part of the structure of the first doped layer is laminated on the surface of the second doped layer away from the substrate.

[0016] In one embodiment, the insulating separation layer covers the separation region, and the edge of the insulating separation layer is adjacent to the edge of the first transparent conductive layer and the edge of the second transparent conductive layer, respectively.

[0017] In one embodiment, the material of the insulating separation layer contains SiOx. The insulating separation layer is further doped with a carbon element and a nitrogen element, and / or In the insulating separation layer, a first doping element is further doped, and the first doping element is the same as the doping element in the first doping layer.

[0018] In one embodiment, the first doping layer covers the first surface, and the edges of the second transparent conductive layer are located on each side surface of the substrate.

[0019] In one embodiment, the thickness of the film layer in the first region near the edge of the first transparent conductive layer gradually decreases along a first direction, and the first direction is from the center of the first transparent conductive layer towards the edge of the first transparent conductive layer and is parallel to the first surface.

[0020] In one embodiment, the minimum width dimension D5 along the first direction of the first region is 100 μm.

[0021] In one embodiment, the heterojunction solar cell further includes a first electrode and a second electrode. The first electrode is provided on the first transparent conductive layer, and the second electrode is provided on the second transparent conductive layer. The projection of the first electrode onto the first plane and the projection of the second electrode onto the first plane are offset from each other, and the first plane is perpendicular to the thickness direction of the substrate.

[0022] In one embodiment, at least one of the first transparent conductive layer and the second transparent conductive layer includes a silver nanowire layer and at least two mutually laminated transparent conductive film layers, the materials of each transparent conductive film layer are different, and one silver nanowire layer is interposed between at least two transparent conductive film layers.

[0023] In one embodiment, the heterojunction solar cell further includes a dielectric layer. At least one dielectric layer is provided on the surface of the first transparent conductive layer away from the substrate, and / or At least one dielectric layer is provided on the surface of the second transparent conductive layer away from the substrate.

[0024] In one embodiment, at least one of the first transparent conductive layer and the second transparent conductive layer includes a silver nanowire layer and a single layer of transparent conductive film layer, and the silver nanowire layer is provided on the surface of the transparent conductive film layer facing the substrate.

[0025] The method for manufacturing a heterojunction solar cell according to the second aspect of the embodiments of the present application is providing a substrate, the substrate includes a base plate, the base plate includes a first surface and a second surface provided opposite to each other, and a plurality of side surfaces adjacent between the first surface and the second surface, the substrate further includes a first intrinsic silicon layer and a first doped layer sequentially laminated on the first surface, and a second intrinsic silicon layer and a second doped layer sequentially laminated on the second surface, and the doping type of the second doped layer is opposite to the doping type of the first doped layer; forming a first transparent conductive layer covering at least a part of the surface of the first surface on the first doped layer; forming a second transparent conductive layer covering at least a part of the surface of the second surface and the plurality of side surfaces on the second doped layer, and providing a separation between the edge of the first transparent conductive layer and the edge of the second transparent conductive layer to define a separation region between the edge of the first transparent conductive layer and the edge of the second transparent conductive layer.

[0026] In one embodiment, the steps of forming the first transparent conductive layer on the first doped layer and the second transparent conductive layer on the second doped layer are forming a first transparent conductive layer on the first doped layer, forming a second transparent conductive layer on the second doped layer, and forming an insulating separation layer covering at least the separation region on the separation region.

[0027] In one embodiment, the steps of forming the first transparent conductive layer on the first doped layer, forming the second transparent conductive layer on the second doped layer, and forming an insulating separation layer on the separation region specifically include putting a carrier plate with a central cut-out portion into the reaction chamber; Placing a substrate on a carrier plate, facing a first doped layer towards the carrier plate, and exposing a second region of the first doped layer to the outside from a cutout portion, wherein the first doped layer further includes a third region which is a portion other than the second region on the surface of the first doped layer away from the substrate. Forming a first transparent conductive layer on the second region of the first doped layer and forming an insulating separation layer on the third region. Forming a second transparent conductive layer on the second doped layer.

[0028] In one embodiment, in the step of forming a first transparent conductive layer on the second region of the first doped layer and forming an insulating separation layer on the third region, the water vapor partial pressure in the reaction chamber is 3e -3 Pa to 9.5e -3 Pa.

[0029] In one embodiment, the step of providing a substrate specifically includes: Forming a first intrinsic silicon layer on a first surface of the substrate, covering at least a part of the surfaces of the first surface and a plurality of side surfaces. Forming a second intrinsic silicon layer on a second surface of the substrate, wherein the second intrinsic silicon layer covers at least a part of the surfaces of the second surface and a plurality of side surfaces, and a part of the structure of the second intrinsic silicon layer is laminated on the surface of the first intrinsic silicon layer away from the substrate. Forming a second doped layer on the surface of the second intrinsic silicon layer away from the substrate, wherein the second doped layer covers at least a part of the surfaces of the second surface and a plurality of side surfaces, and a part of the structure of the second doped layer is laminated on the surface of the first intrinsic silicon layer away from the substrate. Forming a first doped layer on the surface of the first intrinsic silicon layer away from the substrate, wherein the first doped layer covers at least a part of the surfaces of the first surface and a plurality of side surfaces, and a part of the structure of the first doped layer is laminated on the surface of the second doped layer away from the substrate.

[0030] In one embodiment, after the step of forming the second transparent conductive layer on the second doped layer, the method further includes: forming a first electrode on the first transparent conductive layer; forming a second electrode on the second transparent conductive layer, wherein a projection of the first electrode onto a first plane and a projection of the second electrode onto the first plane are offset from each other, and the first plane is perpendicular to the thickness direction of the substrate.

[0031] The solar power generation module according to the third aspect of the embodiments of the present application includes at least one battery string, and each battery string includes at least two of the above heterojunction solar cells.

[0032] The solar power generation system according to the fourth aspect of the embodiments of the present application includes the above solar power generation module.

Advantages of the Invention

[0033] The beneficial effects of the above heterojunction solar cell, its manufacturing method, solar power generation module and solar power generation system are as follows. By providing the edge of the first transparent conductive layer and the edge of the second transparent conductive layer with a gap therebetween, a separation region is defined between the edge of the first transparent conductive layer and the edge of the second transparent conductive layer. Thereby, the first transparent conductive layer and the second transparent conductive layer can be effectively separated, short circuit caused by their contact can be avoided, and efficiency loss can be reduced. In addition, by covering at least a part of the surface of the side of the second transparent conductive layer, a high current density can be ensured, loss of the fill factor can be minimized, and the efficiency of the heterojunction solar cell can be further improved.

Brief Description of the Drawings

[0034]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Embodiments for Carrying Out the Invention

[0035] To make the above objects, features, and advantages of the present application clearer and easier to understand, the following will describe specific embodiments of the present application in detail with reference to the accompanying drawings. In the following description, many specific details are set forth in order to provide a complete understanding of the present application. However, the present application can be implemented in many other forms different from those described herein, and those skilled in the art can make similar improvements without departing from the spirit of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0036] In the description of the present invention, the orientation or positional relationship indicated by terms such as "center", "longitudinal direction", "lateral direction", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial direction", "radial direction", "circumferential direction" is the orientation or positional relationship shown in the drawings, and is only used to make the description of the present invention easier or to simplify the description, and it should be understood that it does not represent or imply that the indicated device or component necessarily has a specific orientation and a specific orientation structure and operation. Therefore, it should not be construed as limiting the present invention.

[0037] Also, the terms "first" and "second" are only used for the purpose of explanation and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features limited to "first" and "second" may include at least one of such features explicitly or implicitly. In the description of the present invention, unless there is a clear and specific limitation, "a plurality" means at least two, for example, two, three, etc.

[0038] In the present invention, unless otherwise clearly defined or limited, terms such as "attachment", "connection", and "coupling" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection, a mechanical connection, an electrical connection, a direct connection, or an indirect connection via an intermediate medium, or it may be the communication inside two members or the interaction relationship between two members. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to specific situations.

[0039] In the present invention, unless otherwise specified, the fact that the first feature is "above" or "below" the second feature may mean that the first and second features are in direct contact, or that the first and second features are indirectly in contact via an intermediate medium. Also, the fact that the first feature is "above", "upward", and "upper surface" of the second feature includes that the first feature is directly above or obliquely above the second feature, or only represents that the horizontal height of the first feature is higher than that of the second feature. The fact that the first feature is "below", "downward", and "lower surface" of the second feature includes that the first feature is directly below or obliquely below the second feature, or only represents that the horizontal height of the first feature is lower than that of the second feature.

[0040] It should be noted that when an element is referred to as being "fixed to" or "provided on" another element, it may be directly present on the other element or there may be intervening elements. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be intervening elements at the same time. The terms "vertical", "horizontal", "above", "below", "left", "right", and similar expressions used in this specification are for illustrative purposes only and do not represent the only embodiments.

[0041] Hereinafter, with reference to the drawings, a heterojunction solar cell according to an embodiment of the present application, a method for manufacturing the same, a solar power generation module, and a solar power generation system will be described.

[0042] FIG. 1 is a schematic structural view of a heterojunction solar cell according to an embodiment of the present application, and FIG. 2 is a schematic view of a film layer structure on a side surface of the heterojunction solar cell according to the embodiment of the present application.

[0043] In the drawings of the present application, only the structure of one corner portion in the longitudinal sectional view along the thickness direction of the heterojunction solar cell 100 is illustrated. However, since the same applies to other portions not shown in the sectional view of the heterojunction solar cell 100, the description thereof is omitted here. Further, in these drawings, only a schematic view of the film layer structure on one side surface of the heterojunction solar cell 100 is shown. However, since the same applies to the structures of other side surfaces of the heterojunction solar cell 100, the description thereof is omitted here.

[0044] As shown in FIGS. 1 and 2, a first aspect of the embodiment of the present application provides a heterojunction solar cell 100 including a substrate 10, a first intrinsic silicon layer 20, a first doped layer 30, a first transparent conductive layer 40, a second intrinsic silicon layer 50, a second doped layer 60, and a second transparent conductive layer 70.

[0045] The substrate 10 includes a first surface F and a second surface S provided opposite to each other, and a plurality of side surfaces C adjacent between the first surface F and the second surface S. The first intrinsic silicon layer 20, the first doped layer 30, and the first transparent conductive layer 40 are sequentially stacked and provided on the first surface F. The second intrinsic silicon layer 50, the second doped layer 60, and the second transparent conductive layer 70 are sequentially stacked and provided on the second surface S, and the doping type of the first doped layer 30 is opposite to the doping type of the second doped layer 60.

[0046] The first transparent conductive layer 40 covers at least a part of the surface of the first surface F, the second transparent conductive layer 70 covers at least a part of the surface of the second surface S and the plurality of side surfaces C, and the edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer are provided at an interval so as to define a separation region 81 therebetween.

[0047] The edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer are provided at an interval so as to define a separation region 81 therebetween. Thereby, the first transparent conductive layer 40 and the second transparent conductive layer 70 can be effectively separated, short - circuit due to their contact can be avoided, and efficiency loss can be reduced. Further, by covering at least a part of the surface of the side surface C with the second transparent conductive layer 70, a high current density can be guaranteed, loss of the fill factor can be minimized, and the efficiency of the heterojunction solar cell 100 can be further improved.

[0048] That the first transparent conductive layer 40 covers at least a part of the surface of the first surface F means that the first transparent conductive layer 40 covers a part of the surface of the first surface F or the first transparent conductive layer 40 covers the entire first surface F.

[0049] Here, the separation region 81 refers to a region where the edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer are electrically separated from each other. Also, in the embodiments of the present application, that one covers the other means that the arrangement range of one is large enough to cover the other, and does not limit whether or not the two are in direct contact. For example, that the first transparent conductive layer 40 covers the entire first surface F means that the projection of the first transparent conductive layer 40 onto the first surface F can completely cover the first surface F, the arrangement range of the first transparent conductive layer 40 is larger than the arrangement range of the first surface F, but it does not limit whether or not the first transparent conductive layer 40 and the first surface F are in direct contact.

[0050] In the embodiments of the present application, the first intrinsic silicon layer 20 and the second intrinsic silicon layer 50 exhibit amorphous or microcrystalline, mainly amorphous, and contain elements such as oxygen, carbon, nitrogen, etc. The first intrinsic silicon layer 20 and the second intrinsic silicon layer 50 may both be, for example, intrinsic amorphous silicon.

[0051] The first doped layer 30 or the second doped layer 60 is N-type or P-type doped, contains elements such as oxygen, carbon, nitrogen, etc., one of the doping types of both is N-type, and the other is P-type. Also, the first doped layer 30 and the second doped layer 60 exhibit amorphous or microcrystalline, with microcrystalline being the main. Exemplarily, one of the first doped layer 30 and the second doped layer 60 is P-type doped microcrystalline silicon, and the other is N-type doped microcrystalline silicon.

[0052] At least one of the first transparent conductive layer 40 and the second transparent conductive layer 70 includes a silver nanowire layer and at least two mutually laminated transparent conductive film layers (not shown), the materials of each transparent conductive film layer are different or the same, and one layer of silver nanowire layer is interposed between at least two transparent conductive film layers. A silver nanowire layer may be provided between any two adjacent transparent conductive film layers, or a silver nanowire layer may be provided between some of the transparent conductive film layers. Here, by providing silver nanowires, conductivity is guaranteed, the thickness of the transparent conductive film layer is reduced, thereby reducing the thickness of the first transparent conductive layer 40 and the second transparent conductive layer 70, and reducing the TCO usage amount in the transparent conductive film layer.

[0053] In another embodiment, at least one of the first transparent conductive layer 40 and the second transparent conductive layer 70 includes a silver nanowire layer and one transparent conductive film layer, and the silver nanowire layer may be provided on the surface facing the substrate 10 in the transparent conductive film layer. In this way, the thickness of the first transparent conductive layer 40 and the second transparent conductive layer 70 can be similarly reduced.

[0054] Here, the material of the transparent conductive film layer may be, for example, indium oxide (ITO), indium tungsten oxide (IWO), indium cobalt oxide (ICO), zinc oxide (AZO), etc.

[0055] In the embodiment of the present application, the heterojunction solar cell 100 further includes a dielectric layer (not shown), and at least one dielectric layer is provided on the surface of the first transparent conductive layer 40 away from the substrate 10.

[0056] Furthermore, at least one dielectric layer is provided on the surface of the second transparent conductive layer 70 away from the substrate 10. Here, the dielectric layer may include at least one of an antireflection layer and a passivation layer. The material of the dielectric layer may include at least one of SiO2, SiNx, and SiON.

[0057] In an embodiment of the present application, as shown in FIG. 1, the heterojunction solar cell 100 may further include a first electrode 91 and a second electrode 92. The first electrode 91 is provided on the first transparent conductive layer 40, and the second electrode 92 is provided on the second transparent conductive layer 70. Specifically, when provided, the projection of the first electrode 91 on the first plane and the projection of the second electrode 92 on the first plane may be shifted from each other, and the first plane is perpendicular to the thickness direction of the substrate 10. In this way, the metal grid lines at both electrodes of the heterojunction solar cell 100 are not aligned. In this way, the first electrode 91 located on the first surface F side (back surface) can improve the current density of the heterojunction solar cell 100 by reflecting the light rays incident on the first electrode 91 and the first transparent conductive layer 40.

[0058] In an embodiment of the present application, referring to FIGS. 1 and 2 regarding the arrangement status of each film layer, the second doped layer 60 covers the second intrinsic silicon layer 50, and the second transparent conductive layer 70 covers the second doped layer 60, that is, the arrangement range of the second intrinsic silicon layer 50 is smaller than that of the second doped layer 60 and cannot extend outside the coverage range of the second doped layer 60. The arrangement range of the second doped layer 60 is smaller than that of the second transparent conductive layer 70 and cannot extend outside the coverage range of the second transparent conductive layer 70. The arrangement range of the first intrinsic silicon layer 20 is larger than that of the first doped layer 30 and can extend outside the coverage range of the first doped layer 30.

[0059] The first intrinsic silicon layer 20 and the first doped layer 30 may overlap with the second intrinsic silicon layer 50 and the second doped layer 60 on the side surface C of the substrate 10, or may have a gap without contacting each other. Here, an example will be described in which the first intrinsic silicon layer 20 and the first doped layer 30 can overlap a part of the structure of the second intrinsic silicon layer 50 and the second doped layer 60 on the side surface C of the substrate 10.

[0060] In the embodiment of the present application, the first doped layer 30 may cover at least a part of the surface of the first surface F and the plurality of side surfaces C, or the first doped layer 30 may be provided only on the first surface F side and may not extend to the side surface C.

[0061] When the first doped layer 30 covers at least a part of the surface of the first surface F and the plurality of side surfaces C, both the second intrinsic silicon layer 50 and the second doped layer 60 cover at least a part of the surface of the second surface S and the plurality of side surfaces C. The first intrinsic silicon layer 20 covers at least a part of the surface of the first surface F and the plurality of side surfaces C. A part of the structure of the second intrinsic silicon layer 50 is laminated on the surface of the first intrinsic silicon layer 20 away from the substrate 10. A part of the structure of the second doped layer 60 is laminated on the surface of the first intrinsic silicon layer 20 away from the substrate 10. A part of the structure of the first doped layer 30 is laminated on the surface of the second doped layer 60 away from the substrate 10. In this way, the current density can be improved, the loss of the fill factor can be minimized, and the efficiency of the heterojunction solar cell 100 can be further improved. Of course, the lamination relationship between the first intrinsic silicon layer 20 and the first doped layer 30 and the second intrinsic silicon layer 50 and the second doped layer 60 is not limited to this, and may be other. It is mainly related to the formation order between these film layers. A part of the structure of the later film layer in the manufacturing process is laminated on the adjacent earlier film layer structure in the manufacturing process.

[0062] In an embodiment of the present application, the first transparent conductive layer 40 may be provided only on the first surface F side, that is, the first transparent conductive layer 40 does not extend to the side surface C. In order to ensure that the first transparent conductive layer 40 is separated from the second transparent conductive layer 70 as much as possible, the first transparent conductive layer 40 may cover only a part of the first surface F. For example, the edge 41 of the first transparent conductive layer may be located inside the boundary of the first surface F. Of course, the present application includes such situations, but is not limited thereto. The arrangement range of the first transparent conductive layer 40 can extend to the side surface C of the substrate 10.

[0063] FIG. 3 is a schematic structural view of a heterojunction solar cell 100 according to another embodiment of the present application. FIG. 4 is a schematic structural view of a heterojunction solar cell 100 according to still another embodiment of the present application. FIG. 5 is a schematic structural view of a heterojunction solar cell 100 according to still another embodiment of the present application.

[0064] Referring to FIG. 3, when the first transparent conductive layer 40 is provided on the first surface F, the thickness of the film layer in the first region Z1 near the edge of the first transparent conductive layer 40 gradually decreases along the first direction Y, and the first direction Y is from the center of the first transparent conductive layer 40 toward the edge 41 of the first transparent conductive layer and is parallel to the first surface F. Further, the minimum width dimension D5 of the first region Z1 along the first direction Y is 100 μm.

[0065] In an embodiment of the present application, regarding the arrangement region of the second transparent conductive layer 70, as shown in FIGS. 1 and 3, the edge 71 of the second transparent conductive layer may be located on the side surface C. Alternatively, as shown in FIGS. 4 and 5, the second transparent conductive layer 70 may completely cover each side surface C and also cover a part of the region of the first surface F.

[0066] As shown in FIGS. 1 and 3, when the edge 71 of the second transparent conductive layer is located on the side surface C, the minimum distance D1 between the edge 41 of the first transparent conductive layer and the boundary of the first surface F is 100 μm. Since the edge 41 of the first transparent conductive layer may have an irregular shape, the distance between the edge 41 of the first transparent conductive layer and the boundary of the first surface F may refer to the distance between any point on the edge 41 of the first transparent conductive layer and the corresponding point on the boundary line of the first surface F. At this distance, the minimum distance D1 is 100 μm. In this case, since the edge 41 of the first transparent conductive layer has a sufficient distance from the side surface C of the substrate 10, that is, the edge 71 of the second transparent conductive layer, the first transparent conductive layer 40 and the second transparent conductive layer 70 can be effectively separated to avoid short - circuit.

[0067] Furthermore, the maximum distance D2 between the edge 71 of the second transparent conductive layer and the first surface F is 100 μm. In this way, the second transparent conductive layer 70 has a sufficiently large covering area on the side surface C of the substrate 10, can improve the current density as much as possible, and minimize the loss of the fill factor, thereby improving the efficiency of the heterojunction solar cell 100.

[0068] As shown in FIGS. 4 and 5, when the second transparent conductive layer 70 completely covers each side surface C and also covers a part of the region of the first surface F, the edge 71 of the second transparent conductive layer is located outside the edge 41 of the first transparent conductive layer.

[0069] Furthermore, the minimum distance D3 between the edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer is 50 μm. In this way, when both the edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer are located on the first surface F, there is a sufficient distance between the edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer, and the first transparent conductive layer 40 and the second transparent conductive layer 70 can be effectively separated to avoid short - circuit.

[0070] In addition, the maximum distance D4 between the edge 71 of the second transparent conductive layer and the boundary with the first surface F is 1000 μm. This is to control the arrangement range of the second transparent conductive layer 70 on the first surface F. The smaller the distance between the edge 71 of the second transparent conductive layer and the boundary with the first surface F, the better. The electroplating covering on the first surface F of the second transparent conductive layer 70 causes a decrease in the parallel resistance of the battery and affects the fill factor of the heterojunction solar cell 100. By limiting the maximum distance D4 to 1000 μm, the occurrence of such a situation can be avoided.

[0071] Furthermore, regardless of whether the position of the edge 71 of the second transparent conductive layer corresponds to the side surface C or the first surface F, the edge 71 of the second transparent conductive layer can be laminated on the surface away from the substrate 10 of the first doped layer 30.

[0072] FIG. 6 is a schematic structural diagram of a heterojunction solar cell 100 according to still another embodiment of the present application. FIG. 7 is a schematic diagram of the film layer structure on the battery side surface C of the heterojunction solar cell 100 in FIG. 6. FIG. 8 is a schematic structural diagram of a heterojunction solar cell 100 according to still another embodiment of the present application. FIG. 9 is a schematic diagram of the film layer structure close to the corner region of the battery on the first surface of the heterojunction solar cell 100 in FIG. 8.

[0073] In the embodiments of the present application, in order to improve the separation effect of the separation region 81, it is also conceivable to provide an insulating separation layer 80 on the separation region 81.

[0074] Specifically, referring to FIGS. 1, 4, 6, and 8, the heterojunction solar cell 100 further includes an insulating separation layer 80 that is laminated and provided in the separation region 81 and at least covers the separation region 81. By providing the insulating separation layer 80, the separation region 81 can be insulated and protected, and the occurrence of short circuits can be further reduced.

[0075] Exemplarily, the material of the insulating separation layer 80 includes SiOx, and the insulating separation layer 80 is further doped with carbon and nitrogen elements.

[0076] Furthermore, the insulating isolation layer 80 is further doped with a first doping element, and the first doping element is the same as the doping element in the first doping layer 30.

[0077] Exemplarily, the thickness of the insulating isolation layer 80 is 1.8 nm or more. Thus, the insulating isolation layer 80 has a sufficient thickness to provide an insulating protection effect for the separation region 81.

[0078] In the embodiment of the present application, the arrangement range of the insulating isolation layer 80 may cover only the separation region 81, or may be slightly larger than the separation region 81.

[0079] Referring to FIGS. 1 and 4, as one possible embodiment, the insulating isolation layer 80 covers the separation region 81, and the edges of the insulating isolation layer 80 are adjacent to the edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer, respectively.

[0080] Continuing to refer to FIGS. 6, 7, 8, and 9, FIGS. 6 and 7 show the case where the edge 71 of the second transparent conductive layer is located on the side surface C, and FIGS. 8 and 9 show the case where the edge 71 of the second transparent conductive layer extends to the first surface F. In these two cases, the insulating isolation layer 80 covers the separation region 81 by completely covering the first doping layer 30, and at least a part of the structure of the insulating isolation layer 80 is located between the first doping layer 30 and the second transparent conductive layer 70. Thus, due to the thick thickness of the part of the insulating isolation layer 80 located between the first doping layer 30 and the second transparent conductive layer 70, the tunneling effect of carriers becomes difficult, achieving the purpose of separating the first doping layer 30 and the second transparent conductive layer 70. Of course, in these two cases, the insulating isolation layer 80 completely covers at least the first doping layer 30 to achieve the optimal separation purpose.

[0081] FIG. 10 is a schematic structural diagram of a heterojunction solar cell 100 according to still another embodiment of the present application.

[0082] In the embodiments of the present application, the first doped layer 30 and the second transparent conductive layer 70 do not necessarily need to be in direct contact. Specifically, when realized, as shown in FIG. 10, the first doped layer 30 is provided only on the first surface F and does not necessarily extend to the side surface C. Exemplarily, the first doped layer 30 covers the first surface F, and the edges of the second transparent conductive layer 70 are located on each side surface C of the substrate 10. In this way, the contact between the second transparent conductive layer 70 and the first doped layer 30 is avoided as much as possible.

[0083] FIG. 11 is a flowchart of a method for manufacturing a heterojunction solar cell according to an embodiment of the present application, and FIG. 12 is a schematic structural view of a substrate 110 in the method for manufacturing a heterojunction solar cell according to an embodiment of the present application. FIG. 13 is a schematic view of forming a first transparent conductive layer 40 and an insulating separation layer 80 on the substrate 110 in the method for manufacturing a heterojunction solar cell according to an embodiment of the present application, and FIG. 14 is a schematic structural view of a heterojunction solar cell 100 formed by the method for manufacturing a heterojunction solar cell according to an embodiment of the present application.

[0084] Referring to FIGS. 1, 11, and 12, the method for manufacturing a heterojunction solar cell according to the second aspect of the embodiment of the present application includes the following steps S10 to S30.

[0085] In S10, a substrate 110 is provided. The substrate 110 includes a substrate 10, and the substrate 10 includes a first surface F and a second surface S provided opposite to each other, and a plurality of side surfaces C adjacent between the first surface F and the second surface S. The substrate 110 further includes a first intrinsic silicon layer 20 and a first doped layer 30 sequentially stacked on the first surface F, and a second intrinsic silicon layer 50 and a second doped layer 60 sequentially stacked on the second surface S. The doping type of the second doped layer 60 is opposite to that of the first doped layer 30.

[0086] In S20, a first transparent conductive layer 40 covering at least a part of the surface of the first surface F is formed on the first doped layer 30.

[0087] In S30, a second transparent conductive layer 70 that covers at least a part of the surfaces of the second surface S and the plurality of side surfaces C is formed on the second doped layer 60, and the edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer are provided with a gap therebetween, thereby defining a separation region 81 between the edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer.

[0088] In the embodiment of the present application, by providing the edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer with a gap therebetween, a separation region 81 is defined between the edge 41 of the first transparent conductive layer and the edge 71 of the second transparent conductive layer. Thereby, the first transparent conductive layer 40 and the second transparent conductive layer 70 can be effectively separated, short - circuit due to their contact can be avoided, and efficiency loss can be reduced. Also, since the second transparent conductive layer 70 covers at least a part of the side surface C, a high current density can be guaranteed, loss of the fill factor can be minimized, and the efficiency of the heterojunction solar cell 100 can be further improved.

[0089] Referring to FIG. 12, in the above step S10, the step of providing the substrate 110 specifically includes forming a first intrinsic silicon layer 20 that covers at least a part of the surfaces of the first surface F and the plurality of side surfaces C on the first surface F of the substrate 10; forming a second intrinsic silicon layer 50 on the second surface S of the substrate 10, wherein the second intrinsic silicon layer 50 covers at least a part of the second surface S and the plurality of side surfaces C, and a part of the structure of the second intrinsic silicon layer 50 is laminated on the surface of the first intrinsic silicon layer 20 away from the substrate 10; forming a second doped layer 60 on the surface of the second intrinsic silicon layer 50 away from the substrate 10, wherein the second doped layer 60 covers at least a part of the surfaces of the second surface S and the plurality of side surfaces C, and a part of the structure of the second doped layer 60 is laminated on the surface of the first intrinsic silicon layer 20 away from the substrate 10; Forming a first doped layer 30 on a surface of the first true silicon layer 20 away from the substrate 10, the first doped layer 30 covering at least a part of the surface of the first surface F and a plurality of side surfaces C, and a part of the structure of the first doped layer 30 being laminated on a surface of the second doped layer 60 away from the substrate 10.

[0090] In an embodiment of the present application, in step S20 and step S30, forming a first transparent conductive layer 40 on the first doped layer 30 and forming a second transparent conductive layer 70 on the second doped layer 60 includes forming a first transparent conductive layer 40 on the first doped layer 30, forming a second transparent conductive layer 70 on the second doped layer 60, and forming an insulating separation layer 80 covering at least the separation region 81 on the separation region 81.

[0091] Here, the insulating separation layer 80 may be formed simultaneously in the steps of forming the first transparent conductive layer 40 and the second transparent conductive layer 70. For example, the insulating separation layer 80 may be formed in the process of forming the first transparent conductive layer 40.

[0092] Exemplarily, referring to FIGS. 13, 6, and 14, forming a first transparent conductive layer 40 on the first doped layer 30, forming a second transparent conductive layer 70 on the second doped layer 60, and forming an insulating separation layer 80 on the separation region 81 specifically includes the following steps. Put a carrier plate 120 with a cutout portion 121 formed in the center into a reaction chamber (not shown). Place the substrate 110 on the carrier plate 120, direct the first doped layer 30 towards the carrier plate 120, expose a second region of the first doped layer 30 to the outside from the cutout portion 121, and the second region is a region of the first doped layer 30 corresponding to the cutout portion 121. The first doped layer 30 further includes a third region which is a portion other than the second region on the surface of the first doped layer 30 away from the substrate 10. Form a first transparent conductive layer 40 on the second region of the first doped layer 30 and form an insulating separation layer 80 on the third region of the first doped layer 30. Form a second transparent conductive layer 70 on the second doped layer 60.

[0093] A part of the structure of the edge 71 of the second transparent conductive layer may be laminated on the surface of the insulating separation layer 80 away from the substrate 10. In this way, a part in the third region not covered by the edge 71 of the second transparent conductive layer forms a separation region 81. In this way, while covering the separation region 81, the part of the insulating separation layer 80 located between the second transparent conductive layer 70 and the first doped layer 30 functions as insulation separation.

[0094] Also, as shown in FIG. 3, due to the influence of the edge of the cutout portion 121 of the carrier plate 120, the thickness of the film layer in the first region Z1 close to the edge in the first transparent conductive layer 40 formed at this time gradually decreases along the first direction.

[0095] Exemplarily, in the step of forming the first transparent conductive layer 40 in the second region of the first doped layer 30 and forming the insulating separation layer 80 in the third region of the first doped layer 30, the water vapor partial pressure in the reaction chamber is 3e -3 Pa to 9.5e -3 Pa, preferably 5e -3 Pa to 8e -3 Pa. The temperature of the carrier plate 120 may be set higher than 85°C. The formation of the insulating separation layer 80 is realized by controlling the water vapor partial pressure in the reaction chamber.

[0096] The first transparent conductive layer 40 may be formed by, for example, PVD. The plasma of the target of the first transparent conductive layer 40 (including water vapor and oxygen-containing ions) passes through the cutout portion 121 region shown in FIG. 13 and then forms on the surface of the second region to form the first transparent conductive layer 40. At the same time, the free oxygen-containing ions also form an insulating separation layer 80 on the part other than the second region of the first doped layer 30.

[0097] Specifically, due to a high water vapor pressure, a temperature of the carrier plate 120 higher than 85°C, and an oxygen-containing plasma, in a region of the surface of the first doped layer 30 away from the substrate 10 blocked by the carrier plate 120 and a portion other than the second region on the surface, are oxidized by free oxygen-containing ions to form an insulating separation layer 80, and the oxygen-containing ions include, for example, O - ions, HO - ions. A part of the structure of the formed insulating separation layer 80 is located on the first surface F, and another part of the structure extends to the side surface C of the substrate 10.

[0098] Since the second transparent conductive layer 70 is manufactured after the insulating separation layer 80 is formed, the insulating separation layer 80 separates the second transparent conductive layer 70 from the first doped layer 30, the thickness of the insulating separation layer 80 is 1.8 nm or more, and silicon oxide with this thickness is no longer regarded as a tunnel layer and has a high resistance, thereby playing a role of electrically insulating the second transparent conductive layer 70 and the first doped layer 30 in the overlapping region between the second transparent conductive layer 70 and the first doped layer 30. Since the insulating separation layer 80 is formed on the surface of the first doped layer 30, the doping element in the insulating separation layer 80 may be partially the same as that in the first doped layer 30, for example, it may be boron.

[0099] In the embodiment of the present application, in step S30, after the step of forming the second transparent conductive layer 70 on the second doped layer 60, the step of forming the first electrode 91 on the first transparent conductive layer 40 and the step of forming the second electrode 92 on the second transparent conductive layer 70, wherein the projection of the first electrode 91 on the first plane and the projection of the second electrode 92 on the first plane are shifted from each other, and the first plane is perpendicular to the thickness direction of the substrate 10, are further included.

[0100] Hereinafter, referring to FIGS. 12, 13, and 14, a manufacturing method of a heterojunction solar cell according to the present application will be described with specific examples, and the method includes the following steps 1 to 5.

[0101] In step 1, the substrate 10 is cleaned through a cleaning and texturing process, and a pyramidal texture structure is manufactured on the surface of the substrate 10.

[0102] In step 2, the first intrinsic silicon layer 20, the second intrinsic silicon layer 50, the second doped layer 60, and the first doped layer 30 are deposited in sequence by a PECVD apparatus. Specifically, the first intrinsic silicon layer 20 is formed on the first surface F of the substrate 110, the second intrinsic silicon layer 50 is formed on the second surface S of the substrate 110, the second doped layer 60 is formed on the surface of the second intrinsic silicon layer 50 away from the substrate 10, and the first doped layer 30 is formed on the surface of the first intrinsic silicon layer 20 away from the substrate 10.

[0103] In step 3, the first transparent conductive layer 40, the insulating isolation layer 80, and the second transparent conductive layer 70 are manufactured in sequence by a PVD apparatus or an RPD apparatus. Specifically, the substrate 10 on which the first doped layer 30 is formed is placed on the carrier plate 120, the first doped layer 30 is oriented towards the carrier plate 120, the second region of the first doped layer 30 is exposed to the outside from the cutout portion 121, the water vapor partial pressure in the reaction chamber is set to 3e -3 Pa~9.5e -3 Pa. When the temperature of the carrier plate 120 is greater than 85 °C, the first transparent conductive layer 40 is formed in the second region of the first doped layer 30, and the insulating isolation layer 80 is formed in the remaining region of the first doped layer 30, that is, the third region. Next, the second transparent conductive layer 70 is formed on the second doped layer 60.

[0104] In step 4, a metal paste is printed on the first transparent conductive layer 40 and the second transparent conductive layer 70 by screen printing and cured at a certain temperature to form the first electrode 91 and the second electrode 92 respectively.

[0105] In step 5, light injection and annealing are performed by a light injection apparatus to form the heterojunction solar cell 100.

[0106] The third aspect of the present application is that the photovoltaic module includes at least one battery string, and each battery string includes at least two of the above heterojunction solar cells 100.

[0107] Between each heterojunction solar cell 100, they are connected by series welding, so that the electrical energy generated by a single heterojunction solar cell 100 can be collected for subsequent transportation. In one embodiment, the heterojunction solar cells 100 may be arranged at intervals or stacked.

[0108] Exemplarily, the photovoltaic module further includes a sealing layer covering the surface of the battery string and a cover plate covering the surface of the sealing layer away from the battery string.

[0109] The photovoltaic power generation system according to the fourth aspect of the present application includes the above photovoltaic module.

[0110] The photovoltaic power generation system can be applied to photovoltaic power generation plants such as ground power plants, rooftop power plants, and water surface power plants, and can also be applied to facilities or devices that generate electricity using sunlight, such as user photovoltaic power sources, solar street lights, solar cars, and solar buildings. Of course, as understood, the application scenarios of the photovoltaic power generation system are not limited to this. That is, the photovoltaic power generation system is applicable to any field that requires power generation by sunlight. Taking the photovoltaic power generation system network as an example, the photovoltaic power generation system may include a photovoltaic power generation array, a power collection box, and an inverter. The photovoltaic power generation array can be a combination of an array of a plurality of photovoltaic modules. For example, a plurality of photovoltaic modules can form a plurality of photovoltaic power generation arrays. The photovoltaic power generation array is connected to the power collection box, and the power collection box can collect the current generated by the photovoltaic power generation array. The collected current is converted into alternating current required by the commercial power grid through an inverter and then connected to the commercial power grid to realize photovoltaic power supply.

[0111] Each of the technical features of the above-described embodiments may be arbitrarily combined. For the sake of brevity, not all possible combinations of the technical features in the above-described embodiments are described, but all these combinations should be considered to fall within the scope described in this specification.

[0112] The above has described some aspects of the present invention with reference to specific embodiments, but it should not be understood as limiting the patent scope of the present invention. For those skilled in the art, various modifications and improvements may be made to the present invention without departing from the spirit of the present invention, and these modifications and corrections also belong to the scope of the present invention. Therefore, the protection scope of the present invention depends on the appended claims.

Description of Reference Numerals

[0113] 100 Heterojunction solar cell 110 Substrate 10 Substrate 20 First intrinsic silicon layer 30 First doped layer 40 First transparent conductive layer 41 Edge of the first transparent conductive layer 50 Second intrinsic silicon layer 60 Second doped layer 70 Second transparent conductive layer 71 Edge of the second transparent conductive layer 80 Insulating separation layer 81 Separation region 91 First electrode 92 Second electrode 120 Carrier plate 121 Cutout portion F First surface S Second surface C Side surface Z1 First region Y First direction

Claims

1. a substrate, a first intrinsic silicon layer, a first doped layer, a first transparent conductive layer, a second intrinsic silicon layer, a second doped layer, and a second transparent conductive layer; the substrate includes a first surface and a second surface opposed to each other, and a plurality of side surfaces adjacent to the first surface and the second surface; the first intrinsic silicon layer, the first doped layer, and the first transparent conductive layer are stacked in order on the first surface; the second intrinsic silicon layer, the second doped layer and the second transparent conductive layer are sequentially stacked on the second surface, and the doping type of the first doped layer is opposite to the doping type of the second doped layer; the first transparent conductive layer covers at least a portion of the first surface, the second transparent conductive layer covers the second surface and at least a portion of the surfaces of the side surfaces, and an edge of the first transparent conductive layer and an edge of the second transparent conductive layer are spaced apart to define a separation region between the edge of the first transparent conductive layer and the edge of the second transparent conductive layer; the first doped layer covers a portion of the surfaces of the side surfaces, a portion of the second transparent conductive layer is located on a side of the first doped layer away from the substrate, and the second transparent conductive layer and the first doped layer have a film layer region that faces each other; The heterojunction solar cell further includes an insulating isolation layer disposed on a surface of the isolation region and completely covering the isolation region; a portion of the insulating separation layer directly contacts the opposite film layer regions of the second transparent conductive layer and the first doped layer, and is located between the opposite film layer regions of the second transparent conductive layer and the first doped layer; an edge of the second transparent conductive layer is disposed on a side of the first doped layer away from the substrate; the second intrinsic silicon layer and the second doped layer both cover the second surface and at least a portion of the surfaces of the side surfaces; the first intrinsic silicon layer covers the first surface and at least a portion of the surfaces of the side surfaces; A heterojunction solar cell, characterized in that a portion of the structure of the second intrinsic silicon layer is stacked on a side of the first intrinsic silicon layer away from the substrate, a portion of the structure of the second doped layer is stacked on a side of the first intrinsic silicon layer away from the substrate, and a portion of the structure of the first doped layer is stacked on a side of the second doped layer away from the substrate.

2. The heterojunction solar cell of claim 1 , wherein an edge of the second transparent conductive layer is located on the side surface.

3. an edge of the first transparent conductive layer is located within a boundary of the first surface; 3. The heterojunction solar cell of claim 2, wherein the minimum distance D1 between the edge of the first transparent conductive layer and the boundary of the first surface is 100 μm.

4. 3. The heterojunction solar cell of claim 2, wherein the maximum distance D2 between the edge of the second transparent conductive layer and the first surface is 100 μm.

5. the second transparent conductive layer completely covers each of the side surfaces and covers a partial area of ​​the first surface; The heterojunction solar cell of claim 1 , wherein an edge of the second transparent conductive layer is located outside an edge of the first transparent conductive layer.

6. 6. The heterojunction solar cell of claim 5, wherein the minimum distance D3 between an edge of the first transparent conductive layer and an edge of the second transparent conductive layer is 50 μm.

7. 6. The heterojunction solar cell of claim 5, wherein the maximum distance D4 between the edge of the second transparent conductive layer and the boundary of the first surface is 1000 μm.

8. 2. The heterojunction solar cell of claim 1, wherein the insulating isolation layer has a thickness of 1.8 nm or more.

9. 2. The heterojunction solar cell of claim 1, wherein an edge of the insulating isolation layer is adjacent to an edge of the first transparent conductive layer.

10. The material of the insulating separation layer includes SiOx, The insulating isolation layer is further doped with carbon and nitrogen elements, and / or 2. The heterojunction solar cell of claim 1, wherein the insulating isolation layer is further doped with a first doping element, the first doping element being the same as the doping element in the first doped layer.

11. The heterojunction solar cell of claim 1 , wherein an edge of the second transparent conductive layer is located on each of the sides of the substrate.

12. 2. The heterojunction solar cell of claim 1, wherein the thickness of the film layer in a first region near an edge of the first transparent conductive layer gradually decreases along a first direction, the first direction being from a center of the first transparent conductive layer to an edge of the first transparent conductive layer and parallel to the first surface.

13. The heterojunction solar cell of claim 12 , wherein the first region has a minimum width dimension D5 along the first direction of 100 μm.

14. Further comprising a first electrode and a second electrode, the first electrode is provided on the first transparent conductive layer, and the second electrode is provided on the second transparent conductive layer; 2. The heterojunction solar cell of claim 1, wherein a projection of the first electrode onto the first plane and a projection of the second electrode onto the first plane are offset from each other, and the first plane is perpendicular to a thickness direction of the substrate.

15. The heterojunction solar cell of claim 1, characterized in that at least one of the first transparent conductive layer and the second transparent conductive layer includes a silver nanowire layer and at least two transparent conductive film layers stacked on top of each other, the transparent conductive film layers being made of different materials, and one silver nanowire layer being interposed between the at least two transparent conductive film layers.

16. further comprising a dielectric layer; At least one of the dielectric layers is provided on a surface of the first transparent conductive layer remote from the substrate; and / or 16. The heterojunction solar cell of claim 15, wherein at least one of the dielectric layers is provided on a surface of the second transparent conductive layer remote from the substrate.

17. 2. The heterojunction solar cell of claim 1, wherein at least one of the first transparent conductive layer and the second transparent conductive layer includes a silver nanowire layer and one transparent conductive film layer, and the silver nanowire layer is provided on a surface of the transparent conductive film layer facing the substrate.

18. providing a substrate, the substrate including a substrate having a first surface and a second surface opposed to each other, and a plurality of side surfaces adjacent to the first surface and the second surface, the substrate further including a first intrinsic silicon layer and a first doped layer sequentially stacked on the first surface, and a second intrinsic silicon layer and a second doped layer sequentially stacked on the second surface, the second doped layer having a doped type opposite to that of the first doped layer, the first doped layer covering a portion of the surfaces of the plurality of side surfaces; forming a first transparent conductive layer on the first doped layer, the first transparent conductive layer covering at least a portion of the first surface; forming a second transparent conductive layer on the second doped layer to cover the second surface and at least a portion of the surfaces of the side surfaces, and defining a separation region between an edge of the first transparent conductive layer and an edge of the second transparent conductive layer by spacing an edge of the first transparent conductive layer and an edge of the second transparent conductive layer; forming an insulating isolation layer over the isolation region, the insulating isolation layer completely covering the isolation region; a portion of the second transparent conductive layer is located on a side of the first doped layer away from the substrate, and the second transparent conductive layer and the first doped layer have a film layer region that faces each other; a portion of the insulating separation layer directly contacts the opposite film layer regions of the second transparent conductive layer and the first doped layer, and is located between the opposite film layer regions of the second transparent conductive layer and the first doped layer; an edge of the second transparent conductive layer is disposed on a side of the first doped layer away from the substrate; The step of providing a substrate specifically includes: forming a first intrinsic silicon layer on a first surface of the substrate, the first surface covering the first surface and at least a portion of the surfaces of the side surfaces; forming a second intrinsic silicon layer on a second surface of the substrate, the second intrinsic silicon layer covering the second surface and at least a portion of the surfaces of the side surfaces, and a portion of the structure of the second intrinsic silicon layer being stacked on a side of the first intrinsic silicon layer away from the substrate; forming a second doped layer on a surface of the second intrinsic silicon layer away from the substrate, the second doped layer covering the second surface and at least a portion of the surfaces of the side surfaces, and a portion of the structure of the second doped layer being stacked on a side of the first intrinsic silicon layer away from the substrate; forming a first doped layer on a surface of the first intrinsic silicon layer away from the substrate, the first doped layer covering the first surface and at least a portion of the surfaces of the multiple side surfaces, and a portion of the structure of the first doped layer being stacked on a side of the second doped layer away from the substrate.

19. The steps of forming a first transparent conductive layer on the first doped layer, forming a second transparent conductive layer on the second doped layer, and forming an insulating separation layer on the separation region specifically include: a step of placing a carrier plate having a hollow portion formed in a center thereof into a reaction chamber; placing the substrate on the carrier plate, with the first doped layer facing the carrier plate, and exposing a second region of the first doped layer to the outside through the hollow portion, the first doped layer further including a third region which is a portion of the surface of the first doped layer away from the substrate other than the second region; forming the first transparent conductive layer in a second region of the first doped layer and forming the insulating isolation layer in a third region of the first doped layer; and forming a second transparent conductive layer on the second doped layer.

20. In the step of forming the first transparent conductive layer in the second region of the first doped layer and forming the insulating isolation layer in the third region, the partial pressure of water vapor in the reaction chamber is 3e －３ ~9.5e －３ The method for producing a heterojunction solar cell according to claim 19, wherein the first and second electrodes are each 0.1 to 0.5 Pa.

21. forming a first electrode on the first transparent conductive layer after the step of forming a second transparent conductive layer on the second doped layer; 21. The method for manufacturing a heterojunction solar cell according to any one of claims 18 to 20, further comprising a step of forming a second electrode on the second transparent conductive layer, wherein a projection of the first electrode onto a first plane and a projection of the second electrode onto the first plane are offset from each other, and the first plane is perpendicular to a thickness direction of the substrate.

22. A photovoltaic module comprising at least one cell string, each of said cell strings comprising at least two heterojunction solar cells according to any one of claims 1 to 17.

23. A photovoltaic power generation system comprising the photovoltaic power generation module according to claim 22.

Images