Semiconductor device

Abstract

This semiconductor apparatus comprises: a first conductive-type semiconductor layer that has a main surface and includes a device region; a second conductive-type base region that is formed on the surface layer of the main surface in the device region; a first conductive-type source region that is formed on the surface layer of the base region and defining a channel region between the first conductive-type source region and the semiconductor layer; a second conductive-type base contact region that is formed on the surface layer of the base region; a first conductive-type well region that is formed on the surface payer of the main surface at a distance from the base region in the device region and defines a drift region between the first conductive-type well region and the base region; a first conductive-type drain region that is formed on the surface layer of the well region; a second conductive-type impurity region that is formed on the surface layer of the well region; and a gate structure having a gate electrode facing the channel region with a gate insulating film therebetween and electrically connected to the source region and the base contact region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having an EIS (Electrode-Insulator-Semiconductor) type diode structure with a laminated structure of an electrode, an insulator, and a semiconductor.

Background Art

[0002] Patent Document 1 discloses a semiconductor device having an EIS type diode structure. This semiconductor device includes an n-type semiconductor substrate, a p-type base region, an n-type source region, a p-type anode region, an n-type cathode region, a gate insulating film, and a gate electrode.

[0003] The base region is formed in the surface layer portion of the semiconductor substrate. The source region is formed in the surface layer portion of the base region at an interval inward from the edge of the base region, and defines a channel region with the semiconductor substrate. The anode region is formed in a region different from the source region in the surface layer portion of the base region. The cathode region is formed in the surface layer portion of the semiconductor substrate at an interval from the base region, and defines a drift region with the base region. The gate insulating film covers the channel region on the semiconductor substrate. The gate electrode is formed on the gate insulating film and faces the channel region with the gate insulating film interposed therebetween. The gate electrode is electrically connected to the source region and the anode region.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The EIS-type diode structure has a structural feature of low electrostatic surge tolerance. The electrostatic surge tolerance is also referred to as the ESD (electro static discharge) tolerance.

[0006] One embodiment of the present invention provides a semiconductor device including an EIS-type diode structure and capable of improving the electrostatic surge tolerance.

Means for Solving the Problem

[0007] One embodiment of the present invention includes a semiconductor layer of a first conductivity type having a main surface and including a device region, a base region of a second conductivity type formed in a surface layer portion of the main surface in the device region, a source region of the first conductivity type formed in a surface layer portion of the base region at an inner side with a space from an edge portion of the base region and defining a channel region with the semiconductor layer, a base contact region of the second conductivity type formed in a region different from the source region in the surface layer portion of the base region and having an impurity concentration exceeding the impurity concentration of the base region, a well region of the first conductivity type formed in a surface layer portion of the main surface at a space from the base region in the device region and defining a drift region with the base region, a drain region of the first conductivity type formed in a surface layer portion of the well region, an impurity region of the second conductivity type formed in a surface layer portion of the well region and electrically connected to the drain region, a gate insulating film covering the channel region on the main surface, and a gate structure having a gate electrode facing the channel region on the gate insulating film and electrically connected to the source region and the base contact region.

[0008] This semiconductor device includes an EIS-type diode structure in a device region. Specifically, the diode structure includes a base region, a source region, a base contact region, a well region, a drain region, and a gate structure. Further, this semiconductor device includes a thyristor structure electrically connected to the diode structure in the device region. Specifically, the thyristor structure includes an impurity region (second conductivity type), a semiconductor layer (first conductivity type), a base region (second conductivity type), and a source region (first conductivity type) formed in this order along the main surface of the semiconductor layer.

[0009] More specifically, the thyristor structure includes a first transistor structure of a first polarity type on the well region side and a second transistor structure of a second polarity type on the base region side. The first transistor structure includes an impurity region (second conductivity type), a semiconductor layer (first conductivity type), and a base region (second conductivity type) formed in this order along the main surface of the semiconductor layer. The second transistor structure includes a source region (first conductivity type), a base region (second conductivity type), and a semiconductor layer (first conductivity type) formed in this order along the main surface of the semiconductor layer.

[0010] When a forward voltage is applied to the diode structure, the diode structure turns on while the thyristor structure turns off. The thyristor structure turns off because the drain region and the impurity region are fixed at the same potential. As a result, the diode structure conducts and a forward current flows through the diode structure. This forward voltage also flows through the first transistor structure electrically connected to the diode structure. Therefore, when a forward overvoltage caused by static electricity or the like is applied to the diode structure, the forward overcurrent can be handled by the diode structure and the first transistor structure.

[0011] On the one hand, when a reverse voltage is applied to the diode structure, the diode structure turns off while the thyristor structure turns on. As a result, the thyristor structure conducts and a reverse current flows through the thyristor structure. Therefore, when a reverse overvoltage caused by static electricity or the like is applied to the diode structure, the thyristor structure can handle the reverse overcurrent. Thus, according to this semiconductor device, the electrostatic surge tolerance can be improved.

[0012] The above-mentioned, or further other objects, features, and effects in the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0014] FIG. 1 is a circuit diagram showing the electrical structure of the main part of the semiconductor device 1 according to an embodiment of the present invention. The semiconductor device 1 is a transceiver integrated circuit device used for CAN (Controller Area Network), which is a type of in-vehicle network. The semiconductor device 1 includes an input terminal IN, an output terminal OUT, a power supply terminal VCC, a ground terminal GND, a high-side terminal CANH, a low-side terminal CANL, a control circuit 2, a high-side output circuit 3, a low-side output circuit 4, and a gate driver circuit 5.

[0015] The number of input terminals IN is arbitrary. In FIG. 1, an example is shown in which the input terminals IN include a first input terminal IN1 and a second input terminal IN2. In FIG. 1, an example is shown in which a microcomputer 6 is connected to the input terminal IN and the output terminal OUT, and a resistor dividing circuit 7, a capacitor 8, and a termination resistor 9 are connected between the high-side terminal CANH and the low-side terminal CANL.

[0016] The control circuit 2 is electrically connected to a plurality of input terminals IN, an output terminal OUT, and a ground terminal GND. The control circuit 2 includes an electrical signal generation circuit 10 and a function circuit 11. The electrical signal generation circuit 10 generates a predetermined electrical signal for driving various circuits based on an input signal from the input terminal IN, and outputs the signal to the various circuits. The function circuit 11 generates an electrical signal for monitoring various circuits based on an input signal from the input terminal IN or an electrical signal from various circuits, and outputs the signal to the output terminal OUT.

[0017] The function circuit 11 includes, for example, one or more protection circuits for protecting various circuits. As an example of the protection circuit, the function circuit 11 may include at least one of an overcurrent protection circuit, an overheat protection circuit, and a low-voltage malfunction suppression circuit. The overcurrent protection circuit protects various circuits from overcurrent. The overheat protection circuit protects various circuits from heating. The low-voltage malfunction suppression circuit suppresses malfunction of various circuits in a low-voltage state.

[0018] The high-side output circuit 3 is electrically connected to the power supply terminal VCC, the high-side terminal CANH, and the gate driver circuit 5. The high-side output circuit 3 has a series circuit including a first drive transistor 12, a first freewheeling diode 13, and a first protection transistor 14. The first drive transistor 12 and the first protection transistor 14 are each formed of a p-type (first polarity type or second polarity type) MISFET (Metal Insulator Field Effect Transistor).

[0019] The gate of the first drive transistor 12 is electrically connected to the gate driver circuit 5. The source of the first drive transistor 12 is connected to the power supply terminal VCC. The anode of the first freewheeling diode 13 is connected to the drain of the first drive transistor 12. The gate of the first protection transistor 14 is electrically connected to the ground terminal GND. The source of the first protection transistor 14 is connected to the cathode of the first freewheeling diode 13. The drain of the first protection transistor 14 is connected to the high-side terminal CANH. The first protection transistor 14 suppresses the outflow of current from the high-side terminal CANH to the outside (termination resistor 9 side) when the high-side terminal CANH becomes a negative voltage.

[0020] The low-side output circuit 4 is electrically connected to the ground terminal GND, the low-side terminal CANL, and the gate driver circuit 5. The low-side output circuit 4 has a series circuit including a second drive transistor 15, a second protection transistor 16, and a second freewheeling diode 17. The second drive transistor 15 and the second protection transistor 16 are each formed of an n-type MISFET having a polarity type opposite to that of the p-type.

[0021] The gate of the second drive transistor 15 is electrically connected to the gate driver circuit 5. The source of the second drive transistor 15 is connected to the ground terminal GND. The gate of the second protection transistor 16 is connected to the power supply terminal VCC. The source of the second protection transistor 16 is connected to the drain of the second drive transistor 15. The cathode of the second reverse current blocking diode 17 is connected to the drain of the second protection transistor 16. The anode of the second reverse current blocking diode 17 is connected to the low side terminal CANL. The second protection transistor 16 suppresses the inflow of current from the outside (termination resistor 9 side) to the low side terminal CANL when the low side terminal CANL becomes a positive voltage.

[0022] The gate driver circuit 5 is electrically connected to the control circuit 2, the high side output circuit 3, the low side output circuit 4, and the ground terminal GND. The gate driver circuit 5 generates a first control signal H / L having a predetermined pulse waveform and a second control signal L / H having a predetermined pulse waveform in response to an electrical signal from the control circuit 2. The second control signal L / H consists of an inverted signal of the first control signal H / L. The first control signal H / L is input to the gate of the first drive transistor 12, and the second control signal L / H is input to the gate of the second drive transistor 15.

[0023] The resistance dividing circuit 7 includes a first resistor R1 and a second resistor R2. One end of the first resistor R1 is connected to the high side terminal CANH. One end of the second resistor R2 is connected to the other end of the first resistor R1. The other end of the second resistor R2 is connected to the low side terminal CANL. One end of the capacitor 8 is connected to the connection portion of the first resistor R1 and the second resistor R2. The other end of the capacitor 8 is grounded. One end of the termination resistor 9 is connected to the high side terminal CANH via the first bus line L1. The other end of the termination resistor 9 is connected to the low side terminal CANL via the second bus line L2.

[0024] When a low-level first control signal H / L is input to the first drive transistor 12 and a high-level second control signal L / H is input to the second drive transistor 15, the first drive transistor 12 and the second drive transistor 15 turn on. As a result, a bus signal SH of 3.5V (standard value) is output to the high-side terminal CANH, and a bus signal SL of 1.5V (standard value) is output to the low-side terminal CANL (dominant state).

[0025] On the other hand, when a high-level first control signal H / L is input to the first drive transistor 12 and a low-level second control signal L / H is input to the second drive transistor 15, the first drive transistor 12 and the second drive transistor 15 turn off. As a result, a bus signal SH of 2.5V (standard value) is output to the high-side terminal CANH, and a bus signal SL of 2.5V (standard value) is output to the low-side terminal CANL (recessive state). Hereinafter, the structure of the semiconductor device 1 will be described.

[0026] FIG. 2 is a perspective view showing the semiconductor device 1 shown in FIG. 1. In FIG. 2, illustration of the input terminal IN, the power supply terminal VCC, the ground terminal GND, the high-side terminal CANH, and the low-side terminal CANL described above is omitted.

[0027] Referring to FIG. 2, the semiconductor device 1 includes, in this embodiment, a semiconductor chip 20 made of silicon. The semiconductor chip 20 is formed in a rectangular parallelepiped shape. The semiconductor chip 20 has a first main surface 21 on one side, a second main surface 22 on the other side, and first to fourth side surfaces 23A to 23D connecting the first main surface 21 and the second main surface 22.

[0028] The first main surface 21 and the second main surface 22 are formed in a square shape in a plan view (hereinafter simply referred to as "plan view") as viewed from the normal direction Z thereof. The first side surface 23A and the second side surface 23B extend in the first direction X and face each other in a second direction Y orthogonal to the first direction X. The third side surface 23C and the fourth side surface 23D extend in the second direction Y and face each other in the first direction X.

[0029] In this form, the semiconductor chip 20 has a stacked structure including a p-type (first conductivity type) semiconductor substrate 24 and an n-type (second conductivity type) semiconductor layer 25 made of a conductivity type opposite to that of the p-type, which are formed in this order from the second main surface 22 side toward the first main surface 21 side. The semiconductor substrate 24 forms part of the second main surface 22 and the first to fourth side surfaces 23A to 23D. The semiconductor layer 25 forms part of the first main surface 21 and the first to fourth side surfaces 23A to 23D.

[0030] The p-type impurity concentration of the semiconductor substrate 24 may be 1×10 13 cm -3 or more and 1×10 16 cm -3 or less. The thickness of the semiconductor substrate 24 may be 100 μm or more and 1000 μm or less. Preferably, the thickness of the semiconductor substrate 24 is 200 μm or more and 700 μm or less.

[0031] In this form, the semiconductor layer 25 is an epitaxial layer formed on the semiconductor substrate 24. The n-type impurity concentration of the semiconductor layer 25 may be 1×10 14 cm -3 or more and 1×10 16 cm -3 or less. The thickness of the semiconductor layer 25 is less than the thickness of the semiconductor substrate 24. The thickness of the semiconductor layer 25 may be 1 μm or more and 50 μm or less. Preferably, the thickness of the semiconductor layer 25 is 5 μm or more and 20 μm or less.

[0032] The semiconductor chip 20 includes a plurality of device regions 26 defined on the first main surface 21. The plurality of device regions 26 include one or more (a plurality in this form) functional device regions 27 and one or more (two in this form) diode regions 28. The number and arrangement of the functional device regions 27 and the diode regions 28 are arbitrary.

[0033] The functional device region 27 is a region where various functional devices that constitute part or all of the aforementioned control circuit 2, gate driver circuit 5, first drive transistor 12, first protection transistor 14, second drive transistor 15, second protection transistor 16, etc. are formed. The functional devices are formed using the first main surface 21 and / or the surface layer portion of the first main surface 21. The functional devices may include at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional devices may include a circuit network in which a semiconductor switching device, a semiconductor rectifying device, and a passive device are combined.

[0034] The semiconductor switching device may include at least one of a MISFET, CMIS (Complementary - MISFET), BJT (Bipolar Junction Transistor), IGBT (Insulated Gate Bipolar Junction Transistor), and JFET (Junction Field Effect Transistor). The semiconductor switching devices include the aforementioned first drive transistor 12, first protection transistor 14, second drive transistor 15, and second protection transistor 16.

[0035] The semiconductor rectifying device may include at least one of a pn junction diode, pin junction diode, Zener diode, Schottky barrier diode, and fast recovery diode. The passive device may include at least one of a resistor, a capacitor, and an inductor.

[0036] The plurality of diode regions 28 are partitioned at intervals from the plurality of functional device regions 27. The plurality of diode regions 28 are regions where the aforementioned first reverse current blocking diode 13 and second reverse current blocking diode 17 are respectively formed. The structures within the plurality of diode regions 28 are similar. Hereinafter, taking the diode region 28 on the side of the first reverse current blocking diode 13 (region III shown in FIG. 2) as an example, the specific structure of the diode region 28 will be described. The description of the diode region 28 on the side of the second reverse current blocking diode 17 applies to the description of the diode region 28 on the side of the first reverse current blocking diode 13.

[0037] FIG. 3 is an enlarged view of region III shown in FIG. 2. FIG. 4 is an enlarged view of the main part of the structure shown in FIG. 3. FIG. 5 is a view obtained by removing the structure above the semiconductor layer 25 from the structure shown in FIG. 4. FIG. 6 is an enlarged view of region VI shown in FIG. 5. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 5. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5.

[0038] Referring to FIGS. 3 to 8, the semiconductor device 1 includes a region isolation structure 30 that partitions a partial region of the semiconductor layer 25 as a diode region 28 on the first main surface 21. The region isolation structure 30 electrically isolates the diode region 28 from the plurality of functional device regions 27. The region isolation structure 30 is formed in an annular shape (a square annular shape in this form) surrounding the diode region 28 in a plan view. The planar shape of the diode region 28 is adjusted by the inner edge of the region isolation structure 30. In this form, the region isolation structure 30 partitions the diode region 28 into a square shape in a plan view.

[0039] In this form, the region isolation structure 30 is composed of p-type column regions 31 formed in a wall shape on the semiconductor layer 25 so as to be electrically connected to the semiconductor substrate 24. The column region 31 includes a column buried region 32, a column well region 33, and a column contact region 34.

[0040] The column implantation region 32 is formed across the boundary between the semiconductor substrate 24 and the semiconductor layer 25 and is electrically connected to the semiconductor substrate 24. In this form, one column implantation region 32 is formed, but the number of column implantation regions 32 is arbitrary as long as it is electrically connected to the semiconductor substrate 24. A plurality of column implantation regions 32 may be stacked from the boundary toward the first main surface 21 side. The p-type impurity concentration of the column implantation region 32 is 1×10 16 cm -3 or more and 1×10 20 cm -3 or less may be sufficient.

[0041] The column well region 33 is formed in the surface layer portion of the first main surface 21. Specifically, the column well region 33 is formed in the region between the first main surface 21 and the column implantation region 32 in the semiconductor layer 25 and is electrically connected to the column implantation region 32. The column well region 33 may have a p-type impurity concentration lower than that of the column implantation region 32. The p-type impurity concentration of the column well region 33 is 1×10 15 cm -3 or more and 1×10 17 cm -3 or less may be sufficient.

[0042] The column contact region 34 is formed in the surface layer portion of the column well region 33 at a distance from the bottom of the column well region 33 toward the first main surface 21 side. The column contact region 34 has a p-type impurity concentration exceeding that of the column well region 33. The p-type impurity concentration of the column contact region 34 is 1×10 18 cm -3 or more and 1×10 20 cm -3 or less may be sufficient.

[0043] The semiconductor device 1 includes an n-type embedded region 35 formed across the boundary between the semiconductor substrate 24 and the semiconductor layer 25 in the diode region 28. In FIGS. 3 to 5, the embedded region 35 is indicated by a dashed line. The embedded region 35 has an n-type impurity concentration exceeding the n-type impurity concentration of the semiconductor layer 25. The n-type impurity concentration of the embedded region 35 is 1×10 16 cm -3 or more and may be 1×10 20 cm -3 or less.

[0044] The embedded region 35 is formed at a distance from the first main surface 21 toward the semiconductor substrate 24 side and faces the first main surface 21 with a part of the semiconductor layer 25 interposed therebetween. The embedded region 35 is formed at a distance inward from the region isolation structure 30. In this case, a part of the n-type impurities in the embedded region 35 may diffuse to the periphery of the diode region 28. That is, the embedded region 35 may have a concentration gradient in which the n-type impurity concentration on the peripheral side of the diode region 28 is lower than the n-type impurity concentration on the inner part side of the diode region 28.

[0045] The semiconductor device 1 includes one or more (a plurality in this embodiment) p-type base regions 40 formed in the surface layer portion of the first main surface 21 in the diode region 28. The plurality of base regions 40 are each formed as a part of the anode region of the first reverse current blocking diode 13. The p-type impurity concentration of each base region 40 is 1×10 15 cm -3 or more and may be 1×10 17 cm -3 or less.

[0046] The plurality of base regions 40 are specifically formed in regions surrounded by the edges of the embedded region 35 in a plan view. The plurality of base regions 40 are formed at intervals from the embedded region 35 toward the first main surface 21 side, and face the embedded region 35 with a part of the semiconductor layer 25 interposed therebetween. In this form, the plurality of base regions 40 are each formed in a strip shape extending in the first direction X and are formed at intervals in the second direction Y. As a result, the plurality of base regions 40 are formed in a stripe shape extending in the first direction X in a plan view.

[0047] The semiconductor device 1 includes one or a plurality (a plurality in this form) of n-type source regions 41 formed in the surface layer portions of the respective base regions 40. Each source region 41 has an n-type impurity concentration exceeding the n-type impurity concentration of the semiconductor layer 25. The n-type impurity concentration of each source region 41 is 1×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0048] The plurality of source regions 41 are formed at intervals in the first direction X in the surface layer portions of the respective base regions 40. The plurality of source regions 41 are each formed at intervals inward from the edges of the respective base regions 40, and each define a channel region 42 formed by the surface layer portion of the base region 40 between the semiconductor layer 25. The plurality of source regions 41 are formed at intervals inward from both edges of each base region 40 with respect to the first direction X, and expose both edges of each base region 40 from the first main surface 21.

[0049] The planar shape of the plurality of source regions 41 is arbitrary. The plurality of source regions 41 may be formed in a square shape in a plan view, or may be formed in a circular shape (including an elliptical shape). In this form, the plurality of source regions 41 are each formed in a strip shape extending in the second direction Y.

[0050] The semiconductor device 1 includes one or more (in this embodiment, a plurality) of p-type base contact regions 43 formed in a region different from the source region 41 in the surface layer portion of each base region 40. The plurality of base contact regions 43 are each formed as a part of the anode region of the first reverse current blocking diode 13. Each base contact region 43 has a p-type impurity concentration exceeding the p-type impurity concentration of each base region 40. The p-type impurity concentration of each base contact region 43 may be 1×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0051] In this embodiment, the plurality of base contact regions 43 are formed at intervals in the first direction X in the surface layer portion of each base region 40. Specifically, the plurality of base contact regions 43 are alternately formed with the plurality of source regions 41 in a manner of sandwiching one source region 41. Thereby, a loop array including the plurality of source regions 41 and the plurality of base contact regions 43 is formed in the surface layer portion of each base region 40. In this embodiment, both the start point and the end point of the loop array are formed by the source region 41. However, either one or both of the start point and the end point of the loop array may be formed by the base contact region 43.

[0052] The planar shape of the plurality of base contact regions 43 is arbitrary. The plurality of base contact regions 43 may be formed in a square shape in plan view, or may be formed in a circular shape (including an elliptical shape). In this embodiment, the plurality of base contact regions 43 are each formed in a strip shape extending in the second direction Y.

[0053] The semiconductor device 1 includes one or more (a plurality in this embodiment) n-type well regions 50 formed in the surface layer portion of the first main surface 21 at a distance from the base region 40 in the diode region 28. The number of well regions 50 is adjusted according to the number of base regions 40. The plurality of well regions 50 are each formed as a part of the cathode region of the first reverse blocking diode 13. Each well region 50 defines a drift region 51 with each base region 40. The drift region 51 is adjacent to the channel region 42. Each well region 50 has an n-type impurity concentration exceeding the n-type impurity concentration of the semiconductor layer 25. The n-type impurity concentration of each well region 50 may be 1×10 15 cm -3 or more and 1×10 17 cm -3 or less.

[0054] The plurality of well regions 50 are formed at a distance from the embedded region 35 toward the first main surface 21 side, and face the embedded region 35 with the semiconductor layer 25 interposed therebetween. The plurality of well regions 50 are each formed in an annular shape (a square annular shape in this embodiment) surrounding one corresponding base region 40 in plan view. Thereby, each drift region 51 is defined in an annular shape in plan view. The planar shape of the well region 50 is arbitrary and may be formed in an oval annular shape.

[0055] Referring to FIG. 6, the plurality of well regions 50 each have a well width W. The well width W is the width in a direction orthogonal to the direction in which the well region 50 extends. The well width W may be 0.5 μm or more and 5 μm or less. The well width W is preferably 1 μm or more and 4 μm or less.

[0056] The plurality of well regions 50 each include a first region 52 and a second region 53 that extend in different directions from each other. The first region 52 extends along the long side of the base region 40 (i.e., the first direction X). The second region 53 extends along the short side of the base region 40 (i.e., the second direction Y). The well width W of the second region 53 may be different from the well width W of the first region 52. In this embodiment, the well width W of the second region 53 is less than the well width W of the first region 52. Of course, the well width W of the second region 53 may be equal to the well width W of the first region 52, or may exceed the well width W of the first region 52.

[0057] In this embodiment, the first regions 52 of the plurality of well regions 50 are integrally formed between a plurality of adjacent base regions 40. As a result, the plurality of well regions 50 form a single ladder well region that surrounds the plurality of base regions 40 in a ladder shape in plan view. The plurality of first regions 52 are alternately formed with the plurality of base regions 40 in the second direction Y in a manner that sandwiches one drift region 51.

[0058] The semiconductor device 1 includes one or more (a plurality in this embodiment) n-type drain regions 54 formed in the surface layer portion of the plurality of well regions 50. The plurality of drain regions 54 are each formed as part of the cathode region of the first reverse current blocking diode 13. Each drain region 54 has an n-type impurity concentration that exceeds the n-type impurity concentration of each well region 50. The n-type impurity concentration of each drain region 54 may be 1×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0059] The plurality of drain regions 54 are formed in the surface layer portion of the first region 52 of each well region 50, spaced apart from the second region 53 of each well region 50. Specifically, the plurality of drain regions 54 are formed only in the surface layer portion of the first region 52 of each well region 50 and not in the second region 53. In this form, the plurality of drain regions 54 are formed only in the region of the surface layer portion of the first region 52 that faces the base region 40 in the second direction Y. The first region 52 of the well region 50 is formed as an effective region in which a main current path is formed by the plurality of drain regions 54.

[0060] The plurality of drain regions 54 are formed at intervals in the first direction X in the surface layer portion of the first region 52 of each well region 50. The plurality of drain regions 54 face the plurality of source regions 41 in a one-to-one correspondence in the second direction Y. According to this structure, the plurality of drain regions 54 form a current path that connects the plurality of source regions 41 in the shortest distance in the drift region 51. Therefore, the resistance component in the current path can be reduced. The plurality of drain regions 54 do not necessarily have to face the plurality of source regions 41 in a one-to-one correspondence. The plurality of drain regions 54 may face the plurality of base contact regions 43 in a one-to-one correspondence in the second direction Y.

[0061] The plurality of drain regions 54 are formed at intervals inward from the edge of the first region 52 of each well region 50 with respect to the second direction Y. The planar shape of the plurality of drain regions 54 is arbitrary. The plurality of drain regions 54 may be formed in a square shape in plan view, or may be formed in a circular shape (including an elliptical shape). In this form, the plurality of drain regions 54 are each formed in a strip shape extending in the second direction Y.

[0062] Referring to FIG. 6, the plurality of drain regions 54 each have a first drain width WD1 in the first direction X and a second drain width WD2 in the second direction Y. The first drain width WD1 may be 0.1 μm or more and 3 μm or less. The first drain width WD1 is preferably 0.5 μm or more and 2.5 μm or less. The first drain width WD may be equal to the width of the source region 41 in the first direction X. The second drain width WD2 is preferably less than the well width W of the well region 50. The second drain width WD2 may be 0.1 μm or more and 4 μm or less. The second drain width WD2 is preferably 0.5 μm or more and 3.5 μm or less.

[0063] The semiconductor device 1 includes a plurality of n-type outer drain regions 55 formed in a region outside the plurality of drain regions 54 in the surface layer portion of the plurality of well regions 50. Each outer drain region 55 has an n-type impurity concentration exceeding the n-type impurity concentration of each well region 50. Each outer drain region 55 has an n-type impurity concentration equal to the n-type impurity concentration of the drain region 54.

[0064] The plurality of outer drain regions 55 are respectively formed in the surface layer portion of the second region 53 of the plurality of well regions 50. The plurality of outer drain regions 55 are further drawn from the second region 53 to the first region 52 in each well region 50 and are integrally formed with two drain regions 54 located at both ends of the plurality of drain regions 54. The plurality of outer drain regions 55 are formed at intervals inward from the edge of each well region 50. The plurality of outer drain regions 55 suppress undesired channel inversion in the well region 50.

[0065] The semiconductor device 1 includes one or more (in this form, a plurality) of p-type impurity regions 56 formed in the surface layer portion of the plurality of well regions 50. Each impurity region 56 has a p-type impurity concentration exceeding the p-type impurity concentration of each base region 40. The p-type impurity concentration of each impurity region 56 is 1×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0066] The plurality of impurity regions 56 are formed in the surface layer portion of the first region 52 of each well region 50, spaced apart from the second region 53 of each well region 50. Specifically, the plurality of impurity regions 56 are formed only in the surface layer portion of the first region 52 of each well region 50 and are not formed in the second region 53. In this form, the plurality of impurity regions 56 are formed only in the region of the surface layer portion of the first region 52 of each well region 50 that faces the base region 40 in the second direction Y.

[0067] The plurality of impurity regions 56 are formed at intervals in the first direction X in the surface layer portion of the first region 52 of each well region 50. Specifically, the plurality of impurity regions 56 are formed alternately with the plurality of drain regions 54 in a manner that sandwiches one drain region 54 in the surface layer portion of the first region 52 of each well region 50. That is, the plurality of impurity regions 56 are electrically connected to the plurality of drain regions 54 in the first direction X and are not electrically connected to the plurality of drain regions 54 in the second direction Y.

[0068] The plurality of impurity regions 56 are formed at intervals inward from the edge of the first region 52 of each well region 50. That is, the plurality of impurity regions 56 are electrically connected to the well region 50 in the second direction Y. It is preferable that the edges of the plurality of impurity regions 56 on the base region 40 side are formed inward of the well region 50 with respect to the edges of the plurality of drain regions 54 on the base region 40 side. In this form, with respect to the second direction Y, both edges of the plurality of impurity regions 56 are formed inward of the well region 50 with respect to both edges of the drain region 54.

[0069] The plurality of impurity regions 56 face the plurality of base contact regions 43 in a one-to-one correspondence in the second direction Y. The plurality of impurity regions 56 do not necessarily have to face the plurality of base contact regions 43 in a one-to-one correspondence. The plurality of impurity regions 56 may face the plurality of source regions 41 in a one-to-one correspondence in the second direction Y according to the arrangement of the plurality of drain regions 54.

[0070] The planar shape of the plurality of impurity regions 56 is arbitrary. The plurality of impurity regions 56 may be formed in a square shape or a circular shape (including an elliptical shape) in a plan view. In this form, the plurality of impurity regions 56 are each formed in a strip shape extending in the second direction Y.

[0071] Referring to FIG. 6, the plurality of impurity regions 56 each have a first width W1 in the first direction X and a second width W2 in the second direction Y. The first width W1 may be 0.1 μm or more and 3 μm or less. The first width W1 is preferably 0.5 μm or more and 2.5 μm or less. The first width W1 may be equal to the first drain width WD1 of the drain region 54. The first width W1 may be equal to the width of the base contact region 43 in the first direction X. The second width W2 is less than the second drain width WD2 of the drain region 54. The second width W2 may be 0.1 μm or more and 3.5 μm or less. The second width W2 is preferably 0.5 μm or more and 3 μm or less.

[0072] The semiconductor device 1 includes a p-type guard region 60 formed in the surface layer portion of the first main surface 21 at a distance from the plurality of well regions 50 on the side opposite to the plurality of base regions 40 in the diode region 28. Specifically, the guard region 60 is formed in the region between the region isolation structure 30 and the plurality of well regions 50 in the surface layer portion of the first main surface 21.

[0073] The guard region 60 is formed at a distance from the buried region 35 toward the first main surface 21 side, and faces the buried region 35 with a part of the semiconductor layer 25 interposed therebetween. The guard region 60 is formed in an annular shape (a square annular shape in this form) that collectively surrounds the plurality of well regions 50 in a plan view. The guard region 60 shields the leakage current path formed between the region isolation structure 30 and the plurality of base regions 40.

[0074] The guard region 60 includes a guard well region 61 and a guard contact region 62. The guard well region 61 is formed in the surface layer portion of the first main surface 21. Specifically, the guard well region 61 is formed at a depth position between the first main surface 21 and the column implantation region 32 in the semiconductor layer 25. The p-type impurity concentration of the guard well region 61 may be 1×10 15 cm -3 or more and 1×10 17 cm -3 or less.

[0075] The guard well region 61 may be formed at the same depth as the column well region 33. The guard well region 61 may have a p-type impurity concentration equal to that of the column well region 33. According to this structure, the guard well region 61 and the column well region 33 can be formed in the same process.

[0076] The guard contact region 62 is formed in the surface layer portion of the guard well region 61 with a space from the bottom of the guard well region 61 toward the first main surface 21 side. The guard contact region 62 has a p-type impurity concentration exceeding that of the guard well region 61. The p-type impurity concentration of the guard contact region 62 may be 1×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0077] The guard contact region 62 may be formed at the same depth as the column contact region 34. The guard contact region 62 may have a p-type impurity concentration equal to that of the column contact region 34. According to this structure, the guard contact region 62 and the column contact region 34 can be formed in the same process.

[0078] The semiconductor device 1 includes an n-type channel stop region 65 formed in the semiconductor layer 25 at a distance from the guard region 60 on the side opposite to the plurality of well regions 50 in the diode region 28. Hereinafter, "channel stop" will be abbreviated as "CS (channel stop)". The CS region 65 is formed in the region between the region isolation structure 30 and the guard region 60 in the surface layer portion of the first main surface 21. The CS region 65 is formed along the periphery of the diode region 28. Specifically, the CS region 65 is formed in an annular shape (a square annular shape in this form) surrounding the guard region 60 in a plan view.

[0079] The CS region 65 is formed in a wall shape in the semiconductor layer 25 so as to be electrically connected to the buried region 35. Specifically, the CS region 65 includes a CS buried region 66, a CS well region 67, and a CS surface layer region 68.

[0080] The CS buried region 66 is formed across the boundary between the buried region 35 and the semiconductor layer 25 and is electrically connected to the buried region 35. In this form, one CS buried region 66 is formed, but the number of CS buried regions 66 is arbitrary as long as it is electrically connected to the buried region 35. A plurality of CS buried regions 66 may be stacked from the buried region 35 toward the first main surface 21 side. The n-type impurity concentration of the CS buried region 66 is 1×10 16 cm -3 or more and 1×10 20 cm -3 or less may be sufficient.

[0081] The CS well region 67 is formed in the surface layer portion of the first main surface 21. Specifically, the CS well region 67 is formed in the region between the first main surface 21 and the CS buried region 66 in the semiconductor layer 25 and is electrically connected to the CS buried region 66. The CS buried region 66 may have an n-type impurity concentration lower than the n-type impurity concentration of the CS buried region 66. The n-type impurity concentration of the CS well region 67 is 1×10 16 cm -3 or more and 1×10 20 cm -3 or less may be sufficient.

[0082] The CS surface region 68 is formed in the surface portion of the CS well region 67 at a distance from the bottom of the CS well region 67 toward the first main surface 21. The CS surface region 68 has an n-type impurity concentration exceeding that of the CS well region 67. The n-type impurity concentration of the CS surface region 68 is 1×10 18 cm -3 or more and may be 1×10 20 cm -3 or less. The CS surface region 68 may have an n-type impurity concentration equal to that of the source region 41 (drain region 54).

[0083] The semiconductor device 1 includes an insulating film 70 that selectively covers the first main surface 21. In this form, the insulating film 70 is a field oxide film. The field oxide film may be referred to as a LOCOS (local oxidation of silicon) film. The insulating film 70 is formed on the first main surface 21 so as to expose the region isolation structure 30, the plurality of base regions 40, the plurality of well regions 50, the guard region 60, and the CS region 65 and cover the drift region 51. Specifically, the insulating film 70 includes a plurality of first insulating films 70A, one second insulating film 70B, one third insulating film 70C, one fourth insulating film 70D, and one fifth insulating film 70E.

[0084] The plurality of first insulating films 70A are respectively formed in the regions between the corresponding base regions 40 and well regions 50 so as to respectively cover the corresponding drift regions 51. Each first insulating film 70A is formed in an annular shape surrounding the corresponding base region 40 in plan view. The inner end portion of each first insulating film 70A covers the edge of the base region 40, exposing the channel region 42, the source region 41, and the base contact region 43.

[0085] The outer end portions of each first insulating film 70A cover the inner edge portions of the well region 50, exposing the inner portions of the well region 50, the drain region 54, the outer drain region 55, and the impurity regions 56. Specifically, the outer end portions of each first insulating film 70A cover the edges of the plurality of drain regions 54 (outer drain regions 55) and expose the edges of the plurality of impurity regions 56. Thereby, the outer end portions of each first insulating film 70A expose the well region 50 from the regions between the edges of the plurality of impurity regions 56.

[0086] The second insulating film 70B is formed in the region between the well region 50 and the guard region 60. The second insulating film 70B is formed in an annular shape surrounding the well region 50 in a plan view. The inner end portion of the second insulating film 70B covers the outer edge portion of the well region 50 and exposes the outer drain region 55. Specifically, the inner end portion of the second insulating film 70B covers the edges of the plurality of outer drain regions 55 and exposes the inner portions of the plurality of outer drain regions 55.

[0087] The inner end portion of the second insulating film 70B further covers the outer edge portion of the outermost formed well region 50, exposing the inner portion of the well region 50, the drain region 54, the outer drain region 55, and the impurity regions 56. Specifically, the inner end portion of the second insulating film 70B covers the edges of the plurality of drain regions 54 (outer drain regions 55) and exposes the edges of the plurality of impurity regions 56. Thereby, the inner end portion of the second insulating film 70B exposes the well region 50 from the regions between the edges of the plurality of impurity regions 56. The outer end portion of the second insulating film 70B covers the edge of the guard region 60 and exposes the inner portion of the guard region 60.

[0088] The third insulating film 70C is formed in the region between the guard region 60 and the CS region 65. The third insulating film 70C is formed in an annular shape surrounding the guard region 60 in a plan view. The inner end portion of the third insulating film 70C covers the outer edge portion of the guard region 60 and exposes the inner portion of the guard region 60. The outer end portion of the third insulating film 70C covers the inner edge portion of the CS region 65 and exposes the inner portion of the CS region 65.

[0089] The fourth insulating film 70D is formed in a region between the CS region 65 and the region isolation structure 30 (column region 31). The fourth insulating film 70D is formed in an annular shape surrounding the CS region 65 in plan view. The inner end portion of the fourth insulating film 70D covers the outer edge portion of the CS region 65 and exposes the inner portion of the CS region 65. The outer end portion of the fourth insulating film 70D covers the inner edge portion of the region isolation structure 30 (column region 31) and exposes the inner portion of the region isolation structure 30 (column region 31).

[0090] The fifth insulating film 70E is formed in a region outside the region isolation structure 30 (column region 31). The fifth insulating film 70E covers the outer edge portion of the region isolation structure 30 (column region 31) and exposes the inner portion of the region isolation structure 30 (column region 31).

[0091] The semiconductor device 1 includes a plurality of gate structures 71 formed on the first main surface 21 in the diode region 28. The plurality of gate structures 71 are respectively formed on a plurality of channel regions 42 exposed from the insulating film 70. That is, the plurality of gate structures 71 are respectively formed in a region surrounded by the inner end portions of the plurality of first insulating films 70A. The plurality of gate structures 71 each have a stacked structure including a gate insulating film 72 and a gate electrode 73 stacked in this order from the first main surface 21 side.

[0092] The gate insulating film 72 has a thickness less than the thickness of the insulating film 70. The gate insulating film 72 may contain silicon oxide. The gate insulating film 72 covers the channel region 42, the edges of the source region 41, and the edges of the base contact region 43. Specifically, the gate insulating film 72 is formed in an annular shape including inner and outer end portions in plan view.

[0093] The inner end portion of the gate insulating film 72 demarcates the contact opening 74. The contact opening 74 exposes the inner portions of the base region 40, the inner portions of the plurality of source regions 41, and the inner portions of the plurality of base contact regions 43. In this form, the contact opening 74 is formed in a strip shape extending in the first direction X. The outer end portion of the gate insulating film 72 is connected to the insulating film 70 (the inner end portion of the first insulating film 70A).

[0094] The gate electrode 73 includes conductive polysilicon in this form. The gate electrode 73 is formed on the gate insulating film 72 and faces the channel region 42 with the gate insulating film 72 interposed therebetween. The gate electrode 73 has a lead-out portion 75 drawn from above the gate insulating film 72 onto the insulating film 70 (the first insulating film 70A). The lead-out portion 75 of the gate electrode 73 faces the drift region 51 with the insulating film 70 (the first insulating film 70A) interposed therebetween.

[0095] Specifically, the gate electrode 73 includes an inner end portion and an outer end portion in plan view and is formed in an annular shape surrounding the base region 40. The inner end portion of the gate electrode 73, together with the inner end portion of the gate insulating film 72, demarcates the contact opening 74.

[0096] The outer end portion of the gate electrode 73 is formed by the lead-out portion 75 and is formed on the insulating film 70 with a space inward from the inner end portion of the well region 50 in plan view. In this form, the outer end portion of the gate electrode 73 is located in the region between the base region 40 and the well region 50 in plan view. The outer end portion of the gate electrode 73 is formed in a rectangular shape (specifically, a rectangular shape extending in the first direction X) in plan view. The planar shape of the outer end portion of the gate electrode 73 is arbitrary and may be formed in an oval shape.

[0097] The plurality of source regions 41 and the plurality of base contact regions 43 may be respectively formed self-aligned with respect to the gate electrode 73. That is, the plurality of source regions 41 and the plurality of base contact regions 43 may be respectively formed by introducing n-type impurities and p-type impurities through an ion implantation mask that exposes at least the inner end portion of the gate electrode 73. In this case, loop arrays of n-type regions and p-type regions corresponding to the loop arrays of the plurality of source regions 41 and the plurality of base contact regions 43 are formed at least at the inner end portion of the gate electrode 73.

[0098] The semiconductor device 1 includes an interlayer insulating film 80 formed on the first main surface 21. The interlayer insulating film 80 is formed on the insulating film 70 and covers the diode region 28 in a lump. The interlayer insulating film 80 covers portions exposed from the insulating film 70 in the region isolation structure 30 (column region 31), the plurality of base regions 40, the plurality of source regions 41, the plurality of base contact regions 43, the plurality of well regions 50, the plurality of drain regions 54, the plurality of outer drain regions 55, the plurality of impurity regions 56, the guard region 60, and the CS region 65.

[0099] The semiconductor device 1 includes one or a plurality (one in this embodiment) of region isolation connection electrodes 81, a plurality of source connection electrodes 82, a plurality of drain connection electrodes 83, one or a plurality (one in this embodiment) of guard connection electrodes 84, and a plurality of gate connection electrodes 86.

[0100] The region isolation connection electrode 81 penetrates the interlayer insulating film 80 and is electrically connected to the region isolation structure 30 (column contact region 34). The region isolation connection electrode 81 is fixed to a substrate potential (for example, ground potential). The region isolation connection electrode 81 may be formed in a strip shape (specifically, an annular shape) extending along the region isolation structure 30 in a plan view. A plurality of region isolation connection electrodes 81 may be formed at intervals along the region isolation structure 30 in a plan view.

[0101] The plurality of source connection electrodes 82 penetrate the interlayer insulating film 80 and are electrically connected to the corresponding base regions 40, the corresponding plurality of source regions 41, and the corresponding plurality of base contact regions 43, respectively. The plurality of source connection electrodes 82 are fixed at the gate potential. That is, the plurality of source connection electrodes 82 are fixed at the same potential as the gate electrode 73.

[0102] The plurality of source connection electrodes 82 are respectively formed in a strip shape across the plurality of source regions 41 and the plurality of base contact regions 43 in the first direction X within the corresponding contact openings 74. Both ends of the plurality of source connection electrodes 82 are electrically connected to both edge portions of the corresponding base region 40, respectively. Thereby, the base region 40, the source region 41, and the base contact region 43 are fixed at the same potential (gate potential).

[0103] The plurality of drain connection electrodes 83 penetrate the interlayer insulating film 80 and are electrically connected to the corresponding plurality of drain regions 54 and the corresponding plurality of impurity regions 56, respectively. The plurality of drain connection electrodes 83 are fixed at the drain potential. The plurality of drain connection electrodes 83 are respectively formed in a strip shape across the plurality of drain regions 54 and the plurality of impurity regions 56 in the first direction X.

[0104] Both ends of the plurality of drain connection electrodes 83 are connected to the drain regions 54 at both ends, respectively. That is, the plurality of drain connection electrodes 83 are electrically connected to the plurality of outer drain regions 55 through the drain regions 54 at both ends. Thereby, the well region 50, the drain region 54, the outer drain region 55, and the impurity region 56 are fixed at the same potential (drain potential).

[0105] The guard connection electrode 84 penetrates the interlayer insulating film 80 and is electrically connected to the guard region 60. The guard connection electrode 84 is fixed at the same potential (drain potential) as the plurality of drain connection electrodes 83. That is, the guard region 60 is fixed at the same potential as the drain region 54 and the like. The guard connection electrode 84 may be formed in a strip shape (specifically, an annular shape) extending along the guard region 60 in a plan view. A plurality of guard connection electrodes 84 may be formed at intervals along the guard region 60 in a plan view.

[0106] The plurality of gate connection electrodes 86 penetrate the interlayer insulating film 80 and are electrically connected to the corresponding gate electrodes 73, respectively. Specifically, the plurality of gate connection electrodes 86 are electrically connected to arbitrary positions of the lead-out portions 75 of the corresponding gate electrodes 73, respectively. In this form, the plurality of gate connection electrodes 86 are electrically connected to both ends of the plurality of gate electrodes 73 with respect to the first direction X. In FIGS. 7 and 8, the gate connection electrodes 86 are illustrated for convenience to show the connection form. The plurality of gate connection electrodes 86 are fixed at the gate potential. That is, the gate electrode 73 is fixed at the same potential as the base region 40, the source region 41, the base contact region 43, and the like.

[0107] Referring to FIG. 7, the first reverse current blocking diode 13 includes an EIS (Electrode-Insulator-Semiconductor) type diode structure 90. Specifically, the diode structure 90 includes a p-type base region 40, an n-type source region 41, a p-type base contact region 43, an n-type well region 50, an n-type drain region 54, and a gate structure 71.

[0108] Referring to FIG. 8, the first reverse current blocking diode 13 includes a thyristor structure 91 electrically connected to the diode structure 90. Specifically, the thyristor structure 91 includes a p-type impurity region 56, an n-type semiconductor layer 25, a p-type base region 40, and an n-type source region 41 formed in this order along the first main surface 21 of the semiconductor layer 25.

[0109] The thyristor structure 91 more specifically includes a first transistor structure 92 of pnp type (first polarity type) on the well region 50 side and a second transistor structure 93 of npn type (second polarity type) on the base region 40 side. The first transistor structure 92 includes a p-type impurity region 56, an n-type semiconductor layer 25, and a p-type base region 40 formed in this order along the first main surface 21 of the semiconductor layer 25. The second transistor structure 93 includes an n-type source region 41, a p-type base region 40, and an n-type semiconductor layer 25 formed in this order along the first main surface 21 of the semiconductor layer 25.

[0110] When the forward voltage VF of the diode structure 90 is applied to the source connection electrode 82 (gate electrode 73) and the drain connection electrode 83, the diode structure 90 is turned on while the thyristor structure 91 is turned off. The thyristor structure 91 is turned off because the drain region 54 and the impurity region 56 are fixed at the same potential. As a result, the diode structure 90 conducts, and the forward current IF flows through the diode structure 90. This forward voltage VF further flows through the first transistor structure 92 electrically connected to the diode structure 90.

[0111] On the other hand, when the reverse voltage VR of the diode structure 90 is applied to the source connection electrode 82 (gate electrode 73) and the drain connection electrode 83, the diode structure 90 is turned off while the thyristor structure 91 is turned on. As a result, the thyristor structure 91 conducts, and the reverse current IR flows through the thyristor structure 91.

[0112] FIG. 9 is a graph showing the current-voltage characteristics of the reverse current blocking diode according to the comparative example. FIG. 10 is a graph showing the current-voltage characteristics of the first reverse current blocking diode 13 according to the present embodiment. The current-voltage characteristics shown in FIGS. 9 and 10 were examined by a known TLP (Transmission Line Pulse) measurement method.

[0113] In FIGS. 9 and 10, the vertical axis represents current [A], and the horizontal axis represents voltage [V]. A positive current means the forward current IF, and a negative current means the reverse current IR. A positive voltage means the forward voltage VF, and a negative voltage means the reverse voltage VR. The reverse current blocking diode according to the comparative example does not include the impurity region 56. That is, the reverse current blocking diode according to the comparative example includes only the diode structure 90 and does not include the thyristor structure 91.

[0114] In the reverse current blocking diode according to the comparative example, the forward current IF leading to electrostatic breakdown was about +5 A, while the reverse current IR leading to electrostatic breakdown was about -0.5 A. On the other hand, in the first reverse current blocking diode 13 according to the present embodiment, the forward current IF leading to electrostatic breakdown was about +25 A, while the reverse current IR leading to electrostatic breakdown was about -24 A. In the first reverse current blocking diode 13 according to the present embodiment, the electrostatic surge tolerance was improved in both the forward and reverse directions as compared with the reverse current blocking diode according to the comparative example.

[0115] In the first reverse current blocking diode 13 according to the present embodiment, different from the reverse current blocking diode according to the comparative example, when a forward overvoltage caused by static electricity or the like is applied, the forward overcurrent can be processed by the diode structure 90 and the first transistor structure 92.

[0116] Also, in the first reverse current blocking diode 13 according to the present embodiment, when a reverse overvoltage caused by static electricity or the like is applied, the reverse overcurrent can be processed by the thyristor structure 91. As a result, in the first reverse current blocking diode 13 according to the present embodiment, the electrostatic surge tolerance was improved as compared with the reverse current blocking diode according to the comparative example.

[0117] Therefore, according to the semiconductor device 1, the electrostatic surge tolerance can be improved. In particular, in the structure incorporating the thyristor structure 91, the improvement in the electrostatic surge tolerance on the forward voltage VF (forward current IF) side due to the action of the first transistor structure 92 is a heterogeneous effect that cannot be achieved by a general thyristor device used as a protection device against the reverse voltage VR.

[0118] Also, according to the semiconductor device 1, the impurity region 56 is formed in the surface layer portion of the well region 50 at an interval inward from the edge of the well region 50. According to this structure, in the lateral direction parallel to the first main surface 21, a part of the well region 50 is interposed in the region between the impurity region 56 and the semiconductor layer 25, and the base resistance of the first transistor structure 92 is formed by a part of the well region 50. Thereby, the thyristor structure 91 can be operated appropriately.

[0119] For example, when the drain region 54 is formed in the region between the impurity region 56 and the semiconductor layer 25 in the surface layer portion of the well region 50, the base of the first transistor structure 92 is short-circuited to the emitter of the first transistor structure 92 by the relatively low-resistance drain region 54. Therefore, the operation of the thyristor structure 91 becomes unstable.

[0120] Therefore, in the semiconductor device 1, the edge of the impurity region 56 on the base region 40 side is formed inward of the well region 50 with respect to the edge of the drain region 54 on the base region 40 side. According to this structure, it is possible to appropriately suppress the short-circuiting of the base and emitter of the first transistor structure 92 by the drain region 54. Therefore, the thyristor structure 91 can be operated more appropriately. Also, according to this structure, when an overvoltage is applied between the drain region 54 and the source region 41, punch-through between the drain region 54 and the source region 41 can be suppressed. Therefore, a decrease in the punch-through breakdown voltage can be suppressed.

[0121] Also, according to the semiconductor device 1, the impurity region 56 faces the drain region 54 in a direction orthogonal to the facing direction of the base region 40 and the well region 50. According to this structure, a thyristor structure 91 can be formed on the line connecting the base region 40 and the impurity region 56. Thereby, it is possible to appropriately suppress the operation of the thyristor structure 91 from being inhibited by the drain region 54.

[0122] Further, the semiconductor device 1 includes a p-type guard region 60 formed in the regions of the column region 31 and the well region 50 in the surface layer portion of the first main surface 21. The guard region 60 is fixed to the same potential as the drain region 54 or the like. Specifically, the semiconductor device 1 includes a drain connection electrode 83 connected to the drain region 54 or the like on the first main surface 21, and a guard connection electrode 84 electrically connected to the guard region 60 on the first main surface 21 and fixed to the same potential as the drain connection electrode 83.

[0123] In the diode region 28, in the region between the column region 31 and the base region 40, a pnp-type (first polarity type) first parasitic transistor including a p-type base region 40, an n-type semiconductor layer 25, and a p-type column region 31 is formed. When the forward voltage VF of the diode structure 90 is applied to the source connection electrode 82 (gate electrode 73) and the drain connection electrode 83, a leakage current flows through the first parasitic transistor to the column region 31.

[0124] Therefore, in the semiconductor device 1, a guard region 60 is formed in the region between the column region 31 and the well region 50. According to this structure, in the diode region 28, in the region between the column region 31 and the base region 40, a pnp-type (first polarity type) second parasitic transistor including a p-type base region 40, an n-type semiconductor layer 25, and a p-type guard region 60 is formed.

[0125] Thus, when the forward voltage VF of the diode structure 90 is applied, a leakage current can flow into the guard connection electrode 84 through the second parasitic transistor. As a result, the leakage current can be reduced without being inhibited by the thyristor structure 91. Reducing the leakage current is effective in improving the electrical characteristics of the diode region 28, and is also effective in suppressing fluctuations in the electrical characteristics of the other functional device region 27 caused by the leakage current.

[0126] Embodiments of the present invention can be implemented in still other forms.

[0127] In the foregoing embodiment, an example in which the insulating film 70 is a field oxide film has been described. However, the insulating film 70 may be buried in the trench. In this case, a STI (shallow trench isolation) structure may be formed by the trench and the insulating film 70.

[0128] In the foregoing embodiment, an example in which the “first conductivity type” is “p-type” and the “second conductivity type” is “n-type” has been described. However, the “first conductivity type” may be “n-type” and the “second conductivity type” may be “p-type”. The specific configuration in this case can be obtained by replacing the “n-type region” with the “p-type region” and the “p-type region” with the “n-type region” in the foregoing description and the accompanying drawings. In the foregoing embodiment, an example in which “p-type” is expressed as the “first conductivity type” and “n-type” is expressed as the “second conductivity type” has been described for the sake of clarity in the order of explanation. However, “p-type” may be expressed as the “second conductivity type” and “n-type” may be expressed as the “first conductivity type”.

[0129] In the foregoing embodiments, an example in which the first reverse-blocking diode 13 (the second reverse-blocking diode 17) is incorporated into the circuit section of the CAN has been described. However, the first reverse-blocking diode 13 (the second reverse-blocking diode 17) can also be incorporated into the circuit sections of various applications other than CAN. For example, the first reverse-blocking diode 13 (the second reverse-blocking diode 17) can be incorporated into the circuit sections of in-vehicle networks such as LIN (Local Interconnect Network) and FlexRay, the circuit section of an in-vehicle switch IC, the circuit section of a DC / DC converter, and the like. The first reverse-blocking diode 13 (the second reverse-blocking diode 17) may be incorporated into the circuit section of an application other than in-vehicle use.

[0130] Examples of features extracted from this specification and the drawings are shown below. The EIS-type diode structure has a structural feature of low electrostatic surge tolerance. The electrostatic surge tolerance is also referred to as the ESD (electro static discharge) tolerance. The following [A1] to [A17] provide a semiconductor device including an EIS-type diode structure and capable of improving the electrostatic surge tolerance.

[0131] [A1]A semiconductor device including: a semiconductor layer of a first conductivity type having a main surface and including a device region; a base region of a second conductivity type formed in a surface layer portion of the main surface in the device region; a source region of the first conductivity type formed in a surface layer portion of the base region at an inner side spaced apart from an edge of the base region and defining a channel region with the semiconductor layer; a base contact region of the second conductivity type formed in a region different from the source region in the surface layer portion of the base region and having an impurity concentration exceeding an impurity concentration of the base region; a well region of the first conductivity type formed in the surface layer portion of the main surface spaced apart from the base region in the device region and defining a drift region with the base region; a drain region of the first conductivity type formed in a surface layer portion of the well region; an impurity region of the second conductivity type formed in the surface layer portion of the well region and electrically connected to the drain region; a gate insulating film covering the channel region on the main surface; and a gate structure having a gate electrode facing the channel region on the gate insulating film and electrically connected to the source region and the base contact region.

[0132] This semiconductor device includes an EIS-type diode structure in the device region. Specifically, the diode structure includes a base region, a source region, a base contact region, a well region, a drain region, and a gate structure. Further, this semiconductor device includes a thyristor structure electrically connected to the diode structure in the device region. Specifically, the thyristor structure includes an impurity region (second conductivity type), a semiconductor layer (first conductivity type), a base region (second conductivity type), and a source region (first conductivity type) formed in this order along the main surface of the semiconductor layer.

[0133] The thyristor structure more specifically includes a first transistor structure of a first polarity type on the well region side and a second transistor structure of a second polarity type on the base region side. The first transistor structure includes an impurity region (second conductivity type), a semiconductor layer (first conductivity type), and a base region (second conductivity type) formed in this order along the main surface of the semiconductor layer. The second transistor structure includes a source region (first conductivity type), a base region (second conductivity type), and a semiconductor layer (first conductivity type) formed in this order along the main surface of the semiconductor layer.

[0134] When a forward voltage is applied to the diode structure, the diode structure turns on while the thyristor structure turns off. The thyristor structure turns off because the drain region and the impurity region are fixed at the same potential. As a result, the diode structure conducts and a forward current flows through the diode structure. This forward voltage also flows through the first transistor structure electrically connected to the diode structure. Therefore, when a forward overvoltage caused by static electricity or the like is applied to the diode structure, the diode structure and the first transistor structure can handle the forward overcurrent.

[0135] On the other hand, when a reverse voltage is applied to the diode structure, the diode structure turns off while the thyristor structure turns on. As a result, the thyristor structure conducts and a reverse current flows through the thyristor structure. Therefore, when a reverse overvoltage caused by static electricity or the like is applied to the diode structure, the thyristor structure can handle the reverse overcurrent. Thus, according to this semiconductor device, the electrostatic surge tolerance can be improved.

[0136] [A2] The semiconductor device according to A1, wherein the impurity region is formed at an interval inward from the edge of the well region.

[0137] [A3] The semiconductor device according to A1 or A2, wherein the impurity region is connected to the drain region in a direction orthogonal to the direction facing the base region and the well region.

[0138] [A4] The semiconductor device according to any one of A1 to A3, wherein a plurality of the impurity regions are formed so as to sandwich one drain region.

[0139] [A5] The semiconductor device according to any one of A1 to A4, wherein a plurality of the drain regions are formed at intervals.

[0140] [A6] The semiconductor device according to any one of A1 to A5, wherein the base region is formed in a strip shape extending along one direction in plan view, and the impurity region is formed in a region facing the long side of the base region in the well region.

[0141] [A7] The semiconductor device according to any one of A1 to A6, wherein the well region is formed in an annular shape surrounding the base region in plan view, and the gate electrode is formed in an annular shape surrounding the base region in a region between the base region and the well region in plan view.

[0142] [A8] The semiconductor device according to any one of A1 to A7, further including an isolation structure formed on the main surface for electrically separating the device region from other regions.

[0143] [A9] The semiconductor device according to A8, wherein the isolation structure includes a column region of a second conductivity type formed in the semiconductor layer.

[0144] [A10] The semiconductor device according to A9, further including a guard region of a second conductivity type formed in a region between the well region and the column region in the surface layer portion of the main surface and electrically connected to the drain region.

[0145] [A11] The base contact region is formed in the surface layer portion of the base region at an interval inward from the edge of the base region and is electrically connected to the source region. The semiconductor device according to any one of A1 to A10.

[0146] [A12] Further includes an insulating film covering the drift region on the main surface. The gate insulating film has a thickness less than the thickness of the insulating film and is continuous with the insulating film. The semiconductor device according to any one of A1 to A11.

[0147] [A13] The gate electrode is drawn out from above the gate insulating film onto the insulating film and includes a drawn-out portion facing the drift region with the insulating film interposed therebetween. The semiconductor device according to A12.

[0148] [A14] Further includes a semiconductor substrate of a second conductivity type. The semiconductor layer is laminated on the semiconductor substrate. The semiconductor device according to any one of A1 to A13.

[0149] [A15] Further includes an embedded region of a first conductivity type formed across the boundary between the semiconductor substrate and the semiconductor layer in the device region. The base region and the well region face the embedded region with a part of the semiconductor layer interposed therebetween. The semiconductor device according to A14.

[0150] [A16] Further includes a channel stop region of a first conductivity type formed in the semiconductor layer along the periphery of the device region in the device region. The semiconductor device according to A15.

[0151] [A17] The channel stop region extends in a wall shape toward the embedded region and is electrically connected to the embedded region. The semiconductor device according to A16.

[0152] This application corresponds to Japanese Patent Application No. 2019-217069 filed with the Japan Patent Office on November 29, 2019, and the entire disclosure of this application is incorporated herein by reference. Although embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples. The scope of the present invention is limited by the appended claims.

Explanation of Reference Numerals

[0153] 1 Semiconductor device 3 First main surface 6 Semiconductor substrate 7 Semiconductor layer 28 Diode region (device region) 31 Column region 35 Embedded region 40 Base region 41 Source region 42 Channel region 43 Base contact region 50 Well region 51 Drift region 54 Drain region 56 Impurity region 60 Guard region 65 Channel stop region 70 Insulating film 71 Gate structure 72 Gate insulating film 73 Gate electrode 73 Lead-out portion

Claims

1. A semiconductor layer of a first conductivity type having a main surface and including a device region; A base region of a second conductivity type formed in a surface layer portion of the main surface in the device region; A source region of a first conductivity type formed in a surface layer portion of the base region at an inner side with a space from an edge of the base region and defining a channel region between the semiconductor layer; A base contact region of a second conductivity type formed in a region different from the source region in the surface layer portion of the base region and having an impurity concentration exceeding the impurity concentration of the base region; A well region of a first conductivity type formed in a surface layer portion of the main surface at a space from the base region in the device region and defining a drift region between the well region and the base region; A drain region of a first conductivity type formed in a surface layer portion of the well region; An impurity region of a second conductivity type formed in a surface layer portion of the well region and electrically connected to the drain region; A gate insulating film covering the channel region on the main surface, and a gate structure having a gate electrode facing the channel region on the gate insulating film and electrically connected to the source region and the base contact region; The well region is formed in an annular shape surrounding the base region in a plan view; The gate electrode is formed in an annular shape surrounding the base region in a region between the base region and the well region in a plan view. A semiconductor device.

2. The semiconductor device according to claim 1, wherein the impurity region is formed at an inner side with a space from an edge of the well region.

3. The semiconductor device according to claim 1 or 2, wherein the impurity region is connected to the drain region in a direction orthogonal to a direction in which the base region and the well region face each other.

4. The semiconductor device according to any one of claims 1 to 3, wherein a plurality of the impurity regions are formed so as to sandwich one drain region.

5. The semiconductor device according to any one of claims 1 to 4, wherein a plurality of the drain regions are formed with a space therebetween.

6. The base region is formed in a strip shape extending along one direction in a plan view; The semiconductor device according to any one of claims 1 to 5, wherein the impurity region is formed in a region of the well region facing a long side of the base region.

7. The semiconductor device according to any one of claims 1 to 6, further including a region isolation structure formed on the main surface for electrically isolating the device region from other regions.

8. The semiconductor device according to claim 7, wherein the region isolation structure includes a column region of a second conductivity type formed in the semiconductor layer.

9. The semiconductor device according to claim 8, further including a guard region of a second conductivity type formed in a region between the well region and the column region in a surface layer portion of the main surface and electrically connected to the drain region.

10. The semiconductor device according to any one of claims 1 to 9, wherein the base contact region is formed in a surface layer portion of the base region at an inner side with a space from an edge of the base region and is electrically connected to the source region.

11. Further including an insulating film covering the drift region on the main surface, The semiconductor device according to any one of claims 1 to 10, wherein the gate insulating film has a thickness less than that of the insulating film and is continuous with the insulating film.

12. The semiconductor device according to claim 11, wherein the gate electrode is drawn out from above the gate insulating film onto the insulating film and includes a drawn-out portion facing the drift region with the insulating film interposed therebetween.

13. Further including a semiconductor substrate of a second conductivity type, The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor layer is laminated on the semiconductor substrate.

14. The semiconductor device according to claim 13, further including an embedded region of a first conductivity type formed across a boundary between the semiconductor substrate and the semiconductor layer in the device region. The semiconductor device according to claim 13, wherein the base region and the well region face the embedded region with a part of the semiconductor layer interposed therebetween.

15. The semiconductor device according to claim 14, further including a channel stop region of a first conductivity type formed in the semiconductor layer along a periphery of the device region in the device region.

16. The semiconductor device according to claim 15, wherein the channel stop region extends in a wall shape toward the embedded region and is electrically connected to the embedded region.

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