Solid-state imaging device, and imaging apparatus

Abstract

The present invention improves the sensitivity of pixels in a solid-state imaging element that performs time delay integration. The solid-state imaging element includes a plurality of photoelectric conversion elements, and a prescribed number of transistors. In this solid-state imaging element, the plurality of photoelectric conversion elements are arrayed along a prescribed direction at prescribed intervals. The size, in the prescribed direction, of each of the plurality of photoelectric conversion elements arrayed at the prescribed intervals does not exceed the prescribed interval. Additionally, in the solid-state imaging element, the prescribed number of transistors are each disposed between the plurality of photoelectric conversion elements, and the transistors generate signals corresponding to an electric charge amount generated by any of the plurality of photoelectric conversion elements.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging device. More specifically, it relates to a solid-state imaging device and an imaging apparatus that integrate digital signals.

Background Art

[0002] Conventionally, in the fields of FA (Factory Automation) and aerial photography, time delay integration (TDI) sensors have been used. This TDI sensor is a sensor that performs TDI processing for integrating the amount of charge while shifting the time in accordance with the moving speed of the subject. For example, a solid-state imaging device has been proposed in which adjacent two lines share a floating diffusion layer for one line, and the charges of the two lines are transferred to the floating diffusion layer with a time shift (see, for example, Patent Document 1). TDI processing is realized by this charge transfer. A plurality of transistors such as a photoelectric conversion element and a transfer transistor are arranged for each pixel in the line.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the above-described conventional technology, improvement in brightness and noise reduction are achieved by TDI processing. However, in the above-described solid-state imaging device, in order to improve the sensitivity of the pixel, by reducing the area of the floating diffusion layer and the number of transistors, even if the light-receiving area of the photoelectric conversion element is widened, the performance of the solid-state imaging device may deteriorate.

[0005] The present technology has been created in view of such a situation, and an object thereof is to improve the sensitivity of pixels in a solid-state imaging device that performs time delay integration.

Means for Solving the Problem

[0006] This technology has been made to solve the above problems. Its first aspect is a solid-state imaging device comprising a plurality of photoelectric conversion elements arranged at predetermined intervals along a predetermined direction, with the size of each of the above-mentioned predetermined directions not exceeding the above-mentioned predetermined interval, and a predetermined number of transistors arranged between the above-mentioned plurality of photoelectric conversion elements and generating a signal corresponding to the amount of charge generated by any one of the above-mentioned plurality of photoelectric conversion elements. This brings about the effect that the light-receiving area of the photoelectric conversion element becomes wider compared to the case where there is no interval.

[0007] Also, in this first aspect, any one of the above-mentioned plurality of photoelectric conversion elements may be arranged in a pixel circuit that generates a pixel signal, and the above-mentioned predetermined number of transistors may be arranged in the above-mentioned pixel circuit and an amplification circuit that amplifies the above-mentioned pixel signal. This brings about the effect that the pixel signal is amplified.

[0008] Also, in this first aspect, the above-mentioned predetermined number of transistors includes a pair of differential transistors that differentially amplify a predetermined reference signal and the above-mentioned pixel signal, the above-mentioned amplification circuit includes a pair of transistors and a capacitor connected in series to a power supply, one gate of the above-mentioned pair of transistors is connected to a floating diffusion layer, and the above-mentioned capacitor may be inserted between the connection point of the above-mentioned pair of transistors and one gate of the above-mentioned pair of differential transistors. This brings about the effect that the coupling between the gate-source capacitance and the floating diffusion layer is relaxed.

[0009] Also, in this first aspect, it further includes a floating diffusion layer disposed between the plurality of photoelectric conversion elements and a transfer transistor that transfers charges from any one of the plurality of photoelectric conversion elements to the floating diffusion layer. The predetermined number of transistors includes a discharge transistor that discharges charges from the floating diffusion layer. Any one of the plurality of photoelectric conversion elements, the floating diffusion layer, the transfer transistor, and the discharge transistor may be disposed within the pixel circuit. This brings about the effect of generating a pixel signal.

[0010] Also, in this first aspect, the predetermined number of transistors includes a gain control transistor that controls the analog gain with respect to the voltage of the floating diffusion layer, and the gain control transistor may be disposed within the pixel circuit. This brings about the effect of controlling the analog gain.

[0011] Also, in this first aspect, the predetermined number of transistors includes a reset transistor that initializes the floating diffusion layer, and the reset transistor may be disposed within the pixel circuit. This brings about the effect of initializing the floating diffusion layer.

[0012] Also, in this first aspect, it can further include an analog-to-digital conversion unit that converts a pixel signal corresponding to the light reception amount of each of the plurality of photoelectric conversion elements into a digital signal. This brings about the effect of generating a digital signal.

[0013] Also, in this first aspect, it can further include a time delay integration circuit that performs time delay integration processing on the digital signal. This brings about the effect of improving brightness and reducing noise through time delay integration processing.

[0014] Also, in this first aspect, the plurality of photoelectric conversion elements and the predetermined number of transistors are arranged on a predetermined light-receiving chip, and the analog-digital conversion unit may be arranged on a predetermined circuit chip. This brings about the effect that miniaturization of pixels is facilitated by the stacked structure.

[0015] Further, a second aspect of the present technology is an imaging device including: a plurality of photoelectric conversion elements arranged at predetermined intervals along a predetermined direction, each size in the predetermined direction not exceeding the predetermined interval; a predetermined number of transistors arranged between the plurality of photoelectric conversion elements and generating a signal according to the amount of charge generated by any one of the plurality of photoelectric conversion elements; and a signal processing circuit that processes a digital signal according to the amount of light received by each of the plurality of photoelectric conversion elements. This brings about the effect that digital signals of pixels with improved sensitivity are processed.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0017] Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First Embodiment (Example of Arranging a Plurality of Photoelectric Conversion Elements at Intervals) 2. Second Embodiment (Example of Arranging a Plurality of Photoelectric Conversion Elements at Intervals and Reducing Reset Transistors) 3. Third Embodiment (Example in Which Multiple Pixels Share a Floating Diffusion Layer)

[0018] <1. First Embodiment> [Configuration Example of Imaging Device] FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present technology. This imaging device 100 is a device that captures image data, and includes an optical unit 110, a solid-state imaging device 200, a storage unit 120, a control unit 130, and a communication unit 140.

[0019] The optical unit 110 condenses incident light and guides it to the solid-state imaging device 200. The solid-state imaging device 200 captures image data. This solid-state imaging device 200 supplies the image data to the storage unit 120 via a signal line 209.

[0020] The storage unit 120 stores image data. The control unit 130 controls the solid-state imaging device 200 to capture image data. This control unit 130 supplies, for example, a vertical synchronization signal VSYNC indicating imaging timing to the solid-state imaging device 200 via a signal line 208.

[0021] The communication unit 140 reads out image data from the storage unit 120 and transmits it to the outside.

[0022] FIG. 2 is a diagram for explaining a usage example of the imaging device 100 according to the first embodiment of the present technology. As illustrated in the figure, the imaging device 100 is used in a factory or the like where a belt conveyor 510 is provided.

[0023] The belt conveyor 510 moves a subject 511 in a predetermined direction at a constant speed. The imaging device 100 is fixed near the belt conveyor 510, captures this subject 511, and generates image data. The image data is used, for example, for inspections such as the presence or absence of defects. Thereby, FA is realized.

[0024] Note that the imaging device 100 is imaging a subject 511 moving at a constant speed, but is not limited to this configuration. A configuration in which the imaging device 100 moves and images a subject at a constant speed, such as aerial photography, may also be used.

[0025] [Configuration Example of Solid-State Imaging Device] FIG. 3 is a diagram showing an example of a stacked structure of a solid-state imaging device 200 according to the first embodiment of the present technology. This solid-state imaging device 200 includes a circuit chip 202 and a light-receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via connection portions such as vias. In addition to vias, they can also be connected by Cu-Cu bonding or bumps.

[0026] FIG. 4 is a block diagram showing a configuration example of the light-receiving chip 201 according to the first embodiment of the present technology. The light-receiving chip 201 is provided with a pixel array unit 210 and a peripheral circuit 212.

[0027] In the pixel array unit 210, a plurality of pixel circuits 220 are arranged in a two-dimensional grid. The pixel array unit 210 is divided into a plurality of pixel blocks 211. In each of these pixel blocks 211, for example, pixel circuits 220 arranged in 4 rows × 2 columns are arranged. Further, a plurality of transistors are further arranged outside the pixel circuit 220 for each pixel circuit 220, but those transistors are omitted in the figure for convenience of description.

[0028] In the peripheral circuit 212, for example, a circuit for supplying a DC (Direct Current) voltage is arranged.

[0029] FIG. 5 is a block diagram showing a configuration example of the circuit chip 202 in the first embodiment of the present technology. In this circuit chip 202, a DAC (Digital to Analog Converter) 251, a pixel driving circuit 252, a time code generation unit 253, a pixel AD conversion unit 254, and a vertical scanning circuit 255 are arranged. Further, a control circuit 256, a signal processing circuit 400, an image processing circuit 260, and an output circuit 257 are arranged in the circuit chip 202.

[0030] The DAC 251 generates a reference signal by DA (Digital to Analog) conversion over a predetermined AD conversion period. For example, a sawtooth-shaped ramp signal is used as the reference signal. The DAC 251 supplies the reference signal to the pixel AD conversion unit 254.

[0031] The time code generation unit 253 generates a time code indicating the time within the AD conversion period. The time code generation unit 253 is realized by, for example, a counter. As the counter, for example, a Gray code counter is used. The time code generation unit 253 supplies the time code to the pixel AD conversion unit 254.

[0032] The pixel driving circuit 252 drives each of the pixel circuits 220 to generate an analog pixel signal.

[0033] The pixel AD conversion unit 254 performs AD conversion to convert each analog signal (i.e., pixel signal) of the pixel circuit 220 into a digital signal. This pixel AD conversion unit 254 is divided by a plurality of clusters 300. The cluster 300 is provided for each pixel block 211 and converts the analog signal within the corresponding pixel block 211 into a digital signal.

[0034] The pixel AD conversion unit 254 generates image data in which digital signals are arranged by AD conversion as a frame and supplies it to the signal processing circuit 400.

[0035] The vertical scanning circuit 255 drives the pixel AD conversion unit 254 to perform AD conversion.

[0036] The signal processing circuit 400 performs predetermined signal processing on a frame. As the signal processing, various processes including CDS (Correlated Double Sampling) processing and TDI processing are executed. This signal processing circuit 400 supplies the processed frame to the image processing circuit 260.

[0037] The image processing circuit 260 executes predetermined image processing on the frame from the signal processing circuit 400. As the image processing, image recognition processing, black level correction processing, image correction processing, demosaic processing, etc. are executed. This image processing circuit 260 supplies the processed frame to the output circuit 257.

[0038] The output circuit 257 outputs the frame after image processing to the outside.

[0039] The control circuit 256 controls the operation timings of the DAC 251, the pixel driving circuit 252, the vertical scanning circuit 255, the signal processing circuit 400, the image processing circuit 260, and the output circuit 257 in synchronization with the vertical synchronization signal VSYNC.

[0040] [Configuration Example of Pixel AD Conversion Unit] FIG. 6 is a diagram showing a configuration example of the pixel AD conversion unit 254 in the first embodiment of the present technology. In this pixel AD conversion unit 254, a plurality of ADCs 310 are arranged in a two-dimensional grid. The ADC 310 is arranged for each pixel circuit 220. When the number of rows and columns of the pixel circuits 220 is N rows (N is an integer) and M columns (M is an integer), N×M ADCs 310 are arranged.

[0041] In each of the clusters 300, the same number of ADCs 310 as the number of pixel circuits 220 in the pixel block 211 is arranged. When 4 rows × 2 columns of pixel circuits 220 are arranged in the pixel block 211, 4 rows × 2 columns of ADCs 310 are also arranged in the cluster 300.

[0042] The ADC310 performs AD conversion on the analog pixel signal generated by the corresponding pixel circuit 220. In this AD conversion, the ADC310 compares the pixel signal with a reference signal and holds the time code at the moment when the comparison result is inverted. Then, the ADC310 outputs the held time code as a digital signal after AD conversion.

[0043] Also, a repeater section 360 is arranged for each column of the cluster 300. When the number of columns of the cluster 300 is M / 2, M / 2 repeater sections 360 are arranged. The repeater section 360 transfers the time code. The repeater section 360 transfers the time code from the time code generation section 253 to the ADC310. Also, the repeater section 360 transfers the digital signal from the ADC310 to the signal processing circuit 400. This transfer of the digital signal is also called "reading out" of the digital signal.

[0044] Also, in the same figure, the numbers in parentheses indicate an example of the reading order of the digital signals of the ADC310. For example, the digital signals of the odd-numbered columns in the first row are read out first, and the digital signals of the even-numbered columns in the first row are read out second. The digital signals of the odd-numbered columns in the second row are read out third, and the digital signals of the even-numbered columns in the second row are read out fourth. Similarly, hereinafter, the digital signals of the odd-numbered and even-numbered columns in each row are read out in order.

[0045] Note that although the ADC310 is arranged for each pixel circuit 220, the configuration is not limited to this. A configuration in which a plurality of pixel circuits 220 share one ADC310 may also be used.

[0046] [Configuration Example of ADC] FIG. 7 is a block diagram showing a configuration example of the ADC310 in the first embodiment of the present technology. This ADC310 includes a differential input circuit 320, a positive feedback circuit 330, a latch control circuit 340, and a plurality of latch circuits 350.

[0047] Also, an amplification circuit 230 is disposed between the pixel circuit 220 and the ADC 310. This amplification circuit 230 amplifies the pixel signal from the pixel circuit 220 and supplies it to the ADC 310. The circuit composed of these pixel circuit 220 and amplification circuit 230 functions as one pixel.

[0048] Also, the pixel circuit 220, the amplification circuit 230, and a part of the differential input circuit 320 are disposed on the light-receiving chip 201, and the rest of the differential input circuit 320 and the subsequent-stage circuit are disposed on the circuit chip 202.

[0049] The differential input circuit 320 compares the pixel signal from the amplification circuit 230 with the reference signal from the DAC 251. This differential input circuit 320 supplies a comparison result signal indicating the comparison result to the positive feedback circuit 330.

[0050] The positive feedback circuit 330 adds a part of the output to the input (comparison result signal) and supplies it to the latch control circuit 340 as the output signal VCO.

[0051] The latch control circuit 340 causes the plurality of latch circuits 350 to hold the time code at the time when the output signal VCO is inverted according to the control signal xWORD from the vertical scanning circuit 255.

[0052] The latch circuit 350 holds the time code from the repeater section 360 according to the control of the latch control circuit 340. The latch circuit 350 is provided in the number corresponding to the number of bits of the time code. For example, when the time code is 15 bits, 15 latch circuits 350 are disposed in the ADC 310. Also, the held time code is read out by the repeater section 360 as a digital signal after AD conversion.

[0053] With the configuration illustrated in the figure, the ADC 310 converts the pixel signal from the amplification circuit 230 into a digital signal.

[0054] [Configuration Example of Differential Input Circuit and Positive Feedback Circuit] FIG. 8 is a circuit diagram showing a configuration example of a pixel circuit 220, a differential input circuit 320, and a positive feedback circuit 330 in the first embodiment of the present technology.

[0055] The differential input circuit 320 includes pMOS (p-channel Metal Oxide Semiconductor) transistors 321, 324, and 326. The differential input circuit 320 also includes nMOS (n-channel MOS) transistors 322, 323, 325, 327, and 328. Among these, the nMOS transistors 322, 323, 325, and 328 are arranged on the light-receiving chip 201, and the rest are arranged on the circuit chip 202.

[0056] The nMOS transistors 322 and 325 form a differential pair, and the sources of these transistors are commonly connected to the drain of the nMOS transistor 323. Also, the drain of the nMOS transistor 322 is connected to the drain of the pMOS transistor 321 and the gates of the pMOS transistors 321 and 324. The drain of the nMOS transistor 325 is connected to the drain of the pMOS transistor 324 and the gate of the pMOS transistor 326. Also, a reference signal REF from the DAC 251 is input to the gate of the nMOS transistor 322.

[0057] A predetermined bias voltage Vb is applied to the gate of the nMOS transistor 323, and a predetermined ground voltage is applied to the source of the nMOS transistor 323.

[0058] A pixel signal SIG from the amplifier circuit 230 is input to the gate of the nMOS transistor 325.

[0059] The pMOS transistors 321, 324, and 326 form a current mirror circuit. A power supply voltage VDDH is applied to the sources of the pMOS transistors 321, 324, and 326. This power supply voltage VDDH is higher than the power supply voltage VDDL described later.

[0060] A power supply voltage VDDL is applied to the gate of the nMOS transistor 327. Also, the drain of the nMOS transistor 327 is connected to the drain of the pMOS transistor 326, and the source is connected to the positive feedback circuit 330.

[0061] The nMOS transistor 328 shorts the gate and the drain of the nMOS transistor 325 according to the auto-zero signal AZ from the pixel driving circuit 252.

[0062] The positive feedback circuit 330 includes pMOS transistors 331, 332, 334, and 335 and nMOS transistors 333, 336, and 337. The pMOS transistors 331 and 332 and the nMOS transistor 333 are connected in series to the power supply voltage VDDL. Also, a driving signal INI2 from the vertical scanning circuit 255 is input to the gate of the pMOS transistor 331. The connection point of the pMOS transistor 332 and the nMOS transistor 333 is connected to the source of the nMOS transistor 327.

[0063] A ground voltage is applied to the source of the nMOS transistor 333, and a driving signal INI1 from the vertical scanning circuit 255 is input to the gate.

[0064] The pMOS transistors 334 and 335 are connected in series to the power supply voltage VDDL. Also, the drain of the pMOS transistor 335 is connected to the gate of the pMOS transistor 332 and the drains of the nMOS transistors 336 and 337. A control signal TESTVCO from the vertical scanning circuit 255 is input to the gates of the pMOS transistor 335 and the nMOS transistor 337. Also, the gates of the pMOS transistor 334 and the nMOS transistor 336 are connected to the connection point of the pMOS transistor 332 and the nMOS transistor 333.

[0065] From the connection point of the pMOS transistor 335 and the nMOS transistor 337, an output signal VCO is output. Also, a ground voltage is applied to the sources of the nMOS transistors 336 and 337.

[0066] Note that each of the differential input circuit 320 and the positive feedback circuit 330 is not limited to the circuit illustrated in FIG. 8 as long as it has the functions described with reference to FIG. 7.

[0067] [Configuration Examples of Amplification Circuit and Pixel Circuit] FIG. 9 is a circuit diagram showing a configuration example of the pixel circuit 220 and the amplification circuit 230 in the first embodiment of the present technology.

[0068] The pixel circuit 220 includes a discharge transistor 221, a photoelectric conversion element 222, a transfer transistor 223, a reset transistor 224, a capacitor 225, a gain control transistor 226, and a floating diffusion layer 227. As the discharge transistor 221, the transfer transistor 223, the reset transistor 224, and the gain control transistor 226, for example, nMOS transistors are used.

[0069] The discharge transistor 221 discharges the charges accumulated in the photoelectric conversion element 222 in accordance with the drive signal OFG from the pixel drive circuit 252. The photoelectric conversion element 222 generates charges by photoelectric conversion.

[0070] The transfer transistor 223 transfers charges from the photoelectric conversion element 222 to the floating diffusion layer 227 in accordance with the transfer signal TG from the pixel drive circuit 252.

[0071] The reset transistor 224 initializes the floating diffusion layer 227 in accordance with the reset signal RST from the pixel drive circuit 252.

[0072] The capacitor 225 is inserted between the connection node of the reset transistor 224 and the gain control transistor 226 and the ground terminal.

[0073] The gain control transistor 226 controls the analog gain with respect to the voltage of the floating diffusion layer 227 in accordance with the control signal FDG from the pixel drive circuit 252. By reducing and outputting the voltage of the floating diffusion layer 227 by the analog gain, the amount of the handling signal of the pixel circuit 220, that is, the saturation signal amount, can be enlarged.

[0074] The floating diffusion layer 227 accumulates the transferred charge and generates a voltage corresponding to the amount of the charge.

[0075] Also, the amplifier circuit 230 includes nMOS transistors 231 and 232 and a capacitor 233. The nMOS transistors 231 and 232 are connected in series between the power supply and the ground terminal. The gate of the nMOS transistor 231 on the power supply side is connected to the floating diffusion layer 227. A predetermined bias voltage VB2 is applied to the gate of the nMOS transistor 232 on the ground side.

[0076] Also, the connection node of the nMOS transistors 231 and 232 is connected to the differential input circuit 320 via the capacitor 233. Assuming that the gate-source capacitance of the nMOS transistor 325 on the pixel signal side among the differential pair in the differential input circuit 320 is Cgs, the capacitance value of the capacitor 233 is set to a value much larger than the gate-source capacitance Cgs. If the floating diffusion layer 227 and the gate of the nMOS transistor 325 are directly connected, the fluctuation of the floating diffusion layer 227 may increase due to the coupling between the gate-source capacitance Cgs and the floating diffusion layer 227, and the AD conversion period may be prolonged. However, by adding the capacitor 233, the influence of this coupling can be mitigated.

[0077] Note that each of the pixel circuit 220 and the amplifier circuit 230 is not limited to the circuit illustrated in FIG. 9 as long as it has the functions described in FIG. 7.

[0078] FIG. 10 is a plan view showing an example of the layout of elements in a pixel in the first embodiment of the present technology. The optical axis of incident light is defined as the Z axis, a predetermined axis perpendicular to the Z axis is defined as the X axis, and an axis perpendicular to the Z axis and the X axis is defined as the Y axis.

[0079] In the light-receiving surface, that is, in the XY plane, a plurality of photoelectric conversion elements 222 in N rows and M columns are arranged in a two-dimensional lattice. The size of these photoelectric conversion elements 222 in the Y-axis direction is denoted as Y1. In this XY plane, M photoelectric conversion elements 222 are arranged adjacent to each other without gaps along the X-axis direction. A set of M photoelectric conversion elements 222 arranged in the X-axis direction and a set of digital signals corresponding thereto are hereinafter referred to as a "line". On the other hand, along the Y-axis direction, N photoelectric conversion elements 222 are arranged with an interval of Y2 therebetween. In other words, N lines are arranged with an interval of Y2 therebetween. Here, it is assumed that the following relationship holds between the size Y1 and the interval Y2. Y1 ≦ Y2 ··· Equation 1

[0080] In the figure, the interval Y2 has the same value as the size Y1. Note that, as exemplified in Equation 1, the interval Y2 can be made larger than the size Y1. When the interval Y2 is made larger than the size Y1, the interval Y2 is set to an integer multiple of Y1. The larger the interval Y2, the larger the size of the lower ADC 310 in the Y-axis direction can be, and accordingly, the size of the ADC 310 in the X-axis direction can be reduced to miniaturize the pixels in the X-axis direction.

[0081] Also, in the Y-axis direction, a transistor arrangement region 241 is provided in the gap region 240 between each of the N photoelectric conversion elements 222. In this transistor arrangement region 241, a predetermined number of transistors, a floating diffusion layer 227, and capacitors 233 and 225 are arranged. The predetermined number of transistors includes an output transistor 221, a reset transistor 224, and a gain control transistor 226, and nMOS transistors 231, 232, 322, 323, and 325. In other words, in the transistor arrangement region 241, the transistors in the differential input circuit 320 illustrated in FIG. 8 and the transistors in the pixel circuit 220 and the amplifier circuit 230 illustrated in FIG. 9 are arranged. These transistors generate a signal (a pixel signal or a signal obtained by amplifying the pixel signal) corresponding to the amount of charge generated by any one of the plurality of photoelectric conversion elements 222, as described with reference to FIG. 9. Further, a transfer transistor 223 is arranged between the transistor arrangement region 241 and the photoelectric conversion element 222.

[0082] Here, assume a comparative example in which N rows and M columns of photoelectric conversion elements 222 are arranged without gaps along the X-axis direction and the Y-axis direction, and various transistors such as the output transistor 221 and the floating diffusion layer 227 are arranged around the photoelectric conversion elements 222. In this comparative example, the light-receiving area of the photoelectric conversion element 222 becomes narrower as the number of transistors increases.

[0083] On the other hand, as illustrated in the same figure, in a configuration in which N photoelectric conversion elements 222 are arranged at predetermined intervals in the Y-axis direction, transistors and the like can be arranged in the gap region 240, so that the light-receiving area can be made wider than in the comparative example. By expanding the light-receiving area, the sensitivity of the pixel can be improved. Also, since more transistors can be arranged than in the comparative example, additional circuits such as the amplifier circuit 230 can be further arranged in addition to the pixel circuit 220.

[0084] [Configuration Example of Signal Processing Circuit] FIG. 11 is a block diagram showing a configuration example of a signal processing circuit 400 in the first embodiment of the present technology. This signal processing circuit 400 includes a plurality of selectors 405, a plurality of arithmetic circuits 410, a CDS frame memory 440, and a TDI frame memory 450.

[0085] The selector 405 is arranged for each column of the cluster 300, in other words, for each repeater section 360. When two columns of ADCs 310 are arranged in the cluster 300, the selector 405 is arranged for every two columns. Also, the arithmetic circuit 410 is arranged for each column of the ADC 310. When there are M columns of ADCs 310, M / 2 selectors 405 and M arithmetic circuits 410 are arranged.

[0086] As described above, the repeater section 360 outputs the digital signals of the odd-numbered columns and the digital signals of the even-numbered columns in order.

[0087] The selector 405 selects the output destination of the digital signal according to the control of the control circuit 256. When the odd-numbered column is output by the repeater section 360, the selector 405 outputs the digital signal to the arithmetic circuit 410 corresponding to that odd-numbered column. On the other hand, when the even-numbered column is output, the selector 405 outputs the digital signal to the arithmetic circuit 410 corresponding to that even-numbered column.

[0088] The arithmetic circuit 410 performs CDS processing and TDI processing on the digital signal from the selector 405.

[0089] Here, the digital signal includes a P-phase level and a D-phase level. The P-phase level indicates the level when the pixel circuit 220 is initialized by the reset signal RST. On the other hand, the D-phase level indicates the level corresponding to the exposure amount when the charge is transferred by the transfer signal TG. The P-phase level is also called the reset level, and the D-phase level is also called the signal level.

[0090] In the CDS process, the M arithmetic circuits 410 cause the CDS frame memory 440 to hold a P-phase frame in which P-phase levels are arranged. Then, the M arithmetic circuits 410 obtain the difference between the P-phase level and the D-phase level for each pixel, and generate a CDS frame in which the difference data is arranged. On the other hand, in the TDI process, the M arithmetic circuits 410 cause the TDI frame memory 450 to hold the frame after the CDS process, and update the TDI frame memory 450 with the integrated data.

[0091] Also, the M arithmetic circuits 410 supply the CDS frame and the TDI frame after the TDI process to the image processing circuit 260.

[0092] [Configuration Example of Arithmetic Circuit] FIG. 12 is a circuit diagram showing a configuration example of the arithmetic circuit 410 in the first embodiment of the present technology. This arithmetic circuit 410 includes a TDI circuit 420 and a CDS circuit 430. The TDI circuit 420 includes a buffer 421, a selector 422, an adder 423, and a switch 424. The CDS circuit 430 includes a selector 431, a buffer 432, a selector 433, a subtractor 434, and a switch 435. The operations of the selectors 422, 431, and 433 and the switches 424 and 425 are controlled by, for example, the control circuit 256.

[0093] The selector 431 selects either the digital signal from the selector 405 or the digital signal from the TDI frame memory 450 and outputs it to the buffer 421.

[0094] The buffer 421 delays the signal from the selector 431 and outputs it. Note that the buffer 421 is an example of the second buffer described in the claims.

[0095] The selector 422 selects either the digital signal from the buffer 421 or the digital signal having a value of "0" in decimal and outputs it to the adder 423.

[0096] The adder 423 adds the digital signal from the selector 422 and the digital signal from the buffer 432. This adder 423 supplies a digital signal indicating the added value as integrated data to the switch 424.

[0097] The switch 424 opens and closes the path between the adder 423 and the TDI frame memory 450.

[0098] The buffer 432 delays and outputs the signal from the CDS frame memory 440. Note that the buffer 432 is an example of the first buffer described in the claims.

[0099] The selector 433 selects either the digital signal from the buffer 432 or the digital signal with a value of "0" in decimal and outputs it to the subtractor 434.

[0100] The subtractor 434 calculates the difference between the digital signal from the buffer 421 and the digital signal from the selector 433. This subtractor 434 supplies a digital signal indicating the difference as difference data to the switch 435.

[0101] The switch 435 opens and closes the path between the subtractor 434 and the CDS frame memory 440.

[0102] With the configuration illustrated in the figure, the CDS circuit 430 can perform CDS processing. Also, the TDI circuit 420 can perform TDI processing.

[0103] FIG. 13 is a diagram showing an example of TDI processing in the first embodiment of the present technology. For example, the CDS frame memory 440 and the TDI frame memory 450 are initialized, and first, frame F1 is imaged, and subsequently, frames F2, F3, F4, F5, F6, F7, and F8 are imaged in order. In the figure, frames after F5 are omitted. Also, the arrows in the figure indicate the moving direction of the subject. As illustrated in the figure, this subject moves one line at a time in the direction in which the row address increases along the Y-axis direction. The gray portions between the lines in the figure indicate the gap regions between the lines. The gap region is one line.

[0104] In the TDI process, the signal processing circuit 400 integrates line L1 of frame F1 after CDS processing, line L2 of frame F3, line L3 of frame F5, and line L4 of frame F7. As described above, since the subject moves one line at a time and the gap region is one line, the patterns of each line to be integrated are the same. The signal processing circuit 400 outputs the integrated line as the last line of the TDI frame.

[0105] Also, in the TDI process, the signal processing circuit 400 integrates line L1 of frame F2 after CDS processing, line L2 of frame F4, line L3 of frame F6, and line L4 of frame F8. The signal processing circuit 400 outputs the integrated line as the second last line of the TDI frame. Similarly for other lines, they are generated by integrating four lines after frame F3.

[0106] When the moving speed of the subject is fast, it is necessary to shorten the exposure time in order to prevent blur. Although shortening the exposure time may cause the image to become dark, by performing TDI processing, it is possible to improve the brightness by integrating a plurality of lines of the same pattern. Also, the more lines are integrated, the more the noise is reduced due to the smoothing effect. By improving the brightness and reducing the noise, the image quality of the frame (i.e., image data) can be improved compared to the case where TDI processing is not performed.

[0107] Note that although the signal processing circuit 400 integrates four lines, the number of lines to be integrated is not limited to four as long as it is two or more. Also, although the signal processing circuit 400 integrates four lines starting from the first line for the first eight frames, it is not limited to this configuration. For example, when the moving direction of the subject is reversed, the signal processing circuit 400 may integrate four lines starting from the last line for the first eight frames.

[0108] Also, although there is a gap region of one line between lines, by skipping every other frame to be integrated, such as frames F1, F3, F5, and F7, lines of the same pattern can be integrated. Note that when the gap region between lines is two lines or three lines, every other two frames or every other three frames to be integrated may be skipped.

[0109] [Operation Example of Solid-State Image Sensor] FIG. 14 is an example of a flowchart showing an example of the operation of the solid-state image sensor 200 in the first embodiment of the present technology. This operation starts, for example, when a predetermined application for imaging a frame is executed.

[0110] The pixel driving circuit 252 in the solid-state image sensor 200 drives all pixels and simultaneously starts exposure (step S901). In this way, the control to expose all pixels simultaneously is called the global shutter method.

[0111] Just before the end of exposure, the ADC 310 performs AD conversion on the P-phase level (step S902). Then, at the end of exposure, the ADC 310 performs AD conversion on the D-phase level, and the arithmetic circuit 410 performs CDS processing (step S903).

[0112] The image processing circuit 260 performs predetermined image processing on the frame after CDS processing (step S904), and the arithmetic circuit 410 performs TDI processing (step S905). The image processing circuit 260 performs predetermined image processing on the frame after TDI processing (step S906), and the output circuit 257 outputs the processing result (step S907). After step S907, the solid-state imaging device 200 finishes the process of imaging one frame. When continuously imaging two or more frames, steps S901 to S907 are repeatedly executed in synchronization with the vertical synchronization signal VSYNC.

[0113] Thus, according to the first embodiment of the present technology, a plurality of photoelectric conversion elements 222 are arranged at regular intervals along the Y-axis direction, and transistors are arranged between them. Therefore, the light-receiving area of the photoelectric conversion elements 222 can be made larger than when no interval is provided. Thereby, the sensitivity of the pixel can be improved.

[0114] <2. Second Embodiment> In the above-described first embodiment, the reset transistor 224 is arranged in the pixel circuit 220 to initialize the floating diffusion layer 227. However, in this configuration, as the number of pixels increases, the circuit scale on the light-receiving chip 201 side increases. The pixel circuit 220 of this second embodiment is different from the first embodiment in that the reset transistor 224 is reduced.

[0115] FIG. 15 is a circuit diagram showing a configuration example of the pixel circuit 220 and the amplifier circuit 230 in the second embodiment of the present technology. The pixel circuit 220 of this second embodiment is different from the first embodiment in that the reset transistor 224 is not arranged. In this second embodiment, the floating diffusion layer 227 is initialized, for example, when the pixel drive circuit 252 turns on the discharge transistor 221 and the transfer transistor 223. By reducing the reset transistor 224, the circuit scale of the light-receiving chip 201 can be reduced.

[0116] Thus, according to the second embodiment of the present technology, since the pixel driving circuit 252 turns on the discharge transistor 221 and the transfer transistor 223 to initialize the floating diffusion layer 227, the reset transistor 224 can be reduced. As a result, the circuit scale of the light receiving chip 201 can be reduced.

[0117] <3. Third Embodiment> In the above-described first embodiment, circuits such as the amplification circuit 230 are added to the gap region between the lines. However, in this configuration, there is a risk that the circuit scale on the light receiving chip 201 side increases as the number of pixels increases. The pixel circuit 220 of this second embodiment is different from the first embodiment in that a plurality of pixels share the floating diffusion layer 227.

[0118] FIG. 16 is a circuit diagram showing a configuration example of the differential input circuit 320, the positive feedback circuit 330, and the FD sharing block 235 in the third embodiment of the present technology. A plurality of pixels sharing one floating diffusion layer 227 are arranged in the FD sharing block 235. This FD sharing block 235 is connected one-to-one with an ADC 310 including a differential input circuit 320 and a positive feedback circuit 330. That is, the ADC 310 is also shared by a plurality of pixels.

[0119] FIG. 17 is a circuit diagram showing a configuration example of the FD sharing block 235 in the third embodiment of the present technology. This FD sharing block 235 includes discharge transistors 221 and 236, photoelectric conversion elements 222 and 237, transfer transistors 223 and 238, and a floating diffusion layer 227.

[0120] The connection configuration between the discharge transistor 221, the photoelectric conversion element 222, the transfer transistor 223, and the floating diffusion layer 227 is the same as that in the first embodiment. However, a transfer signal TG1 is input to the transfer transistor 223, and a drive signal OFG1 is input to the discharge transistor 221.

[0121] The discharge transistor 236 discharges the charges accumulated in the photoelectric conversion element 227 in accordance with the drive signal OFG2 from the pixel drive circuit 252. The photoelectric conversion element 237 generates charges by photoelectric conversion.

[0122] The transfer transistor 238 transfers charges from the photoelectric conversion element 237 to the floating diffusion layer 227 in accordance with the transfer signal TG2 from the pixel drive circuit 252.

[0123] The circuit composed of the discharge transistor 221, the photoelectric conversion element 222, the transfer transistor 223, and the floating diffusion layer 227 functions as one pixel. Also, the circuit composed of the discharge transistor 236, the photoelectric conversion element 237, the transfer transistor 238, and the floating diffusion layer 227 functions as one pixel. That is, the floating diffusion layer 227 is shared by two pixels. By sharing the floating diffusion layer 227 among a plurality of pixels, the circuit scale per pixel of the light-receiving chip 201 can be reduced.

[0124] Although one floating diffusion layer 227 is shared by two pixels, the number of pixels sharing the floating diffusion layer 227 can also be three or more.

[0125] FIG. 18 is a plan view showing an example of the layout of elements in a pixel in the third embodiment of the present technology. Lines in which N photoelectric conversion elements 222 are arranged in the X-axis direction are arranged with an interval of one line in the Y-axis direction. Between the lines composed of the photoelectric conversion elements 222, lines in which N floating diffusion layers 227 are arranged are disposed. And between the photoelectric conversion elements 222 and 237, a transistor arrangement region 241 is provided, and elements such as the discharge transistor 221 and the floating diffusion layer 227 are arranged in the transistor arrangement region 241. Also, transfer transistors 223 and 238 are arranged between the transistor arrangement region 241 and each of the photoelectric conversion elements 222 and 237.

[0126] In addition, when the number of pixels sharing the floating diffusion layer 227 is three or more, the interval between the lines formed by the photoelectric conversion elements 222 may be two or more lines. The larger the interval between the lines formed by the photoelectric conversion elements 222, the larger the size of the lower ADC 310 in the Y direction can be made, so that the miniaturization of the pixels in the X-axis direction becomes easier.

[0127] As described above, according to the third embodiment of the present technology, since a circuit sharing the floating diffusion layer 227 is arranged between the lines formed by the floating diffusion layer 227, the circuit scale per pixel of the light-receiving chip 201 can be reduced as compared with the case where sharing is not performed.

[0128] Note that the above-described embodiments show examples for embodying the present technology, and there is a corresponding relationship between the matters in the embodiments and the invention specifying matters in the claims. Similarly, there is a corresponding relationship between the invention specifying matters in the claims and the matters in the embodiments of the present technology having the same name. However, the present technology is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the gist thereof.

[0129] Note that the effects described in this specification are merely examples and are not limiting, and there may be other effects.

[0130] Note that the present technology can also have the following configuration. (1) A plurality of photoelectric conversion elements arranged at predetermined intervals along a predetermined direction, each of the sizes of the respective predetermined directions not exceeding the predetermined intervals, and A predetermined number of transistors arranged between the plurality of photoelectric conversion elements and generating a signal corresponding to the amount of charge generated by any one of the plurality of photoelectric conversion elements A solid-state imaging device comprising. (2) Any one of the plurality of photoelectric conversion elements is arranged in a pixel circuit that generates a pixel signal, The predetermined number of transistors are arranged in the pixel circuit and an amplifier circuit that amplifies the pixel signal The solid-state imaging device according to (1) above. (3) The predetermined number of transistors includes a pair of differential transistors that differentially amplify a predetermined reference signal and the pixel signal. The amplification circuit includes a pair of transistors and a capacitor connected in series to a power supply. One gate of the pair of transistors is connected to the floating diffusion layer, and the capacitor is inserted between the connection point of the pair of transistors and one gate of the pair of differential transistors. The solid-state imaging device according to (2) above. (4) A floating diffusion layer disposed between the plurality of photoelectric conversion elements, A transfer transistor that transfers charges from any one of the plurality of photoelectric conversion elements to the floating diffusion layer, and further includes The predetermined number of transistors includes a discharge transistor that discharges charges from the floating diffusion layer, Any one of the plurality of photoelectric conversion elements, the floating diffusion layer, the transfer transistor, and the discharge transistor are disposed within the pixel circuit. The solid-state imaging device according to (2) or (3) above. (5) The predetermined number of transistors includes a gain control transistor that controls the analog gain with respect to the voltage of the floating diffusion layer. The gain control transistor is disposed within the pixel circuit. The solid-state imaging device according to any one of (2) to (4) above. (6) The predetermined number of transistors includes a reset transistor that initializes the floating diffusion layer. The reset transistor is disposed within the pixel circuit. The solid-state imaging device according to (5) above. (7) Further includes an analog-to-digital conversion unit that converts a pixel signal corresponding to the light reception amount of each of the plurality of photoelectric conversion elements into a digital signal. The solid-state imaging device according to any one of (1) to (6) above. Further comprising a time delay integration circuit that performs time delay integration processing on the digital signal The solid-state imaging device according to (7) above. (9) The plurality of photoelectric conversion elements and the predetermined number of transistors are arranged on a predetermined light-receiving chip, The analog-to-digital conversion unit is arranged on a predetermined circuit chip The solid-state imaging device according to (7) or (8) above. (10) A plurality of photoelectric conversion elements arranged at predetermined intervals along a predetermined direction, each of the sizes in the predetermined direction not exceeding the predetermined interval, A predetermined number of transistors arranged between the plurality of photoelectric conversion elements and generating a signal according to the amount of charge generated by any one of the plurality of photoelectric conversion elements, A signal processing circuit that processes digital signals according to the amount of light received by each of the plurality of photoelectric conversion elements An imaging device comprising:

Explanation of Reference Numerals

[0131] 100 Imaging device 110 Optical unit 120 Storage unit 130 Control unit 140 Communication unit 200 Solid-state imaging device 201 Light-receiving chip 202 Circuit chip 210 Pixel array unit 211 Pixel block 212 Peripheral circuit 220 Pixel circuit 221, 236 Drain transistors 222, 237 Photoelectric conversion elements 223, 238 Transfer transistors 224 Reset transistor 225, 233 Capacitors 226 Gain control transistor 227 Floating diffusion layer 230 Amplification circuit 231, 232, 322, 323, 325, 327, 328, 333, 336, 337 nMOS transistors 235 FD shared block 240 Gap region 241 Transistor placement region 251 DAC 252 Pixel drive circuit 253 Time code generation unit 254 Pixel AD conversion unit 255 Vertical scanning circuit 256 Control circuit 257 Output circuit 260 Image processing circuit 300 Cluster 310 ADC 320 Differential input circuit 321, 324, 326, 331, 332, 334, 335 pMOS transistors 330 Positive feedback circuit 340 Latch control circuit 350 Latch circuit 360 Repeater section 400 Signal processing circuit 405, 422, 431, 433 Selectors 410 Arithmetic circuit 420 TDI circuit 421, 432 Buffers 423 Adder 424, 435 Switches 430 CDS circuit 434 Subtractor 440 CDS frame memory 450 TDI frame memory 510 Belt conveyor 511 Subject

Claims

1. A plurality of photoelectric conversion elements arranged at predetermined intervals along a predetermined direction, each of the sizes of the predetermined direction not exceeding the predetermined intervals; A predetermined number of transistors arranged between the plurality of photoelectric conversion elements and generating a signal according to the amount of charge generated by any one of the plurality of photoelectric conversion elements; Comprising; Any one of the plurality of photoelectric conversion elements is arranged in a pixel circuit for generating a pixel signal; The predetermined number of transistors are arranged in the pixel circuit and an amplification circuit for amplifying the pixel signal; The predetermined number of transistors includes a pair of differential transistors for differentially amplifying a predetermined reference signal and the pixel signal; The amplification circuit includes a pair of transistors connected in series to a power supply and a capacitor; One gate of the pair of transistors is connected to a floating diffusion layer, and the capacitor is inserted between the connection point of the pair of transistors and one gate of the pair of differential transistors; Solid-state imaging device.

2. A floating diffusion layer arranged between the plurality of photoelectric conversion elements; A transfer transistor for transferring charge from any one of the plurality of photoelectric conversion elements to the floating diffusion layer; Further comprising; The predetermined number of transistors; Includes a discharge transistor for discharging charge from the floating diffusion layer; Any one of the plurality of photoelectric conversion elements, the floating diffusion layer, the transfer transistor, and the discharge transistor are arranged in the pixel circuit; The solid-state imaging device according to Claim 1.

3. The predetermined number of transistors includes a gain control transistor for controlling the analog gain with respect to the voltage of the floating diffusion layer; The gain control transistor is arranged in the pixel circuit; The solid-state imaging device according to Claim 1.

4. The predetermined number of transistors includes a reset transistor for initializing the floating diffusion layer; The reset transistor is arranged in the pixel circuit; The solid-state imaging device according to Claim 3.

5. Further comprising an analog-to-digital conversion unit for converting a pixel signal corresponding to the amount of light received by each of the plurality of photoelectric conversion elements into a digital signal; The solid-state imaging device according to Claim 1.

6. Further comprising a time delay integration circuit for performing time delay integration processing on the digital signal; The solid-state imaging device according to Claim 5.

7. The plurality of photoelectric conversion elements and the predetermined number of transistors are arranged on a predetermined light-receiving chip; The analog-to-digital conversion unit is arranged on a predetermined circuit chip; The solid-state imaging device according to claim 5.

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