3D DRAM Structure and Manufacturing Method

Abstract

A memory device incorporating bridged word lines is described. The memory device includes a plurality of active areas spaced apart along a first direction, a second direction, and a third direction. A plurality of conductive layers are arranged such that at least one conductive layer is adjacent to at least one side of each of the active areas along the third direction. A conductive bridge extends along the second direction and connects each of the conductive layers to one or more adjacent conductive layers. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. In particular, embodiments of the present disclosure provide a dynamic random access memory having bridged word lines and / or an etch stop layer.

Background Art

[0002]

[0002] Electronic devices, such as personal computers, workstations, computer servers, mainframes, and other computer-related equipment such as printers, scanners, and hard disk drives, use memory devices that provide a fairly large data storage capacity while consuming low power. There are two main types of random access memory cells suitable for use in electronic devices, namely, dynamic and static. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but may require periodic reprogramming or "refreshing" to maintain this voltage beyond a very short period. Static random access memory (SRAM) is so named because they do not require periodic refreshing.

[0003]

[0003] DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location capable of storing 1 bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components. That is, a field effect transistor (FET) and a capacitor.

[0004]

[0004] The manufacture of DRAM cells involves fabricating transistors, capacitors, and three contacts. Each of the three is for a bit line, a word line, and a reference voltage. The manufacture of DRAM is a highly competitive business. In order to be able to pack more memory on a single memory chip, it is constantly required to reduce the size of individual cells, and in particular, to increase the memory cell density to a density exceeding 256 megabits. The limitations on the reduction of cell size are the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of the array device with non-array devices.

[0005]

[0005] In a 3D memory device, the word lines of a unit cell layer should be connected. However, the active layer of the unit cell should not be connected. Further, the length of the capacitor needs to be controlled without interference from the effects of variations during the selective removal process. The length of the capacitor is longer than the gate length of the cell transistor. A longer selective removal length results in greater length variations due to the variable removal rate. Thus, there is a need in the art for a memory device and a method of forming a memory device that includes one or more of a connected word line, a separated active region, or etching control.

Summary of the Invention

[0006]

[0006] One or more embodiments of the present disclosure are directed to a memory device including a plurality of active regions spaced apart along a first direction, a second direction, and a third direction. A plurality of conductive layers are arranged such that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction and connects each conductive layer to one or more adjacent conductive layers.

[0007]

[0007] A further embodiment of the present disclosure is directed to a memory device comprising a plurality of pairs of active regions spaced along a first direction, a second direction, and a third direction. A plurality of bit lines extend along a third direction between pairs of active regions spaced in the first direction. A plurality of conductive layers are arranged such that at least one conductive layer is adjacent to at least one side of each of the active regions. At least one side is positioned along a third direction with respect to the active region. A conductive bridge extends along a second direction and connects each conductive layer to one or more adjacent conductive layers.

[0008]

[0008] A further embodiment of the present disclosure is directed to a method of forming a memory device. A stack of films including a sacrificial layer and a channel layer is patterned to form a pair of pre-bridge stacks separated along a first direction and a separation film stack extending along the first direction. The pre-bridge stacks are formed on both sides of the separation film stack along a second direction, generating an opening between the pre-bridge stacks and an opening outside the pre-bridge stacks along the first direction, and generating a gap between the separation film stack and an adjacent film stack along the second direction. The channel layer is removed from the pre-bridge stacks through the opening and recessed into the separation film stack to form a recessed channel layer within the separation film stack. The opening and the recessed channel layer are filled with a dielectric. A trench is formed within the separation film stack along the second direction. The trench is formed between a pair of pre-bridge stacks along the first direction. A portion of the sacrificial layer is removed from the separation film stack through the trench to form a recessed sacrificial layer having a recessed sacrificial layer surface and a word line opening, exposing the surface of the channel layer. A gate oxide layer is formed within the word line opening on the surface of the channel layer exposed through the trench. A conductive layer is deposited within the word line opening on the gate oxide layer. The trench is filled with a dielectric. A slit pattern is formed through the sacrificial layer and the channel layer. The slit pattern is formed outside the conductive layer within the word line opening on both sides of the position where the trench is formed. The slit pattern exposes the sidewalls of the channel layer and the sidewalls of the sacrificial layer. A portion of the channel layer is removed through the slit pattern to form a capacitor opening, exposing the surfaces of the sacrificial layer and the recessed channel layer. A capacitor is formed within the capacitor opening adjacent to the recessed channel layer.

[0009]

[0009] To enable a more detailed understanding of the above features of the present disclosure, a more specific description of the present disclosure, briefly summarized above, can be made by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the present disclosure, and thus the present disclosure should not be regarded as limiting the scope of the present disclosure, as other equally valid embodiments can be recognized. In the embodiments described herein, the accompanying drawings are used for illustration purposes rather than limitation, and like elements are denoted by like reference numerals in the drawings.

Brief Description of the Drawings

[0010]

Figure 1

[0010] A schematic parallel projection view of a memory device showing coordinate naming according to one or more embodiments of the present disclosure is shown.

Figure 2A

[0011] An isometric view of a memory device having one or two word lines adjacent to an active region according to one or more embodiments of the present disclosure is shown.

Figure 2B

Figure 2C

Figure 3

[0012] A parallel projection view of a memory device according to one or more embodiments of the present disclosure is shown.

Figure 4

[0013] An isometric view of a section of a memory device according to one or more embodiments of the present disclosure is shown.

Figure 5

[0014] A schematic cross-sectional view of a film stack for a memory device according to one or more embodiments of the present disclosure is shown.

Figure 6

[0015] A schematic top view of a memory device after separation patterning according to one or more embodiments is shown.

Figure 6A

[0016] Shows a cross-sectional slice of the memory device taken along line A-A of FIG. 6.

Figure 6B

[0017] Shows a cross-sectional slice of the memory device taken along line B-B of FIG. 6.

Figure 6C

[0018] Shows a cross-sectional slice of the memory device taken along line C-C of FIG. 6.

Figure 6D

[0019] Shows a cross-sectional slice of the memory device taken along line D-D of FIG. 6.

Figure 7

[0020] Shows a schematic top view of the memory device after active separation according to one or more embodiments.

Figure 7A

[0021] Shows a cross-sectional slice of the memory device taken along line A-A of FIG. 7.

Figure 7B

[0022] Shows a cross-sectional slice of the memory device taken along line B-B of FIG. 7.

Figure 7C

[0023] Shows a cross-sectional slice of the memory device taken along line C-C of FIG. 7.

Figure 7D

[0024] Shows a cross-sectional slice of the memory device taken along line D-D of FIG. 7.

Figure 8

[0025] Shows a schematic top view of the memory device after dielectric filling according to one or more embodiments.

Figure 8A

[0026] Shows a cross-sectional slice of the memory device taken along line A-A of FIG. 8.

Figure 8B

[0027] Shows a cross-sectional slice of the memory device taken along line B-B of FIG. 8.

Figure 8C

[0028] Shows a cross-sectional slice of the memory device taken along line C-C of FIG. 8.

Figure 8D

[0029] Shows a cross-sectional slice of a memory device taken along line D-D of FIG. 8.

Figure 9

[0030] Shows a schematic top view of a memory device after trench formation according to one or more embodiments.

Figure 9A

[0031] Shows a cross-sectional slice of a memory device taken along line A-A of FIG. 9.

Figure 9B

[0032] Shows a cross-sectional slice of a memory device taken along line B-B of FIG. 9.

Figure 9C

[0033] Shows a cross-sectional slice of a memory device taken along line C-C of FIG. 9.

Figure 9D

[0034] Shows a cross-sectional slice of a memory device taken along line D-D of FIG. 9.

Figure 10

[0035] Shows a schematic top view of a memory device after dielectric pullback according to one or more embodiments.

Figure 10A

[0036] Shows a cross-sectional slice of a memory device taken along line A-A of FIG. 10.

Figure 10B

[0037] Shows a cross-sectional slice of a memory device taken along line B-B of FIG. 10.

Figure 10C

[0038] Shows a cross-sectional slice of a memory device taken along line C-C of FIG. 10.

Figure 10D

[0039] Shows a cross-sectional slice of a memory device taken along line D-D of FIG. 10.

Figure 11

[0040] Shows a schematic top view of a memory device after gate oxide formation according to one or more embodiments.

Figure 11A

[0041] Shows a cross-sectional slice of a memory device taken along line A-A of FIG. 11.

Figure 11B

[0042] Shows a cross-sectional slice of the memory device taken along line B-B of FIG. 11.

Figure 11C

[0043] Shows a cross-sectional slice of the memory device taken along line C-C of FIG. 11.

Figure 11D

[0044] Shows a cross-sectional slice of the memory device taken along line D-D of FIG. 11.

Figure 12

[0045] Shows a schematic top view of the memory device after word line formation according to one or more embodiments.

Figure 12A

[0046] Shows a cross-sectional slice of the memory device taken along line A-A of FIG. 12.

Figure 12B

[0047] Shows a cross-sectional slice of the memory device taken along line B-B of FIG. 12.

Figure 12C

[0048] Shows a cross-sectional slice of the memory device taken along line C-C of FIG. 12.

Figure 12D

[0049] Shows a cross-sectional slice of the memory device taken along line D-D of FIG. 12.

Figure 13

[0050] Shows a schematic top view of the memory device after oxide filling according to one or more embodiments.

Figure 13A

[0051] Shows a cross-sectional slice of the memory device taken along line A-A of FIG. 13.

Figure 13B

[0052] Shows a cross-sectional slice of the memory device taken along line B-B of FIG. 13.

Figure 13C

[0053] Shows a cross-sectional slice of the memory device taken along line C-C of FIG. 13.

Figure 13D

[0054] Shows a cross-sectional slice of the memory device taken along line D-D of FIG. 13.

Figure 14

[0055] Shows a cross-sectional slice of a memory device after slit patterning according to one or more of the above embodiments.

Figure 15

[0056] Shows a cross-sectional slice of a memory device after capacitor opening formation according to one or more of the above embodiments.

Figure 16

[0057] Shows a cross-sectional view of a memory device after doping of the active region according to one or more of the above embodiments.

Figure 17

[0058] Shows an enlarged cross-sectional view of region 17 of FIG. 16.

Figure 18

[0059] Shows an enlarged cross-sectional view of a memory device after capacitor formation according to one or more of the above embodiments.

Figure 19

[0060] Shows an enlarged cross-sectional view of region 17 of FIG. 16 of a memory device after expanding the capacitor opening according to one or more of the above embodiments.

Figure 20

[0061] Shows an enlarged cross-sectional view of a memory device after forming a capacitor in the expanded opening according to one or more of the above embodiments.

Figure 21

[0062] Shows an enlarged cross-sectional view of region 21 of FIG. 16.

Figure 22

[0063] Shows an enlarged cross-sectional view of a memory device after forming bit line openings and source / drain regions according to one or more of the above embodiments.

Figure 23

[0064] Shows an enlarged cross-sectional view of a memory device after forming a liner and bit lines according to one or more of the above embodiments.

Figure 24

[0065] Shows a schematic diagram of a memory device according to one or more of the embodiments of the present disclosure.

Figure 25

[0066] Shows an enlarged view of region 25 of FIG. 24.

Figure 26

[0067] Shows a cross-sectional view of the memory device of FIG. 24 after trench formation and replacement gate recess according to one or more of the above embodiments.

Figure 27

[0068] FIG. 26 shows an enlarged cross-sectional view of the memory device after formation of the etching stop layer according to one or more of the above embodiments.

Figure 28

[0069] FIG. 28 shows an enlarged cross-sectional view of the memory device after formation of the active region according to one or more of the above embodiments.

Figure 29

[0070] FIG. 28 shows an enlarged cross-sectional view of the memory device after recessing the dielectric and the etching stop layer according to one or more of the above embodiments.

Figure 30

[0071] FIG. 29 shows an enlarged cross-sectional view of the memory device after formation of the word line according to one or more of the above embodiments.

Figure 31

[0072] FIG. 30 shows an enlarged cross-sectional view of the memory device after filling the trench, performing slit patterning, and performing replacement gate etching to form the capacitor opening according to one or more of the above embodiments.

Figure 32

[0073] FIG. 31 shows an enlarged cross-sectional view of the memory device after removal of the etching stop layer according to one or more of the above embodiments.

Figure 33

[0074] FIG. 32 shows an enlarged cross-sectional view of the memory device after doping the active region before capacitor formation according to one or more of the above embodiments.

Figure 34

[0075] FIG. shows a schematic view of a memory device according to one or more of the embodiments of the present disclosure.

Figure 35

[0076] FIG. shows a cross-sectional view of a film stack having an etching layer according to one or more of the above embodiments.

Figure 36

[0077] FIG. 35 shows a cross-sectional view of the memory device after recessing the sacrificial layer according to one or more of the above embodiments.

Figure 37

[0078] FIG. 36 shows a cross-sectional view of the memory device after a plurality of processes for forming the word line and the active region and after slit patterning according to one or more of the above embodiments.

Figure 38

[0079] The cross-sectional view of the memory device of FIG. 37 after replacement gate etching to the etching stop layer according to one or more of the above embodiments is shown.

Figure 39

[0080] The cross-sectional view of the memory device of FIG. 38 after removing the etching stop layer and doping the active region before forming the capacitor according to one or more of the above embodiments is shown.

Best Mode for Carrying Out the Invention

[0011]

[0081] Before explaining some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or process steps presented in the following description. The present disclosure can have other embodiments and can be implemented or executed in various ways.

[0012]

[0082] When used in this specification and the appended claims, terms such as "precursor", "reactant", "reaction gas" are used interchangeably to refer to any gas species that can react with the substrate surface.

[0013]

[0083] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores data bits by storing a packet of charge (i.e., binary 1) on a capacitor or by having no charge (i.e., binary 0). The charge is gate-controlled to the capacitor via an access transistor, and the same transistor is turned on to sense the voltage perturbation generated by dumping the charge packet onto the interconnect line on the transistor output. Thus, a single DRAM cell is fabricated with one transistor and one capacitor. A DRAM device is formed of an array of DRAM cells.

[0014]

[0084] Conventionally, DRAM cells have placed a high work function metal structure within an embedded word line structure. In a DRAM device, bit lines are formed within a metal level placed on a substrate, while word lines are formed at a polysilicon gate level on the surface of the substrate. In an embedded word line (bWL), the word line is embedded beneath the surface of the semiconductor substrate using a metal as the gate electrode.

[0015]

[0085] In one or more embodiments, a memory device having stacked DRAM cells is provided, as a result of which the bit density of the DRAM cells increases, which is proportional to the number of multiple pairs of membranes. The DRAM devices of one or more embodiments have vertical bit lines, minimize bit line capacitance, and reduce the capacitance burden of the capacitor.

[0016]

[0086] Some embodiments advantageously provide a memory device having an increased device density and a method of forming a memory device having an increased device density. Some embodiments provide a device in which the active regions of each unit cell are horizontally separated by an insulator between each active region. Some embodiments provide a word line to each cell of the same row and the same stack level connected via a bridge. In some embodiments, the bridge is smaller than the width of the gate. In some embodiments, one side of the active region is connected to a capacitor and the other side is connected to a bit line.

[0017]

[0087] Some embodiments provide a memory device and a method of forming a memory device with improved integration for fabricating 3D DRAM. In some embodiments, the length of the capacitor is controlled to eliminate or minimize variations resulting from a selective removal process of a sacrificial layer. In some embodiments, the length of the capacitor is longer than the gate length of the cell transistor.

[0018]

[0088] Figure 1 shows a general three-dimensional structure of a 3D DRAM device 10 according to one or more embodiments of the present disclosure. The device 10 has a three-dimensional array of active regions arranged in rows, columns, and layers. In the convention used herein, the rows are referred to as the X-axis or the first direction 20, the columns are referred to as the Y-axis or the second direction 30, and the layers are referred to as the Z-axis or the third direction 40. The angle 25 between the first direction 20 and the second direction 30 is any suitable angle in the range of 30 degrees to 150 degrees, or in the range of 45 degrees to 135 degrees, or in the range of 60 degrees to 120 degrees, or in the range of 75 degrees to 105 degrees, or in the range of 85 degrees to 95 degrees. The angle 35 between the first direction 20 and the third direction 40 is any suitable angle in the range of 30 degrees to 150 degrees, or in the range of 45 degrees to 135 degrees, or in the range of 60 degrees to 120 degrees, or in the range of 75 degrees to 105 degrees, or in the range of 85 degrees to 95 degrees. The angle 45 between the second direction 30 and the third direction 40 is any suitable angle in the range of 30 degrees to 150 degrees, or in the range of 45 degrees to 135 degrees, or in the range of 60 degrees to 120 degrees, or in the range of 75 degrees to 105 degrees, or in the range of 85 degrees to 95 degrees. In some embodiments, each of the angles 25, 35, and 45 is in the range of 85 degrees to 95 degrees.

[0019]

[0089] Figures 2A through 2C show three arrangements of an active region 115, a conductive layer 120, and a bridge 130 connecting adjacent conductive layers 120. In Figure 2A, the conductive layer 120 and the bridge 130 are below the active region 115. As used herein, the terms "above", "below", "upper", "lower", etc. refer to the physical orientation along the Z-axis or the third direction 40, and the scope of the present disclosure should not be construed as limited to any particular orientation related to the normal gravitational attraction. In Figure 2B, the conductive layer 120 and the bridge 130 are above the active region 115. In Figure 2C, the conductive layer 120 and the bridge 130 are both above and below the active region 115.

[0020]

[0090] Figure 3 shows a parallel projection view of the memory device 100 according to one or more embodiments of the present disclosure. Figure 4 shows an isometric schematic view of the 3D memory device 100. The illustrated device 100 has a total of six bit lines 170 and twelve word lines 160. A total of thirty-six active regions 115 are connected to the conductive layer 120 and the bridge 130. The embodiment shown in Figure 3 shows two unit cells 105 on both sides of the bit line 170, and each unit cell 105 includes a portion of the bit line 170. Each of the unit cells 105 in some embodiments stores data independently.

[0021]

[0091] Referring to FIGS. 3 and 4, the memory device 100 in some embodiments includes a plurality of active regions 115 spaced along a first direction 20 (as shown in FIGS. 3 and 4), a second direction 30 (as shown in FIG. 4), and a third direction 40 (as shown in FIG. 4). Some embodiments of the active regions 115 include transistors. Some embodiments of the active regions 115 include a stack of material layers (not shown) including a charge tunneling layer, a charge trapping layer, and a charge blocking layer. Those skilled in the art will understand the process for forming a transistor. The individual layers are not shown for clarity.

[0022]

[0092] The plurality of conductive layers 120 are arranged such that at least one conductive layer 120 is adjacent to at least one side of each of the active regions 115 along the third direction 40. When used in this way, the term "adjacent to" means next to, in direct contact with, or having a minimum number of components or distance between the described components. For example, the conductive layer 120 shown in FIG. 3 is adjacent to the active region 115 with the gate oxide 140 layer therebetween.

[0023]

[0093] In some embodiments, at least some of the active regions 115 have one conductive layer 120 adjacent thereto, as shown in FIGS. 2A, 2B, and 4. In some embodiments, as shown in FIGS. 2C and 3, each of the active regions 115 has conductive layers 120 on both sides of the active region 115 along a third direction. When used in this way, the arrangement of components along a particular direction means that the described components are aligned along that direction. For example, as shown in FIG. 3, the conductive layers 120 on both sides of the active region 115 mean that the conductive layers 120 are aligned with the active region 115 along the third direction 40 (Z-axis direction).

[0024]

[0094] The conductive bridge 130 extends along the second direction 20. The conductive bridge 130 connects the conductive layer 120 to one or more adjacent conductive layers. The conductive bridge 130 shown in FIG. 4 shows connections to a plurality of adjacent conductive layers 120. The conductive bridge 130 forms a connection between the conductive layers 120 along the second direction 20, i.e., the Y-axis direction.

[0025]

[0095] In some embodiments, as shown in FIG. 3, the gate oxide 140 is disposed between the active region 115 and the conductive layer 120. The gate oxide 140 can be any suitable dielectric material including low-k and high-k dielectric materials. In some embodiments, the gate oxide 140 includes one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0026]

[0096] Some embodiments of the memory device 100 include a capacitor 180 on a side of the active region 115 along the first direction 20. The capacitor 180 is electrically separated from the conductive layer 120 and the conductive bridge 130. In other words, the capacitor 180 is not in direct contact with the conductive layer 120 or the conductive bridge 130.

[0027]

[0097] The capacitor 180 of some embodiments includes a lower electrode 186, a high-k dielectric 184, and an upper electrode 182. The lower electrode 186 is in contact with the active region 115. The high-k dielectric 184 is adjacent to the lower electrode 186 and is on the side opposite to the active region 115 with the lower electrode 186 therebetween. The upper electrode 182 is adjacent to the high-k dielectric 184 and is on the side opposite to the lower electrode 186. In some embodiments, the high-k dielectric 184 is in direct contact with the lower electrode 186. In some embodiments, the upper electrode 182 is in direct contact with the high-k dielectric 184.

[0028]

[0098] In some embodiments, the doped layer 117 is between the active region 115 and the lower electrode 186 along the first direction 20. The doped layer 117 may be any suitable material known to those skilled in the art. In some embodiments, the doped layer 117 includes titanium nitride.

[0029]

[0099] In some embodiments, the active region 115 includes a source / drain region 119 adjacent to the bit line 170. The source / drain region 119 can be formed by any suitable technique known to those skilled in the art.

[0030]

[0100] The memory device 100 of some embodiments further includes a bit line 170 extending along the third direction 40. The bit line 170 is adjacent to the active regions 115 spaced apart along the third direction 40 (as shown in FIG. 4). The bit line 170 of some embodiments is in direct contact with the active region 115. In some embodiments, the bit line 170 is separated from the active region 115 by a conductive material.

[0031]

[0101] For the sake of uniformity of the relationship between the measured values and the sizes, the length of any given component is measured along the first direction 20 (X-axis direction), the width is measured along the second direction 30 (Y-axis direction), and the height is measured along the third direction 40 (Z-axis direction).

[0032]

[0102] In some embodiments, the length of the active region 115 along the first direction 20 ranges from 50 nm to 300 nm, or from about 75 nm to about 200 nm, or from about 100 nm to about 150 nm, or from about 110 nm to about 130 nm. In some embodiments, the source / drain region 119 is positioned at the end of the active region 115 adjacent to the bit line 170, and the source / drain region 119 is included in the entire length of the active region 115. In some embodiments, the doped layer 117 is positioned at the end of the active region 115 adjacent to the capacitor 180, and the doped layer 117 is included in the entire length of the active region. In some embodiments, both the doped layer 117 and the source / drain region 119 are included in the length of the active region 115.

[0033]

[0103] In some embodiments, the width of the active region 115 along the second direction 30 ranges from 50 nm to 300 nm, or from about 75 nm to about 200 nm, or from about 100 nm to about 150 nm, or from about 110 nm to about 130 nm.

[0034]

[0104] In some embodiments, the length of the capacitor 180 along the first direction 20 ranges from 200 nm to 1500 nm, or from about 300 nm to about 1000 nm, or from about 400 nm to about 750 nm, or from about 450 nm to about 550 nm. In some embodiments, the width of the capacitor 180 along the second direction 30 ranges from 50 nm to 300 nm, or from about 75 nm to about 200 nm, or from about 100 nm to about 150 nm, or from about 110 nm to about 130 nm.

[0035]

[0105] In some embodiments, the length of the conductive layer 120 along the first direction 20 ranges from 50 nm to 200 nm, or from 75 nm to 150 nm, or from 90 nm to 125 nm. In some embodiments, the width of the conductive layer 120 along the second direction 30 ranges from 40 nm to 250 nm, or from 50 nm to 200 nm, or from 75 nm to 150 nm, or from 90 nm to 125 nm.

[0036]

[0106] In some embodiments, the conductive layer 120 is spaced apart from the bit line 170 along the first direction 20. In one or more embodiments, the space between the conductive layer 120 and the bit line 170 along the first direction 20 is in the range of 5 nm to 20 nm, or in the range of 8 nm to 15 nm, or about 10 nm. In some embodiments, the conductive layer 120 is spaced apart from the capacitor 180 along the first direction 20. In one or more embodiments, the space between the conductive layer 120 and the capacitor 180 along the first direction 20 is in the range of 5 nm to 20 nm, or in the range of 8 nm to 15 nm, or about 10 nm.

[0037]

[0107] In some embodiments, the conductive bridge 130 has a length in the range of 5 nm to 180 nm, or in the range of 5 nm to about 180 nm, or in the range of 10 nm to 150 nm, or in the range of 15 nm to 100 nm, or in the range of 20 nm to 80 nm, or in the range of 30 nm to 70 nm, or in the range of 40 nm to 60 nm along the first direction 20. In some embodiments, the conductive bridge 130 has a length shorter than the length of the active region 115. In some embodiments, the conductive bridge 130 has a length shorter than the length of the conductive region 120. In some embodiments, the length of the conductive bridge 130 along the first direction 20 is in the range of 10% to 90% of the length of the conductive layer 120. In some embodiments, the length of the conductive bridge 130 along the first direction 20 is in the range of 20% to 80%, or 30% to 70%, or 40% to 60% of the length of the conductive layer 120.

[0038]

[0108] In some embodiments, the width of the conductive bridge 130 along the second direction 30 is in the range of 50 nm to 200 nm, or in the range of 60 nm to 150 nm, or in the range of 70 nm to 125 nm, or in the range of 90 nm to 110 nm. The width of the conductive bridge 130 in some embodiments is the same as the spacing between the rows of the unit cell 105.

[0039]

[0109] In some embodiments, the bit line 170 has a length in the range of 50 nm to 150 nm, or 60 nm to 130 nm, or 70 nm to 110 nm, or 75 nm to 90 nm along the first direction 20. In some embodiments, the bit line 170 has a width in the range of 50 nm to 150 nm, or 60 nm to 130 nm, or 70 nm to 110 nm, or 75 nm to 90 nm along the second direction 30.

[0040]

[0110] In some embodiments, each layer of the unit cell 105 has a height in the range of 10 nm to 50 nm, or 15 nm to 30 nm, or 20 nm to 25 nm along the third direction 40.

[0041]

[0111] In some embodiments, the memory device 100 includes a plurality of pairs of active regions spaced apart in the first direction 20. FIG. 3 shows an embodiment having a pair of active regions 115 on both sides of the bit line 170 along the first direction 20. In other words, in some embodiments, a plurality of bit lines 170 extend along the third direction 40 between pairs of active regions 115 spaced apart in the first direction 20. As shown in FIG. 3, the bit line 170 and the two active regions 115 (forming a pair of active regions) are aligned along the first direction 20 (X-axis direction).

[0042]

[0112] In this specification, exemplary embodiments are described with reference to cross-sectional views that are schematic diagrams of exemplary embodiments (and intermediate structures). Thus, for example, variations from the shape of the figures as a result of manufacturing techniques and / or tolerances are expected. Thus, exemplary embodiments should not be construed as limited to the specific shapes of the regions shown herein, but may include, for example, variations in the shapes resulting from manufacturing.

[0043]

[0113] As used herein, "substrate" refers to any substrate or the surface of a material formed on a substrate on which film processing is performed during a manufacturing process. For example, the substrate surface on which processing can be performed may include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, etc., depending on the application, as well as any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. The substrate includes, but is not limited to, semiconductor wafers. The substrate may be subjected to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to directly performing film processing on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on an underlying layer formed on the substrate, as will be disclosed in more detail below. The term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. The substrates of some embodiments comprise one or more of an insulator, a metallization layer, or a peripheral circuit. In the illustrated embodiment, for example, the substrate includes an insulator.

[0044]

[0114] Figures 5 through 19 illustrate one or more methods for forming the memory device 100 shown in FIGS. 3 and 4. For ease of explanation, each of FIGS. 6 through 13 is divided into five figures. Each of the numbered figures, and the figures without an attached letter (e.g., FIG. 6), shows a view looking down the third direction 40 (Z-axis) in a plane formed by the first direction 20 (X-axis) and the second direction 30 (Y-axis). Each of the "A" view (e.g., FIG. 6A) and the "B" view (e.g., FIG. 6B) shows an electronic device viewed along the second direction 30 (Y-axis) in a plane formed by the first direction 20 (X-axis) and the third direction 40 (Z-axis). The "A" view is a slice of the device of the corresponding numbered view taken along line A-A. The "B" view is a slice of the device of the corresponding numbered view taken along line B-B. The "C" view (e.g., FIG. 6C) and the "D" view (e.g., FIG. 6D) show an electronic device viewed along the first direction 20 (X-axis) in a plane formed by the second direction 30 (Y-axis) and the third direction 40 (Z-axis). The "C" view is a slice of the device of the corresponding numbered view taken along line C-C. The "D" view is a slice of the device of the corresponding numbered view taken along line D-D. Each of FIGS. 14 through 19 shows a view of an electronic device similar to the "B" views of FIGS. 6 through 13. The cases of FIGS. 14 through 19 show slices of an electronic device viewed along the second direction 30 (Y-axis) in a plane formed by the first direction 20 (X-axis) and the third direction 40 (Z-axis).

[0045]

[0115] FIG. 5 shows a substrate 200 on which a stack 201 of layers is formed. The layers of the stack 201 are generally formed in a plane formed by the first direction (X-axis) and the second direction (Y-axis) and have a thickness along the third direction (Z-axis) (shown from top to bottom of the printed page), and each layer is at a higher height along the third direction 40 (Z-axis) than the layer below it.

[0046]

[0116] The illustrated laminate 201 of layers includes a sacrificial layer 202 having alternating channel layers 204 and insulator layers 206. In the illustrated embodiment, each of the channel layers 204 is sandwiched between the sacrificial layers 202. During the process, the active region 115 is positioned where the channel layer 204 is located, and the sacrificial layer 202 will be replaced by the word line 125 composed of the conductive layer 120 and the bridge 130. If there are sacrificial layers 202 above and below the channel layer 204, there will be word lines 125 above and below the active region 115, as shown in FIG. 3. If the channel layer 204 has a sacrificial layer 202 only below the active region 115, one word line can be formed below the active region 115, as shown in FIG. 4.

[0047]

[0117] FIGS. 6 and 6A-6D show an electronic device after patterning the laminate 201 to form the separator laminate 260 and a pair of pre-bridge laminates 261. The separator laminate 260 extends along a first direction 20 (X-axis), as shown in FIGS. 6, 6B, and 6D. When used in this way, the term "extends along" means that the longer axis of the described component is the described axis or direction. For example, extending along the first direction means that the component has a longer axis in the X direction. In the laminate of membranes, the longer axis is considered for the individual membranes, not for the entire laminate of membranes, which can be much larger than the eight illustrated layers.

[0048]

[0118] The pre-bridge laminate 261 is formed on one or both side surfaces 265 of the separator laminate 260 and extends along a second direction 30 (Y-axis). The pre-bridge laminate 261 generates an opening 263 between the pre-bridge laminates 261 and an opening 264 outside the pre-bridge laminate along the first direction 20 (X-axis). The opening 264 forms a gap along the second direction 30 (Y-axis) between the separator laminate 260 and an adjacent separator laminate.

[0049]

[0119] Patterning can be performed by any suitable technique known to those skilled in the art. For example, in some embodiments, patterning the laminate 201 includes forming a patterned hard mask (not shown) on top of the laminate 201 and then etching (e.g., anisotropically etching) the film laminate 201 through the openings in the patterned hard mask. The top view shown in FIG. 6 shows the device after the etching has left a pattern 262 in the insulating layer 206. The patterned hard masks of some embodiments are the negative of the pattern formed such that the opening regions in the hard mask result in the removal of the film laminate.

[0050]

[0120] A pair of film laminates 261 are separated along a first direction 20 (X-axis), creating an opening 263 between the pair of film laminates 261. In some embodiments, the patterning process creates an opening 264 outside the pair of film laminates 261. Those skilled in the art will recognize that the illustrated process separates the pair of film laminates 261 in the first direction 20 (X-axis). The width of the film laminate 261 along the first direction 20 (X-axis) in some embodiments is substantially the same as the width of the bridge 160. The distance between the pair of film laminates 261, which is the width of the opening 263 along the first direction 20, is the distance between the bridges 160 along the first direction 20.

[0051]

[0121] FIGS. 7 and 7A-7D illustrate an electronic device after removing the channel layer 204 from the pre-bridge laminate 261, recessing the channel layer 204 into the separation membrane laminate 260, and forming a recessed channel layer 270 within the separation membrane laminate 260. The removal process is performed through the openings 263 and 264, leaving an opening 271 where the channel layer 204 was removed. The channel layer 204 can be removed by any suitable technique known to those skilled in the art. In some embodiments, the removal of the channel layer 204 is performed by a dry process or an oxidation process. FIG. 7A shows an etching process removing the channel layer 204 from the pre-bridge stack 261 and forming an opening 271 in the pre-bridge laminate 261. FIGS. 7C and 7D show an etching process removing a portion of the channel layer 204 and forming a recessed channel layer 270 having an opening 271 within the side surface 265 of the separation membrane laminate 260. The side surface 265 of the separation membrane laminate 260 is shown as a dotted line in FIG. 7D. The central portion of the separation membrane laminate 260 shown in FIG. 7B remains unchanged.

[0052]

[0122] The process of recessing the channel layer 204 forms the inner edge of the active region 115, as shown in FIG. 3. When used in this way, the term "inner edge" means the edge of the active region closest to the bit line 170 along the first direction 20. The term "outer edge" means the edge of the active region 115 furthest from the bit line 170 along the first direction. The distance between the inner edge and the outer edge of the active region 115 is the length of the active region 115.

[0053]

[0123] Figures 8 and 8A - 8D illustrate an electronic device after filling the openings 264, 265, 271 with a dielectric material 280. In some embodiments, the dielectric material is an oxide filler. The dielectric material 280 (also referred to as an oxide filler) is deposited through the openings 264, 265 and fills the fill opening 271. In some embodiments, the dielectric material 280 is deposited with an overburden and then planarized so that the dielectric material is substantially coplanar with the top surface of the isolation film stack 260. In one or more embodiments, the oxide filler includes one or more of oxides, carbon - doped oxides, silicon monoxide (SiO), porous silicon dioxide (SiO2), silicon monoxide (SiO), silicon nitride (SiN), silicon oxide / silicon nitride, carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, borosilicate glass, fluorosilicate (SiOF) glass, or organosilicate (SiOCH) glass. The dielectric material 280 may be deposited by any technique known to those skilled in the art, including but not limited to atomic layer deposition or chemical vapor deposition.

[0054]

[0124] Figures 9 and 9A - 9D illustrate an electronic device after forming a trench 290 in the isolation film stack 260. The trench 290 is formed along a second direction 30 (Y - axis) and is disposed between a pair of pre - bridge stacks 261 along a first direction 20. The trench 290 separates the isolation film stack 260 into two isolation film stack sections 260a, 260b. In the following description, unless otherwise specified, the isolation film stack 260 is used to describe both the isolation film stack sections 260a, 260b. Ultimately, bit lines 170 will be formed within the trench 290 to form two unit cells 105. The trench 290 can be formed by any suitable technique known to those skilled in the art. For example, in some embodiments, a patterned mask is applied followed by etching.

[0055]

[0125] The C-C line shown in FIGS. 10 to 13 is different from that in FIGS. 6 to 9. The portion shown in FIGS. 6 to 9 remains unchanged in the process described in FIGS. 10 to 13. FIGS. 10 and 10A to 10D show an electronic device after removing a part of the sacrificial layer 202 from the separation membrane laminate 260. The sacrificial layer 202 is removed through the trench 290 to form the recessed sacrificial layer 300. By recessing the sacrificial layer 202 to form the recessed sacrificial layer 300, at least one surface 301 and end face 303 of the recessed channel layer 270 are exposed. In the illustrated embodiment, the recessed channel layer 270 has two surfaces 301, 302 and an end face 303. When the sacrificial layer 202 is recessed, the surface 305 of the sacrificial layer 202 moves away from the trench 290 in the first direction 20 to form the word line opening 304. The word line opening 304 is bounded by the surface 305 of the recessed sacrificial layer 300, the surfaces 301, 302 of the recessed channel layer 270, and the trench 290. The sacrificial layer 202 can be recessed by any suitable technique known to those skilled in the art.

[0056]

[0126] Figures 11 and 11A - 11D show an electronic device after forming a gate oxide layer 140 within a word - line opening 304. The gate oxide layer 140 is deposited through a trench 290 by any suitable technique known to those skilled in the art. The illustrated embodiment shows the gate oxide layer 140 as a conformal layer having a uniform shape. However, those skilled in the art will recognize that this is for illustrative purposes only, and the gate oxide layer 140 can be formed isotropically such that the gate oxide layer 140 has a rounded appearance. In some embodiments, the gate oxide layer 140 is selectively deposited as a conformal layer on the surface of the recessed channel layer 270. In some embodiments of the gate oxide layer 140, it is formed on the end face 303 of the recessed channel layer 270. In some embodiments, the gate oxide layer 140 formed on the end face 271 is removed by an anisotropic etching process to expose the end face 303, leaving the gate oxide layer 140 on the surfaces 301, 302. In some embodiments, the gate oxide 140 is formed by oxidation of the semiconductor surface.

[0057]

[0127] In one or more embodiments, the gate oxide layer 140 includes a gate oxide material. In one or more embodiments, the gate oxide layer 140 includes one or more of silicon oxynitride (SiON), silicon oxide, or a high - dielectric - constant dielectric material. The term "silicon oxide" may be used to describe the gate oxide layer 140, but those skilled in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, the terms "silicon oxide" and "silicon dioxide" may both be used to describe a material having silicon and oxygen in any suitable stoichiometric ratio. The same can be said for other materials mentioned in the present disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, etc.

[0058]

[0128] Figures 12 and 12A - 12D show an electronic device after depositing an optional liner 325 and a conductive layer 120 within the word - line opening 304. The conductive layer 120 has an outer end 121 and an inner end 122 closer to the trench 290 than the outer end 121. The conductive layer 120 forms a word - line and a bridge 130 within the electronic device on the gate - oxide layer 140. The illustrated embodiment shows the optional liner 325 as a conformal layer having a uniform shape. However, those skilled in the art will recognize that this is for illustrative purposes only and that the optional liner 325 can be formed isotropically. The cross - sectional views of FIGS. 12A and 12D show the bridge 130, and the views of FIGS. 12B and 12C show the conductive layer 120.

[0059]

[0129] In one or more embodiments, the word - line metal 112 includes one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). The conductive layer 120 (word - line metal) is deposited using any one of several methods known to those skilled in the art, including but not limited to chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, the bridge section (shown in FIG. 12D) is filled with the word - line metal.

[0060]

[0130] As used herein, "atomic layer deposition" or "cyclical deposition" refers to the sequential exposure of two or more reactive compounds for depositing a layer of material on a substrate surface. The substrate or a portion of the substrate is individually exposed to two or more reactive compounds introduced into the reaction zone of the processing chamber. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay to allow each compound to adhere to and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, separate portions of the substrate surface or material on the substrate surface are simultaneously exposed to two or more reactive compounds such that no given point on the substrate is substantially simultaneously exposed to more than one reactive compound. As used in this specification and the appended claims, the term "substantially" as so used means that while a small portion of the substrate may potentially be simultaneously exposed (by diffusion) to multiple reactive gases, such simultaneous exposure is not intended, as would be understood by one of ordinary skill in the art.

[0061]

[0131] In one aspect of a time-domain ALD process, after a first reactive gas (i.e., a first precursor or compound A, such as an aluminum precursor) pulses into the reaction zone, it is delayed for a first time. Next, a second precursor or compound B (e.g., an oxidizing agent) pulses into the reaction zone and is then delayed for a second time. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or reaction by-products from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds pulse in alternation until a desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, the purge gas, compound B, and the purge gas is a cycle. The cycle may start with either compound A or compound B and continue through each sequence of that cycle until a film having a predetermined thickness is achieved.

[0062]

[0132] In an embodiment of a spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are supplied to the reaction zone simultaneously but are separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply device. Thereby, any given point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0063]

[0133] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to a precursor and / or a co-reagent simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either flowing simultaneously or having a majority of the exposure of the precursor overlap.

[0064]

[0134] Plasma enhanced chemical vapor deposition (PECVD) is widely known for depositing thin films due to its cost efficiency and versatility of film properties. In the PECVD process, for example, a hydrocarbon source such as vapor of a gas-phase hydrocarbon or a liquid-phase hydrocarbon entrained in a carrier gas is introduced into the PECVD chamber. A plasma initiation gas, usually helium, is also introduced into the chamber. Next, a plasma is initiated in the chamber, generating excited CH radicals. The excited CH radicals chemically bond to the surface of a substrate disposed in the chamber, and a desired film is formed thereon. Embodiments described herein in connection with the PECVD process may be implemented using any suitable thin film deposition system. The description of any apparatus herein is exemplary and should not be understood or construed as limiting the scope of the embodiments described herein.

[0065]

[0135] FIGS. 13 and 13A-13D show an electronic device after filling trench 290 with dielectric 230. In some embodiments, dielectric 230 forms an electrical boundary inside the word line. The dielectric material is deposited using any one of several methods known to those skilled in the art, including but not limited to chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The dielectric material can have the same composition as any of the other insulating materials within the electronic device. In some embodiments, dielectric 230 is the same material as dielectric material 280. In some embodiments, dielectric 230 is etch selective with respect to dielectric material 280. In some embodiments, before filling the trench with dielectric 230, the inner end of recessed channel layer 270 is doped to form source / drain regions 119.

[0066]

[0136] Each of FIGS. 14 to 19 shows a view of an electronic device cut along line B-B of FIG. 13. Each of these figures is a view along the second direction 30 in a slice cut within a plane formed by the first direction 20 and the third direction 40. FIG. 14 shows the electronic device after forming the slit pattern 340 through the recessed sacrificial layer 300 and the recessed channel layer 270 to form the slit pattern 340. The slit pattern 340 is formed on both sides of the position where the trench 290 is filled with the dielectric 230. When used in this way, "both sides" means that one slit is formed on one side of the dielectric 230 in the first direction 20 and the other slit is formed on the other side of the dielectric 230 in the first direction 20. The slit pattern 340 is formed outside the conductive layer 120 formed within the word line opening. When used in this way, the term "outside" means that the slit pattern 340 is formed on the opposite side of the conductive layer 120 as seen from the dielectric 230. In the case of FIG. 14, the dielectric 230 is in the center of the drawing, the conductive layer 120 is on the left and right of the dielectric 230, and the slit pattern 340 is at the left and right edges of the drawing, on both sides of the dielectric 230 and outside the conductive layer 120. The slit pattern 340 exposes the sidewall 346 of the recessed channel layer 270 and the sidewall 342 of the recessed sacrificial layer 300.

[0067]

[0137] FIG. 15 shows an electronic device after a portion of the recess channel layer 270 has been removed through the slit pattern 340 and the sidewall 346 of the recess channel layer 270 has been moved toward the conductive layer 120. This process recesses the recess channel layer 270 from the side of the slit pattern 340. A portion of the recess channel layer 270 can be removed by any suitable technique known to those skilled in the art. By removing a portion of the recess channel layer 270, the active region 115 and the capacitor opening 350 are formed. The active region 115 has an outer end 116 adjacent to the capacitor opening 350 and an inner end 118 adjacent to the dielectric 230. This process is sometimes referred to as a "pull back" process. In one or more embodiments, the channel layer 270 comprises polysilicon and the process shown in FIG. 15 is a polysilicon pull back.

[0068]

[0138] FIG. 16 shows an electronic device after an optional vapor phase doping process. The vapor phase doping process forms a doped layer 117 on the outer edge of the active region 115. In some embodiments, the doping is performed during the deposition of the active region material using a dopant source. For example, phosphorus doped silica glass (PSG) or boron phosphorus doped glass (BPSG) is diffused into the material. In some embodiments, the doped layer 117 is in the range of 1 to 20 nm in thickness (measured from the outer edge of the active region 115 toward the bit line).

[0069]

[0139] FIG. 17 shows an enlarged view of region 17 of FIG. 16 showing the capacitor opening 350. As shown in FIG. 18, in some embodiments, capacitor 180 is formed within capacitor opening 350 adjacent to recessed channel layer 115. In some embodiments, capacitor 180 is first formed by depositing lower electrode 186 within capacitor opening 350. Lower electrode 186, also referred to as a lower electrode or lower contact, can be formed by any suitable technique known to those of skill in the art. In some embodiments, lower electrode 186 is a conformal film deposited by atomic layer deposition. In one or more embodiments, lower electrode 186 comprises a material selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In some embodiments, the capacitor includes a lower electrode, a capacitor dielectric, and an upper electrode. In some embodiments, the capacitor includes a bilayer. For example, a silicon germanium bilayer is added to the upper electrode and titanium nitride.

[0070]

[0140] The high-k dielectric 184 is deposited on the lower electrode 186 within the capacitor opening 350. The high-k dielectric 184 of some embodiments includes hafnium oxide. In some embodiments, the high-k dielectric 184 is deposited as a conformal film by atomic layer deposition. The upper electrode 182 is formed within the capacitor opening 350 within the extent of the high-k dielectric 184. The upper electrode 182, also referred to as the upper contact or upper electrode, can be formed by any suitable technique known to those skilled in the art. In one or more embodiments, the upper electrode 182 comprises a conductive material including one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In some embodiments, the dielectric 188 is deposited to fill any open space remaining within the capacitor opening 350 after the formation of the upper electrode 182. The dielectric 188 of some embodiments separates individual unit cells from adjacent unit cells to prevent shorting.

[0071]

[0141] FIG. 19 shows region 17 of another embodiment of the present disclosure, where capacitor opening 350 is widened before forming the capacitor to form widened capacitor opening 351. Capacitor opening 350 can be widened by any suitable technique known to those skilled in the art. After capacitor opening 350 is widened, capacitor 180 is formed inside as shown in FIG. 20. In some embodiments, the capacitor opening is widened by a ratio of the thickness of the insulating layer (the layer between the active regions). In some embodiments, the capacitor is widened by an amount in the range of 10% to 80% of the thickness of the insulating layer (measured as a combination of upper and lower widening). In some embodiments, the capacitor is widened by an amount in the range of 20% to 75%, or 30% to 60%. In some embodiments, capacitor opening 350 of the capacitor is widened in a second direction 30 (Y-axis) and a third direction 40 (Z-axis). In some embodiments, capacitor opening 350 is widened using dilute HF (about 1% HF in water) wet etching. In some embodiments, widening the capacitor opening results in an increase in capacitor surface area in the range of 1% to 85%, or 5% to 80%, or 10% to 75%, or 20% to 60%.

[0072]

[0142] FIG. 21 shows a partial view of region 21 of FIG. 16. FIG. 22 shows an electronic device after forming bit line holes 360 (also referred to as bit line openings) between the recessed channel layers forming active region 115. In some embodiments, the electronic device is patterned to form a plurality of bit line holes 360. Bit line holes 360 can be formed by any suitable process known to those skilled in the art. In some embodiments, bit line holes 360 are formed by disposing a patterned hard mask and etching dielectric 230 through the hard mask.

[0073]

[0143] In the illustrated embodiment, the source / drain region 119 is formed on the inner end of the active region 115. In some embodiments, the source / drain region 119 is formed by exposing the end face 303 to dopant gas. The source / drain region 119 can be formed by any suitable technique known to those skilled in the art.

[0074]

[0144] FIG. 23 shows a partial view of region 21 of FIG. 16 after depositing bit line 365 in bit line hole 360. In the illustrated embodiment, the bit line 365 includes an optional bit line liner 370 (also referred to as a bit line barrier layer), and bit line metal 375.

[0075]

[0145] The optional bit line liner 370 can be made of any suitable material deposited by any suitable technique known to those skilled in the art. In some embodiments, the bit line liner 370 is conformally deposited in a plurality of bit line holes 360 and deposited on the exposed surface of the dielectric 231 and the end face 303 (or exposed surface) of the active material 115. In the illustrated embodiment, the bit line liner 370 is deposited on the source / drain region 119 at the inner end of the active material 115. The bit line liner 370 can be any suitable material including, but not limited to, titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the optional bit line liner 370 includes or consists essentially of titanium nitride (TiN). When used in this way, the term "consists essentially of" means that the composition of the film is about 95%, 98%, 99%, or 99.5% or more of the stated species. In some embodiments, the optional bit line liner 370 includes or consists essentially of tantalum nitride (TaN). In some embodiments, the bit line liner 370 is a conformal layer. In some embodiments, the bit line liner 370 is deposited by atomic layer deposition.

[0076]

[0146] In some embodiments, bit line metal 375 comprises, or consists essentially of, one or more of tungsten silicide (WSi), tungsten nitride (WN), or tungsten (W). Bit line metal 375 can be deposited by any suitable technique known to those skilled in the art and can be any suitable material. In one or more embodiments, forming bit line metal 375 further includes forming a bit line metal seed layer (not shown) prior to depositing bit line metal 375.

[0077]

[0147] Some embodiments of the present disclosure are directed to electronic devices incorporating an etch stop layer (ESL) for improved process control. FIGS. 24 through 33 show schematic cross-sectional views of an electronic device similar to that shown in FIG. 3. Those skilled in the art will recognize the similarities between the processes described in FIGS. 26 through 33 and the processes described in FIGS. 5 through 23. The view of FIG. 24 is taken by cutting through a plane formed by a first direction 20 (X-axis) and a third direction 40 (Z-axis) at a location along a second direction 30 (Y-axis). FIG. 25 shows an enlarged view of region 25 from FIG. 24.

[0078]

[0148] In the illustrated embodiment, the etch stop layer 410 is adjacent to the outer end 116 of the active region 115. The etch stop layer 410 is adjacent to the lower electrode 186 of the capacitor along the third direction 40 (Z-axis), and is adjacent to the outer end 116 of the active region 115 along the third direction 40 (Z-axis). The etch stop layer 410 in some embodiments is adjacent to the doped layer 117 along the third direction 40 (Z-axis), and is adjacent to the outer end 116 of the active region 115 along the third direction 40 (Z-axis). In some embodiments, the etch stop layer 410 is adjacent to the doped layer 117 and the lower electrode 186 of the capacitor along the third direction 40 (Z-axis). In some embodiments, the etch stop layer 410 is substantially absent from the region between the outer end 116 of the active region 115 (and / or doped region 117) and the capacitor 186 along the first direction 20. When used in this way, the term "substantially absent" means that the etch stop layer 410 occupies less than 25%, 20%, 10%, or 5% of the area between the active region 115 and the lower electrode 186 along the first direction 20 (X-axis).

[0079]

[0149] One or more embodiments of the present disclosure are directed to a method of manufacturing the electronic device of FIG. 24. FIG. 26 shows an embodiment of an electronic device in which the trench 290 is formed through an alternating stack of the sacrificial layer 202 and the replacement channel layer 420. The replacement channel 420 in some embodiments is of the same material as the channel layer 204 shown in FIGS. 5-23. In some embodiments, the replacement channel layer 420 is of a material different from the channel layer 204 shown in FIGS. 5-23. The material of the replacement channel layer 420 does not affect the described process flow.

[0080]

[0150] After forming the trench 290, as shown in FIG. 26, the replacement channel layer 420 is recessed to form a recessed replacement channel layer 420 as shown, and an opening 425 is formed between adjacent sacrificial layers 202 (if there are two) in the third direction 40 (Z-axis). The replacement channel layer is recessed to a depth sufficient to form an active material of a predetermined length in the final electronic device. In the illustrated embodiment, the opening 425 is bounded along the first direction 20 (X-axis) by the recessed replacement channel layer 420 and the inner end 422 of the trench 290, and is bounded above and below along the third direction 40 (Z-axis) by the exposed surface 203 of the sacrificial layer 202.

[0081]

[0151] After forming the opening 425, as shown in FIG. 27, an etching stop layer 410 is formed on the exposed sacrificial surface 203 of the sacrificial layer 202 and the inner end 422 of the recessed replacement channel layer 420. A portion 432 of the etching stop layer 410 is on the surface 203 of the sacrificial layer 202, and the end wall 411 of the etching stop layer 410 is formed on the inner end 422 of the recessed replacement channel layer 420. The opening 425 remains as it is and is bounded by the etching stop layer 410. The size of the opening 425 in some embodiments increases, decreases, or remains the same after forming the etching stop layer 410. The etching stop layer 410 may be any suitable material formed by any suitable process known to those skilled in the art. The etching stop layer 410 in some embodiments is a material that is etching selective with respect to the sacrificial layer 202 and the replacement channel layer 420. In some embodiments, the etching stop layer 410 is a conformal film deposited by atomic layer deposition.

[0082]

[0152] In some embodiments, the opening 425 is widened by any suitable technique known to those skilled in the art before depositing the etching stop layer 410. The size of the opening 425 can be adjusted to provide an active substance 115 having a predetermined dimension.

[0083]

[0153] Figure 28 shows the electronic device of FIG. 27 after depositing the active material 115 within the opening 425 in the etch stop layer 410. The active material 115 forms a pair of channel layers 204 on both sides of the trench 290 along the first direction 20 (X-axis).

[0084]

[0154] Figure 29 shows the electronic device of FIG. 28 after removing a portion of the sacrificial layer 202 to form a recessed sacrificial layer 300 similar to that shown in FIG. 10B.

[0085]

[0155] In some embodiments, the sacrificial layer 202 is recessed to a depth less than the depth to which the replacement channel layer 420 was recessed before forming the etch stop layer 410. In some embodiments, the sacrificial layer 202 is recessed to a depth less than a sufficient depth so that the end wall 411 portion of the etch stop layer 410 on the surface 422 of the recessed replacement channel layer 420 is not exposed. In some embodiments, the surface 305 of the recessed sacrificial layer 300 is within a range of 5 nm to 20 nm closer to the trench 290 than the end wall 411 of the etch stop layer 410 along the first direction 20 (X-axis). In some embodiments, the surface 305 of the recessed sacrificial layer 300 is within a range of 5 nm to 20 nm closer to the trench 290 than the outer end 116 of the active material 115 along the first direction 20 (X-axis).

[0086]

[0156] In some embodiments, as shown in FIG. 29, a portion 432 of the etch stop layer 410 on the surface 203 of the sacrificial layer 202 is removed. In some embodiments, a portion 432 of the etch stop layer 410 is removed simultaneously with recessing the sacrificial layer 202 to form the recessed sacrificial layer 300. In some embodiments, removing a portion 432 of the etch stop layer 410 is performed separately from recessing the sacrificial layer 202, resulting in the formation of the recessed sacrificial layer 300, and subsequently, a portion 432 of the etch stop layer 410 is removed.

[0087]

[0157] FIG. 30 shows the electronic device of FIG. 29 after forming a gate oxide 140 on an active material 115, forming an optional liner 325 in an opening 435 in which a recessed sacrificial layer 300 is formed, and forming a conductive layer 120 in the optional liner 325.

[0088]

[0158] FIG. 31 shows the electronic device of FIG. 30 after filling a trench 290 with a dielectric 230, forming a slit pattern 340, and removing a replacement channel layer 420 through the slit pattern 340 in one or more processes similar to those described with respect to FIGS. 13 - 16. After removing the replacement channel layer 420, a capacitor opening 350 is formed. The inner end 352 (the end farthest from the slit pattern) of the capacitor opening 350 is bounded by an end wall 431 of an etch stop layer 410.

[0089]

[0159] FIG. 32 shows the electronic device of FIG. 31 after removing an end wall 411 of an etch stop layer 410 from the inner end 352 of a capacitor opening 350. By removing the etch stop layer 410, an outer end 116 of the active material 115 is exposed. In some embodiments, portions of the etch stop layer 410 remain above and below (with respect to a third direction 40) the inner end 352 of the capacitor opening 350. In some embodiments, portions of the etch stop layer 410 span an interface between the outer end 116 of the active material 115 and the capacitor opening 350.

[0090]

[0160] FIG. 33 shows the electronic device of FIG. 32 after doping an outer end 116 of an active material 115 through a capacitor opening 350 to form a doped layer 117. The process of some embodiments proceeds as illustrated and described with respect to FIGS. 16 - 23, and as shown in FIG. 24, the etch stop layer 410 remains in the final device. In some embodiments, the capacitor opening 350 is widened as described with respect to FIGS. 19 and 20.

[0091]

[0161] FIG. 34 shows an electronic device 500 according to one or more embodiments of the present disclosure. Device 500 is similar to the device of FIG. 3 with an added etch stop material 410 formed along a third direction 40 (Z-axis). The etch stop material 410 extends through device 500 at a position equivalent to the inner end 352 of the capacitor opening 350. The etch stop material 410 in some embodiments includes a dielectric material to prevent electrical short circuits. The etch stop material 410 passes through the insulator layer 206 and the recessed sacrificial layer 300. In some embodiments, the etch stop material 410 interrupts the continuity of the insulator layer 206 and the recessed sacrificial layer 300 along a first direction 20 (X-axis).

[0092]

[0162] Some embodiments of the present disclosure are directed to a method of forming an electronic device 500. FIGS. 35-39 provide cross-sectional views showing a method according to one or more embodiments. The process of forming device 500 is similar to that shown in FIGS. 5-23, and several points along the process are shown to point out differences.

[0093]

[0163] FIG. 35 shows a film stack similar to that of FIG. 5 having an etch stop layer (ESL) opening 405 formed through the stack along a third direction 40 (Z-axis). The ESL opening 405 is filled with an etch stop material 410. The etch stop material 410 may be any suitable material deposited by any suitable technique known to those skilled in the art. In some embodiments, as shown, the ESL openings 405 are formed on both sides in a first direction 20 (X-axis) at the point where the trenches 290 are formed.

[0094]

[0164] FIG. 36 shows the electronic device of FIG. 35 after a process similar to the processes of FIGS. 9, 9A-9D, 10, and 10A-10D. The trenches 290 in some embodiments are formed along a first direction 20 (X-axis) substantially centered between two ESL openings 405.

[0095]

[0165] Etch the sacrificial layer 202 to form a recessed sacrificial layer 300. In some embodiments, the etching process moves the surface 305 of the recessed sacrificial layer 300 away from the trench 290 by a distance shorter than the distance from the trench 290 to the ESL opening 405. In some embodiments, the etching process moves the surface 305 to the etch stop material 410.

[0096]

[0166] FIG. 37 shows the electronic device of FIG. 36 after a process similar to the process of FIGS. 11-13 (including the sub-drawings of FIGS. 11-13 (A-D)). A conductive layer 120, an optional liner 325, a gate oxide 140, and a dielectric 230 are formed. The illustrated embodiment also includes forming source / drain regions 119 on the inner ends of the active material 115.

[0097]

[0167] FIG. 38 shows the electronic device of FIG. 37 after a process similar to the process of FIGS. 14-16 (including the sub-drawings of FIGS. 14-16 (A-D)). A capacitor opening 350 is formed by slit patterning 340 and an etching process. The sidewalls 346 of the recessed channel layer, which are the inner walls of the capacitor opening 350, are moved to the etch stop material 410 within the ESL opening 405.

[0098]

[0168] FIG. 39 shows the electronic device of FIG. 38 after removing the etch stop material 410 through the capacitor opening 350. The outer ends 116 of the active material 115 are optionally doped to form doped regions 117. The process flow of some embodiments ends with the formation of a capacitor according to a process similar to the process described in FIGS. 17-20 and the formation of bit lines 375 according to a process similar to the process described in FIGS. 21-23.

[0099]

[0169] Spatial relative terms such as "lower", "below", "underside", "upper", "above", "upper side", etc. may be used in this specification to facilitate description of the relationship of one element or feature to another element or feature(s) as shown in the drawings. It should be understood that spatial relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawing is turned over, an element described as "below" or "lower" than another element or feature will be oriented "above" the other element or feature. Thus, the exemplary term "lower" may include both upward and downward orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used in this specification may be interpreted accordingly.

[0100]

[0170] In the context of describing the materials and methods described herein (in particular, in the context of the following claims), the use of the terms "a", "an", and "the" and similar indicators are to be construed as covering both the singular and the plural unless the contrary is indicated herein or is clearly contradicted by the context. The recitation of a range of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein may be performed in any suitable order unless the contrary is indicated herein or is otherwise clearly contradicted by the context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is merely intended to better illustrate the materials and methods and does not limit the scope unless otherwise claimed. Words in the specification should not be construed as indicating any element essential to the practice of the disclosed materials and methods that is not claimed.

[0101]

[0171] Throughout this specification, references to "one embodiment", "certain embodiments", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments", "in certain embodiments", "in one embodiment", or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0102] Although the disclosure of this specification has been described with reference to certain embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the invention. Accordingly, the invention is intended to cover modifications and variations that are within the scope of the appended claims and their equivalents.

Claims

1. A plurality of active regions spaced apart along a first direction, a second direction, and a third direction, A plurality of conductive layers, at least one conductive layer being disposed adjacent to at least one side surface of each of the active regions along the third direction, and A conductive bridge extending along the second direction and connecting each conductive layer to one or more adjacent conductive layers, Each of the plurality of active regions includes a gate oxide layer between the conductive layer and the active region in the third direction, a capacitor on one side surface of the active region in the first direction, a doped layer between the capacitor and the active region in the first direction, and a source / drain region on the other side surface of the active region in the first direction, The capacitor has a first electrode in contact with the doped layer, a high-k dielectric provided inside the first electrode, and a second electrode provided inside the high-k dielectric, The first electrode extends in the first direction so as to cover the high-k dielectric, the high-k dielectric extends in the first direction so as to cover the second electrode, and the second electrode extends in the first direction so as to cover the dielectric, A memory device.

2. The memory device according to claim 1, wherein the capacitor is not in direct contact with the conductive layer or the conductive bridge.

3. The memory device according to claim 1, wherein the active region is part of a transistor.

4. The memory device according to claim 1, wherein at least some of the active regions have one conductive layer adjacent to the active region.

5. The memory device according to claim 1, wherein each of the active regions has conductive layers on both sides of the active region along the third direction.

6. The memory device according to claim 1, further comprising bit lines extending along the third direction and adjacent to the active regions spaced apart along the third direction.

7. A plurality of pairs of active regions spaced apart along a first direction, a second direction, and a third direction, A plurality of bit lines extending along the third direction between pairs of active regions spaced apart in the first direction, A plurality of conductive layers, at least one conductive layer being disposed adjacent to at least one side surface of each of the active regions, wherein the at least one side surface is positioned along the third direction with respect to the active region, including a conductive bridge that extends along the second direction and connects each conductive layer to one or more adjacent conductive layers, each of the active regions is provided with a gate oxide layer between the conductive layer and the active region in the third direction, a capacitor on one side surface of the active region opposite to the bit line in the first direction, a doped layer between the capacitor and the active region in the first direction, and a source / drain region on the other side surface of the active region adjacent to the bit line in the first direction, the capacitor has a first electrode in contact with the doped layer, a high-k dielectric provided inside the first electrode, and a second electrode provided inside the high-k dielectric, the first electrode extends in the first direction so as to cover the high-k dielectric, the high-k dielectric extends in the first direction so as to cover the second electrode, and the second electrode extends in the first direction so as to cover the dielectric, A memory device. **Claim 8** The memory device according to claim 7, wherein the capacitor is not in direct contact with the conductive layer or the conductive bridge. **Claim 9** The memory device according to claim 7, wherein the active region is part of a transistor. **Claim 10** The memory device according to claim 9, wherein the transistor has a length in the range of 50 nm to 300 nm along the first direction, the conductive bridge has a length in the range of 5 nm to 180 nm along the first direction, and the length of the conductive bridge is shorter than the length of the transistor.

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