Non-volatile memory device and method for manufacturing the same

Abstract

To provide a high-performance non-volatile memory element having excellent information retention characteristics capable of mass production, and a manufacturing method thereof.SOLUTION: A non-volatile memory element 1 has a laminated structure part in which Al2O3 layers 4 and SiO2 layers 6 are alternately arranged as two insulating layers, which are formed with different compositions, and at each of these junction interfaces, and O-M1-O layer 5 of 0.5 to 2.0 molecular layers formed by a chemical bond between metal element M1 other than the elements constituting the insulating layer and oxygen is arranged. Information is stored by modulating the interfacial dipole induced in the vicinity of the O-M1-O layer 5 by external electrical stimulation.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a non-volatile memory device having a modulated structure of an interfacial dipole induced between an aluminum oxide and a silicon oxide, and a method for manufacturing the same.

Background Art

[0002] As an information storage device incorporated in information devices such as mobile terminals, the market for semiconductor storage devices using NAND-type flash memories is expanding. The NAND-type flash memory is a device characterized by high integration, large capacity, and non-volatile information storage. Currently, research and development for increasing the capacity and performance mainly by microfabrication and three-dimensional structure technology are underway.

[0003] The microfabrication is approaching the processing limit due to physical limits in the operating principle, and there are many problems with the three-dimensional structure technology. There is a situation where it cannot be expected that the NAND-type flash memory will continue to increase in capacity and performance in the future. In particular, low write endurance and slow read / write speeds are cited as the disadvantages of the NAND-type flash memory.

[0004] To overcome these disadvantages, the present inventor has proposed a first non-volatile memory device that utilizes modulation of an interfacial dipole (see Patent Document 1). According to this proposal, high-performance memory operation exceeding the performance of the NAND flash memory can be expected without significantly changing the MOS structure and constituent materials in the NAND flash memory and the like. However, in the first non-volatile element, since it has a metal oxide layer / semiconductor interface structure and a metal element responsible for the modulation operation of the interfacial dipole is arranged in the vicinity of the surface of the semiconductor, when a transistor structure is applied, there is a risk of deterioration of electrical characteristics due to an increase in the interface level density in the insulating layer / semiconductor structure.

[0005] Therefore, the present inventor has further proposed a second non-volatile memory element obtained by improving the first non-volatile memory element (see Patent Document 2). In the second non-volatile memory element, instead of the modulation operation of the interfacial dipole in the metal oxide layer / semiconductor structure in the first non-volatile memory element, an O-M1-O layer (interfacial dipole modulation layer) is disposed at the interface between two different insulating layers, and by changing the intensity or polarity of the interfacial dipole induced in the vicinity of the O-M1-O layer, the problem associated with the interfacial level density of the first non-volatile memory element is solved. Specifically, an HfO2 layer (the insulating layer) is deposited by an electron beam evaporation method, and then, on this layer, a single molecular layer-level O-M1-O layer is deposited by the electron beam evaporation method, and then, an SiO2 layer (the insulating layer) is deposited by the electron beam evaporation method, and then, it is heated to 450 °C to reduce defects in the HfO2 layer and the SiO2 layer, thereby forming a modulation structure of the interfacial dipole in the second non-volatile memory element (see Examples 1 and 2 of Patent Document 2). Note that the electron beam evaporation method is a film formation method that forms a film with a small area while obtaining a delicate film.

[0006] However, in subsequent research, it has become clear that the second non-volatile memory element with the interfacial dipole modulation structure formed by the HfO2 layer / the O-M1-O layer / the SiO2 layer has the following two problems. First, the retention time of the memory information of the second non-volatile memory element is short, and there is a problem in terms of performance (see Non-Patent Document 1). Second, when manufacturing using the ALD (Atomic Layer Deposition) method capable of film formation on a large area at once, after film formation by the ALD method, when post-annealing is performed at 400 °C or higher, there is a problem that memory characteristics are lost due to low heat resistance (see Non-Patent Document 2). In the manufacturing process using the ALD method, since high-temperature heat treatment after film formation is an essential process for obtaining a target film, low heat resistance means that mass production by a practical manufacturing method is difficult.

Prior Art Documents

Patent Documents

[0007] [Patent Document 1] Japanese Patent No. 6145756 [Patent Document 2] Japanese Patent No. 6472149 [Non-Patent Document]

[0008] [Non-Patent Document 1] N. Miyata, Sci. Rep. 8, 8486 (2018) [Non-Patent Document 2] S. Asanuma, K. Sumita, Y. Miyaguchi, K. Horita, T. Jimbo, K. Saito, and N. Miyata, AIP Adv. 10, 085114 (2020) [Summary of the Invention] [Problems to be Solved by the Invention]

[0009] An object of the present invention is to solve the above-described conventional problems and achieve the following objects. That is, an object of the present invention is to provide a nonvolatile memory element having excellent information retention characteristics, high performance, and practical mass productivity, and a method for manufacturing the same.

[0010] The inventor of the present invention has intensively studied to solve the above problems and obtained the following findings. That is, after repeated trials, the inventor formed a modulation structure of the interfacial dipole by an Al2O3 layer / the O-M1-O layer / the SiO2 layer instead of the modulation structure of the interfacial dipole by the HfO2 layer / the O-M1-O layer / the SiO2 layer. As a result, it was found that the memory characteristics due to the modulation structure of the interfacial dipole were not lost even after high-temperature heat treatment after film formation by the ALD method. Further, when verifying the information retention characteristics of the non-volatile memory element due to the modulation structure of the interfacial dipole by the obtained Al2O3 layer / the O-M1-O layer / the SiO2 layer, surprisingly, it was found that memory information can be retained longer compared to the modulation structure of the interfacial dipole by the HfO2 layer / the O-M1-O layer / the SiO2 layer. In Patent Document 2, Al2O3 is cited as a forming material for one of the two different insulating layers. However, no consideration has been given to making the combination of the forming materials of these two insulating layers the Al2O3 layer / the SiO2 layer, and no consideration has been given to the information retention characteristics and heat resistance when the Al2O3 layer / the SiO2 layer is used. The findings obtained this time will make a great contribution to the practical application of the non-volatile memory element utilizing the modulation of the interfacial dipole.

Means for Solving the Problems

[0011] The present invention is based on the above findings, and the means for solving the problems are as follows. That is, <1> A plurality of first insulating layers and second insulating layers formed of different compositions are alternately arranged, and an O-M1-O layer of 0.5 molecular layer to 2.0 molecular layers formed by a chemical bond of a metal element M1 other than the elements constituting the first insulating layer and the second insulating layer and oxygen is arranged at each bonding interface between the first insulating layer and the second insulating layer. A laminated structure portion, a silicon semiconductor substrate, and a silicon oxide underlying layer laminated on the surface of the silicon semiconductor substrate are arranged. The first insulating layer of the laminated structure portion is laminated on the silicon oxide underlying layer, and the outermost surface of the laminated structure portion has the second insulating layer with the surface on the first insulating layer side laminated on the silicon oxide underlying layer as the bottom surface, and the O-M1-O layer is provided on the outermost surface and A It has a structure in which a metal electrode underlying layer of aluminum oxide and a metal electrode are laminated in this order, and information is stored by modulating an interfacial dipole induced in the vicinity of the O-M1-O layer by an external electrical stimulus. In the non-volatile memory element, the first insulating layer is formed of aluminum oxide, the second insulating layer is formed of silicon oxide, the thickness of the first insulating layer is 2 nm or less, the thickness of the second insulating layer is 2 nm or less, and the O-M1-O layer capable of modulating the interfacial dipole is six or more layers, and the thickness of the aluminum oxide metal electrode underlying layer is 1 nm to 5 nm. A non-volatile memory element characterized by this. <2> The non-volatile memory element according to <1>, wherein the metal element M1 is Ti. <3> The silicon semiconductor substrate has a semiconductor region of a first conductivity type and a source region and a drain region of a second conductivity type that are spaced apart from each other with a part of the surface exposed, and the strength or polarity of an interfacial dipole induced in the vicinity of the O-M1-O layer by an electrical signal applied to the metal electrode is changed. The non-volatile memory element according to any one of <1> to <2>. <4> A method for manufacturing a non-volatile memory element according to any one of <1> to <3>, including a deposition step of depositing and forming a first insulating layer, an O-M1-O layer, a second insulating layer, and an aluminum oxide metal electrode underlying layer by an ALD method, and a post-heat step of heating the laminated structure portion at a temperature of 250 ° C. or higher after the deposition step. A method for manufacturing a non-volatile memory element characterized by this.

Effect of the Invention

[0012] According to the present invention, the above problems in the prior art can be solved, and a nonvolatile memory element having excellent information retention characteristics, high performance, and being practically mass-producible, and a manufacturing method thereof can be provided.

Brief Description of the Drawings

[0013]

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Embodiments for Carrying Out the Invention

[0014] (First Embodiment) FIG. 1 is a cross-sectional structure diagram according to a first embodiment of a nonvolatile memory element according to the present invention. As shown in FIG. 1, the non-volatile memory element 1 according to the first embodiment includes a silicon semiconductor substrate 2, a silicon oxide base layer 3 (hereinafter, SiO2 base layer 3), an aluminum oxide layer 4 as a first insulating layer (hereinafter, Al2O3 layer 4), an O-M1-O layer 5, a silicon oxide layer 6 as a second insulating layer (hereinafter, SiO2 layer 6), an aluminum oxide metal electrode base layer 7 (hereinafter, Al2O3 metal electrode base layer 7), and a metal electrode 8.

[0015] The Al2O3 layer 4 and the SiO2 layer 6 formed with different compositions are arranged alternately in plurality (two by two), and an O-M1-O layer 5 formed by a chemical bond of a metal element M1 other than the elements constituting the Al2O3 layer 4 and the SiO2 layer 6 and oxygen is arranged at their bonding interface. The core of the technology of the non-volatile memory element according to the present invention is that two insulating layers formed with different compositions are composed of an Al2O3 layer 4 and a SiO2 layer 6. With such a configuration, long-term information retention characteristics can be obtained, and excellent heat resistance can be obtained. The excellent heat resistance gives resistance to high-temperature post-annealing performed after deposition by the ALD method, and enables a practical mass production method of the non-volatile memory element using the ALD method.

[0016] The laminated structure portion composed of the Al2O3 layer 4, the O-M1-O layer 5, and the SiO2 layer 6 enables modulation of the interfacial dipole induced in the vicinity of the O-M1-O layer 5 by an external electrical stimulus. The interfacial dipole means the potential difference between the Al2O3 layer 4 and the SiO2 layer 6. Aluminum oxide (Al2O3) with a large dielectric constant causes a small potential fluctuation between an Al atom having a positive charge and an O atom having a negative charge, while silicon oxide (SiO2) with a small dielectric constant causes a large potential fluctuation between a Si atom having a positive charge and an O atom having a negative charge. As a result, the interfacial dipole is induced between the Al2O3 layer 4 and the SiO2 layer 6. At this time, by alternately arranging the Al2O3 layer 4 and the SiO2 layer 6, two O-M1-O layers 5 are formed at two opposing interfaces of Al2O3 / SiO2 and SiO2 / Al2O3 in a form that shares the intermediate SiO2, and the potential difference generated between the upper and lower Al2O3s can be made larger than that in a configuration where one O-M1-O layer 5 is arranged at the Al2O3 / SiO2 interface. The interface dipole can be modulated by changing the positions of O atoms and M1 atoms in the vicinity of the bonding interface by an external electrical stimulus. In the nonvolatile memory element 1, by controlling the external electrical stimulus, a nonvolatile information storage operation utilizing the modulation phenomenon of the interface dipole is performed. The modulation of the interface dipole can be observed as the hysteresis voltage in the capacitance-voltage characteristics when an external electrical stimulus is applied. The larger the hysteresis voltage, the better the information storage characteristics with a larger modulation width can be obtained.

[0017] From the viewpoint of obtaining a large hysteresis voltage, the thickness of the Al2O3 layer 4 is preferably 2 nm or less, and particularly preferably 1 nm or less. Also, from the viewpoint of obtaining a large hysteresis voltage, the thickness of the SiO2 layer 6 is preferably 2 nm or less, and particularly preferably 1 nm or less. There is no particular limitation on the lower limit of the thicknesses of these Al2O3 layer 4 and SiO2 layer 6, and it becomes the thickness of a single molecular layer.

[0018] The thickness of the O-M1-O layer 5 is the thickness of 1 to 2 molecular layers, and is arranged at the bonding interface as 0.5 to 2.0 molecular layers by multiplying the coverage rate (1.0 or less) on the formation surface. Examples of the metal element M1 include one or more elements selected from magnesium, titanium, strontium, yttrium, lanthanum, tantalum, gallium, and antimony. Among them, titanium is preferable. In the example shown in FIG. 1, the number of O-M1-O layers 5 is four. However, the larger the number of O-M1-O layers 5 capable of modulating the interfacial dipole, the easier it is to obtain a large hysteresis voltage. Therefore, six or more layers are preferable, eight or more layers are more preferable, and twelve or more layers are particularly preferable. Note that the upper limit of the number of these layers is about twenty layers from the viewpoints of required performance and ease of manufacturing.

[0019] As a method for forming each constituent layer of the stacked structure portion composed of the Al2O3 layer 4, the O-M1-O layer 5, and the SiO2 layer 6, a forming method including a deposition process by the ALD method and a post-heat treatment for film quality improvement, which is a post-heat process of heating at a temperature of 250°C or higher after the deposition process, is preferable. The deposition process and the post-heat process can be carried out using a known ALD apparatus, heating apparatus, etc. Since the ALD method can form a film over a large area at one time, according to this forming method, the nonvolatile memory element 1 can be practically mass-produced. The heating temperature in the post-heat process is not particularly limited as long as it is at least 250°C. However, from the viewpoint of obtaining a denser structure, 350°C or higher is preferable, and 450°C or higher is particularly preferable. Note that the upper limit of this heating temperature is about 600°C.

[0020] In the example of the nonvolatile memory element 1, a SiO2 underlayer 3 laminated on the surface of the silicon semiconductor substrate 2 is provided. This structure can be formed by thermally oxidizing the surface layer of a known silicon semiconductor substrate, and an insulating layer / semiconductor structure with a low interface state density can be obtained.

[0021] In the example of the nonvolatile memory element 1, with the surface of the Al2O3 layer 4 laminated on the SiO2 underlayer 3 as the bottom surface, the outermost surface of the stacked structure portion is the SiO2 layer 6, and the O-M1-O layer 5, the Al2O3 metal electrode underlayer 7, and the metal electrode 8 are laminated in this order on the outermost surface. At the bonding interface between the SiO2 layer 6 and the Al2O3 metal electrode underlayer 7 on the outermost surface of the stacked structure portion, similar to the bonding interface between the SiO2 layer 6 and the Al2O3 layer 4, by providing the O-M1-O layer 5, the interfacial dipole can be induced in the vicinity of the O-M1-O layer 5 at the bonding interface between SiO2 / Al2O3. In this sense, the structure of the SiO2 layer 6, the O-M1-O layer 5, and the Al2O3 metal electrode underlayer 7 on the outermost surface has a role common to that of the stacked structure portion. In the expression of the number of layers of the O-M1-O layer 5 capable of modulating the interfacial dipole, the O-M1-O layer 5 disposed at the bonding interface between the SiO2 layer 6 and the Al2O3 metal electrode underlayer 7 is also included. However, unlike the Al2O3 layer 4, the Al2O3 metal electrode underlayer 7 serves as an underlayer for the metal electrode 8, and its thickness is set independently of the Al2O3 layer 4. The thickness of the Al2O3 metal electrode underlayer 7 is preferably 1 nm to 5 nm. If the thickness is less than 1 nm, modulation operation may not occur in this layer, and if it exceeds 5 nm, a high voltage may be required to obtain the modulation operation. Note that the Al2O3 metal electrode underlayer 7 can be formed by the same formation method as the Al2O3 layer 4. Also, as the metal electrode 8, known electrode materials such as iridium, gold, aluminum, and titanium nitride can be used as the formation material, and it can be formed by known formation methods such as electron beam evaporation, vacuum evaporation, and sputtering. Also, as the non-volatile memory element according to the present invention, instead of the example of the non-volatile memory element 1, it can also be configured as a modified example having an O-M1-O layer 5 between the SiO2 underlayer 3 and the Al2O3 layer 4 laminated on the SiO2 underlayer 3. The O-M1-O layer 5 between the SiO2 underlayer 3 and the Al2O3 layer 4 according to this modified example can also modulate the interfacial dipole, and while being counted as the number of layers of the O-M1-O layer 5 capable of modulating the interfacial dipole, it is beneficial for obtaining a large hysteresis voltage. In this case, the O-M1-O layer 5 between the SiO2 underlayer 3 and the Al2O3 layer 4 can be formed by the same formation method as the other O-M1-O layers 5.

[0022] In the non-volatile memory element 1 configured as described above, when a voltage is applied to the metal electrode 8, due to the action of the electric field, oxygen atoms and M1 atoms near each of the bonding interfaces slightly move, causing a change in the electrostatic potential distribution. Even if the movement of oxygen atoms and M1 atoms is slight, the interface dipole (potential difference) is sensitive to the positions (charge distributions) of oxygen atoms and M1 atoms, and the change in the electrostatic potential distribution becomes significant. Also, when a reverse voltage is applied to the metal electrode 8, the oxygen atoms and M1 atoms move in the reverse direction, returning to the original electrostatic potential distribution. That is, the non-volatile memory element 1 can control the modulation of the interface dipole (potential difference) by voltage control with respect to the metal electrode 8 and perform a non-volatile information storage operation. Note that the non-volatile memory element 1 has the structure of a MOS (Metal-Oxide-Semiconductor) capacitor. When measuring the capacitance-voltage characteristics (C-V characteristics), when the silicon semiconductor substrate 2 is a p-type semiconductor, clockwise, and when it is an n-type semiconductor, counterclockwise hysteresis characteristics are confirmed. This hysteresis characteristic has a relationship opposite to that of the hysteresis characteristic shown by a general MOS capacitor formed of a metal electrode - insulating film - semiconductor due to carrier capture, which is counterclockwise when it is a p-type semiconductor and clockwise when it is an n-type semiconductor.

[0023] (Second Embodiment) FIG. 2 is a cross-sectional structure diagram according to a second embodiment of the non-volatile memory element according to the present invention. As shown in FIG. 2, the non-volatile memory element 10 according to the second embodiment is configured by disposing the SiO2 underlayer 3, Al2O3 layer 4, O-M1-O layer 5, SiO2 layer 6, Al2O3 metal electrode underlayer 7, and metal electrode 8 in the non-volatile memory element 1 according to the first embodiment on a silicon semiconductor substrate 11 instead of the silicon semiconductor substrate 2. These SiO2 underlayer 3, Al2O3 layer 4, O-M1-O layer 5, SiO2 layer 6, Al2O3 metal electrode underlayer 7, and metal electrode 8 can be formed in the same manner as the non-volatile memory element 1.

[0024] The silicon semiconductor substrate 11 is of p-type (first conductivity type), and an n-type semiconductor region is formed in the substrate. It has a p-type (first conductivity type) semiconductor region and n-type (second conductivity type) source region 12 and drain region 13 that are arranged apart from each other with a part of them exposed from the surface. Note that, different from the illustrated example, the silicon semiconductor substrate 11 may be of n-type, and in this case, p-type source region 12 and drain region 13 are formed. As the silicon semiconductor substrate 11, known p-type and n-type ones can be used. Further, as a method for forming the source region 12 and the drain region 13 on the silicon semiconductor substrate 11, for example, known formation methods such as an ion implantation method can be mentioned.

[0025] The nonvolatile memory element 10 configured as described above has a three-terminal field effect transistor structure of source (S), drain (D), and gate (G). The operating principle of the nonvolatile memory element 10 is substantially the same as that of a flash memory that utilizes a threshold change due to charges trapped in the gate stack structure, except that it utilizes a threshold change based on the modulation of the interface dipole. That is, using the metal electrode 8 as a gate electrode, information is written by changing the intensity or polarity of the interface dipole induced in the vicinity of the O-M1-O layer 5 by an electrical signal applied to the gate electrode to modulate the interface dipole. Also, information is read by utilizing the fact that when a change is given to the threshold value (for example, flat band voltage) of the field effect transistor structure based on the modulation of the given interface dipole, the current value between the source region 12 and the drain region 13 changes. At this time, in the nonvolatile memory element 10, since two insulating layers formed with different compositions are composed of the Al2O3 layer 4 and the SiO2 layer 6, excellent information retention characteristics are exhibited. Further, since the nonvolatile memory element 10 has components that are common as silicon devices and does not require special process technology, it can be easily manufactured using existing manufacturing equipment. In addition, it can be mass-produced practically by a manufacturing method using the ALD method capable of film formation over a large area at one time.

Example

[0026] (Examples 1 to 5) According to the structure of the non-volatile memory element 1 shown in FIG. 1, the non-volatile memory element according to Example 1 was manufactured as follows. However, in the non-volatile memory element according to Example 1, the formation of the Al2O3 layer 4, the O-M1-O layer 5, the SiO2 layer 6, and the repeating unit structure A of the O-M1-O layer 5 was repeated 6 times, and the number of layers of the O-M1-O layer 5 capable of modulating the interfacial dipole was set to 12 layers.

[0027] First, a p-type silicon semiconductor substrate with a thermally oxidized surface layer having a thickness of 5 nm was prepared, and this was used as the silicon semiconductor substrate 2 and the SiO2 underlayer 3. Next, by a formation method using the ALD method with a single-wafer ALD apparatus, on the SiO2 underlayer 3, a repeating unit structure A composed of an Al2O3 layer 4 with a thickness of 1.5 nm, a TiO2 layer (O-M1-O layer 5) with a thickness of 0.14 nm, a SiO2 layer 6 with a thickness of 1.5 nm, and a TiO2 layer (O-M1-O layer 5) with a thickness of 0.14 nm was repeated 6 times to make the O-M1-O layer 5 have 12 layers, and finally an Al2O3 metal electrode underlayer 7 with a thickness of 3.5 nm was formed to form a sample (deposition process). Further, this sample was placed in a horizontal externally heated furnace capable of evacuating, and post-annealing was performed at a heating temperature of 350 °C for 30 minutes in an O2 / Ar (21 vol%) mixed gas atmosphere (post-annealing process). Next, an iridium (Ir) layer with a thickness of 50 nm was deposited on the Al2O3 metal electrode underlayer 7 by a vapor deposition method using a stencil mask to form a metal electrode 8. The deposition of the iridium (Ir) layer was performed using an electron beam vapor deposition apparatus. Thus, the non-volatile memory element according to Example 1 was manufactured.

[0028] Also, except that the heating temperature in the post-annealing process was changed from 350 °C to 250 °C, 300 °C, 400 °C, 450 °C, the non-volatile memory elements according to Examples 2 to 5 were manufactured in the same manner as in Example 1. The non-volatile memory element according to Example 2 was manufactured at a heating temperature of 250°C, Example 3 at a heating temperature of 300°C, Example 4 at a heating temperature of 400°C, and Example 5 at a heating temperature of 450°C.

[0029] (Comparative Examples 1 to 5) By the formation method using the ALD method, a HfO₂ layer with a thickness of 2.0 nm was formed instead of the Al₂O₃ layer 4 with a thickness of 1.5 nm, a SiO₂ layer with a thickness of 2.0 nm was formed instead of the SiO₂ layer 6 with a thickness of 1.5 nm, the formation of the repeating unit structure A was repeated 3 times to make the O-M1-O layer 5 into 6 layers, and a HfO₂ layer with a thickness of 4.0 nm was formed instead of the Al₂O₃ metal electrode underlayer 7 with a thickness of 3.5 nm. Except that the heating temperature in the post-heat treatment process was changed from 350°C to 450°C, and a Au layer with a thickness of 50 nm was formed by a resistance heating evaporation apparatus instead of an Ir layer with a thickness of 50 nm to make the metal electrode 8, a non-volatile memory element according to Comparative Example 1 was manufactured in the same manner as in Example 1.

[0030] Also, except that the heating temperature in the post-heat treatment process was changed from 450°C to 250°C, 300°C, 350°C, and 400°C, non-volatile memory elements according to Comparative Examples 2 to 5 were manufactured in the same manner as in Comparative Example 1. The non-volatile memory element according to Comparative Example 2 was manufactured at a heating temperature of 250°C, Comparative Example 3 at a heating temperature of 300°C, Comparative Example 4 at a heating temperature of 350°C, and Comparative Example 5 at a heating temperature of 400°C.

[0031] <Capacitance-Voltage Characteristic (C-V Characteristic)> For each of the non-volatile memory elements according to Example 1 and Comparative Example 1, a measurement test of the capacitance-voltage characteristic (C-V characteristic) was performed as follows using an E4980A (LCR meter) manufactured by Keysight Technologies. First, a high-frequency C-V measurement at 1 MHz was performed by a method (double sweep) in which a gate voltage that is swept in the negative direction from a positive voltage to a negative voltage is applied to the metal electrode 8, and then a gate voltage that is swept in the positive direction from the negative voltage to the positive voltage is applied again, and the measurement results of the capacitance-voltage characteristics (C-V characteristics) were obtained. In addition, for the gate voltage setting, for the non-volatile memory element according to Example 1, the negative voltage and the positive voltage were set to -11 V and +11 V, respectively. For the non-volatile memory element according to Comparative Example 1, since the total oxide film thickness is thinner than that of the non-volatile memory element according to Example 1, the negative voltage and the positive voltage were set lower at -7 V and +7 V, respectively. According to such a measurement method, the magnitude of the potential change caused by the application of positive and negative gate voltages can be evaluated.

[0032] The measurement results of the capacitance-voltage characteristics (C-V characteristics) of the non-volatile memory element according to Example 1 are shown in FIG. 3. As shown in FIG. 3, in the non-volatile memory element according to Example 1, a clockwise hysteresis characteristic is confirmed. This clockwise hysteresis characteristic means that a change in the MOS threshold voltage (for example, the flat band voltage) due to the interface dipole modulation has occurred. In addition, in the structure of a general MOS capacitor formed of metal-insulator-semiconductor that is not affected by the modulation of the interface dipole, due to the hole injection from the p-type semiconductor, a counterclockwise hysteresis characteristic is obtained.

[0033] Next, the measurement results of the capacitance-voltage characteristics (C-V characteristics) of the non-volatile memory element according to Comparative Example 1 are shown in FIG. 4. As shown in FIG. 4, in the non-volatile memory element according to Comparative Example 1, a counterclockwise hysteresis characteristic is confirmed, and it is also confirmed that the hysteresis voltage is small. From this, it can be concluded that the interface dipole modulation does not occur in the non-volatile memory element according to Comparative Example 1.

[0034] <Information retention characteristics> Next, for each of the non-volatile memory elements according to Example 1 and Comparative Example 4, a measurement test of the information retention characteristics was performed using the same apparatus as the measurement test of the C-V characteristics. Specifically, after applying a gate voltage fixed at either a positive voltage or a negative voltage, the time dependence of the capacitance value was measured near 0V. However, when applying a positive voltage after applying a negative voltage, a low-frequency measurement of 5 kHz was performed under visible light irradiation. This voltage application condition is necessary to generate minority carriers in the silicon semiconductor substrate 2 to form an inversion state and generate a sufficient electric field. Note that Comparative Example 4 relates to a sample that was post-annealed at a heating temperature of 350°C in the same manner as in Example 1.

[0035] The measurement results of the information retention characteristics of the non-volatile memory element according to Example 1 are shown in FIG. 5. As shown in FIG. 5, the non-volatile memory element according to Example 1 has sufficient information retention characteristics even after exceeding 100,000 seconds. Next, the measurement results of the information retention characteristics of the non-volatile memory element according to Comparative Example 4 are shown in FIG. 6. As shown in FIG. 6, the non-volatile memory element according to Comparative Example 4 cannot retain information after exceeding 100,000 seconds. From the above, it is concluded that forming two different insulating layers with Al2O3 / SiO2 can retain information longer than forming them with HfO2 / SiO2.

[0036] <Heat resistance> Next, the heat resistance is evaluated from the hysteresis characteristics - heat treatment temperature characteristics of each of the non-volatile memory elements according to Examples 1 to 5 and Comparative Examples 1 to 5. The hysteresis characteristics - heat treatment temperature characteristics of each of the non-volatile memory elements according to Examples 1 to 5 are shown in FIG. 7, and the hysteresis characteristics - heat treatment temperature characteristics of each of the non-volatile memory elements according to Comparative Examples 1 to 5 are shown in FIG. 8, respectively. Note that the vertical axis in each figure, the hysteresis voltage (V), is the amount of change in the flat band voltage estimated from the C-V characteristic measurement test. A positive value means having a clockwise hysteresis characteristic based on the interface dipole modulation, and a negative value means having a counterclockwise hysteresis characteristic not caused by the interface dipole modulation.

[0037] As shown in FIG. 7, in each of the non-volatile memory elements according to Examples 2 to 5 (post-annealing at 250°C, 300°C, 400°C, 450°C) other than the non-volatile memory element according to Example 1 (post-annealing at 350°C) verified previously, the hysteresis voltage (V) is a positive value, and it has a clockwise hysteresis characteristic based on the interface dipole modulation. In particular, the non-volatile memory element according to Example 5 (post-annealing at 450°C) has a large hysteresis voltage, enabling high-performance memory operation. On the other hand, as shown in FIG. 8, in the non-volatile memory element according to Comparative Example 5 other than the non-volatile memory element according to Comparative Example 1 (post-annealing at 450°C) verified previously, the hysteresis voltage (V) is a negative value, and it is concluded that the interface dipole modulation does not occur. In the post-annealing process, it has been pointed out in Non-Patent Document 2 that when heating after ALD film formation is performed at a temperature of 400°C or higher, the memory characteristics based on the interface dipole modulation are lost, and the same result was obtained in this verification. From the above, it is concluded that forming with Al2O3 / SiO2 is superior in heat resistance than forming with HfO2 / SiO2 for two different insulating layers.

[0038] (Examples 6 to 8 and Reference Example 1 ) Next, the suitable thicknesses of the Al2O3 layer 4 and the SiO2 layer 6 are verified.

[0039] The thickness of the Al2O3 layer 4 was changed from 1.5 nm to 0.5 nm, the thickness of the SiO2 layer 6 was changed from 1.5 nm to 0.5 nm, the formation of the repeating unit structure A was repeated 4 times to make the O-M1-O layer 5 eight layers, the heating temperature in the post-heat treatment was changed from 350 °C to 400 °C, and an aluminum (Al) layer with a thickness of 50 nm was formed by a resistance heating evaporation apparatus instead of an iridium (Ir) layer with a thickness of 50 nm to make the metal electrode 8. Except for this, a non-volatile memory element according to Example 6 was manufactured in the same manner as in Example 1.

[0040] Also, except that the thicknesses of the Al2O3 layer 4 and the SiO2 layer 6 were changed to 1.0 nm, 2.0 nm, and 3.0 nm, respectively, a non-volatile memory element according to Example 7 was manufactured in the same manner as in Example 6. , 8 and Reference Example 1 was manufactured. The one manufactured with a thickness of 1.0 nm is the non-volatile memory element according to Example 7, the one manufactured with a thickness of 2.0 nm is the non-volatile memory element according to Example 8, and the one manufactured with a thickness of 3.0 nm is Reference Example 1 the non-volatile memory element according to.

[0041] The Al2O3 / SiO2 thickness dependence of the hysteresis voltage obtained by taking the hysteresis voltage described for the hysteresis characteristics - heat treatment temperature characteristics on the vertical axis and the thicknesses of the Al2O3 layer 4 and the SiO2 layer 6 on the horizontal axis is shown in FIG. 9. As shown in FIG. 9, all of the non-volatile memory elements according to Examples 6 to 8 and Reference Example 1 have a hysteresis voltage that is a positive value and have a clockwise hysteresis characteristic based on the interface dipole modulation. However, as the thicknesses of the Al2O3 layer 4 and the SiO2 layer 6 increase, a tendency for the hysteresis voltage to decrease is confirmed. When the thickness is 3.0 nm, the hysteresis voltage becomes approximately 0.1 V. Therefore, from the viewpoint of obtaining high-performance memory operation with a large hysteresis voltage, it is concluded that the suitable thicknesses of the Al2O3 layer 4 and the SiO2 layer 6 are 2.0 nm or less.

Explanation of symbols

[0042] 1, 10 Non-volatile memory element 2, 11 Silicon semiconductor substrate 3 SiO2 underlayer 4 Al2O3 layer (first insulating layer) 5 O-M1-O layer 6 SiO2 layer (second insulating layer) 7 Al2O3 Metal electrode underlayer 8 metal electrode 12 source region 13 drain region

Claims

1. A plurality of first insulating layers and second insulating layers formed of different compositions are alternately arranged, and a metal element M other than the elements constituting the first insulating layer and the second insulating layer is present at each bonding interface between the first insulating layer and the second insulating layer １ An O-M １ -O layer having a thickness of 0.5 molecular layer to 2.0 molecular layers formed by a chemical bond with oxygen is disposed, and A silicon semiconductor substrate and a silicon oxide underlayer laminated on the surface of the silicon semiconductor substrate are provided. The first insulating layer of the laminated structure portion is laminated on the silicon oxide underlayer, and the outermost surface of the laminated structure portion has the second insulating layer with the surface on the side of the first insulating layer laminated on the silicon oxide underlayer as the bottom surface. The O-M １ -O layer, an aluminum oxide metal electrode underlayer, and a metal electrode are laminated in this order, and has a structure in which By modulating the interfacial dipole induced near the O-M １ -O layer by an external electrical stimulus, in a non-volatile memory device in which information is stored the first insulating layer is formed of aluminum oxide and the second insulating layer is formed of silicon oxide, the thickness of the first insulating layer is 2 nm or less, the thickness of the second insulating layer is 2 nm or less, The O-M that can modulate the interface dipole １ -O layer is made to be 6 layers or more, the nonvolatile memory element characterized in that the thickness of the aluminum oxide metal electrode base layer is 1 nm to 5 nm.

2. Metal element M １ The non-volatile memory device according to claim 1, wherein １ is Ti.

3. the silicon semiconductor substrate has a semiconductor region of a first conductivity type and a source region and a drain region of a second conductivity type which are arranged apart from each other with a part thereof exposed from the surface, An electrical signal applied to the metal electrode changes the intensity or polarity of the interfacial dipole induced near the O-M １ -O layer. The non-volatile memory element according to any one of claims 1 to 2.

4. A method for manufacturing a nonvolatile memory element according to any one of Claims 1 to 3, The first insulating layer, O-M １ -O layer, a second insulating layer, and an aluminum oxide metal electrode underlayer are deposited and formed by ALD method in a deposition process, a post-heat step of heating the laminated structure portion at a temperature of 250°C or higher after the deposition step, the method for manufacturing a nonvolatile memory element characterized by including the same.

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