Non-volatile memory cell array formed in a P well within a deep N well in a P substrate
JP7701988B2Active Publication Date: 2025-07-02SILICON STORAGE TECHNOLOGY INC
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Patent Information
- Application Number
- JP2023566989
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2021-08-30
- Filing Date
- 2021-09-02
- Publication Date
- 2025-07-02
- Estimated Expiration
- 2041-09-02
Abstract
Numerous embodiments are disclosed of an array of non-volatile memory cells formed in a p-well formed in a deep n-well formed in a p-substrate. During an erase operation, a negative voltage is applied to the p-well to reduce the peak positive voltage that needs to be applied to the cells to erase them.
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