Transient voltage absorbing element

Abstract

A transient voltage absorption element (11) comprises: a semiconductor substrate (Sub); an epitaxial layer (Epi) formed on a surface of the semiconductor substrate (Sub); a p+ region and an n+ region formed in the epitaxial layer (Epi); an embedded layer (BL) formed in the semiconductor substrate (Sub); and a trench (TR). The epitaxial layer (Epi), the p+ region, and the n+ region constitute, and are included in, each of a plurality of diodes. The trench TR extends from the surface of the epitaxial layer (Epi) to the embedded layer (BL) and separates the diodes. The embedded layer (BL) has a higher impurity concentration than the semiconductor substrate (Sub), and is separated between adjacent diodes.

Description

Technical Field

[0001] The present invention relates to a transient voltage absorption element that absorbs transient abnormal voltages caused by ESD (electrostatic discharge) or the like, as well as surges such as lightning surges and switching surges.

Background Art

[0002] Generally, when a transient voltage absorption element is inserted between a transmission line and ground, the high-frequency signal that should originally be transmitted leaks to ground due to the stray capacitance of the transient voltage absorption element. That is, the transmission characteristics of the transmission line deteriorate.

[0003] Patent Document 1 discloses a low-capacity semiconductor device that suppresses an increase in parasitic capacitance due to a surface electrode even when the area of a low-capacity PN diode is reduced to reduce the element capacitance.

[0004] FIG. 11 is a cross-sectional view of a transient voltage absorption element disclosed in Patent Document 1. The transient voltage absorption element shown in FIG. 11 includes a semiconductor substrate 401, a buried layer 402, an epitaxial layer 403, a trench 404, a trench 407, an oxide film 410, a first diffusion layer 405, a second diffusion layer 406, and a surface electrode 414.

[0005] The trench 404 reaches the buried layer 402. The first diffusion layer 405 is formed on the surface of the epitaxial layer 403 opposite to the surface on which the buried layer 402 is formed. The second diffusion layer 406 is formed on the surface of the epitaxial layer 403. The trench 407 is formed so as to surround the second diffusion layer 406. A surface electrode 414 connected to the first diffusion layer 405 and the second diffusion layer 406 is formed on the surface of the epitaxial layer 403.

[0006] A low-capacity PN diode 421 is formed by the epitaxial layer 403 and the buried layer 402, and a Zener diode 420 is formed by the buried layer 402 and the semiconductor substrate 401. Further, a low-capacity PN diode 422 is formed by the epitaxial layer 403 and the second diffusion layer 406.

Prior Art Documents

Patent Document

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] According to the above configuration, by increasing the thickness of the oxide film 410, the parasitic capacitance with the surface electrode 414 as one of the electrodes can be suppressed. However, the impurity concentration of the semiconductor substrate 401 described in Patent Document 1 is on the order of 1×10 20 / cm 3 and is generally a high concentration. Therefore, even if the oxide film 410 is thickened, the parasitic capacitance generated between the semiconductor substrate 401 and the surface electrode 414 etc. cannot be made very small.

[0009] When the impurity concentration of the substrate is reduced to reduce the above parasitic capacitance, since the trench portion will be adjacent to this low-concentration substrate, the polarity of the impurities is inverted by autodoping at the lower part of the trench, and thereby the leakage current increases.

[0010] In order to avoid the increase in the above leakage current, it is effective to form an embedded layer with a high impurity concentration between the substrate and the epitaxial layer. That is, autodoping can be avoided in this way. However, when the embedded layer with a high impurity concentration is formed, the parasitic capacitance increases in the same way as when a substrate with a high impurity concentration is used.

[0011] Thus, reducing the impurity concentration of the substrate for reducing the parasitic capacitance and forming a high-concentration embedded layer for suppressing the leakage current are in a trade-off relationship.

[0012] Therefore, an object of the present invention is to provide a transient voltage absorption element that avoids the above trade-off relationship, suppresses the leakage current, and reduces the parasitic capacitance.

Means for Solving the Problem

[0013] A transient voltage absorbing element as an example of the present disclosure includes a semiconductor substrate, an epitaxial layer formed on the surface of the semiconductor substrate, a first p+ region, a second p+ region, a first n+ region, and a second n+ region formed in the epitaxial layer, a first buried layer and a second buried layer formed in the semiconductor substrate, a first trench and a second trench, and is provided with A first diode is formed including a part of the epitaxial layer, the first p+ region, and the first n+ region surrounded by the first trench, A second diode is formed including a part of the epitaxial layer, the second p+ region, and the second n+ region surrounded by the second trench, The first trench reaches the first buried layer from the surface side of the epitaxial layer, The second trench reaches the second buried layer from the surface side of the epitaxial layer, The first buried layer and the second buried layer have a higher impurity concentration than the semiconductor substrate and are separated between the adjacent first diode and the second diode, which is characterized by.

Effect of the Invention

[0014] According to the present invention, a transient voltage absorbing element with suppressed leakage current and a small parasitic capacitance can be obtained.

Brief Description of the Drawings

[0015]

Figure 1

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Figure 11

DETAILED DESCRIPTION OF THE INVENTION

[0016] FIG. 1 is a cross-sectional view of the transient voltage absorbing element 11 according to the first embodiment. The transient voltage absorbing element 11 is composed of a semiconductor substrate portion and a rewiring portion. The semiconductor substrate portion includes a semiconductor substrate Sub, a buried layer BL, an epitaxial layer Epi, a trench TR, an insulator Ins1, and conductors Cond11, Cond12, Cond13. The semiconductor substrate Sub is, for example, a Si substrate, a GaAs substrate, or the like. As the material of the insulator Ins1, a SiO2 film may be used. As the materials of the conductors Cond11, Cond12, Cond13, for example, Al or Cu may be used.

[0017] The rewiring portion includes insulators Ins2, Ins3, Ins4, Ins5, a conductor Cond2, and a pad Pad.

[0018] The insulator Ins2 is, for example, SiN, and the insulators Ins3, Ins4, Ins5 are organic resins such as epoxy. For the material of the conductor Cond2, for example, Cu may be used. The pad Pad is composed of, for example, a conductor for forming a multi-layer electrode. For example, the pad Pad may include a base layer and a surface layer. Further, an adhesion layer may be further included between the base layer and the surface layer. Ni may be used for the material of the base layer, Ti may be used for the material of the adhesion layer, and Au may be used for the material of the surface layer.

[0019] The epitaxial layer Epi is formed on the surface of the semiconductor substrate Sub. A p+ region and an n+ region are formed on the surface layer of the epitaxial layer Epi. An insulator Ins1 is formed on the surface of the epitaxial layer Epi. Conductors Cond11, Cond12, Cond13 are formed from the surface of the epitaxial layer Epi to the p+ region and the n+ region. Further, a trench TR is formed from the insulator Ins1 to the buried layer BL.

[0020] A conductor Cond2 that conducts to the conductors Cond11, Cond13 is formed in the rewiring portion. A pad Pad is formed on the uppermost conductor Cond2.

[0021] The epitaxial layer Epi, the p+ region, and the n+ region respectively constitute a diode. When the epitaxial layer Epi is an n-type epitaxial layer, a depletion layer is formed at the interface between the epitaxial layer Epi and the p+ region.

[0022] The buried layer BL is buried in the semiconductor substrate Sub. The impurity concentration of the buried layer BL is higher than that of the semiconductor substrate Sub. For example, the impurity concentration of the semiconductor substrate Sub is on the order of 1×10 14 / cm 3 order, and the impurity concentration of the buried layer BL is 1×10 18 / cm 3to 1×10 20 / cm 3 is of the order of.

[0023] The trench TR is frame-shaped with an internal region when viewed from the surface side. The trench TR reaches the buried layer BL from the surface side of the epitaxial layer Epi. The trench TR is disposed inside the outer end of the buried layer BL when viewed from the surface side. That is, the buried layer BL for each trench TR has an inner region and an outer region surrounded by the trench TR.

[0024] And the trench TR is formed so as to surround the diode formation region when viewed from the surface side. A plurality of trenches TR are formed for each diode. The plurality of trenches TR each include a diode formation region in their respective internal regions when viewed from the surface side. Thereby, the plurality of trenches TR separate between a plurality of diodes (a first diode and a second diode).

[0025] As typically shown in region A in FIG. 1, the trench TR is covered with the buried layer BL without contacting the semiconductor substrate Sub. Therefore, as described below, the formation of a leakage current path due to autodoping can be avoided.

[0026] Here, with reference to FIGS. 9(A) and 9(B), the current leakage due to autodoping during the formation of the trench TR will be described. FIG. 9(A) is a cross-sectional view in a state where an epitaxial layer Epi is formed on a semiconductor substrate Sub and holes for trench formation are provided. FIG. 9(B) is a cross-sectional view in a state after the formation of the trench TR, p+ region, and n+ region.

[0027] As shown in FIG. 9(A), when a hole for forming the trench TR is formed by etching and the temperature is raised to form an oxide film on the sidewall inside the hole, due to autodoping from the sidewall of the epitaxial layer Epi, the wall surface (sidewall, bottom) of the hole for forming the trench TR in the p-type semiconductor substrate Sub is inverted to n-type. That is, an n-type region is formed on the wall surface (sidewall, bottom) of the hole for forming the trench TR in the semiconductor substrate Sub.

[0028] Therefore, as shown in FIG. 9(B), a path of n+ region → epitaxial layer Epi → n-type region → epitaxial layer Epi → n-type region → epitaxial layer Epi → n+ region is configured as a leakage current path.

[0029] In contrast, in the present embodiment, as shown in FIG. 1, since the trench TR is covered with the buried layer BL without contacting the semiconductor substrate Sub, formation of the leakage current path due to the autodoping can be avoided.

[0030] Further, in the transient voltage absorbing element 11 of the present embodiment, as shown in FIG. 1, parasitic capacitances are formed between the conductors Cond11, Cond12, Cond13 and the semiconductor substrate Sub, and between the conductor Cond2 and the semiconductor substrate Sub. However, in the region B other than the diode formation region, since there is no buried layer BL, the parasitic capacitance is small. Also, in the region C, the buried layer BL is separated for each diode. Therefore, the frequency characteristics of the parasitic capacitance of the transient voltage absorbing element 11 are improved as compared with the case where the buried layer BL is buried in the entire surface of the semiconductor substrate Sub or is continuously formed in adjacent diode forming portions as in the comparative example shown later. Note that the parasitic capacitance generated in the region D will be described later.

[0031] FIG. 2 is a cross-sectional view showing a gradation layer formed at the interface between the buried layer BL and the semiconductor substrate Sub.

[0032] In order to surely separate the adjacent buried layers BL, it is necessary to form the buried layers BL at a distance greater than a certain value. In the semiconductor substrate Sub with a low impurity concentration, in order to form the buried layer BL with a high impurity concentration, a range (gradation layer) in which the impurity concentration gradually changes due to the difference in impurity concentration is generated. The formation range of the buried layer BL is a range including the gradation layer. If the impurity concentration of the semiconductor substrate Sub is 1×10 14 / cm 3 and the impurity concentration of the buried layer BL is 1×10 18 / cm 3 then the impurity concentration of the gradation layer is 1×1018 / cm 3 from 1×10 14 / cm 3 and continuously changes within the range of.

[0033] The interval G of the buried layer BL for each diode (the interval G shown in FIG. 2) is the interval at which the gradient layers of the buried layer BL are separated. By providing this interval G, the buried layers BL are not substantially continuous. That is, if the impurity concentration at the tip of the buried layer BL is the same as the impurity concentration of the semiconductor substrate Sub, which is 1×10 14 / cm 3 it can be regarded that the adjacent buried layers BL are separated from each other.

[0034] FIG. 3 is a circuit diagram of the transient voltage absorbing element 11. Although only two diodes appear in the cross-section shown in FIG. 1, the transient voltage absorbing element 11 also includes other diodes. The dashed arrows in FIG. 3 indicate the path and direction of the current flowing through the transient voltage absorbing element 11. That is, when a positive potential is applied to the conductor Cond11 in FIG. 3 and a voltage exceeding the forward voltage of each diode is applied, the current flows through the path of [Cond11] → diode D11 → [Cond12] → diode D12 → [Cond13]. Also, when a positive potential is applied to the conductor Cond13 in FIG. 3 and a voltage exceeding the forward voltage of each diode is applied, the current flows through the path of [Cond13] → diode D21 → [Cond12] → diode D22 → [Cond11].

[0035] FIG. 4 is a diagram showing the frequency characteristics of the parasitic capacitance of the transient voltage absorbing element 11. This FIG. 4 also shows the characteristics of the transient voltage absorbing element as a comparative example.

[0036] FIGS. 10(A) and 10(B) are cross-sectional views of the transient voltage absorbing element as the above comparative example. In the transient voltage absorbing element shown in FIG. 10(A), the buried layer BL is formed on the entire surface of the semiconductor substrate Sub. In the transient voltage absorbing element shown in FIG. 10(B), the buried layer BL is continuously formed in adjacent diode forming portions.

[0037] In the transient voltage absorbing element shown in Fig. 10(A), since the buried layer BL with a high impurity concentration is formed on the entire surface of the semiconductor substrate Sub, the parasitic capacitances formed between the conductors Cond11, Cond12, Cond13 and the semiconductor substrate Sub, and between the conductor Cond2 and the semiconductor substrate Sub are large. Also, in the transient voltage absorbing element shown in Fig. 10(B), since the buried layer BL with a high impurity concentration is formed over a wide area on the upper part of the semiconductor substrate Sub, the parasitic capacitances formed between the conductors Cond11, Cond12, Cond13 and the semiconductor substrate Sub, and between the conductor Cond2 and the semiconductor substrate Sub are large.

[0038] In Fig. 4, the characteristic curve E is the characteristic of the transient voltage absorbing element 11 of the present embodiment, the characteristic curve Ca is the characteristic of the transient voltage absorbing element as a comparative example shown in Fig. 10(A), and the characteristic curve Cb is the characteristic of the transient voltage absorbing element as a comparative example shown in Fig. 10(B).

[0039] In Fig. 4, the above-mentioned parasitic capacitance at 10 GHz is as follows.

[0040] E: 0.126 pF Ca: 0.178 pF Cb: 0.136 pF That is, at 10 GHz, which is the operating frequency band, the parasitic capacitance of the transient voltage absorbing element 11 of the present embodiment is smaller than that of the transient voltage absorbing element as a comparative example.

[0041] Thus, since the trench TR that separates adjacent diodes reaches the buried layer BL from the surface side of the epitaxial layer Epi, the leakage current due to autodoping is suppressed. Also, although the buried layer BL with a high impurity concentration is provided, since this buried layer BL is separated for each diode, the resulting parasitic capacitance is small. That is, the trade-off relationship between lowering the impurity concentration of the semiconductor substrate Sub for reducing the parasitic capacitance and forming a high-concentration buried layer BL for suppressing the leakage current is eliminated. As a result, a transient voltage absorbing element that suppresses the leakage current and reduces the parasitic capacitance can be obtained.

[0042] Next, a new effect obtained by separating the embedding layer BL for each diode will be described.

[0043] FIG. 5 is a circuit diagram of the transient voltage absorption circuit 101. This transient voltage absorption circuit 101 includes a first terminal T1, a second terminal T2, a third terminal T3, and a signal line SL existing between the first terminal T1 and the second terminal T2. The third terminal T3 is connected to a reference potential such as ground. Further, a transient voltage absorption element 11 is shunt-connected between the signal line SL and the third terminal T3 (reference potential).

[0044] The transient voltage absorption element 11 is a two-terminal element, and a diode BD as a main part is provided between its terminals. This transient voltage absorption element 11 includes a first path 1 and a second path 2 shunt-connected between the signal line SL and the third terminal T3 (reference potential).

[0045] The first path 1 is mainly a current path through which surge current flows, and the second path 2 is a current path in the mainly used frequency band (signal frequency band) propagating through the signal line SL. The current path indicated by the broken line in FIG. 1 corresponds to the first path 1, and the current path indicated by the dashed-dotted line in FIG. 1 corresponds to the second path 2. When the signal propagating through the signal line SL is a signal in a low frequency band, the signal flows not only through the second path 2 but also through the first path 1. And as the signal frequency becomes higher, the ratio of the signal current flowing through the second path 2 increases. That is, for the signal, the ratio of the current flowing through the first path 1 and the second path 2 changes depending on the frequency band.

[0046] The first path 1 includes a series circuit of a diode BD including a depletion layer capacitance, a first inductor L1, and a first resistance component R1. The diode BD is composed of a plurality of diodes whose forward directions are opposite to each other. Further, the second path 2 includes a series circuit of a capacitor C2, a second inductor L2, and a second resistance component R2.

[0047] The capacitance C2 is the capacitance generated between the conductors Cond11, Cond12, and Cond13 that conduct to the diode BD (the parasitic capacitance generated in the region D in FIG. 1). The first resistance component R1 is the resistance component of the wiring by the conductors Cond11, Cond12, Cond13, and Cond2, the epitaxial layer (depletion layer), and the buried layer BL. The second resistance component R2 is the resistance component of the wiring in the current path in the high-frequency band. In the present embodiment, as shown in FIG. 1, since the buried layer BL is separated for each diode, the resistance value of the first resistance component R1 can be increased as described below.

[0048] As shown in FIG. 9(B), if the buried layer BL is not separated, a current path flowing through the buried layer BL, indicated by a broken line in FIG. 9(B), is formed. Even if this current path itself is long, since the buried layer BL has a low resistance, the total resistance value is low. That is, in this case, there is a region where the current flows in the thickness direction (the vertical direction in the figure) of the epitaxial layer Epi. In this region, since the buried layer BL flows through a wide cross-section and a thin region, the total resistance value is low.

[0049] On the other hand, in the present embodiment, since the buried layer BL is separated and no current path flowing through the buried layer BL is formed, as shown by the broken-line current path in FIG. 1, the resistance value of the first resistance component R1 is determined by the resistance value of the epitaxial layer Epi and the resistance value of the wiring in the direction along the plane direction (horizontal direction) of the semiconductor substrate Sub. Thus, when the current flows in the horizontal direction through the epitaxial layer Epi, the current flows through a high-resistance region for a certain distance, so the resistance value of the first resistance component R1 increases.

[0050] Therefore, by separating the buried layer BL, the first resistance component R1 can be increased. Here, if the capacitance of the diode BD is represented as C1, the capacitance of the capacitance C2 as C2, the resistance value of the first resistance component R1 as R1, and the resistance value of the second resistance component R2 as R2, they are in the relationship of C1 > C2 and R1 > R2. Also, the resonance frequencies of the first path 1 and the second path 2 are different.

[0051] FIG. 6 is a diagram showing the frequency dependence of the impedance due to the stray capacitance (the combined capacitance of the depletion layer capacitance C1 and the capacitance C2 of the diode BD) of the transient voltage absorbing element 11. In FIG. 6, the horizontal axis represents the frequency and the vertical axis represents the impedance. The characteristic curve Z1 in FIG. 6 shows the frequency dependence of the impedance of the first path 1 in FIG. 5, and the characteristic curve Z2 shows the frequency dependence of the impedance of the second path 2 in FIG. 5. The characteristic curve Z1 / / Z2 shows the frequency dependence of the impedance of the transient voltage absorbing element 11. Also, the characteristic curve Z0 shows the frequency characteristics of the impedance of a predetermined capacitance as a comparison target.

[0052] In the example of FIG. 6, the range A indicates a frequency region from 1 GHz to 5.4 GHz, the range B indicates a frequency region from 5.4 GHz to 18 GHz, and the range C indicates a frequency region from 18 GHz to 50 GHz.

[0053] In FIG. 6, the impedance (Z1 / / Z2) of the transient voltage absorbing element 11 is dominated by the impedance Z1 of the first path 1 in the range A (low frequency band), and is dominated by the impedance Z2 of the second path 2 in the range C (high frequency band). The influence of the first resistance component R1 on the impedance Z1 of the first path 1 becomes significant in the high frequency band, and the frequency dependence becomes small.

[0054] As is clear from comparing the characteristic curve (Z1 / / Z2) and the characteristic curve Z0 in FIG. 6, the characteristic curve (Z1 / / Z2) can suppress the decrease in impedance in the high frequency band. That is, on the higher frequency side than the range A in FIG. 6, the decrease in the impedance of the shunt path due to the transient voltage absorbing element 11 is suppressed, and the characteristic deterioration of the transmission line is suppressed.

[0055] According to the present embodiment, in the high frequency band (range C in FIG. 6), the impedance Z2 of the second path 2 is dominant, but the capacitance value of the capacitance C2 becomes small, so that the decrease in the impedance of the transient voltage absorbing element 11 is suppressed. As a result, the amount of signal leakage to the shunt is suppressed. As a result, the deterioration of the insertion loss of the high frequency band signal that is desired to pass through the transmission line can be suppressed.

[0056] FIG. 7 is a diagram showing the frequency characteristics of the insertion loss of a transmission line when the transient voltage absorbing element 11 is provided in the transmission line. FIG. 7 also shows the characteristics of a transient voltage absorbing element as a comparative example. In FIG. 7, the characteristic curve E is the characteristic of the transient voltage absorbing element 11 of the present embodiment, the characteristic curve Ca is the characteristic of the transient voltage absorbing element as a comparative example shown in FIG. 9(A), and the characteristic curve Cb is the characteristic of the transient voltage absorbing element as a comparative example shown in FIG. 9(B).

[0057] In FIG. 7, the insertion loss at 10 GHz is as follows.

[0058] E: -0.612 dB Ca: -0.683 dB Cb: -0.628 dB That is, at 10 GHz which is the operating frequency band, the insertion loss of the transient voltage absorption circuit 101 including the transient voltage absorbing element 11 of the present embodiment is smaller than that of the transient voltage absorbing element as a comparative example.

[0059] Thus, by separating the embedded layer BL for each diode, the insertion loss in the operating frequency band of the transient voltage absorption circuit including the transient voltage absorbing element can be reduced.

[0060] Modification FIG. 8 is a cross-sectional view of a transient voltage absorbing element 12 according to a modification of the present embodiment. The transient voltage absorbing element 12 shown in FIG. 8 is different from the above-described transient voltage absorbing element 11 in the formation pattern of the embedded layer BL. Other configurations of the transient voltage absorbing element 12 are the same as those of the transient voltage absorbing element 11, and the description of the same parts will be omitted.

[0061] The transient voltage absorbing element 12 includes a plurality of embedded layers BL. The embedded layer BL is in a frame shape similar to the trench TR, and has a shape that covers the entire side surface and the entire bottom surface of the trench TR. That is, the embedded layer BL is formed in a shape that covers the trench TR so that the trench TR does not directly contact the semiconductor substrate Sub.

[0062] By adopting such a structure, since the trench TR is surrounded by the buried layer BL, the impedance reduction of the shunt path is suppressed. As a result, the area of the buried layer BL can be reduced, and thus the parasitic capacitance can also be suppressed. Note that the width of the buried layer BL at this time (the distance from the side surface or the bottom surface of the trench TR to the semiconductor substrate Sub) is not limited to that shown in FIG. 8, and the buried layer BL may partially overlap with the p+ region or the n+ region when the transient voltage absorbing element 12 is viewed in plan view (when the transient voltage absorbing element 12 is viewed from the surface side).

[0063] Finally, the present invention is not limited to the above-described embodiments. Those skilled in the art can appropriately modify and change them. The scope of the present invention is defined not by the above-described embodiments but by the claims. Furthermore, the scope of the present invention includes modifications and changes from the embodiments within the scope equivalent to the claims.

[0064] For example, the epitaxial layer Epi may be provided with a well having a higher impurity concentration than this epitaxial layer, and a p+ region and an n+ region may be formed in the well.

[0065] Also, for example, the trench TR is not limited to a shape extending from the surface of the epitaxial layer Epi in the direction of the semiconductor substrate Sub, and may extend from the middle of the insulator Ins1 (SiO2 film) in the direction of the semiconductor substrate Sub.

[0066] The following content is disclosed in this specification.

[0067] <1> A semiconductor substrate, An epitaxial layer formed on the surface of the semiconductor substrate, A first p+ region, a second p+ region, a first n+ region, and a second n+ region formed in the epitaxial layer, A first buried layer and a second buried layer formed in the semiconductor substrate, A first trench and a second trench, Comprising, A first diode is formed including a part of the epitaxial layer, the first p+ region, and the first n+ region surrounded by the first trench, A second diode is formed including a part of the epitaxial layer, the second p+ region, and the second n+ region surrounded by the second trench, The first trench reaches the first buried layer from the surface side of the epitaxial layer, The second trench reaches the second buried layer from the surface side of the epitaxial layer, The first buried layer and the second buried layer have a higher impurity concentration than the semiconductor substrate and are separated between the adjacent first diode and the second diode, Transient voltage absorption element.

[0068] <2> The interval between the first buried layer and the second buried layer is an interval at which the gradient layers generated between the first buried layer and the second buried layer and the semiconductor substrate are separated, The transient voltage absorption element according to <1>.

[0069] <3> The first buried layer is formed in the inner region surrounded by the first trench and is also formed in the outer region of the first trench when viewed from the surface side, The transient voltage absorption element according to <1> or <2>.

[0070] <4> The first buried layer is formed at a portion in contact with the first trench in the inner region surrounded by the first trench, and there is a portion in the inner region where the first buried layer is not formed, The transient voltage absorption element according to <3>.

[0071] <5> The second buried layer is formed in the inner region surrounded by the second trench and is also formed in the outer region of the second trench when viewed from the surface side, The transient voltage absorption element according to any one of <1> to <4>.

[0072] <6> The second buried layer is formed at a portion in contact with the second trench in the inner region surrounded by the second trench, and there is a portion in the inner region where the second buried layer is not formed, The transient voltage absorption element according to <5>.

Explanation of Symbols

[0073] BD…Diode BL…Buried Layer Cond11,Cond12,Cond13,Cond2…Conductor C2…Capacitance D11,D12,D21,D22…Diode Epi…Epitaxial Layer G…Gap Ins1,Ins2,Ins3,Ins4,Ins5…Insulator L1…First Inductor L2…Second Inductor Pad…Pad R1…First Resistance Component R2…Second Resistance Component Sub…Semiconductor Substrate SL…Signal Line T1…The 1st terminal T2…The 2nd terminal T3…The 3rd terminal TR…Trench 1…The 1st path 2…The 2nd path 11…Transient voltage absorption element 101…Transient voltage absorption circuit 401…Semiconductor substrate 402…Embedded layer 403…Epitaxial layer 404…Trench 405…The 1st diffusion layer 406…The 2nd diffusion layer 407…Trench 410…Oxide film 414…Surface electrode 420…Zener diode 421,422…PN diode

Claims

1. A semiconductor substrate, an epitaxial layer formed on the surface of the semiconductor substrate, a first p+ region, a second p+ region, a first n+ region, and a second n+ region formed in the epitaxial layer, a first buried layer and a second buried layer formed in the semiconductor substrate, a first trench and a second trench, and comprising: A first diode is formed including a part of the epitaxial layer, the first p+ region, and the first n+ region surrounded by the first trench, A second diode is formed including a part of the epitaxial layer, the second p+ region, and the second n+ region surrounded by the second trench, The first trench reaches the first buried layer from the surface side of the epitaxial layer, The second trench reaches the second buried layer from the surface side of the epitaxial layer, The first buried layer and the second buried layer have a higher impurity concentration than the semiconductor substrate and are separated between the adjacent first diode and the second diode, A transient voltage absorption element.

2. The distance between the first buried layer and the second buried layer is a distance at which the gradient layers generated between the first buried layer and the second buried layer and the semiconductor substrate are separated from each other, The transient voltage absorption element according to Claim 1.

3. The first buried layer is formed in the inner region surrounded by the first trench and is also formed in the outer region of the first trench when viewed from the surface side, The transient voltage absorption element according to Claim 1 or Claim 2.

4. The first buried layer is formed at a portion in contact with the first trench in the inner region surrounded by the first trench, and there is a portion in the inner region where the first buried layer is not formed, The transient voltage absorption element according to Claim 3.

5. The second buried layer is formed in the inner region surrounded by the second trench and is also formed in the outer region of the second trench when viewed from the surface side, The transient voltage absorption element according to Claim 1.

6. The second buried layer is formed at a portion in contact with the second trench in the inner region surrounded by the second trench, and there is a portion in the inner region where the second buried layer is not formed, The transient voltage absorption element according to Claim 5.

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