Semiconductor device

Abstract

To provide a semiconductor device which can be suppressed in the occurrence of failures caused by latch-up.SOLUTION: A semiconductor device includes first to third electrodes, first to fifth semiconductor regions, a first conductive portion, and a first contact region. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided on a part of the third semiconductor region. The third electrode is opposed to the third semiconductor region via a first insulating film. The first contact region is provided on a part of the third semiconductor region, is arranged side by side with the third electrode in a third direction. The fifth semiconductor region is connected with the first contact region. The fifth semiconductor region includes first and second portions. The first portion is arranged side by side with a boundary portion between the third semiconductor region and the first insulating film in a third direction. The second portion is arranged side by side with the boundary portion in a second direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device.

Background Art

[0002] For example, in a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor), latch-up may occur in which parasitic elements operate. When latch-up occurs, problems such as malfunction may occur.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing problems caused by latch-up.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a third electrode, a first contact region, and a fifth semiconductor region. The first semiconductor region has a first conductivity type provided on the first electrode. The second semiconductor region is provided on the first semiconductor region and has a second conductivity type. The third semiconductor region is provided on the second semiconductor region and has a first conductivity type. The fourth semiconductor region is provided on a part of the third semiconductor region, is electrically connected to the second electrode, and has a second conductivity type. The third electrode extends in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region, and faces the third semiconductor region through a first insulating film in a third direction perpendicular to the first direction and the second direction. The first contact region is provided on a part of the third semiconductor region, is aligned with the first conductive portion in the third direction, has a first conductivity type impurity concentration higher than that of the third semiconductor region, is electrically connected to the second electrode, and has a first conductivity type. The fifth semiconductor region is connected to the first contact region and has a first conductivity type impurity concentration higher than that of the third semiconductor region. The fifth semiconductor region includes a first portion and a second portion. The first portion is aligned in the third direction with a boundary portion between the second semiconductor region and the fourth semiconductor region and the first insulating film. The second portion is aligned in the second direction with the boundary portion.

Brief Description of Drawings

[0006]

Figure 1

Figure 2

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Figure 11

Embodiments for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In the present specification and each figure, the same reference numerals are given to the same elements as those already described, and the detailed description will be omitted as appropriate. Regarding each embodiment described below, each embodiment may be implemented by inverting the p-type (an example of the first conductivity type) and n-type (an example of the second conductivity type) of each semiconductor region.

[0008] FIGS. 1(a) and 1(b) are schematic plan views showing a semiconductor device according to an embodiment. As shown in FIG. 1(a), the semiconductor device 100 includes, for example, an element region R1 and a termination region R2. The outer periphery of the element region R1 is surrounded by the termination region R2. A guard ring or the like may be appropriately provided in the termination region R2. A first electrode 11 (see FIG. 3) is provided on the back surface of the semiconductor device 100, and a second electrode 12 is provided on the surface of the element region R1.

[0009] FIG. 1(b) shows an enlarged view of a part of the layout of the lower layer of the second electrode 12. As shown in FIG. 1(b), in this example, the semiconductor device 100 has a periodic repeating structure.

[0010] In the description of the embodiment, the first direction D1, the second direction D2, and the third direction D3 are used. The direction from the first electrode 11 to the second electrode 12 is defined as the first direction D1. A direction perpendicular to the first direction D1 is defined as the second direction D2. A direction perpendicular to the first direction D1 and perpendicular to the second direction D2 is defined as the third direction D3. Also, for the sake of explanation, the direction from the first electrode 11 to the second electrode 12 is referred to as "up", and the opposite direction is referred to as "down". These directions are based on the relative positional relationship between the first electrode 11 and the second electrode 12 and are independent of the direction of gravity.

[0011] FIG. 2 is a schematic plan view showing a semiconductor device according to an embodiment. FIG. 2 represents, for example, one of the unit structures that are repeated in FIG. 1(b). That is, in the semiconductor device 100, the structure shown in FIG. 2 is periodically arranged in each of the second direction D2 and the third direction D3. In this example, the semiconductor device 100 is an IGBT.

[0012] The semiconductor device 100 has a plurality of trenches (a plurality of first trenches T1 and a plurality of second trenches T2). The first trenches T1 and the second trenches T2 each extend in the second direction D2. The plurality of trenches are arranged in the third direction D3.

[0013] The semiconductor device 100 includes a plurality of insulating films (a plurality of first insulating films 51 and a plurality of second insulating films 52) and a plurality of conductive portions (a plurality of first conductive portions 31 and a plurality of second conductive portions 32) provided in a plurality of trenches. The first insulating film 51 (for example, the first gate insulating film) and the first conductive portion 31 (the third electrode (for example, the first gate electrode)) are provided in the first trench T1 and extend in the second direction D2. The second insulating film 52 (for example, the second gate insulating film) and the second conductive portion 32 (the fourth electrode (for example, the second gate electrode)) are provided in the second trench T2 and extend in the second direction D2. In this example, the second conductive portion 32 is electrically connected to the first conductive portion 31, and the potential of the second conductive portion 32 is the same as the potential of the first conductive portion 31.

[0014] On the first to third semiconductor regions (see FIG. 3) described later, the semiconductor device 100 includes a plurality of fourth semiconductor regions 24 (for example, the first emitter region) shown in FIGS. 1(b) and 2, a fifth semiconductor region 25 (for example, the pillar region), a plurality of sixth semiconductor regions 26 (for example, the second emitter region), and a plurality of contact regions (a plurality of first contact regions 41 and a plurality of second contact regions 42).

[0015] The first contact region 41 and the second contact region 42 are semiconductor regions of the first conductivity type (for example, p-type). The first contact region 41 is located between the first trench T1 and the second trench T2. The first trench T1 is located between the first contact region 41 and the second contact region 42. That is, in the third direction D3, the first trench T1, the first contact region 41, the second trench T2, and the second contact region 42 are repeatedly provided in this order. The first contact region 41 and the second contact region 42 each extend in the second direction D2.

[0016] The fourth semiconductor region 24 and the sixth semiconductor region 26 are each of the second conductivity type (for example, n-type). The fourth semiconductor region 24 is aligned with the sixth semiconductor region 26 in the second direction D2. In this example, the fourth semiconductor region 24 and the sixth semiconductor region 26 each extend in the third direction D3.

[0017] In FIG. 2 (and FIGS. 9 to 11), the range of the fifth semiconductor region 25 is represented by dot hatching. The fifth semiconductor region 25 has a first conductivity type. In this example, the fifth semiconductor region 25 includes a rectangular first portion 251, a rectangular second portion 252, and a connection portion 253 that connects the first portion 251 and the second portion 252.

[0018] For example, the fifth semiconductor regions 25 are periodically arranged in a checkered pattern by the first portion 251 and the second portion 252. As shown in FIG. 1(b), for example, the length W251 of the first portion 251 in the second direction D2 and the length W252 of the second portion 252 in the second direction D2 are each the same as half of the period P2 of the second portion 252 in the second direction D2. Also, as shown in FIG. 1(b), for example, the length L251 of the first portion 251 in the third direction D3 and the length L252 of the second portion 252 in the third direction D3 are each the same as half of the period P3 of the first portion 251 in the third direction D3. And, as shown in FIG. 2, when viewed from above, the corner c1 of the rectangular first portion 251 is connected to the corner c2 of the rectangular second portion 252. For example, the first portion 251 and the second portion 252 are rectangular shapes that share vertices with each other. For example, the position of the vertex of the corner c1 coincides with the position of the vertex of the corner c2.

[0019] When viewed from above, the connection portion 253 is located between a side 251E extending in the second direction D2 of the first portion 251 and a side 252E extending in the third direction D3 of the second portion 252. For example, the connection portion 253 curves to smoothly connect the first portion 251 and the second portion 252. That is, when viewed from above, the outer periphery of the connection portion 253 includes a curve 253E that connects a side 251E of the first portion 251 and a side 252E of the second portion 252.

[0020] Note that the unit structure shown in FIG. 2 may be a substantially rotationally symmetric structure. For example, when the axis extending in the first direction D1 passing through the corner c1 (the vertex of the first portion 251) is used as the rotation axis, the unit structure is symmetric about 180°. Also, in the embodiment, the shapes of the first part 251 and the second part 252 are not limited to the above, and are not necessarily rectangular.

[0021] FIG. 3 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. FIG. 3 shows a cross-section taken along line A-A shown in FIG. 2. In FIG. 3 (and FIGS. 4 to 7), the second electrode 12 and the like are also shown. As shown in FIG. 3, the semiconductor device 100 according to the embodiment further includes a first electrode 11, a first semiconductor region 21, a second semiconductor region 22, a third semiconductor region 23 (for example, a base region), an insulating film 55, and a second electrode 12.

[0022] The first electrode 11 (for example, a collector electrode) is provided on the lower surface of the semiconductor device 100. The first semiconductor region 21 (for example, a collector region) is provided on the first electrode 11 and has a first conductivity type. The first semiconductor region 21 is electrically connected to the first electrode 11.

[0023] The second semiconductor region 22 (for example, a drift region) is provided on the first semiconductor region 21 and has a second conductivity type. In this example, the second semiconductor region 22 is continuous with the first semiconductor region 21.

[0024] The third semiconductor region 23 (for example, a base region) is provided on the second semiconductor region 22 and has a first conductivity type. The impurity concentration of the first conductivity type in the third semiconductor region 23 is lower than the impurity concentration of the first conductivity type in the first semiconductor region 21. The third semiconductor region 23 is continuous with the second semiconductor region 22.

[0025] The fourth semiconductor region 24 is provided on a part of the third semiconductor region 23. The impurity concentration of the second conductivity type in the fourth semiconductor region 24 is higher than the impurity concentration of the first conductivity type in the second semiconductor region 22. A part of the fourth semiconductor region 24 is continuous with the third semiconductor region 23.

[0026] The first trench T1 and the second trench T2 are respectively formed in the second semiconductor region 22, the third semiconductor region 23, and the fourth semiconductor region 24. That is, the first trench T1 and the second trench T2 respectively reach up to the upper part of the second semiconductor region 22 from above.

[0027] The first insulating film 51 is provided on the inner surface (bottom surface and inner wall) of the first trench T1. The first conductive portion 31 is provided inside the first insulating film 51 within the first trench T1. That is, the first insulating film 51 is provided between the second semiconductor region 22 and the first conductive portion 31, between the third semiconductor region and the first conductive portion 31, and between the fourth semiconductor region 24 and the first conductive portion 31. The first conductive portion 31 faces a part of the side surface of the second semiconductor region 22, the side surface of the third semiconductor region 23, and the side surface of the fourth semiconductor region 24 through the first insulating film 51 in the third direction D3.

[0028] Similarly, the second insulating film 52 is provided on the inner surface (bottom surface and inner wall) of the second trench T2. The second conductive portion 32 is provided inside the second insulating film 52 within the second trench T2. That is, the second insulating film 52 is provided between the second semiconductor region 22 and the second conductive portion 32, between the third semiconductor region and the second conductive portion 32, and between the fourth semiconductor region 24 and the second conductive portion 32. The second conductive portion 32 faces a part of the side surface of the second semiconductor region 22, the side surface of the third semiconductor region 23, and the side surface of the fourth semiconductor region 24 through the second insulating film 52 in the third direction D3.

[0029] The first contact region 41 and the second contact region 42 are respectively provided on the third semiconductor region 23. The impurity concentration of the first conductivity type in the first contact region 41 is higher than the impurity concentration of the first conductivity type in the third semiconductor region 23 and higher than the impurity concentration of the first conductivity type in the fifth semiconductor region 25. Similarly, the impurity concentration of the first conductivity type in the second contact region 42 is higher than the impurity concentration of the first conductivity type in the third semiconductor region 23 and higher than the impurity concentration of the first conductivity type in the fifth semiconductor region 25.

[0030] In the cross section shown in FIG. 3, a part of the first contact region 41 is located on the fourth semiconductor region 24 and is continuous with the fourth semiconductor region 24.

[0031] The fifth semiconductor region 25 is formed deeper than the fourth semiconductor region 24 (and the sixth semiconductor region 26). In this example, the fifth semiconductor region 25 is located on the third semiconductor region 23 and is continuous with the third semiconductor region 23. The fifth semiconductor region 25 may be continuous with the second semiconductor region 22. The impurity concentration of the first conductivity type in the fifth semiconductor region 25 is higher than the impurity concentration of the first conductivity type in the third semiconductor region 23.

[0032] The first portion 251 of the fifth semiconductor region 25 is aligned with the boundary portion E1 shown in FIG. 3 in the third direction D3. The boundary portion E1 is the boundary between the third semiconductor region 23 and the first insulating film 51 (the first trench T1) between the second semiconductor region 22 and the fourth semiconductor region 24. The boundary portion E1 corresponds to the region where a channel (inversion layer) is formed, for example, when assuming a MOSFET (metal-oxide-semiconductor field-effect transistor) with the first conductive portion 31 as the gate, the first insulating film 51 as the gate insulating film, the second semiconductor region 22 as the source, and the fourth semiconductor region 24 as the drain. That is, the boundary portion E1 corresponds to the end of the third semiconductor region 23 in contact with the first insulating film 51. The boundary portion E1 is located on each of both side surfaces of the first trench T1 in the third direction D3.

[0033] Also, one end e1 of the first portion 251 in the third direction D3 is located below the first contact region 41, and the other end e2 of the first portion 251 in the third direction D3 is located below the second contact region 42.

[0034] Note that the third semiconductor region 23 and the fourth semiconductor region 24 are each divided in the third direction D3 by the first trench T1 and the second trench T2. The first portion 251 is divided in the third direction D3 by the second trench T2. Thus, the third semiconductor region 23, the fourth semiconductor region 24, and the first portion 251 may each have a plurality of discontinuous portions divided in the third direction D3. More specifically, for example, the first portion 251 has side portions 251a and 251b arranged in the third direction D3. The second insulating film 52 (the second trench T2) is located between the side portion 251a and the side portion 251b and is in contact with the side portion 251a and the side portion 251b.

[0035] The second electrode 12 is provided over the first contact region 41, the second contact region 42, the third semiconductor region 23, and the fourth semiconductor region 24. As shown in FIG. 3, the second electrode 12 is in contact with and electrically connected to the first contact region 41, the second contact region 42, and the fourth semiconductor region 24.

[0036] The insulating film 55 is provided between each of the third semiconductor region 23, the fourth semiconductor region 24, the first conductive portion 31, and the second conductive portion 32 and the second electrode 12. For example, a contact hole 55h penetrating the insulating film 55 is formed in the insulating film 55. The contact hole 55h extends in the second direction D2. Inside the contact hole 55h, the second electrode 12 is in contact with the first contact region 41, the second contact region 42, and the fourth semiconductor region 24.

[0037] FIG. 4 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. FIG. 4 shows a cross-section taken along line B-B shown in FIG. 2. As shown in FIG. 4, the first portion 251 of the fifth semiconductor region 25 is electrically connected to the first contact region 41 and the second contact region 42. The side portion 251a (end portion e1) of the first portion 251 is continuous with the first contact region 41. The side portion 251b (end portion e2) of the first portion 251 is continuous with the second contact region 42.

[0038] Also, a part of the first contact region 41 and a part of the second contact region 42 are each located on the third semiconductor region 23 and are continuous with the third semiconductor region 23.

[0039] FIG. 5 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. FIG. 5 represents a cross-section taken along line C-C shown in FIG. 2. As shown in FIGS. 2 and 5, the second portion 252 of the fifth semiconductor region 25 is aligned with the boundary portion E1 in the second direction D2.

[0040] As shown in FIG. 2, when viewed from above, it is preferable that the distance L1 between the boundary portion E1 and the first portion 251 is equal to the distance L2 between the boundary portion E1 and the second portion 252. The distance L1 is the distance along the third direction D3 from the end Ee1 of the boundary portion E1 in the second direction D2 to the first portion 251. The distance L2 is the distance along the second direction D2 from the end Ee1 to the second portion 252. For example, the distance L1 is preferably 0.9 times or more and 1.1 times or less of the distance L2, and more preferably the same as the distance L2.

[0041] Also, as shown in FIG. 2, when viewed from above, it is preferable that the distance L1 is equal to the distance L3 between the boundary portion E1 and the connection portion 253. The distance L3 is the shortest distance from the end Ee1 of the boundary portion E1 to the curve 253E of the connection portion 253. For example, the distance L1 is preferably 0.9 times or more and 1.1 times or less of the distance L3, and more preferably the same as the distance L3. For example, the curve 253E is provided such that the distance from the end Ee1 of the boundary portion E1 to the nearest connection portion 253 is constant.

[0042] In the present specification, "the same" includes not only being completely identical but also including a range such as manufacturing variations, and it is sufficient if they are substantially the same.

[0043] FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. FIG. 6 represents a cross-section taken along line D-D shown in FIG. 2. In the cross-section shown in FIG. 6, a part of the second contact region 42 is located above the sixth semiconductor region 26 and is continuous with the sixth semiconductor region 26. The second part 252 of the fifth semiconductor region 25 is aligned with the boundary portion E2 shown in FIG. 6 in the third direction D3. The boundary portion E2 is the boundary between the third semiconductor region 23 and the second insulating film 52 (second trench T2) between the second semiconductor region 22 and the sixth semiconductor region 26. The boundary portion E2 corresponds to the region where a channel is formed, for example, when assuming a MOSFET with the second conductive portion 32 as the gate, the second insulating film 52 as the gate insulating film, the second semiconductor region 22 as the source, and the sixth semiconductor region 26 as the drain. That is, the boundary portion E2 corresponds to the end of the third semiconductor region 23 in contact with the second insulating film 52. The boundary portion E2 is located on each of the two side surfaces of the second trench T2 in the third direction D3.

[0044] Also, one end e3 of the second part 252 in the third direction D3 is located below the first contact region 41, and the other end e4 of the second part 252 in the third direction D3 is located below the second contact region 42.

[0045] The second part 252 is divided in the third direction D3 by the first trench T1. Thus, the second part 252 may have a plurality of discontinuous parts divided in the third direction D3. More specifically, for example, the second part 252 has side portions 252a and 252b arranged in the third direction D3. The first insulating film 51 (first trench T1) is located between the side portion 251a and the side portion 251b and is in contact with the side portion 251a and the side portion 251b.

[0046] FIG. 7 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. FIG. 7 represents a cross-sectional view taken along line E-E shown in FIG. 2. As shown in FIG. 7, the second portion 252 of the fifth semiconductor region 25 is electrically connected to the first contact region 41 and the second contact region 42. The side portion 252a (end portion e3) of the second portion 252 is continuous with the first contact region 41. The side portion 252b (end portion e4) of the second portion 252 is continuous with the second contact region 42.

[0047] FIG. 8 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. FIG. 8 represents a cross-sectional view taken along line E-E shown in FIG. 2. As shown in FIGS. 2 and 8, the first portion 251 of the fifth semiconductor region 25 is aligned with the boundary portion E2 in the second direction D2.

[0048] An example of the material of each component of the semiconductor device 100 will be described. The first to sixth semiconductor regions 21 to 26, the first contact region 41, and the second contact region 42 contain, as a semiconductor material, silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. The first conductive portion 31 and the second conductive portion 32 contain a conductive material such as polysilicon. Impurities may be added to the conductive material. The first insulating film 51, the second insulating film 52, and the insulating film 55 contain an insulating material such as silicon oxide or silicon nitride. The first electrode 11 and the second electrode 12 are conductive portions containing a metal such as aluminum or copper.

[0049] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the first electrode 11 with respect to the second electrode 12, a voltage equal to or higher than the threshold value is applied to the first conductive portion 31 and the second conductive portion 32. As a result, a channel is formed in the third semiconductor region 23 (the boundary portion E1 and the boundary portion E2), and the semiconductor device 100 is turned on. When electrons flow through the channel to the second semiconductor region 22, holes are injected from the first semiconductor region 21 into the second semiconductor region 22. Conductivity modulation occurs in the second semiconductor region 22, and the electrical resistance of the semiconductor device 100 decreases significantly. Thereafter, when the voltage applied to the first conductive portion 31 and the second conductive portion 32 becomes lower than the threshold value, the channel in the third semiconductor region 23 disappears, and the semiconductor device 100 becomes off.

[0050] The effects of the embodiment will be described. FIGS. 9(a) and 9(b) are schematic plan views showing semiconductor devices. Similar to FIG. 2, these illustrate a part of the semiconductor device. FIG. 9(a) shows the semiconductor device 190 of the reference example, and FIG. 9(b) shows the semiconductor device 100 according to the embodiment. The semiconductor device 190 of the reference example is different from the semiconductor device 100 in the planar arrangement of the fifth semiconductor region 25. In the semiconductor device 190 of the reference example, the second portion 252 is not provided in the fifth semiconductor region 25. For example, in the semiconductor device 190 of the reference example, the fifth semiconductor region 25 is provided in a stripe shape extending in the second direction D2 instead of a checkerboard pattern.

[0051] Parasitic elements are included in semiconductor devices such as IGBTs. For example, the semiconductor devices 100 and 190 include a bipolar transistor formed by the second semiconductor region 22, the third semiconductor region 23, and the fourth semiconductor region 24. When latch-up occurs in which such a parasitic element is turned on, problems such as malfunction or destruction of the semiconductor device may occur.

[0052] For example, when the potential of the third semiconductor region 23 (the region between the second semiconductor region 22 and the fourth semiconductor region 24) increases, parasitic elements may turn on and latch-up may occur. Therefore, a fifth semiconductor region 25 is provided. The fifth semiconductor region 25 has a higher impurity concentration and a lower resistivity than the third semiconductor region 23. As a result, in the region between the second semiconductor region 22 and the fourth semiconductor region 24, the resistance of the hole current can be reduced. For example, an increase in the potential of the region between the second semiconductor region 22 and the fourth semiconductor region 24 is suppressed. In this way, by providing the fifth semiconductor region 25, the latch-up tolerance can be improved.

[0053] Holes near the boundary portion E1 flow from the third semiconductor region 23 through the fifth semiconductor region 25 to the first contact region 41. Here, in the case of FIG. 9(a), the path of the hole current flowing from the boundary portion E1 to the fifth semiconductor region 25 is, for example, like arrow A1. That is, in the case of FIG. 9(a), the path of the hole current is a one-way path along the third direction D3. On the other hand, in FIG. 9(b), the path of the hole current flowing from the boundary portion E1 to the fifth semiconductor region 25 is, for example, like arrow A2 and arrow A3. Arrow A2 is the path through which holes are drawn into the first portion 251 and is in the direction along the third direction D3. Arrow A3 is the path through which holes are drawn into the second portion 252 and is in the direction along the second direction D2. Thus, according to the embodiment, since the fifth semiconductor region 25 has the first portion 251 and the second portion 252, hole current can be discharged not only in a direction orthogonal to the first conductive portion 31 but also in a parallel direction path. As a result, the resistance of the hole current can be further reduced, and the latch-up tolerance can be further improved.

[0054] Also, in the semiconductor device 100, as described with reference to FIG. 2, the corner c1 of the rectangular first portion 251 is connected to the corner c2 of the rectangular second portion 252. That is, the fifth semiconductor region 25 is arranged so as to surround at least a part of the periphery of the boundary portion E1 (for example, the active FET region) by the first portion 251 and the second portion 252. Thereby, holes are easily discharged in a plurality of directions, and the resistance of the hole current can be further reduced. Therefore, the latch-up tolerance can be further improved.

[0055] Also, as described with reference to FIG. 2, when viewed from above, the distance L1 between the boundary portion E1 and the first portion 251 is, for example, 0.9 times or more and 1.1 times or less of the distance L2 between the boundary portion E1 and the second portion 252. For example, the distance L1 is the same as the distance L2. In this way, when the distance L1 is equivalent to the distance L2, holes near the boundary portion E1 are easily discharged through both the paths in the second direction D2 and the third direction D3. Thereby, the resistance of the hole current can be further reduced.

[0056] Also, in this example, the fifth semiconductor region 25 further includes a connection portion 253 that connects the first portion 251 and the second portion 252. When viewed from above, the outer periphery of the connection portion 253 includes a curve 253E that connects one side 251E of the first portion 251 and one side 252E of the second portion 252. That is, the fifth semiconductor region 25 is arranged so as to surround at least a part of the periphery of the boundary portion E1 by the first portion 251, the second portion 252, and the connection portion 253. Thereby, holes can easily flow into the fifth semiconductor region 25 even through the path represented by the arrow A4 in FIG. 9(b), for example. The arrow A4 is a path through which holes are drawn into the connection portion 253 and extends along a direction between the second direction D2 and the third direction D3. Thereby, holes are easily discharged in a plurality of directions, and the resistance of the hole current can be further reduced.

[0057] Also, as described with reference to FIG. 2, when viewed from above, the distance L1 is, for example, 0.9 times or more and 1.1 times or less of the distance L3 between the boundary portion E1 and the connection portion 253. For example, the distance L1 is the same as the distance L3. In this way, when the distance L1 and the distance L3 are equal, not only in the third direction D3 but also in the direction path between the second direction D2 and the third direction D3, it becomes easier for the discharge to occur. Thereby, the resistance of the hole current can be further reduced.

[0058] For example, as shown in FIG. 1(b), the fourth semiconductor region 24 and the second portion 252 are provided periodically and repeatedly in the second direction D2. Thereby, when a plurality of boundary portions E1 (MOSFETs) are provided along the first conductive portion 31, each boundary portion E1 can be arranged in the second direction D2 with the second portion 252.

[0059] Also, as shown in FIG. 2, the semiconductor device 100 has a second conductive portion 32 and a second insulating film 52, and the first portion 251 of the fifth semiconductor region 25 is provided so as to be in contact with the second insulating film 52. In this case, the first portion 251 is arranged in the second direction D2 with the boundary portion E2 (for example, an active FET region). Thereby, for example, a part of the holes near the boundary portion E2 is drawn out to the first portion 251 through a path in the direction along the second direction D2. That is, also near the boundary portion E2, not only in the third direction D3 but also in the path of the second direction D2, the hole current can be discharged. Thereby, the resistance of the hole current can be further reduced, and the latch-up tolerance can be further improved.

[0060] Also, the first portion 251 has a side portion 251a and a side portion 251b. The second portion 252 has a side portion 252a and a side portion 252b. In this way, the fifth semiconductor region 25 is provided on both sides of the first conductive portion 31 and the second conductive portion 32 in the third direction D3. Thereby, the resistance of the hole current can be further reduced on both sides of the first conductive portion 31 and the second conductive portion 32.

[0061] For example, as shown in FIG. 1(b), the first conductive portion 31, the second conductive portion 32, the first contact region 41, and the first portion 251 are periodically and repeatedly provided in the third direction D3. Thereby, the boundary portions E1 (MOSFETs) adjacent to the respective first conductive portions 31 can be arranged in the third direction D3 with the first portion 251.

[0062] In the semiconductor device 100, the plurality of first conductive portions 31 and the plurality of second conductive portions 32 are connected to each other and have the same potential (gate potential). However, the embodiment is not limited thereto, and a part of the plurality of first conductive portions 31 and the plurality of second conductive portions 32 may have a potential different from the gate potential. For example, a part of the plurality of first conductive portions 31 and the plurality of second conductive portions 32 may be electrically connected to the second electrode 12 and have the same potential as the second electrode 12.

[0063] FIG. 10 is a schematic plan view illustrating another semiconductor device according to the embodiment. The semiconductor device 101 shown in FIG. 10 is different from the semiconductor device 100 in the shape of the fifth semiconductor region 25. In the semiconductor device 101, a connection portion 253 is not provided in the fifth semiconductor region 25. Otherwise, the same description as that of the semiconductor device 100 can be applied to the semiconductor device 101.

[0064] Also in the semiconductor device 101, the fifth semiconductor region 25 has the first portion 251 and the second portion 252. Thereby, similarly to the semiconductor device 100, problems due to latch-up can be suppressed.

[0065] Further, in the embodiment, the first portion 251 and the second portion 252 do not necessarily have to be continuous. That is, the fifth semiconductor region 25 may include a plurality of discrete portions. Even in this case, for example, hole current can be discharged not only in the direction orthogonal to the first conductive portion 31 but also in the parallel direction path. Therefore, the latch-up tolerance can be improved.

[0066] FIG. 11 is a schematic plan view illustrating another semiconductor device according to the embodiment. The semiconductor device 102 shown in FIG. 11 is different from the semiconductor device 100 in the planar shape of the fourth semiconductor region 24 and the sixth semiconductor region 26. In the semiconductor device 102, the fourth semiconductor region 24 and the sixth semiconductor region 26 are not provided at positions overlapping the fifth semiconductor region 25. Otherwise, the same description as that of the semiconductor device 100 can be applied to the semiconductor device 102.

[0067] When the unit structures are arranged periodically, in the semiconductor device 102, unlike the semiconductor device 100, the fourth semiconductor region 24 does not extend in a stripe shape in the third direction D3, but becomes a plurality of discontinuous portions arranged in the third direction D3. Similarly, when the unit structures are arranged periodically, in the semiconductor device 102, unlike the semiconductor device 100, the sixth semiconductor region 26 does not extend in a stripe shape in the third direction D3, but becomes a plurality of discontinuous portions arranged in the third direction D3. The fourth semiconductor region 24 and the sixth semiconductor region 26 do not have to overlap in the second direction D2.

[0068] Also in the semiconductor device 102, the fifth semiconductor region 25 has the first portion 251 and the second portion 252. Thereby, similar to the semiconductor device 100, problems due to latch-up can be suppressed.

[0069] Regarding the relative levels of the impurity concentrations between the semiconductor regions in each of the embodiments described above, for example, it is possible to confirm using SCM (scanning capacitance microscopy). Note that the carrier concentration in each semiconductor region can be regarded as equal to the impurity concentration activated in each semiconductor region. Therefore, the relative levels of the carrier concentrations between the semiconductor regions can also be confirmed using SCM. Also, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (secondary ion mass spectrometry).

[0070] In the present specification, "electrically connected" includes not only the case of being connected by direct contact but also the case of being connected via other conductive members or the like. In this specification, "vertical" and "parallel" include not only strict verticality and strict parallelism, but also, for example, variations in the manufacturing process, etc., and it suffices that they are substantially vertical and substantially parallel.

[0071] As described above, some embodiments of the present invention have been illustrated. However, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof. Also, the above-described embodiments can be implemented in combination with each other.

Explanation of Reference Numerals

[0072] 11 First electrode, 12 Second electrode, 21 - 26 First to sixth semiconductor regions, 31 First conductive portion (third electrode), 32 Second conductive portion (fourth electrode), 41 First contact region, 42 Second contact region, 51 First insulating film, 52 Second insulating film, 55 Insulating film, 55h Contact hole, 100 - 102, 190 Semiconductor device, 251 First portion, 251E, 252E Side, 251a, 251b, 252a, 252b Side portions, 252 Second portion, 253 Connection portion, 253E Curve, R1 Element region, R2 Terminal region, E1, E2 Boundary portions, Ee1 End portion, T1 First trench, T2 Second trench, c1, c2 Corner portions, e1 - e4 End portions

Claims

1. a first electrode, a second electrode, a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of a first conductivity type provided on the second semiconductor region, a fourth semiconductor region of a second conductivity type provided on a part of the third semiconductor region and electrically connected to the second electrode, a third electrode extending in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region and facing the third semiconductor region via a first insulating film in a third direction perpendicular to the first direction and the second direction, a first contact region of a first conductivity type provided on a part of the third semiconductor region, having an impurity concentration of the first conductivity type higher than that of the third semiconductor region, and electrically connected to the second electrode, a fifth semiconductor region of a first conductivity type connected to the first contact region and having an impurity concentration of the first conductivity type higher than that of the third semiconductor region, a first portion including a portion aligned in the third direction with a boundary portion between the third semiconductor region and the first insulating film between the second semiconductor region and the fourth semiconductor region, a second portion including a portion aligned in the second direction with the boundary portion and spaced apart from the boundary portion, a fifth semiconductor region including the first portion and the second portion, a semiconductor device comprising the above.

2. The semiconductor device according to claim 1, wherein the first portion is spaced apart from the boundary portion.

3. When viewed from above, the first portion and the second portion are each rectangular, and a corner of the first portion is connected to a corner of the second portion. The semiconductor device according to claim 1 or 2.

4. When viewed from above, a distance between the boundary portion and the first portion is 0.9 times or more and 1.1 times or less a distance between the boundary portion and the second portion. The semiconductor device according to any one of claims 1 to 3.

5. The fifth semiconductor region includes a connection portion connecting the first portion and the second portion, and when viewed from above, an outer periphery of the connection portion includes a curve connecting one side of the first portion and one side of the second portion. The semiconductor device according to any one of claims 1 to 4.

6. When viewed from above, a distance between the boundary portion and the first portion is 0.9 times or more and 1.1 times or less a distance between the boundary portion and the connection portion. The semiconductor device according to claim 5.

7. The semiconductor device according to any one of claims 1 to 6, wherein the fourth semiconductor region and the second portion are each periodically provided in the second direction in a repeating manner.

8. Further comprising a fourth electrode extending in the second direction and aligned with the third electrode in the third direction, wherein the first contact region is located between the third electrode and the fourth electrode, the fourth electrode faces the third semiconductor region through a second insulating film in the third direction, The semiconductor device according to any one of claims 1 to 7, wherein the first portion is in contact with the second insulating film.

9. The semiconductor device according to claim 8, wherein the third electrode, the fourth electrode, the first contact region, and the first portion are each periodically provided in the third direction in a repeating manner.

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