Memory device using a semiconductor device

Abstract

A substrate has formed thereon a first semiconductor layer 1, a part of which has disposed thereon a first impurity layer 3 extending vertically, and a second semiconductor layer 4 is disposed on top of the first impurity layer. The side walls of the impurity layer and the second semiconductor layer, and the semiconductor layer 1 are covered with a first gate insulating layer 2, which has formed therein a groove in which a first gate conductor layer 22 and a second insulating layer 6 are formed. The second semiconductor layer 4 has disposed thereon: a third semiconductor layer 8 which has, on opposite sides thereof, an n+ layer 7a connected to a source line SL and an n+ layer 7b connected to a bit line BL, respectively; a second gate insulating layer 9 formed so as to cover the third semiconductor layer 8; and a second gate conductor layer 10 connected to a word line WL. The work function of the first gate conductor layer 22 at this case exhibits a numeral value higher than that of the second gate conductor layer 10. By controlling the voltages to be applied to the source line SL, a plate line PL that is connected to the first gate conductor layer 22, the word line WL, and the bit line BL, a data retention operation for retaining, in the vicinity of the gate insulating layers, a hole group generated in a channel region of the third semiconductor layer 8 by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erasing operation for removing the hole group from the n layer 3, the n+ layer 7a, and the n+ layer 7b and removing some holes accumulated in a p layer 4 are carried out. It is characterized in that, during the data retention, the hole density of the second semiconductor layer 4 is higher than the hole density of the third semiconductor layer 8.

Description

Technical Field

[0001] The present invention relates to a memory device using semiconductor elements.

Background Art

[0002] In recent years, in the development of LSI (Large Scale Integration) technology, there has been a demand for higher integration, higher performance, lower power consumption, and higher functionality of memory elements.

[0003] In a normal planar MOS transistor, the channel extends in a horizontal direction along the upper surface of the semiconductor substrate. In contrast, the channel of the SGT extends in a direction perpendicular to the upper surface of the semiconductor substrate (see, for example, Patent Document 1 and Non-Patent Document 1). Therefore, compared with a planar MOS transistor, the SGT enables higher density of semiconductor devices. By using this SGT as a select transistor, high integration can be achieved for a DRAM (Dynamic Random Access Memory, see, for example, Non-Patent Document 2) connected with a capacitor, a PCM (Phase Change Memory, see, for example, Non-Patent Document 3) connected with a resistive change element, an RRAM (Resistive Random Access Memory, see, for example, Non-Patent Document 4), an MRAM (Magneto-resistive Random Access Memory, see, for example, Non-Patent Document 5) that changes the resistance by changing the direction of magnetic spin with current, and the like. Also, there are a DRAM memory cell composed of one MOS transistor without a capacitor (see Non-Patent Document 6), a DRAM memory cell having a groove for storing carriers and two gate electrodes (see Non-Patent Document 8), and the like. However, a DRAM without a capacitor has a problem that the voltage margin cannot be sufficiently ensured because it is greatly affected by the coupling of the gate electrode from the floating body word line. Further, when the substrate is completely depleted, the adverse effect becomes large. The present application relates to a memory device using semiconductor elements that can be composed only of MOS transistors without a resistive change element or a capacitor.

Prior Art Documents

Non-Patent Literature

[0004]

Non-Patent Literature 1

Non-Patent Literature 2

Non-Patent Literature 3

Non-Patent Literature 4

Non-Patent Document 8

Non-Patent Document 9

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a one-transistor type DRAM (gain cell) without a capacitor in a memory device, the capacitive coupling between the word line and the body with a floating element is large. When the potential of the word line is amplitude-modulated during data readout or writing, it is directly transmitted as noise to the body of the semiconductor substrate, which is a problem. As a result, problems such as misreading and incorrect rewriting of stored data are caused, making it difficult to put a one-transistor type DRAM without a capacitor into practical use. And it is necessary to solve the above problems and increase the density of DRAM memory cells.

Means for Solving the Problem

[0006] To solve the above problems, a memory device using the semiconductor device according to the present invention includes a substrate, a first semiconductor layer on the substrate, a first impurity layer at least partially columnar on a surface of a part of the first semiconductor layer, a second semiconductor layer extending vertically in contact with a columnar portion of the first impurity layer, a first insulating layer covering a part of the first semiconductor layer and a part of the first impurity layer, a first gate insulating layer in contact with the first insulating layer and surrounding the first impurity layer and the second semiconductor layer, a first gate conductor layer in contact with the first insulating layer and the first gate insulating layer, a second insulating layer formed to contact the first gate conductor layer and the first gate insulating layer, a third semiconductor layer in contact with the second semiconductor layer, a second gate insulating layer surrounding a part or all of an upper part of the third semiconductor layer, a second gate conductor layer covering a part or all of an upper part of the second gate insulating layer, a second impurity layer and a third impurity layer in contact with a side surface of the third semiconductor layer outside one end of the second gate conductor layer in a horizontal direction in which the third semiconductor layer extends, a first wiring conductor layer connected to the second impurity layer, a second wiring conductor layer connected to the third impurity layer, a third wiring conductor layer connected to the second gate conductor layer, a fourth wiring conductor layer connected to the first gate conductor layer, and Control the voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, and the fourth wiring conductor layer to generate an electron group and a hole group in the third semiconductor layer and the second semiconductor layer by an impact ionization phenomenon or a gate-induced drain leakage current with the current flowing between the second impurity layer and the third impurity layer, perform an operation of removing either the electron group or the hole group, which is a minority carrier in the third semiconductor layer and the second semiconductor layer, among the generated electron group and hole group, and perform an operation of leaving either a part or all of the electron group or the hole group, which is a majority carrier in the third semiconductor layer and the second semiconductor layer, in the third semiconductor layer and the second semiconductor layer, thereby performing a memory write operation. The majority carrier concentration of the second semiconductor layer of the memory cell in the written state is higher than the majority carrier concentration in the third semiconductor layer. Control the voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, and the fourth wiring conductor layer to extract, by recombination with the majority carriers in the first impurity layer, the second impurity layer, and the third impurity layer, either the electron group or the hole group, which is a majority carrier in the remaining second semiconductor layer or third semiconductor layer, from at least one of the first impurity layer, the second impurity layer, and the third impurity layer, thereby performing a memory erase operation. (First Invention).

[0007] In the first invention described above, the first wiring conductor layer connected to the second impurity layer is a source line, the second wiring conductor layer connected to the third impurity layer is a bit line, the third wiring conductor layer connected to the second gate conductor layer is a word line, the fourth wiring conductor layer connected to the first gate conductor layer is a plate line, and voltages are applied to the source line, the bit line, the plate line, and the word line respectively to perform memory writing and erasing (Second Invention).

[0008] In the above-described first invention, it is characterized in that the work functions of the first gate conductor layer and the second gate conductor layer are different (third invention).

[0009] In the above-described third invention, it is characterized in that the majority carriers of the first impurity layer are electrons, the majority carriers of the second semiconductor layer are holes, and the work function of the first gate conductor layer is larger than the work function of the second gate conductor layer (fourth invention).

[0010] In the above-described third invention, it is characterized in that the majority carriers of the first impurity layer are holes, the majority carriers of the second semiconductor layer are holes, and the work function of the first gate conductor layer is smaller than the work function of the second gate conductor layer (fifth invention).

[0011] In the above-described first invention, it is characterized in that the majority carriers of the first impurity layer are different from the majority carriers of the first semiconductor layer (sixth invention).

[0012] In the above-described first invention, it is characterized in that the majority carriers of the second semiconductor layer are the same as the majority carriers of the first semiconductor layer (seventh invention).

[0013] In the above-described first invention, it is characterized in that the majority carriers of the second impurity layer and the third impurity layer are the same as the majority carriers of the first impurity layer (eighth invention).

[0014] In the above-described first invention, it is characterized in that the concentration of the first impurity layer is lower than that of the second impurity layer and the third impurity layer (ninth invention).

[0015] In the above-described first invention, it is characterized in that the vertical distance from the bottom of the third semiconductor layer to the top of the first impurity layer is shorter than the vertical distance from the bottom of the third semiconductor layer to the bottom of the first gate conductor layer (tenth invention).

[0016] In the above-described second invention, a source line contact hole for connecting the source line and the second impurity layer and a first wiring conductor layer are shared with adjacent cells (11th invention).

[0017] In the above-described second invention, a bit line contact hole for connecting the bit line and the third impurity layer and a second wiring conductor layer are shared with adjacent cells (12th invention).

[0018] In the above-described first invention, the first gate conductor layer is separated by a fourth insulating layer in contact with the first gate conductor layer, and is connected to a first plate line and a second plate line respectively, and an independent voltage is applied (13th invention).

[0019] In the above-described 13th invention, there are a plurality of memory cells in contact with the first plate line and a plurality of memory cells in contact with the second plate line, and the same cell does not contact a plurality of plate lines (14th invention).

[0020] In the above-described first invention or second invention, the bottom of the first impurity layer is at a position deeper than the bottom of the first insulating layer, and the first impurity layer is shared by a plurality of cells (15th invention).

[0021] In the above-described 12th invention, it has a fifth wiring conductor layer connected to the first impurity layer, and the fifth wiring conductor layer is a control line and a desired voltage can be applied thereto (16th invention).

Brief Description of Drawings

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Mode for Carrying Out the Invention

[0023] Hereinafter, the structure, driving method, and behavior of accumulated carriers of a memory device using a semiconductor element according to the present invention will be described with reference to the drawings.

[0024] (First Embodiment) With reference to FIGS. 1 to 3, the structure and operation mechanism of a memory cell using the semiconductor device according to the first embodiment of the present invention will be described. With reference to FIG. 1, the cell structure of a memory using the semiconductor device according to this embodiment will be described. With reference to FIG. 2, the writing mechanism of the memory using the semiconductor device and the behavior of carriers will be described, and with reference to FIG. 3, the data erasing mechanism will be described.

[0025] FIG. 1 shows a vertical cross-sectional structure of a memory using a semiconductor device according to the first embodiment of the present invention. There is a p-layer 1 of silicon having a p-type conductivity type containing acceptor impurities on a substrate 20 (an example of the "substrate" in the claims). There is a semiconductor having an n-layer 3 (an example of the "first impurity layer" in the claims) containing columnar donor impurities standing vertically from the surface of the p-layer 1, and further, there is a columnar p-layer 4 (an example of the "second semiconductor layer" in the claims) containing acceptor impurities above it. There is a first insulating layer 2 (an example of the "first insulating layer" in the claims) covering a part of the p-layer 1 and the n-layer 3, and a first gate insulating layer 5 (an example of the "first gate insulating layer" in the claims) covering a part of the p-layer 4. Also, a first gate conductor layer 22 (an example of the "first gate conductor layer" in the claims) is in contact with the first insulating layer 2 and the first gate insulating layer 5. There is a second insulating layer 6 (an example of the "second insulating layer" in the claims) in contact with the gate insulating layer 5 and the gate conductor layer 22. There is a p-layer 8 (an example of the "third semiconductor layer" in the claims) containing acceptor impurities in contact with the p-layer 4.

[0026] There is an n+-layer 7a (an example of the "second impurity layer" in the claims) containing a high concentration of donor impurities on one side of the p-layer 8 (hereinafter, a semiconductor region containing a high concentration of donor impurities is referred to as an "n+-layer"). There is an n+-layer 7b (an example of the "third impurity layer" in the claims) on one side opposite to the n+-layer 7a.

[0027] On the upper surface of the p-layer 8, there is a second gate insulating layer 9 (an example of the "second gate insulating layer" in the claims). This gate insulating layer 9 is in contact with or close to the n+ layers 7a and 7b, respectively. In contact with this gate insulating layer 9, on the opposite side of the semiconductor layer 8, there is a second gate conductor layer 10 (an example of the "second gate conductor layer" in the claims) having a work function lower than that of the first gate conductor layer 22.

[0028] Thus, a memory device using a semiconductor device composed of a substrate 20, a p-layer 1, an insulating layer 2, a gate insulating layer 5, a gate conductor layer 22, an insulating layer 6, an n-layer 3, a p-layer 4, n+ layers 7a, n+ layers 7b, a p-layer 8, a gate insulating layer 9, and a gate conductor layer 10 is formed. The n+ layer 7a is connected to a source line SL (an example of the "source line" in the claims) which is a first wiring conductive layer, the n+ layer 7b is connected to a bit line BL (an example of the "bit line" in the claims) which is a second wiring conductive layer, the gate conductor layer 10 is connected to a word line WL (an example of the "word line" in the claims) which is a third wiring conductive layer, and the gate conductor layer 22 is connected to a plate line PL (an example of the "plate line" in the claims) which is a fourth wiring conductive layer. By operating the potentials of the source line, the bit line, the plate line, and the word line, the memory operates. This memory device is hereinafter referred to as a dynamic flash memory.

[0029] In the memory device of this embodiment, one or a plurality of the above-described dynamic flash memory cells are arranged two-dimensionally on the substrate 20.

[0030] Also, although the p-layer 1 is a p-type semiconductor in FIG. 1, there may be a profile in the impurity concentration. Also, there may be a profile in the impurity concentration of the n-layer 3, the p-layer 4, and the p-layer 8. Also, the p-layer 4 and the p-layer 8 may be independently set with the impurity concentration and the profile.

[0031] Further, when the n+ layer 7a and the n+ layer 7b are formed in a p+ layer in which holes are majority carriers (hereinafter, a semiconductor region containing a high concentration of acceptor impurities is referred to as a "p+ layer"), the p layer 1, the p layer 4, and the p layer 8 are n-type semiconductors, the n layer 3 is a p-type semiconductor, and a material with a work function lower than that of the gate conductor layer 10 is used for the gate conductor layer 22, and the operation of a dynamic flash memory is performed with electrons as the writing carriers.

[0032] Also, in FIG. 1, the first semiconductor layer 1 is a p-type semiconductor. However, even if an n-type semiconductor substrate is used for the substrate 20, a p-well is formed, and this is used as the first semiconductor layer 1, and the memory cell of the present invention is arranged, the operation of the dynamic flash memory is performed.

[0033] Also, in FIG. 1, the insulating layer 2 and the gate insulating layer 5 are shown separately, but they may be formed as one body. Hereinafter, the insulating layer 2 and the gate insulating layer 5 are also collectively referred to as the gate insulating layer 5.

[0034] Also, in FIG. 1, the third semiconductor layer 8 is a p-type semiconductor. However, depending on the majority carrier concentration of the p layer 4, the thickness of the third semiconductor layer 8, the material and thickness of the gate insulating layer 9, and the material of the gate conductor layer 10, the third semiconductor layer 8 can be of any type: p-type, n-type, or i-type.

[0035] Also, in FIG. 1, the bottom of the p layer 8 and the upper surface of the insulating layer 6 are shown to coincide. However, if the p layer 4 and the p layer 8 are in contact and the bottom of the p layer 4 is deeper than the bottom of the insulating layer 6, the interface between the p layer 4 and the p layer 8 does not have to coincide with the upper surface of the insulating layer 6.

[0036] Also, the substrate 20 can be made of any material as long as it can support the p layer 1, whether it is an insulator, a semiconductor, or a conductor.

[0037] Also, since the potential of a part of the memory cell can be changed through the insulating layer 2 or the gate insulating layer 5 for the gate conductor layer 22, and as long as it has a different work function from the gate conductor layer 10, it can be a highly doped semiconductor layer or a conductor layer.

[0038] Further, as long as the wiring conductive layers from the first to the fourth do not contact each other, they may be formed in multiple layers.

[0039] Also, in FIG. 1, the bottom of the n-layer 3 and the bottom of the gate insulating layer 2 are shown to coincide, but the n-layer 3 does not have to coincide as long as it contacts either the p-layer 1 or the gate insulating layer 2.

[0040] Referring to FIG. 2, the carrier behavior, accumulation, and cell current during the write operation of the dynamic flash memory according to the first embodiment of the present invention will be described. First, the majority carriers in the n+ layer 7a and the n+ layer 7b are electrons. For example, p+ poly (hereinafter, poly Si containing a high concentration of acceptor impurities is referred to as "p+ poly") is used for the gate conductor layer 22 connected to the PL. n+ poly (hereinafter, poly Si containing a high concentration of donor impurities is referred to as "n+ poly") is used for the gate conductor layer 10 connected to the WL, and the case where a p-type semiconductor is used as the third semiconductor layer 8 will be described. As shown in FIG. 2(a), the MOSFET in this memory cell operates with the n+ layer 7a serving as the source, the n+ layer 7b serving as the drain, the gate insulating layer 9, the gate conductor layer 10 serving as the gate, and the p-layer 8 serving as the substrate as components. For example, 0V is applied to the p-layer 1, 0V is input to the n+ layer 7a connected to the source line SL, 3V is input to the n+ layer 7b connected to the bit line BL, the gate conductor layer 22 connected to the plate line PL is set to 0V, and for example, 1.5V is input to the gate conductor layer 10 connected to the word line WL. A partial inversion layer 12 is formed directly under the gate insulating layer 9 under the gate conductor layer 10, and a pinch-off point 13 exists. Therefore, the MOSFET having the gate conductor layer 10 operates in the saturation region.

[0041] As a result, the electric field becomes maximum between the pinch-off point 13 and the boundary region of the n+ layer 7b in the MOSFET having the gate conductor layer 10, and the impact ionization phenomenon occurs in this region. Due to this impact ionization phenomenon, electrons accelerated from the n+ layer 7a connected to the source line SL toward the n+ layer 7b connected to the bit line BL collide with the Si lattice, and electron-hole pairs are generated by their kinetic energy. The generated holes diffuse toward the region with a lower hole concentration according to their concentration gradient. Also, part of the generated electrons flows into the gate conductor layer 10, but most of them flow into the n+ layer 7b connected to the bit line BL.

[0042] Note that instead of causing the above impact ionization phenomenon, a gate-induced drain leakage (GIDL) current may be made to flow to generate a hole group (see, for example, Non-Patent Document 7).

[0043] Fig. 2(b) shows hole groups 11 in the p layer 4 and the p layer 8 when all the electrodes WL, BL, PL, and SL have become 0V immediately after writing. The generated hole groups 11 are the majority carriers in the p layer 4 and the p layer 8, but the generated hole concentration temporarily becomes high in the region of the p layer 8 and moves by diffusion toward the p layer 4 according to the concentration gradient. Further, since a p+ poly having a work function higher than that of n+ poly is used for the first gate conductor layer 22, it accumulates in a higher concentration near the first gate insulating layer 5 of the p layer 4. As a result, the hole concentration in the p layer 4 becomes higher than the hole concentration in the p layer 8. Since the p layer 4 and the p layer 8 are electrically connected, the p layer 8, which is substantially the substrate of the MOSFET having the gate conductor layer 10, is charged to a positive bias. Also, although the holes in the depletion layer move toward the SL side, the BL side, or the n layer 3 and gradually recombine with electrons, the threshold voltage of the MOSFET having the gate conductor layer 10 becomes lower due to the positive substrate bias effect caused by the holes temporarily accumulated in the p layer 4 and the p layer 8. As a result, as shown in Fig. 2(c), the threshold voltage of the MOSFET having the gate conductor layer 10 connected to the word line WL becomes lower. This written state is assigned to the logical memory data "1".

[0044] Note that the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL described above are an example for performing a write operation, and other voltage conditions that enable the write operation may also be used.

[0045] Also, in FIG. 2, as an example of the combination of the gate conductor layer 22 and the gate conductor layer 10, a combination of p+ poly (work function 5.15 eV) and n+ poly (work function 4.05 eV) is shown. However, this may be a metal, a metal nitride, or an alloy (including silicide) having a laminated structure such as Ni (work function 5.2 eV) and n+ poly, Ni and W (work function 4.52 eV), Ni and TaN (work function 4.0 eV) / W / TiN (work function 4.7 eV).

[0046] According to the structure of the present embodiment, since the p layer 8 of the MOSFET having the gate conductor layer 10 to which the word line WL is connected is electrically connected to the p layer 4, the capacitance for accumulating the generated holes can be freely changed by adjusting the volume of the p layer 4. That is, for example, the depth of the p layer 4 may be increased to increase the holding time. Therefore, it is required that the bottom of the p layer 4 is at a deeper position than the bottom of the p layer 8. In addition, since the area where the n layer 3, n+ layer 7a, and n+ layer 7b that are involved in recombination with electrons can be intentionally made smaller than the volumes of the p layer 4 and the p layer 8 where the hole carriers are accumulated, recombination with electrons can be suppressed, and the holding time of the accumulated holes can be extended. Furthermore, since p+ poly is used for the gate conductor layer 22, the accumulated holes are accumulated near the interface of the p layer 4, which is the second semiconductor layer in contact with the first gate insulating layer 5. In addition, since the pn junction portion that causes recombination of electrons and holes, that is, the portion where the n+ layer 7a, n+ layer 7b and the p layer 8 are in contact, can be separated from the location where the holes are accumulated, stable hole accumulation can be achieved. For this reason, as this memory element, the effect of the overall substrate bias on the substrate is increased, the time for holding the memory is lengthened, and the voltage margin for writing "1" is widened.

[0047] Next, the erasure operation mechanism will be described with reference to FIG. 3. FIG. 3(a) shows the state immediately after all biases become 0V, with the hole group 11 generated by impact ionization in the previous cycle stored in the p-layer 4 and the p-layer 8 before the erasure operation. As shown in FIG. 3(b), during the erasure operation, the voltage of the source line SL is set to a negative voltage VERA, and the voltage of the PL is set to 2V. Here, VERA is, for example, -0.5V. As a result, regardless of the value of the initial potential of the p-layer 8, the PN junction between the n+ layer 7a serving as the source to which the source line SL is connected and the p-layer 8 becomes forward-biased. As a result, the hole group 11 stored in the p-layer 4 and the p-layer 8, which was generated by impact ionization in the previous cycle, moves to the n+ layer 7a connected to the source line. Also, as a result of applying a voltage of 2V to the PL, an inversion layer 14 is formed at the interface between the gate insulating layer 5 and the p-layer 4 and contacts the n-layer 3. Therefore, the holes accumulated in the p-layer 4 flow from the p-layer 4 to the n-layer 3 and the inversion layer and recombine with electrons. As a result, the hole concentrations in the p-layer 4 and the p-layer 8 decrease with time, the threshold voltage of the MOSFET becomes higher than when writing "1", and it returns to the initial state. As a result, as shown in FIG. 3(c), the MOSFET having the gate conductor layer 10 to which this word line WL is connected returns to its original threshold value. The erased state of this dynamic flash memory becomes the logical storage data "0".

[0048] According to the structure of this embodiment, during data erasure, the effective recombination area of electrons and holes can be increased compared to data storage. Therefore, a stable state of the logical information data "0" can be provided in a short time, and the operating speed of this dynamic flash memory element is improved.

[0049] Note that the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL described above are just an example for performing the erasure operation, and other voltage conditions that enable the erasure operation may also be used. For example, in the above description, an example where the gate conductor layer 22 is biased to 2V was explained. However, during erasure, if, for example, 0.2V is applied to BL, 0V is applied to SL, and the first and second gate conductor layers are biased to 2V, an inversion layer in which electrons are the majority carriers can be formed at the interfaces between the p-layer 8 and the gate insulating layer 9 and between the p-layer 4 and the gate insulating layer 2. The recombination area of electrons and holes can be increased, and the erasure time can be further actively shortened by flowing a current with electrons as the majority carriers between BL and SL.

[0050] Also, if the film thicknesses of the insulating layer 2 and the insulating layer 6 are made the same as that of the gate insulating layer 5, for example, if 2V is applied to PL during data erasure, the n+ layer 7a or 7b and the n-layer 3 can be connected by the inversion layer 14, and the data erasure time can be shortened.

[0051] Also, according to this embodiment, the p-layer 8, which is one of the components of the MOSFET for reading and writing information, is electrically connected to the p-layer 1, the n-layer 3, and the p-layer 4. Furthermore, a voltage can be applied to the gate conductor layer 22. Therefore, in both the write operation and the erase operation, for example, the substrate bias does not become unstable in a floating state during MOSFET operation as in the case of an SOI structure, and the semiconductor portion under the gate insulating layer 9 does not become completely depleted. For this reason, the threshold value, drive current, etc. of the MOSFET are less likely to be affected by the operating conditions. Therefore, the characteristics of the MOSFET can be adjusted by adjusting the thickness of the p-layer 8, the type of impurity, the impurity concentration, the profile, the impurity concentration and profile of the p-layer 4, the thickness and material of the gate insulating layer 9, and the work functions of the gate conductor layers 10 and 22, so that a voltage related to a desired memory operation can be widely set. Also, since the depletion layer spreads in the depth direction of the p-layer 4 without complete depletion under the MOSFET, it is hardly affected by the coupling of the gate electrode from the word line of the floating body, which was a drawback of the DRAM without a capacitor. That is, according to this embodiment, a wide margin of the operating voltage as a dynamic flash memory can be designed.

[0052] Moreover, according to this embodiment, it is effective in preventing malfunction of memory cells. In the operation of memory cells, in the voltage operation of the target cell, an unnecessary voltage is applied to some of the electrodes of the cells other than the target in the cell array, and malfunction is a major problem (for example, Non-Patent Document 9). That is, as a phenomenon, it means that a cell written with "1" becomes "0" due to the operation of other cells, or a cell written with "0" becomes "1" due to the operation of other cells (hereinafter, this phenomenon due to malfunction is referred to as a disturb defect). According to this embodiment, when "1" is originally written as data information, the amount of holes accumulated can be increased by adjusting the depth of the p-layer 4 compared to the amount of recombination of electrons and holes caused by transistor operation. Even under the conditions where disturb defects occur in conventional memories, the influence on the threshold voltage variation of the MOSFET is small and malfunction is less likely to occur. Also, when "0" is originally written as data information, even if unintentional holes are generated by the transistor operation during reading, they immediately diffuse into the p-layer 4. Therefore, if the depth of the p-layer 4 is increased, the change rate of the hole concentration in the entire p-layer 4 and p-layer 8 is small, and in this case too, the influence on the threshold voltage of the MOSFET is small, and the probability of occurrence of disturb defects can be reduced compared to the conventional case. Therefore, according to this embodiment, the structure is resistant to memory disturb defects.

[0053] Also, when the data information is "0", there is a possibility that the holes in the hole-electron pair generated in the depletion layer in the cell during retention accumulate in the p-layer 8 and the data changes from "0" to "1". However, according to the structure of the present invention, since holes are accumulated in the p-layer 4 at a higher concentration, it does not greatly affect the change in the hole concentration in the p-layer 8 directly below the MOSFET, so stable "0" data information can be retained.

[0054] Note that when data is retained, a similar effect can be obtained even if the work functions of the first gate conductor layer and the second gate conductor layer are the same by applying 0 V to BL, WL, and SL and -0.5 V to PL, which is within the scope of the present invention. However, considering the difficulty of generating a negative voltage internally and further controlling it in a timely manner, it is a simpler method from the perspective of electrode potential control to use materials with different work functions for the first gate conductor layer and the second gate conductor layer.

[0055] Also, as is clear from the structure of FIG. 1, the element structure composed of the p-layer 8, n+-layers 7a and 7b, gate insulating layer 9, and gate conductor layer 10 can be formed in common not only for this memory cell but also for MOS circuits including other general CMOS structures. Therefore, this memory cell can be easily combined with conventional CMOS circuits.

[0056] The manufacturing method of the dynamic flash memory according to the present embodiment is shown using FIGS. 4A to 4J (4I is omitted because it is easily confused in notation). In each figure, (a) is a plan view, (b) is a vertical cross-sectional view taken along the X-X' line of (a), and (c) is a vertical cross-sectional view taken along the Y-Y' line of (a). Also, the same or similar components as those shown in FIG. 1 are denoted by the same reference numerals.

[0057] As shown in FIG. 4A, on the substrate 20, a p-layer 1, an n-layer 3, a p-layer 4, an insulating layer 41, and a mask material layer 42 are formed from the bottom. Note that the substrate may be a semiconductor or an insulating film. Also, the p-layer 1 and the n-layer 3 may be well layers. Further, for example, a silicon oxide film can be used for the insulating layer 41, and a silicon nitride film can be used for the mask material layer 42.

[0058] Next, as shown in FIG. 4B, in the region that will become the memory cell in the future, using the mask material layers 42a to 42d as masks, the insulating layer 41, the p-layer 4, and the n-layer 3 are etched by the RIE (Reactive Ion Etching) method. Note that in FIG. 4B, the bottom of the etched groove is depicted as being flush with the bottom of the n-layer 3, but it may be located deeper than the upper part of the n-layer 3.

[0059] Next, as shown in FIG. 4C, an insulating film 2 is selectively formed by oxidation on the sidewalls and bottom of the p-layer 4 and the n-layer 3 left by etching. In FIGS. 1-3, the gate insulating layer 5 and the insulating film 2 were shown separately, but hereafter they will be integrated and denoted as the gate insulating layer 25. Although not shown, for example, the ALD (Atomic Layer Deposition) technique may be used to form an oxide film entirely. In this case, the gate insulating layer 25 is also formed around the mask material layer 42.

[0060] Next, as shown in FIG. 4D, polycrystalline silicon doped with boron at a high concentration is used as the gate conductor layer 22. After depositing it entirely by, for example, the CVD method, etch-back is performed by the selective RIE method, and etching is performed so that the upper surface of the gate conductor layer 22 is at a position lower than the upper surface of the p-layer 4.

[0061] Next, as shown in FIG. 4E, an insulating layer 6 is formed entirely by, for example, the CVD method.

[0062] Next, as shown in FIG. 4F, the insulating layer 6 is polished by the CMP (Chemical Mechanical Polishing) technique until the surfaces of the mask materials 42a to 42d appear, and then the mask materials 42a to 42d are selectively removed. Further, the insulating layer 6 is etched back until the surface of the p-layer 4 appears, and at the same time, the insulating layer 41 is etched.

[0063] Next, as shown in FIG. 4G, the semiconductor layer 8 is grown by, for example, the CVD method under conditions such that it is continuous as a crystal layer from the p-layer 4, and then the portions other than those necessary for operating as a MOSFET in the memory cell are removed.

[0064] Next, as shown in FIG. 4H, a gate insulating layer 9 is formed, and a gate conductor layer 10 is formed of n+ poly having a work function lower than that of the gate conductor layer 22, and is processed to be the gate electrode of the MOSFET in each memory cell. In FIG. 4H, they are denoted as gate insulating layers 9a, 9b, 9c and gate conductor layers 10a, 10c. Thereafter, n+ layers 7a and n+ 7b are formed self-alignedly.

[0065] Next, after forming an insulating layer 31 over the entire surface as shown in FIG. 4J, contact holes 33a to 33d are formed in each memory cell. Thereafter, wiring conductor layers 35 and 36 are formed. The wiring conductor layer 35 is connected to the source line SL. Next, after forming an insulating film 38, second contact holes 37c and 37d are formed to form a wiring conductor layer 39. This is connected to the bit line BL.

[0066] In the plan view of FIG. 4J(a), there are only the second wiring conductor layer 39 and the insulating film 38 in the actual upper part, but for the sake of understanding, the p-layers 4a to 4d of the main lower layer part, the gate conductor layers 10a, 10c, and the contact holes 33a, 33b, 33c, 33d, 37c, 37d are shown. Focusing on the memory cell at the intersection of X-X‘ and Y-Y’ in FIG. 4J(c) of the main components and comparing with FIG. 1, n-layer 3 (FIG. 1) / n-layer 3a (FIG. 4J) (the following similar description), p-layer 4 / p-layer 4a, semiconductor layer 8 / semiconductor layer 8a, n+ layer 7a connected to SL / n+ layer 7a, n+ layer 7b connected to BL / n+ layer 7c, gate insulating layer 9 / gate insulating layer 9a, gate conductor layer 10 connected to WL / gate conductor layer 10a, gate conductor layer 22 connected to PL / gate conductor layer 22.

[0067] In this embodiment, the impurity layer 4 is of p-type, and an example in which p+poly is used for the gate conductor layer 22 and n+poly is used for the gate conductor layer 10 has been described. However, if the work function of the gate conductor layer 22 is larger than that of the gate conductor layer 10, for example, combinations such as a stack of p+poly (5.15 eV) / W and TiN (4.7 eV), a stack of p+poly (5.15 eV) / silicide and n+poly (4.05 eV), a stack of TaN (5.43 eV) / W and TiN (4.7 eV) may also be used. Further, when the impurity layer 4 is of n-type, if the work function of the gate conductor layer 22 is smaller than that of the gate conductor layer 10, for example, if n+poly is used for the gate conductor layer 22 and p+poly is used for the gate conductor layer 10, the same effect can be obtained. Note that the gate conductor layers 10 and 22 may be a semiconductor, a metal, or a compound thereof.

[0068] In FIGS. 4A to 4J, the shape of the groove has been described using a rectangular vertical cross-section, but it may be trapezoidal.

[0069] In this embodiment, the impurity layer 3 and the impurity layer 4 are shown as columns having a quadrangular bottom surface, but they may be columns having other polygonal or circular bottom surfaces.

[0070] Also, the n-layer 3 only needs to exist in a portion where there will be memory cells in the future. Therefore, although FIG. 4A shows the n-layer 3 formed over the entire surface on the p-layer 1, the n-layer 3 may be formed only in a selected region on the p-layer 1.

[0071] Also, the materials of the mask material layers 42a to 42d and the gate insulating layer 25 may be any materials as long as they have an etching selectivity ratio during etching.

[0072] In FIG. 4F, the CMP endpoint material is the mask material layers 42a to 42d, but the gate insulating layer 25, the insulating layer 6, the p-layer 4, etc. may also be used.

[0073] In addition, for the gate insulating layer 25 and the gate insulating layers 8 (9a to 9d), any insulating film used in a normal MOS process, such as an SiO2 film, a SiON film, a HfSiON film, or a laminated film of SiO2 / SiN, can be used.

[0074] Also, in this description, a method of separately forming the wiring conductor layer 36 and the wiring conductor layer 39 to connect to the BL line is shown. However, it is also possible to form the wiring conductor layers 36 and 39 and the contact holes 33c and 37c in a single process using a damascene method or the like.

[0075] Also, in FIG. 4, the gate conductor layer 10, the semiconductor layer 8, and all the wiring conductor layers are shown extending parallel or perpendicular to the X-X' axis or the Y-Y' axis. However, these may be extended in an oblique direction.

[0076] Also, in this embodiment, the MOS circuit portion including peripheral circuits other than the memory cell is not shown. However, it is obvious that for that portion, by using the same mask as the portion of the p-layer 8 in FIG. 4G and controlling the respective impurity concentrations, MOSFETs for circuits other than the memory cell can be formed in the same process after the MOSFETs are created.

[0077] This embodiment has the following features. (Feature 1) The dynamic flash memory according to the first embodiment of the present invention is composed of a p-layer 4 and a p-layer 8 surrounded by an insulating layer 2, a gate insulating layer 5, and an n-layer 3 in a substrate region where a channel of a MOSFET is formed. Due to this structure, majority carriers generated during the writing of logical data "1" can be accumulated in the p-layer 8 and the p-layer 4, and the number can be increased. Furthermore, since a material with a larger work function than the gate conductor layer 10 is used for the gate conductor layer 22, holes generated during writing can be accumulated near the interface of the p-layer 4 near the gate conductor layer 22, and the information retention time becomes longer. Also, during data erasure, a positive voltage is applied to the gate conductor layer 22 to form an inversion layer, and by effectively increasing the recombination area of holes and electrons, the recombination area with electrons is increased, and erasure takes a short time. Furthermore, by applying a negative voltage to the n+ layer 7a connected to the source line SL, the thyristor structure of the n+ layer 7a, the p-layer 8, the p-layer 4, the n-layer 3, and the p-layer 1 can also accelerate the erasure operation. Therefore, the operation margin of the memory can be expanded, power consumption can be reduced, leading to high-speed operation of the memory.

[0078] (Feature 2) The p-layer 8, which is one of the components of the MOSFET in the dynamic flash memory according to the first embodiment of the present invention, is connected to the p-layer 4, the n-layer 3, and the p-layer 1. By adjusting the voltage applied to the gate conductor layer 22, the p-layer 8 and the p-layer 4 under the gate insulating layer 9 are not completely depleted. For this reason, the threshold value, drive current, etc. of the MOSFET are less affected by the operating conditions of the memory. Furthermore, since the area under the MOSFET is not completely depleted, it is not greatly affected by the coupling of the gate electrode from the floating body word line, which was a drawback of DRAM without a capacitor. That is, according to the present invention, the margin of the operating voltage as a dynamic flash memory can be widely designed.

[0079] (Feature 3) The p-layer 8, which is one of the components of the MOSFET in the dynamic flash memory according to the first embodiment of the present invention, is connected to the p-layer 4, and the amount of hole accumulation when writing the information data "1" can be made more than 10 times larger than that of, for example, a conventional zero-capacitor DRAM (Non-Patent Documents 6 and 9). Therefore, even if a disturbance factor occurs in the voltage applied to the memory cell other than for read / write purposes, the data of the written information data "1" is difficult to disappear. Also, when the information data "0" is written in the memory, even if a disturbance factor occurs in the voltage applied to the memory cell other than for read / write purposes and holes other than the intended ones are generated in the memory cell, the amount of holes required for this information to be converted to "1" in a short time does not occur. As a result of these, the present invention has a memory cell structure that is resistant to disturb failures.

[0080] (Feature 4) The gate electrode of the MOSFET of the cell has a structure that surrounds the p-layer 8, and since the effective channel width becomes wider, the amount of surplus holes during writing can be increased, and the cell current can be increased, enabling high-speed operation of the memory.

[0081] (Feature 5) The n+-layer 7a of the dynamic flash memory cell shown in FIG. 4J, the wiring conductor layer 35 connected to the source line SL, and the contact hole 33a are shared by adjacent cells. Also, the n+-layer 7c, the wiring conductor layers 36 and 39 connected to the bit line BL, and the contact holes 33c and 37c are shared by adjacent cells. Therefore, the cell area of the dynamic flash memory according to the present invention is determined by the lines and spaces of the p-layers 8a and 8b and the gate conductors 10a and 10c respectively, or the lines and spaces of the wiring conductor layers 35 and 36. Thus, when the minimum dimension in manufacturing is F, the cell area is 4F 2 and a fine memory cell can be provided.

[0082] (Second Embodiment) Using FIG. 5, the dynamic flash memory according to the second embodiment of the present invention will be described. In FIG. 5, components that are the same as or similar to those in FIGS. 1 and 4 are denoted by the same reference numerals.

[0083] As shown in FIG. 5A(a), the gate conductor layer 22 in FIG. 4J is electrically separated into gate conductor layers 22-1 and 22-2 by an insulating film 32 (an example of the "fourth insulating layer" in the claims). Therefore, the plate line is separated into PL1 (an example of the "first plate line" in the claims) connected to the gate conductor layer 22-1 and PL2 (an example of the "second plate line" in the claims) connected to the gate conductor layer 22-2. Therefore, different voltages can be applied to PL1 and PL2. Also, FIG. 5(a) is a plan view thereof, and (c) is a vertical cross-sectional view taken along the line Y-Y'. Even in such a form, by applying voltages to the source line SL, plate lines PL-1, PL-2, word line WL, and bit line BL in the same manner as in the first embodiment, the operation of the dynamic flash memory is possible.

[0084] An example of the manufacturing method is shown using FIG. 5B. After the process of FIG. 4D is completed, a part of the gate conductor layer 22 is etched by commonly used lithography and etching techniques to form a groove, and a state in which the insulating film 32 is formed in the groove is illustrated. Thereafter, if the processes from FIG. 4E to FIG. 4J are advanced in the same manner, the cell structure of FIG. 5A can be created.

[0085] FIG. 5B shows a cross-sectional view and a plan view of the intermediate progress of manufacturing. A groove is formed in a part of the gate conductor layer 22 by commonly used lithography and etching techniques between the gate conductor layers 22-1 and 22-2, and the illustration is up to the point where the insulating layer 32 is formed in the groove. Thereafter, directly proceed to the process of 4E, and fill this groove simultaneously when forming the insulating layer 6. Of course, it is possible to also use the insulating layer 32 as the insulating layer 6, and in this case, the insulating layer 6 and the insulating layer 32 will be formed of the same material.

[0086] The voltage operation during the read operation of the dynamic flash memory according to the second embodiment of the present invention will be described. Consider the case of reading the information connected to WL1. For example, when 1V is applied to WL1, 0.5V to BL, 1V to PL1, 0V to PL2, and 0V to SL, the threshold value of the MOS transistor connected to WL2 becomes about 0.4V higher than that of the MOS transistor connected to WL1. Of course, this can be operated by the voltages applied to PL1 and PL2. By operating this threshold value, even if WL1 is operated, the effective threshold value of the MOSFET connected to WL2 is high and hardly operates, so the influence of external disturbance factors can be reduced, and the disturb defect described in the first embodiment can be greatly improved.

[0087] In the example of FIG. 5A, an example is shown in which the gate conductor layer 22 is divided into two by the insulating layer 32, but the division location can be arbitrarily set, and a desired number of memory cells can be arranged in the same gate conductor layer.

[0088] In addition, for the insulating film 32, any insulating film used in a normal MOS process, such as a SiO2 film, a SiON film, a HfSiON film, or a laminated film of SiO2 / SiN, can be used.

[0089] The embodiment of the present invention has the following features. (Feature 1) Similar to the first embodiment, by applying voltages to the source line SL, the word line WL, and the bit line BL, and applying independent voltages to the two plate lines, PL-1 and PL-2, the dynamic flash memory can operate. The dynamic flash memory according to the second embodiment of the present invention electrically separates the gate conductor layer 22-1 connected to PL1 where the memory cell is located and the gate conductor layer 22-2 connected to PL2, and can set voltages independently. Therefore, by changing the voltage applied to the PL electrode in contact with the memory to which data information is read and written and the voltage applied to the other PL electrodes, the disturb defect described in the first embodiment can be further reduced. (Feature 2) In the dynamic flash memory according to the second embodiment of the present invention, since the PL electrodes are each divided and can be operated, the power consumption at that time can be reduced. Furthermore, it is also possible to reuse the power generated during the charge and discharge in the integrated circuit.

[0090] (Third Embodiment) The dynamic flash memory according to the third embodiment of the present invention will be described with reference to FIG. 6. In FIG. 6, the same or similar components as those in FIG. 1 are denoted by the same reference numerals.

[0091] As shown in FIG. 6(a), the bottom of the n-layer 3 in FIG. 1 is located deeper than the gate insulating layer 2 and the n-layer 3 is shared by a plurality of cells. Otherwise, it is the same as in FIG. 1. In this case, the gate insulating layer 2 may or may not be in contact with the p-layer 1. Even in such a form, the operation of the dynamic flash memory is possible by applying voltages to the source line SL, the plate line PL, the word line WL, and the bit line BL in the same manner as in the first embodiment.

[0092] Also, when the n-layer 3 is shared by a plurality of cells as shown in FIG. 6(b), by connecting to the control line CDC (an example of the "control line" in the claims), which is the fifth wiring conductive layer, and applying a voltage, a plurality of memory operations can be simultaneously operated.

[0093] Also, when writing the logical memory data "1", in addition to the voltage application conditions of the first embodiment, for example, by applying 1V to the CDC so that the pn junction with the p-layer 4 does not become forward, the recombination of electrons and holes can be suppressed and the accumulation of holes can be promoted.

[0094] Also, when erasing the stored data to “0”, for example, even if a voltage of 2V is applied to the gate conductor layer 22 and a voltage of -1V is applied to the CDC and the p-layer 1 while setting the other potentials to 0V, the pn junction between the p-layer 4 and the n-layer 3 becomes forward-biased, and an inversion layer is formed at the interface between the gate insulating layer 5 in contact with the gate conductor layer 22 and the p-layer 4. Thus, the holes accumulated in the memory cell can be quickly discharged. According to the third embodiment in this way, the margin between the writing of “1” and the erasing operation to “0” of the logical stored data in the first embodiment can be further expanded.

[0095] This embodiment has the following features. (Feature 1) Similar to the first embodiment, by applying voltages to the source line SL, the plate line PL, the word line WL, and the bit line BL, the dynamic flash memory can operate. Further, by applying a voltage to the control line CDC, the operation margin for writing “1” and erasing “0” of the stored information data can be expanded, and a high-speed memory operation can be achieved.

[0096] (Feature 2) Since there are multiple cells in the n-layer 3, “0” erasure can be performed for multiple cells at once.

[0097] Also, the present invention can be implemented in various embodiments and variations without departing from the broad spirit and scope of the present invention. Further, the above-described embodiments are for explaining examples of the present invention and do not limit the scope of the present invention. The above examples and variations can be arbitrarily combined. Furthermore, even if some of the constituent elements of the above embodiments are excluded as necessary, it is still within the scope of the technical idea of the present invention.

Industrial Applicability

[0098] By using the memory function using the semiconductor element according to the present invention, a high-speed dynamic flash memory with a longer storage time and lower power consumption than conventional ones can be provided.

Explanation of Reference Numerals

[0099] 1 First semiconductor layer 2 First insulating layer 3, 3a, 3b, 3c First impurity layer 4, 4a, 4b, 4c, 4d Second semiconductor layer 5 First gate insulating layer 6. Second insulating layer 7a, 7c n+ layer 8, 8a, 8b, 8c Third semiconductor layer 9, 9a, 9b, 9c Second gate insulating layer 10, 10a, 10c Second gate conductor layer 11 Hole group 12 Inversion layer 13 Pinch-off point 14 Inversion layer 20 Substrate 22, 22-1, 22-2 First gate conductor layer 25 Insulating layer (general term for integrating 2 and 5) SL Source line PL PL1, PL2 Plate line WL, WL1, WL2 Word line BL Bit line 31 Third insulating layer 32 Fourth insulating layer 33a, 33b, 33c, 33d Contact hole 35, 36 First wiring conductor layer 37c, 37d Contact hole 39 Second wiring conductor layer 41 Insulating layer 42, 42a, 42b, 42c, 42d Mask material

Claims

1. A substrate, a first semiconductor layer on the substrate, a first impurity layer at least partially columnar on a surface of a part of the first semiconductor layer, a second semiconductor layer extending vertically in contact with a columnar portion of the first impurity layer, a first insulating layer covering a part of the first semiconductor layer and a part of the first impurity layer, a first gate insulating layer in contact with the first insulating layer and surrounding the first impurity layer and the second semiconductor layer, a first gate conductor layer in contact with the first insulating layer and the first gate insulating layer, the first gate conductor layer being electrically separated from the first impurity layer by the first insulating layer and the first gate insulating layer, a second insulating layer formed to contact the first gate conductor layer and the first gate insulating layer, a third semiconductor layer in contact with the second semiconductor layer, a second gate insulating layer surrounding a part or all of an upper part of the third semiconductor layer, a second gate conductor layer covering a part or all of an upper part of the second gate insulating layer, a second impurity layer and a third impurity layer in contact with a side surface of the third semiconductor layer outside one end of the second gate conductor layer in a horizontal direction in which the third semiconductor layer extends, a first wiring conductor layer connected to the second impurity layer, a second wiring conductor layer connected to the third impurity layer, a third wiring conductor layer connected to the second gate conductor layer, a fourth wiring conductor layer connected to the first gate conductor layer, and controlling voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, and the fourth wiring conductor layer to generate an electron group and a hole group in the third semiconductor layer and the second semiconductor layer by an impact ionization phenomenon or a gate-induced drain leakage current with a current flowing between the second impurity layer and the third impurity layer, removing either the electron group or the hole group, which are minority carriers in the third semiconductor layer and the second semiconductor layer, among the generated electron group and hole group, and leaving a part or all of either the electron group or the hole group, which are majority carriers in the third semiconductor layer and the second semiconductor layer, in the third semiconductor layer and the second semiconductor layer to perform a memory writing operation. The majority carrier concentration of the second semiconductor layer of the memory cell in the writing state is higher than the majority carrier concentration in the third semiconductor layer. By controlling the voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, and the fourth wiring conductor layer, either the electron group or the hole group, which are the majority carriers in the remaining second semiconductor layer or third semiconductor layer, is extracted from at least one of the first impurity layer, the second impurity layer, and the third impurity layer and recombined with the majority carriers in the first impurity layer, the second impurity layer, and the third impurity layer, thereby performing a memory erasing operation. A memory device using a semiconductor device characterized by the above.

2. The first wiring conductor layer connected to the second impurity layer is a source line, the second wiring conductor layer connected to the third impurity layer is a bit line, the third wiring conductor layer connected to the second gate conductor layer is a word line, and the fourth wiring conductor layer connected to the first gate conductor layer is a plate line. By applying voltages to the source line, the bit line, the plate line, and the word line respectively, writing and erasing of the memory are performed. A memory device using the semiconductor device according to claim 1, characterized by the above.

3. The work functions of the first gate conductor layer and the second gate conductor layer are different. A memory device using the semiconductor device according to claim 1, characterized by the above.

4. The majority carriers in the first impurity layer are electrons, the majority carriers in the second semiconductor layer are holes, and the work function of the first gate conductor layer is larger than the work function of the second gate conductor layer. A memory device using the semiconductor device according to claim 3, characterized by the above.

5. The majority carriers in the first impurity layer are holes, the majority carriers in the second semiconductor layer are holes, and the work function of the first gate conductor layer is smaller than the work function of the second gate conductor layer. A memory device using the semiconductor device according to claim 3, characterized by the above.

6. The majority carriers in the first impurity layer are different from the majority carriers in the first semiconductor layer. A memory device using the semiconductor device according to claim 1, characterized by the above.

7. The majority carriers in the second semiconductor layer are the same as the majority carriers in the first semiconductor layer. A memory device using the semiconductor device according to claim 1, characterized by the above.

8. A memory device using the semiconductor device according to claim 1, wherein the majority carriers in the second impurity layer and the third impurity layer are the same as the majority carriers in the first impurity layer.

9. A memory device using the semiconductor device according to claim 1, wherein the concentration of the first impurity layer is lower than that of the second impurity layer and the third impurity layer.

10. A memory device using the semiconductor device according to claim 1, wherein a vertical distance from the bottom of the third semiconductor layer to the top of the first impurity layer is shorter than a vertical distance from the bottom of the third semiconductor layer to the bottom of the first gate conductor layer.

11. A memory device using the semiconductor device according to claim 2, wherein a source line contact hole for connecting the source line and the second impurity layer and a first wiring conductor layer are shared with an adjacent cell.

12. A memory device using the semiconductor device according to claim 2, wherein a bit line contact hole for connecting the bit line and the third impurity layer and a second wiring conductor layer are shared with an adjacent cell.

13. A memory device using the semiconductor device according to claim 1, wherein the first gate conductor layer is separated by a fourth insulating layer in contact with the first gate conductor layer, and is connected to a first plate line and a second plate line respectively, and an independent voltage is applied.

14. A memory device using the semiconductor device according to claim 13, wherein there are a plurality of memory cells in contact with the first plate line and a plurality of memory cells in contact with the second plate line, and the same cell does not contact a plurality of plate lines.

15. A memory device using the semiconductor device according to claim 1 or claim 2, wherein the bottom of the first impurity layer is at a position deeper than the bottom of the first insulating layer, and the first impurity layer is shared by a plurality of cells.

16. A memory device using the semiconductor device according to claim 12, having a fifth wiring conductor layer connected to the first impurity layer, and the fifth wiring conductor layer is a control line to which a desired voltage can be applied.

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