Imaging device and electronic apparatus

Abstract

In the present invention, a laminated imaging element can secure both a wide sensitivity region and a charge storage amount. The imaging element includes a pixel comprising: a photoelectric conversion layer (15); a first electrode (11) that is positioned on the a surface of the photoelectric conversion layer, and that is electrically connected to the photoelectric conversion layer; a second electrode (16) positioned on a second surface, which is opposite the first surface of the photoelectric conversion layer; a charge storage electrode (12) which is positioned on the first surface of the photoelectric conversion layer, separated from the first electrode in a direction parallel to the first surface; and a third electrode (200) positioned at a position that includes a portion overlapping, in a direction vertical to the first surface, a gap between the first electrode and the charge storage electrode.

Description

Technical Field

[0001] The present disclosure relates to an imaging device and an electronic device.

Background Art

[0002] A stacked imaging device in which a plurality of photoelectric conversion units having different absorption coefficients for the wavelength of light are stacked has been proposed. In such a stacked imaging device, for example, a first photoelectric conversion unit made of an organic film is formed on a semiconductor layer, and second and third photoelectric conversion units are formed in the semiconductor layer. The first photoelectric conversion unit performs photoelectric conversion in response to light in the first wavelength region received with the organic film as a light receiving surface and generates charges. Further, the second photoelectric conversion unit and the third photoelectric conversion unit each perform photoelectric conversion in response to light in the second wavelength region and the third wavelength region, respectively, which are received through the upper layer, and generate charges.

[0003] In such a configuration, the charges generated by photoelectric conversion in the second and third photoelectric conversion units are once accumulated in these second and third photoelectric conversion units, and at a predetermined timing, they are transferred to second and third floating diffusion regions formed in the semiconductor layer, respectively. On the other hand, the charges generated in the first photoelectric conversion unit formed on the organic film are transferred and accumulated to the first floating diffusion region formed in the semiconductor layer through a contact hole and a wiring layer. Thus, when charges are directly transferred and accumulated from the first photoelectric conversion unit to the first floating diffusion region, kTC noise increases, random noise deteriorates, and there is a risk of deterioration of the imaging image quality.

[0004] On the other hand, a configuration is disclosed in which a charge storage electrode and a readout electrode are provided on a surface of the transparent electrode facing the light-receiving surface of the first photoelectric conversion unit, and the readout electrode is provided at a distance from the charge storage electrode, and a common electrode common to the charge storage electrode and the readout electrode is provided on the light-receiving surface (for example, Patent Document 1). In this configuration, a potential barrier is generated between the charge storage electrode and the readout electrode by applying a bias from the common electrode. By controlling the voltage applied to the charge storage electrode and the readout electrode, the charges generated by photoelectric conversion can be accumulated between the charge storage electrode and the common electrode, and the accumulated charges can be read out by the readout electrode and transferred to the first floating diffusion region. According to this configuration, it is possible to suppress the occurrence of the above-described phenomena such as an increase in kTC noise and deterioration of random noise.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the configuration of Patent Document 1 described above, the potential barrier between the charge storage electrode and the readout electrode ensures the amount of signal charges (stored charge amount) stored by the charge storage electrode. At this time, by increasing the distance between the charge storage electrode and the readout electrode, it becomes possible to generate a high potential barrier and increase the stored charge amount, but the sensitivity region becomes narrow and the sensitivity decreases.

[0007] An object of the present disclosure is to provide an imaging device and an electronic device capable of achieving both ensuring a wide sensitivity region and ensuring the amount of stored charges.

Means for Solving the Problems

[0008] The imaging device according to the present disclosure includes a photoelectric conversion layer, a first electrode located on the first surface side of the photoelectric conversion layer and electrically connected to the photoelectric conversion layer, a second electrode located on the second surface opposite to the first surface of the photoelectric conversion layer, a charge accumulation electrode located on the first surface side of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface, and a third electrode disposed at a position overlapping a gap between the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface, and includes a pixel having the above components. See, the pixel further includes a separation electrode disposed at an outer edge portion of the pixel for electrically separating the pixel from the pixel adjacent to the pixel. The pixels are arranged in a matrix arrangement. The first electrode is shared by a plurality of the pixels sharing vertices in the arrangement. The separation electrode has a shape in which a part including the vertex is cut out from each of two sides including the vertex. The third electrode is obliquely disposed between the first electrode and the charge storage electrode according to each of the cut ends of the separation electrode, and is connected to each of the ends of the separation electrode via a vertical via, respectively. 。

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same parts are denoted by the same reference numerals, and redundant explanations are omitted.

[0011] Hereinafter, embodiments of the present disclosure will be described in the following order. 1. Technologies Applicable to Each Embodiment 1-0-1. Electronic Devices Applicable to Each Embodiment 1-0-2. Prior Art Related to Each Embodiment 1-0-3. Relationship between Electrode Configuration and Amount of Stored Charge According to Prior Art 2. First Embodiment 2-0-1. Outline of Image Sensor According to First Embodiment 2-0-2. More Detailed Configuration Example of Image Sensor According to First Embodiment 2-0-3. Configuration Example of Electrodes According to First Embodiment 2-0-4. Method of Applying Voltage to Barrier Forming Electrodes According to First Embodiment 2-1. First Modification of First Embodiment 2-2. Second Modification of First Embodiment 3. Second Embodiment 4. Third Embodiment 5. Fourth Embodiment 5-1. Application Examples of Technology of the Present Disclosure 5-2. Application Examples to Endoscopic Surgery System 5-3. Application Examples to Mobile Bodies

[0012] [1. Technologies Applicable to Each Embodiment] Prior to the description of each embodiment of the present disclosure, for ease of understanding, the technologies applicable to each embodiment will be briefly described.

[0013] (1-0-1. Electronic Devices Applicable to Each Embodiment) First, electronic devices to which the technologies according to each embodiment of the present disclosure are applicable will be described. FIG. 1 is a block diagram showing the configuration of an example of an electronic device to which the technologies according to each embodiment of the present disclosure are applicable.

[0014] In FIG. 1, the electronic device 1000 includes an optical unit 1010, an imaging device 1011, a signal processing circuit 1012, a display device 1013, and a storage medium 1014. In FIG. 1, as the imaging device 1011, an image sensor as an imaging device according to the present disclosure, the details of which will be described later, is applied. The image sensor includes a plurality of pixels that convert incident light into an electrical signal by photoelectric conversion, and a drive circuit that drives these plurality of pixels. Here, as the electronic device 1000, a digital still camera, a digital video camera, a mobile phone or a smartphone with an imaging function, etc. can be applied.

[0015] The optical unit 1010 includes one or more lenses, a diaphragm mechanism, a focus mechanism, etc., and forms an image of subject image light (incident light) on the imaging surface of the imaging device 1011. As a result, signal charges are accumulated in the imaging device 1011 for a certain period. The signal processing circuit 1012 performs various signal processes including image processing on the pixel signals output from the imaging device 1011. The image signals subjected to the signal processing can be stored in a non-volatile storage medium 1014 such as a flash memory or a hard disk drive. Also, an image based on the pixel signals can be output to the display device 1013.

[0016] (1-0-2. Prior Art Related to Each Embodiment) Next, the prior art related to each embodiment will be schematically described. FIG. 2 is a block diagram showing the configuration of an example of an image sensor applicable to each embodiment of the present disclosure. In FIG. 2, the image sensor 100 includes a pixel array unit 111 in which pixels 101 are arranged in a matrix, and a drive circuit for driving each pixel 101 included in the pixel array unit 111 as a peripheral circuit of the pixel array unit 111. More specifically, the drive circuit includes a vertical drive circuit 112, a column signal processing circuit 113, a horizontal drive circuit 114, an output circuit 115, and a drive control circuit 116.

[0017] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock supplied from outside the imaging device 100, the drive control circuit 116 generates clock signals and control signals that serve as the basis for the operations of the vertical drive circuit 112, column signal processing circuit 113, and horizontal drive circuit 114. The drive control circuit 116 supplies the generated clock signals and control signals to the vertical drive circuit 112, column signal processing circuit 113, and horizontal drive circuit 114.

[0018] The vertical drive circuit 112 is constituted by, for example, a shift register, and sequentially selects and scans each pixel 101 in the pixel array section 111 in the vertical direction row by row. Then, the pixel signal (image signal) based on the current (signal) generated according to the light reception amount in each pixel 101 is sent to the column signal processing circuit 113 via the vertical signal line 117 as a data output line. Note that the vertical signal line 117 is also called a VSL (Vertical Signal Line).

[0019] The column signal processing circuit 113 is arranged, for example, for each column of the pixels 101, and performs signal processing such as noise removal and signal amplification on the image signals output from the pixels 101 in one row by the signals from the black reference pixels for each pixel 101. Note that the black reference pixels are the pixels 101 arranged around the effective pixel region in the pixel array section 111 (not shown). At the output stage of the column signal processing circuit 113, a horizontal selection switch (not shown) is connected and provided between the horizontal signal line 118.

[0020] The horizontal drive circuit 114 is constituted by, for example, a shift register, and sequentially selects each of the column signal processing circuits 113 by sequentially outputting horizontal scanning pulses, and outputs signals from each of the column signal processing circuits 113 to the horizontal signal line 118. The output circuit 115 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 113 via the horizontal signal line 118 and outputs them.

[0021] FIG. 3 is a schematic partial cross-sectional view of pixel 101 as an existing technology. Further, FIG. 4 is a diagram showing an equivalent circuit of pixel 101 shown in FIG. 3. Pixel 101 is a stacked photoelectric conversion element in which a plurality of photoelectric conversion units are stacked. Hereinafter, the configuration of pixel 101 will be described with reference to FIGS. 3 and 4.

[0022] The pixel 101 shown in FIG. 3 includes a plurality of stacked photoelectric conversion units that perform photoelectric conversion respectively. Hereinafter, the photoelectric conversion unit disposed closest to the light-receiving surface in pixel 101 is defined as the first photoelectric conversion unit, and this is set as the uppermost photoelectric conversion unit among the plurality of photoelectric conversion units. In the example of FIG. 3, a second photoelectric conversion unit is disposed below the first photoelectric conversion unit, and a third photoelectric conversion unit is disposed further below.

[0023] The first photoelectric conversion unit includes a photoelectric conversion layer 15, a first electrode 11 located on the first surface side of the photoelectric conversion layer 15 and electrically connected to the photoelectric conversion layer 15, a second electrode 16 located on the second surface opposite to the first surface of the photoelectric conversion layer 15, and a charge storage electrode 12 disposed on the first surface side of the photoelectric conversion layer 15 and spaced apart from the first electrode 11 in a direction parallel to the first surface. Thus, the first electrode 11 and the charge storage electrode 12 are disposed with a gap therebetween by being spaced apart.

[0024] And, pixel 101 further includes a semiconductor substrate (more specifically, a silicon semiconductor layer) 70, and the first photoelectric conversion unit is disposed above the semiconductor substrate 70. Further, it further includes a control unit having a drive circuit provided on the semiconductor substrate 70 and connected to the first electrode 11. Here, the light incident surface of the semiconductor substrate 70 is upward, and the opposite side of the semiconductor substrate 70 is downward. A wiring layer 62 composed of a plurality of wirings is provided below the semiconductor substrate 70.

[0025] Also, at least a first floating diffusion layer FD1 (see FIG. 4) and an amplification transistor TR1 amp (see FIGS. 3 and 4) that constitute the control unit are provided on the semiconductor substrate 70, and the first electrode 11 is connected to the first floating diffusion layer FD1 and the amplification transistor TR1 ampis connected to the gate section. The semiconductor substrate 70 further includes a reset transistor TR1 that constitutes a control section rst and a selection transistor TR1 sel which are provided (see FIGS. 3 and 4).

[0026] The first floating diffusion layer FD1 is connected to one of the source / drain regions of the reset transistor TR1 rst and one of the source / drain regions of the amplification transistor TR1 amp is connected to one of the source / drain regions of the selection transistor TR1 sel and the other source / drain region of the selection transistor TR1 sel is connected to the signal line VSL1 (see FIG. 4). These amplification transistors TR1 amp reset transistor TR1 rst and selection transistor TR1 sel constitute a drive circuit.

[0027] Specifically, the pixel 101 shown in FIG. 3 is a back-illuminated photoelectric conversion element, and more specifically, a stacked photoelectric conversion element, and has a structure in which three photoelectric conversion sections are stacked: a first type of green photoelectric conversion section that is sensitive to green and has a first type of green photoelectric conversion layer that absorbs green light (hereinafter referred to as the first photoelectric conversion section), a second type of blue photoelectric conversion section that is sensitive to blue and has a second type of blue photoelectric conversion layer that absorbs blue light (hereinafter referred to as the second photoelectric conversion section), and a second type of red photoelectric conversion section that is sensitive to red and has a second type of red photoelectric conversion layer that absorbs red light (hereinafter referred to as the third photoelectric conversion section).

[0028] Here, the red photoelectric conversion unit (third photoelectric conversion unit) and the blue photoelectric conversion unit (second photoelectric conversion unit) are provided in the semiconductor substrate 70, and the second photoelectric conversion unit is located closer to the light incident side than the third photoelectric conversion unit. Also, the green photoelectric conversion unit (first photoelectric conversion unit) is provided above the blue photoelectric conversion unit (second photoelectric conversion unit). A single pixel is configured by the stacked structure of the first photoelectric conversion unit, the second photoelectric conversion unit, and the third photoelectric conversion unit. A color filter is not provided.

[0029] In the first photoelectric conversion unit, a first electrode 11 and a charge storage electrode 12 are formed separately on the interlayer insulating layer 81. The interlayer insulating layer 81 and the charge storage electrode 12 are covered by an insulating layer 82. A photoelectric conversion layer 15 is formed on the insulating layer 82, and a second electrode 16 is formed on the photoelectric conversion layer 15. A protective layer 83 is formed on the entire surface including the second electrode 16, and an on-chip micro lens 90 is provided on the protective layer 83.

[0030] The first electrode 11, the charge storage electrode 12, and the second electrode 16 are composed of, for example, a transparent electrode made of ITO (Indium Tin Oxide). The photoelectric conversion layer 15 is composed of a layer (organic film) containing at least a well-known organic photoelectric conversion material having sensitivity to green (for example, organic materials such as rhodamine-based dyes, merocyanine-based dyes, and quinacridone). Also, the photoelectric conversion layer 15 may further include a material layer suitable for charge storage. That is, a material layer suitable for charge storage may be further formed between the photoelectric conversion layer 15 and the first electrode 11 (for example, within the connection portion 67).

[0031] The interlayer insulating layer 81, the insulating layer 82, and the protective layer 83 are composed of well-known insulating materials (for example, SiO2 or SiN). The photoelectric conversion layer 15 and the first electrode 11 are connected by a connection portion 67 provided in the insulating layer 82. The photoelectric conversion layer 15 extends within the connection portion 67. That is, the photoelectric conversion layer 15 extends within an opening 84 provided in the insulating layer 82 and is connected to the first electrode 11.

[0032] The charge storage electrode 12 is connected to the drive circuit. Specifically, the charge storage electrode 12 is connected to the vertical drive circuit 112 that constitutes the drive circuit through a connection hole 66, a pad portion 64, and a wiring V (not shown) provided in the interlayer insulating layer 81. OA (not shown).

[0033] The size (area) of the charge storage electrode 12 is larger than that of the first electrode 11. When the size of the charge storage electrode 12 is area S2 and the size of the first electrode 11 is area S1, the relationship between the areas S1 and S2 is preferably as expressed by the following formula (1). 4 ≦ S2 / S1…(1)

[0034] FIG. 5 is a schematic diagram showing an arrangement example of the first electrode 11 and the charge storage electrode 12 in the pixel 101. FIG. 5 schematically shows the state of the pixel 101 as viewed from the light-receiving surface side. In the example of FIG. 5, the first electrode 11 is arranged along one side of the pixel 101 having a rectangular shape, and the charge storage electrode 12 is arranged spaced apart from the first electrode 11, that is, with a gap of a predetermined width with respect to the first electrode 11. In the example of FIG. 5, the first electrode 11 and the charge storage electrode 12 are formed and arranged such that the area S1 of the first electrode 11 and the area S2 of the charge storage electrode 12 satisfy the relationship of the following formula (2). S2 / S1 = 8 …(2)

[0035] Note that the relationship between the areas S1 and S2 is not limited to the relationships shown in the above formulas (1) and (2).

[0036] FIG. 6 is a schematic diagram showing an arrangement example of the second electrode 16 in the image sensor 100. FIG. 6 schematically shows a part of the pixel array portion 111 as viewed obliquely from the light-receiving surface side. The second electrode 16 is a common electrode provided commonly for each pixel 101 as shown in FIG. 6. Also, a wiring V provided for each row of the pixel array portion 111 below the charge storage electrode 12 OA is connected to the charge storage electrode 12 of each pixel 101 arranged in the row.

[0037] By controlling the voltages applied to the first electrode 11, the charge storage electrode 12, and the second electrode 16 to be predetermined, it is possible to realize the storage and transfer of charges generated by photoelectric conversion in the first photoelectric conversion unit.

[0038] For example, during the exposure of the first photoelectric conversion unit, a negative bias voltage is applied to the second electrode 16, and a positive bias voltage is applied to the charge storage electrode 12 from wiring V OA . Also, a predetermined positive bias voltage is applied to the first electrode 11 as well. Thereby, a potential barrier is generated in the gap between the first electrode 11 and the charge storage electrode 12, and the charges generated by photoelectric conversion are stored between the charge storage electrode 12 and the second electrode 16.

[0039] In response to the end of the exposure, a negative bias voltage is applied to the charge storage electrode 12 from wiring V OA so that the potential corresponding to the charge storage electrode 12 is made higher than the potential barrier in the gap between the first electrode 11 and the charge storage electrode 12. Thereby, the charges stored between the charge storage electrode 12 and the second electrode 16 flow into the first electrode 11 over the potential barrier. The charges flowing into the first electrode 11 are supplied as a current to a predetermined wiring of the wiring layer 62 through the contact hole portion 61 described later.

[0040] Next, the configuration of the semiconductor substrate 70 will be described in more detail. A pixel isolation region 71 is formed on the side of the first surface (front surface) 70A of the semiconductor substrate 70, and an oxide film 72 is formed on the first surface 70A of the semiconductor substrate 70. Further, on the first surface side of the semiconductor substrate 70, a reset transistor TR1 rst that constitutes a control unit of the first photoelectric conversion unit, an amplification transistor TR1 amp and a selection transistor TR1 sel are provided, and further, a first floating diffusion layer FD1 is provided.

[0041] Reset transistor TR1 rstIt is composed of a gate portion 51, a channel formation region 51A, and source / drain regions 51B and 51C. Reset transistor TR1 rst The gate portion 51 of the reset transistor TR1 is connected to the reset line RST1 rst One of the source / drain regions 51C of the reset transistor TR1 also serves as the first floating diffusion layer FD1, and the other source / drain region 51B is connected to the power supply V DD (see FIG. 4).

[0042] The first electrode 11 is connected to one of the source / drain regions 51C (the first floating diffusion layer FD1) of the reset transistor TR1 through a connection hole 65 provided in the interlayer insulating layer 81, a pad portion 63, a semiconductor substrate 70, a contact hole portion 61 formed in the interlayer insulating layer 76, and a wiring layer 62 formed in the interlayer insulating layer 76 rst is connected to the source / drain region 51C (the first floating diffusion layer FD1).

[0043] Amplification transistor TR1 amp is composed of a gate portion 52, a channel formation region 52A, and source / drain regions 52B and 52C. The gate portion 52 is connected to the first electrode 11 and one of the source / drain regions 51C (the first floating diffusion layer FD1) of the reset transistor TR1 through the wiring layer 62 rst One of the source / drain regions 52B shares a region with the other source / drain region 51B that constitutes the reset transistor TR1 and is connected to the power supply V rst is connected to the power supply V DD (see FIG. 4).

[0044] Selection transistor TR1 selIt is composed of a gate portion 53, a channel formation region 53A, and source / drain regions 53B and 53C. The gate portion 53 is connected to a selection line SEL1 (see FIG. 4). Also, one of the source / drain regions 53B shares a region with the other source / drain region 52C that constitutes the amplification transistor TR1amp, and the other source / drain region 53C is connected to a vertical signal line 117 (see FIG. 2). In this case, the vertical signal line 117 corresponds to VSL1 in FIG. 4.

[0045] The second photoelectric conversion unit includes an n-type semiconductor region 41 provided on the semiconductor substrate 70 as a photoelectric conversion layer 400. A transfer transistor TR2 composed of a vertical transistor trs has a gate portion 45 that extends to the n-type semiconductor region 41 and is connected to a transfer gate line TG2 (see FIG. 4). Also, in the region 45C of the semiconductor substrate 70 near the gate portion 45 of the transfer transistor TR2 trs a second floating diffusion layer FD2 (see FIG. 4) is provided. The charges accumulated in the n-type semiconductor region 41 are read out to the second floating diffusion layer FD2 through a transfer channel formed along the gate portion 45.

[0046] In the second photoelectric conversion unit, further, on the first surface side of the semiconductor substrate 70, a reset transistor TR2 rst that constitutes a control portion of the second photoelectric conversion unit, an amplification transistor TR2 amp and a selection transistor TR2 sel are provided.

[0047] The reset transistor TR2 rst is composed of a gate portion, a channel formation region, and source / drain regions. The gate portion of the reset transistor TR2 rst is connected to a reset line RST2, and one of the source / drain regions of the reset transistor TR2 rst is connected to a power supply V DD and the other source / drain region also serves as the second floating diffusion layer FD2 (see FIG. 4).

[0048] Amplifying transistor TR2 amp is composed of a gate portion, a channel formation region, and a source / drain region. The gate portion is connected to the other source / drain region (the second floating diffusion layer FD2, see Fig. 4) of the reset transistor TR2 rst . Also, one of the source / drain regions shares the region with one of the source / drain regions constituting the reset transistor TR2 rst and is connected to the power supply V DD (see Fig. 4).

[0049] Selection transistor TR2 sel is composed of a gate portion, a channel formation region, and a source / drain region. The gate portion is connected to the selection line SEL2 (see Fig. 4). Also, one of the source / drain regions shares the region with the other source / drain region constituting the amplifying transistor TR2 amp and the other source / drain region is connected to the vertical signal line 117 (see Fig. 2). In this case, the vertical signal line 117 corresponds to VSL2 in Fig. 4.

[0050] The third photoelectric conversion unit includes an n-type semiconductor region 43 provided in the semiconductor substrate 70 as a photoelectric conversion layer 401. The gate portion 46 of the transfer transistor TR trs is connected to the transfer gate line TG3 (see Fig. 4). Also, in the region 46C of the semiconductor substrate 70 near the gate portion 46 of the transfer transistor TR3 trs , a third floating diffusion layer FD3 (see Fig. 4) is provided. The charges accumulated in the n-type semiconductor region 43 are read out to the third floating diffusion layer FD3 through the transfer channel 46A formed along the gate portion 46.

[0051] In the third photoelectric conversion unit, further, on the first surface side of the semiconductor substrate 70, a reset transistor TR3 rst constituting the control portion of the third photoelectric conversion unit, an amplifying transistor TR3 amp and a selection transistor TR3 sel are provided.

[0052] Reset transistor TR3 rst is composed of a gate portion, a channel formation region, and a source / drain region. The reset transistor TR3 rst has its gate portion connected to the reset line RST3, and the reset transistor TR3 rst has one of its source / drain regions connected to the power supply V DD and the other source / drain region also serves as the third floating diffusion layer FD3 (see FIG. 4).

[0053] Amplification transistor TR3 amp is composed of a gate portion, a channel formation region, and a source / drain region. The gate portion is connected to the other source / drain region (the third floating diffusion layer FD3) of the reset transistor TR3 rst One of its source / drain regions shares a region with one of the source / drain regions that make up the reset transistor TR3 rst and is connected to the power supply V DD (see FIG. 4).

[0054] Selection transistor TR3 sel is composed of a gate portion, a channel formation region, and a source / drain region. The gate portion is connected to the selection line SEL3 (see FIG. 4). One of its source / drain regions shares a region with the other source / drain region that makes up the amplification transistor TR3 amp and the other source / drain region is connected to the vertical signal line 117 (see FIG. 2). In this case, the vertical signal line 117 corresponds to VSL3 in FIG. 4.

[0055] The above-described reset lines RST1, RST2, and RST3, selection lines SEL1, SEL2, and SEL3, and transfer gate lines TG2 and TG3 are connected to the vertical drive circuit 112 that constitutes the drive circuit. Also, each of the vertical signal lines 117 (VSL1, VSL2, and VSL3) of the first photoelectric conversion unit, the second photoelectric conversion unit, and the third photoelectric conversion unit is connected to the column signal processing circuit 113 that constitutes the drive circuit.

[0056] A p + layer 44 is provided between the n-type semiconductor region 43 and the surface 70A of the semiconductor substrate 70, suppressing the generation of dark current. A p + layer 42 is formed between the n-type semiconductor region 41 and the n-type semiconductor region 43. Further, a part of the side surface of the n-type semiconductor region 43 is surrounded by the p + layer 42. On the back surface 70B side of the semiconductor substrate 70, a p + layer 73 is formed. In the part where the contact hole portion 61 inside the semiconductor substrate 70 is to be formed from the p + layer 73, an HfO2 film 74, which is a film having a negative fixed charge, and an insulating film 75 are formed. Although wirings are formed over a plurality of layers in the interlayer insulating layer 76, they are omitted in FIG. 3.

[0057] Next, with reference to FIG. 7, the operation of the above-described first photoelectric conversion unit will be described. Here, the potential of the first electrode 11 is made higher than the potential of the second electrode 16. That is, for example, the first electrode 11 is set to a positive potential and the second electrode 16 is set to a negative potential, and photoelectric conversion occurs in the photoelectric conversion layer 15, and electrons are read out to the floating diffusion layer. In the case where the first electrode 11 is set to a negative potential and the second electrode 16 is set to a positive potential, and holes generated based on photoelectric conversion in the photoelectric conversion layer 15 are read out to the floating diffusion layer, the potential levels described below may be reversed.

[0058] The meanings of the respective reference numerals used in FIG. 7 are as follows. (1) PA: The potential at point PA in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 (see the lower left diagram of FIG. 7). (2) PB: Potential at point PB in the region of the photoelectric conversion layer 15 facing the region located in the middle between the charge storage electrode 12 and the first electrode 11 (see the lower left figure in Fig. 7). (3) FD: Potential in the first floating diffusion layer FD1. (4) VOA: Potential at the charge storage electrode 12. (5) RST: Reset transistor TR1 rst Potential at the gate portion 51 thereof. (6) VDD: Potential of the power supply V DD thereof.

[0059] The charge storage period will be described with reference to the upper left figure in Fig. 7. During the charge storage period, from the drive circuit, a potential V 11 is applied to the first electrode 11, and a potential V 12 is applied to the charge storage electrode 12. Photoelectric conversion occurs in the photoelectric conversion layer 15 due to the light incident on the photoelectric conversion layer 15. The holes generated by the photoelectric conversion are sent to the drive circuit through the wiring V OU (not shown) from the second electrode 16.

[0060] On the other hand, since the potential of the first electrode 11 is made higher than the potential of the second electrode 16, in other words, for example, if a positive potential is applied to the first electrode 11 and a negative potential is applied to the second electrode 16, then V 12 ≥V 11 , preferably, V 12 >V 11 . As a result, the electrons (charges) generated by the photoelectric conversion are attracted to the charge storage electrode 12 and remain in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12. That is, charges are accumulated in the photoelectric conversion layer 15. Since V 12 >V 11 , the charges generated inside the photoelectric conversion layer 15 do not move toward the first electrode 11. As time elapses during the photoelectric conversion, the potential in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 becomes a more negative value.

[0061] In the latter stage of the charge accumulation period, a reset operation is performed. The upper middle diagram of FIG. 7 schematically shows an example of the state of each part during the reset operation. By the reset operation, the potential FD of the first floating diffusion layer FD1 is reset, and the potential of the first floating diffusion layer FD1 becomes the potential VDD of the power supply V DD .

[0062] After the completion of the reset operation, charge reading is performed. The upper right diagram of FIG. 7 schematically shows the state of each part during the charge reading, that is, the transfer of charges from the charge storage electrode 12 to the first electrode 11. During the charge transfer period, a potential V 21 is applied to the first electrode 11, and a potential V 22 is applied to the charge storage electrode 12. Here, let V 22 <V 21 . As a result, the charges remaining in the region of the photoelectric conversion layer 15 facing the charge storage electrode 12 are read out to the first electrode 11, and further read out from the first electrode 11 to the first floating diffusion layer FD1 through the contact hole portion 61. That is, the charges accumulated in the photoelectric conversion layer 15 are read out to the control unit.

[0063] Thus, a series of operations such as charge accumulation, reset operation, and charge transfer in the first photoelectric conversion unit are completed. The lower right diagram of FIG. 7 shows an example of the changes in the respective potentials VOA, PA, PB, FD, and RST during each operation.

[0064] After electrons are read out to the first floating diffusion layer FD1, the operation of the amplification transistor TR1 amp and the selection transistor TR1 sel is the same as the operation of these existing transistors. Also, a series of operations such as charge accumulation, reset operation, and charge transfer in the second photoelectric conversion unit and the third photoelectric conversion unit are the same as a series of operations such as existing charge accumulation, reset operation, and charge transfer. Also, the reset noise of the first floating diffusion layer FD1 can be removed by correlated double sampling (CDS) processing in the same manner as in the prior art.

[0065] (1-0-3. Relationship between the electrode configuration according to the prior art and the amount of stored charge) Next, with reference to FIG. 8, the relationship between the electrode configuration according to the prior art and the amount of stored charge will be schematically described. Section (a) of FIG. 8 corresponds to the electrode configuration described with reference to FIG. 5. The first electrode 11 is provided along one side of the pixel 101 having a rectangular shape, and the charge storage electrode 12 is provided with a predetermined gap with respect to the first electrode 11.

[0066] As described above, in the configuration of this section (a), a gap 14 is provided between the first electrode 11 and the charge storage electrode 12, and a potential barrier is generated corresponding to the position of the gap 14 by applying a bias with the second electrode 16. At this time, by widening the gap 14, the amount of stored charge Qs accumulated according to the charge storage electrode 12 increases. On the other hand, when the gap 14 is widened, the area of the charge storage electrode 12 becomes smaller, that is, the sensitivity region becomes smaller, and the sensitivity decreases.

[0067] Section (b) of FIG. 8 is an example in which a transfer gate electrode 13 is provided between the first electrode 11 and the charge storage electrode 12. In this case, the potential barrier between the first electrode 11 and the charge storage electrode 12 is generated by applying a voltage to the transfer gate electrode 13. In the configuration of this section (b), since the potential barrier is formed by applying a voltage to the transfer gate electrode 13, a higher potential barrier can be generated, and it is easy to increase the amount of stored charge Qs accumulated according to the charge storage electrode 12. On the other hand, by providing the transfer gate electrode 13, the area of the charge storage electrode 12 becomes smaller, and the sensitivity decreases.

[0068] [2. First Embodiment] (2-0-1. Outline of the imaging device according to the first embodiment) Next, the first embodiment will be described. First, the imaging device according to the first embodiment will be schematically described. FIG. 9 is a schematic diagram for explaining the electrode configuration and operation in the pixel 101 according to the first embodiment. In FIG. 9, section (a) is a schematic diagram of the pixel according to the first embodiment as viewed from the upper surface (light-receiving surface) side, and section (b) is a schematic diagram showing a cross-section of the pixel. Further, section (c) is a diagram schematically showing the state of the potential Pot corresponding to sections (a) and (b).

[0069] As shown in section (b) of FIG. 9, in the pixel 101 according to the first embodiment, the first electrode 11 and the charge storage electrode 12 are spaced apart and arranged with a gap 14 therebetween, and the barrier forming electrode 200, which is the third electrode, is arranged on the lower surface side (the surface opposite to the light-receiving surface) of the first electrode 11 and the charge storage electrode 12. In other words, the barrier forming electrode 200 is arranged between the first electrode 11 and the charge storage electrode 12 and the semiconductor substrate 70. At this time, the barrier forming electrode 200 is arranged without being electrically connected to the first electrode 11 and the charge storage electrode 12. Further, the barrier forming electrode 200 is arranged at a position having an overlapping portion with the gap 14 between the first electrode 11 and the charge storage electrode 12 in a direction perpendicular to the first surface of the photoelectric conversion layer 15.

[0070] In the example of FIG. 9, as shown in section (b), the barrier forming electrode 200 is arranged so that its width is wider than the width 14a of the gap 14 and has an overlapping portion over the entire width of the gap 14. This is not limited to this example, and the barrier forming electrode 200 may be arranged so as to have an overlapping portion with a part of the gap 14. Further, the barrier forming electrode 200 may be arranged so that its width is narrower than the width 14a of the gap 14 and the overlapping portion is included in the gap 14. In this case, the barrier forming electrode 200 will not have an overlapping portion with the first electrode 11 and the charge storage electrode 12.

[0071] In the pixel 101 configured as described above, a bias voltage is applied to the barrier forming electrode 200 to increase the potential barrier in the gap 14. As schematically shown in section (c) of FIG. 9, a predetermined bias voltage is applied to the barrier forming electrode 200, and the potential Pot in the gap 14 portion is set to a potential Pot(b) higher than the potential Pot(a) of the gap 14 portion when no bias voltage is applied to the barrier forming electrode 200, thereby generating a potential barrier due to the potential Pot(b). In this case, the bias voltage applied to the barrier forming electrode 200 is a negative bias voltage that is lower than the voltages applied to the first electrode 11 and the charge storage electrode 12.

[0072] In the first embodiment, as described above, the barrier forming electrode 200 is arranged so as to have an overlapping portion with the gap 14 in a direction facing the lower surface with respect to the gap 14 between the first electrode 11 and the charge storage electrode 12. Then, by applying a negative bias to the barrier forming electrode 200, a higher potential barrier can be generated at the position corresponding to the gap 14. The gap 14 is assumed to have a width 14a such that at least the first electrode 11 and the charge storage electrode 12 do not contact each other.

[0073] The pixel 101 to which the first embodiment having such a configuration is applied can secure the accumulated charge amount Qs while maintaining a wide sensitivity region in the photoelectric conversion unit having a layer (organic film) containing an organic photoelectric conversion material.

[0074] (2-0-2. More detailed configuration example of the imaging device according to the first embodiment) Next, a more detailed configuration example of the imaging device according to the first embodiment will be described. FIG. 10 is a schematic partial cross-sectional view of the pixel 101 according to the first embodiment.

[0075] FIG. 10 is a diagram corresponding to FIG. 3 described above, in which the HfO2 film 74 and the insulating film 75 in FIG. 3 are shown together as an insulating film 700. Further, in FIG. 10, each transistor and the like disposed on the first surface 70A of the semiconductor substrate 70 are omitted. Furthermore, in FIG. 10, an accumulation transfer layer 800 made of a material suitable for charge accumulation is disposed on the surface of the photoelectric conversion layer 15 opposite to the surface on which the second electrode 16 is disposed.

[0076] In the example of FIG. 10, the barrier forming electrode 200 has an overlapping portion in a direction toward the semiconductor substrate 70 with respect to the gap 14 between the first electrode 11 and the charge accumulation electrode 12, and is disposed in the same layer as the pad portions 63 and 64. Also, the overlapping portion of the barrier forming electrode 200 with respect to the gap 14 is set to a width that is included within the gap 14. That is, in the example of FIG. 10, the barrier forming electrode 200 is formed and disposed so as not to have an overlapping portion in a direction toward the semiconductor substrate 70 with respect to the first electrode 11 and the charge accumulation electrode 12. The barrier forming electrode 200 is connected to a wiring in the interlayer insulating layer 81, for example, in the same manner as the pad portion 64, and a fixed bias voltage is applied thereto via the wiring.

[0077] Note that, as described above, the arrangement of the barrier forming electrode 200 is not limited to an arrangement that is completely included in the gap 14 or that completely includes the gap 14. That is, the barrier forming electrode 200 may have an overlapping portion in a direction toward the semiconductor substrate 70 with respect to the gap 14, and a part may protrude from the gap 14, for example, as shown in another arrangement example in FIG. 11.

[0078] Hereinafter, in order to avoid complexity, “having an overlapping portion in a direction toward the semiconductor substrate 70 with respect to the gap 14 (or the first electrode 11, the charge accumulation electrode 12)” will be described as “having an overlapping portion with respect to the gap 14 (or the first electrode 11, the charge accumulation electrode 12)”.

[0079] (2-0-3. Configuration example of the electrode according to the first embodiment) Next, some arrangement examples of the first electrode 11, the charge storage electrode 12, and the barrier formation electrode 200 applicable to the first embodiment will be described with reference to FIGS. 12A to 16B.

[0080] The pixel 101a shown in FIG. 12A is an example of a pixel 101a in which, as shown in the pattern 300a at the left end, the first electrode 11 is arranged along one side of the rectangular pixel 101a, and the charge storage electrode 12 is arranged with a gap 14 opened with respect to the first electrode 11. In this case, the gap 14 is formed between the side of the first electrode 11 that faces the side in contact with the side of the pixel 101a and the side of the charge storage electrode 12 that is closest to the side.

[0081] Hereinafter, a pattern in which the first electrode 11 is arranged along one side of the pixel 101a, like this pattern 300a, is called a one-character pattern.

[0082] The pattern 300b in FIG. 12A is an example in which the barrier formation electrode 200 is arranged so as to have an overlapping portion 210 with each of the first electrode 11 and the charge storage electrode 12 with respect to the arrangement of the pattern 300a. In the pattern 300b, the barrier formation electrode 200 has an overlapping portion with respect to the entire width of the gap 14.

[0083] The pattern 300c in FIG. 12A is an example in which the barrier formation electrode 200 is arranged so as to have an overlapping portion 210 with respect to the charge storage electrode 12 with respect to the arrangement of the pattern 300a. In the pattern 300c, the barrier formation electrode 200 has an overlapping portion on the charge storage electrode 12 side with respect to the gap 14 and does not have an overlapping portion on the first electrode 11 side. The pattern 300d in FIG. 12A is an example in which the barrier formation electrode 200 is arranged so as to have an overlapping portion 210 with respect to the first electrode 11 with respect to the arrangement of the pattern 300a. In the pattern 300c, the barrier formation electrode 200 has an overlapping portion on the first electrode 11 side with respect to the gap 14 and does not have an overlapping portion on the charge storage electrode 12 side.

[0084] The pattern 300e in Fig. 12A is an example in which the barrier forming electrode 200 is arranged so as not to have an overlapping portion with either the first electrode 11 or the charge storage electrode 12 with respect to the arrangement of the pattern 300a. In the pattern 300e, the overlapping portion with respect to the gap 14 of the barrier forming electrode 200 is included in the gap 14.

[0085] Fig. 12B is an example of a pixel 101b in which the pixel isolation electrode 220 is arranged with respect to the pattern 300a in Fig. 12A as shown in the pattern 301a at the left end. The pixel isolation electrode 220 is arranged at the outer edge portion of the pixel 101b, and when a predetermined voltage (for example, a negative bias) is applied, the pixel 101b is electrically separated from the adjacent pixel 101b. In the case of a single-character pattern, the pixel isolation electrode 220 is not arranged on the side where the first electrode 11 is arranged.

[0086] The patterns 301b, 301c, 301d, and 301e in Fig. 12B respectively correspond to the patterns 300b, 300c, 300d, and 300e described with reference to Fig. 12A. That is, the pattern 301b is an example in which the barrier forming electrode 200 is arranged so as to have an overlapping portion 210 with each of the first electrode 11 and the charge storage electrode 12 with respect to the arrangement of the pattern 301a. The pattern 301c is an example in which the barrier forming electrode 200 is arranged so as to have an overlapping portion 210 with respect to the charge storage electrode 12 with respect to the arrangement of the pattern 301a. The pattern 301d is an example in which the barrier forming electrode 200 is arranged so as to have an overlapping portion 210 with respect to the first electrode 11 with respect to the arrangement of the pattern 301a. The pattern 301e is an example in which the barrier forming electrode 200 is arranged so as not to have an overlapping portion with either the first electrode 11 or the charge storage electrode 12 with respect to the arrangement of the pattern 301a.

[0087] FIG. 13A shows an example of a pixel 101c in which a first electrode 11 is disposed at one corner of a rectangular pixel 101c and a charge storage electrode 12 is disposed with a gap 14 therebetween as shown in the pattern 302a at the left end. In this case, the gap 14 is formed between the corner of the first electrode 11 that faces the corner in contact with the corner of the pixel 101c and the corner of the charge storage electrode 12 that is closest to the said corner. That is, in this case, the gap 14 is formed in a diagonal direction with respect to the rectangular shape of the pixel 101c.

[0088] Hereinafter, a pattern in which the first electrode 11 is disposed at the corner of the pixel 101c as in the pattern 302a is referred to as a corner arrangement pattern.

[0089] The pattern 302b in FIG. 13A is an example in which a barrier forming electrode 200 is disposed so as to have overlapping portions 210 with respect to each of the first electrode 11 and the charge storage electrode 12, with respect to the arrangement of the pattern 302a. In the pattern 302b, the barrier forming electrode 200 has an overlapping portion with respect to the entire width of the gap 14.

[0090] The pattern 302c in FIG. 13A is an example in which a barrier forming electrode 200 is disposed so as to have an overlapping portion 210 with respect to the charge storage electrode 12, with respect to the arrangement of the pattern 302a. In the pattern 302c, the barrier forming electrode 200 has an overlapping portion on the charge storage electrode 12 side with respect to the gap 14 and does not have an overlapping portion on the first electrode 11 side. The pattern 302d in FIG. 13A is an example in which a barrier forming electrode 200 is disposed so as to have an overlapping portion 210 with respect to the first electrode 11, with respect to the arrangement of the pattern 302a. In the pattern 302c, the barrier forming electrode 200 has an overlapping portion on the first electrode 11 side with respect to the gap 14 and does not have an overlapping portion on the charge storage electrode 12 side.

[0091] The pattern 302e in FIG. 13A is an example in which a barrier forming electrode 200 is disposed so as not to have an overlapping portion with respect to either the first electrode 11 or the charge storage electrode 12, with respect to the arrangement of the pattern 302a. In the pattern 302e, the overlapping portion of the barrier forming electrode 200 with respect to the gap 14 is included within the gap 14.

[0092] FIG. 13B shows an example of a pixel 101d in which a pixel separation electrode 220 is arranged with respect to the pattern 302a of FIG. 13A as shown in the pattern 303a at the left end. In the corner arrangement pattern, no pixel separation electrode 220 is provided around the corner where the first electrode 11 is arranged.

[0093] Patterns 303b, 303c, 303d, and 303e in FIG. 13B respectively correspond to patterns 302b, 302c, 302d, and 302e described with reference to FIG. 13A. That is, pattern 303b is an example of a pixel 101d in which the barrier forming electrode 200 is arranged so as to have an overlapping portion 210 with each of the first electrode 11 and the charge storage electrode 12 with respect to the arrangement of pattern 303a. Pattern 303c is an example in which the barrier forming electrode 200 is arranged so as to have an overlapping portion 210 with the charge storage electrode 12 with respect to the arrangement of pattern 303a. Pattern 303d is an example in which the barrier forming electrode 200 is arranged so as to have an overlapping portion 210 with the first electrode 11 with respect to the arrangement of pattern 303a. Pattern 303e is an example in which the barrier forming electrode 200 is arranged so as not to have an overlapping portion with either the first electrode 11 or the charge storage electrode 12 with respect to the arrangement of pattern 303a.

[0094] FIG. 14A is a diagram showing an example of the arrangement of the barrier forming electrode 200 when a plurality of pixels 101 share one first electrode 11 in a single-character pattern pixel 101. In FIGS. 14A, 14B, 15A, 15B, 16A, and 16B described later, the horizontal direction of the figure is the row in the pixel array section 111, and the vertical direction is the column.

[0095] As shown in the pattern 304a at the upper left of FIG. 14A, four pixels 101e 11 , 101e 12 , 101e 13 and 101e 14 are in contact at one point, and one first electrode 11a is shared. Similarly, four pixels 101e 21 , 101e 22, 101e 23 and 101e 24 wherein one first electrode 11b is shared. That is, in pattern 304a, one first electrode 11 is shared with four pixels 101 in contact at one point as a sharing unit. In this way, when one first electrode 11 is shared among a plurality of pixels 101, the charge reading from the charge storage electrode 12 of each pixel 101 is performed, for example, with a time shift for each pixel 101.

[0096] In pattern 304a, in this case, all the pixels 101e 11 , 101e 12 , 101d 21 , 102d 22 , … arrayed in one row in the pixel array unit 111 row(a) the barrier forming electrode 200 13 , 101e 14 , 101e 23 , 101d 24 , 102d row(b) is shared. Similarly, in 101e

[0097] the barrier forming electrode 200 according to this first embodiment row(a) and 200 row(b) have voltages applied thereto fixed, so that such sharing among the pixels 101 is enabled. Taking pixels 101e 11 ~101e 14 as an example, by fixing the potentials of the barrier forming electrodes 200 row(a) and 200 row(b) and selectively controlling the charge storage electrode 12 of the target pixel among each of the pixels 101e 11 , 101e 12 , 101e 13 and 101e 14 the charge can be read from the charge storage electrode 12.

[0098] Note that in pattern 304a, the barrier forming electrodes 200 row(a) and 200 row(b)Although it is shown that there is no overlapping portion with each of the first electrodes 11 and each of the charge storage electrodes 12, this is not limited to this example. That is, the barrier forming electrode 200 row(a) and 200 row(b) may have an overlapping portion with each of the first electrodes 11 and each of the charge storage electrodes 12, or may have an overlapping portion with only one of the first electrodes 11 and each of the charge storage electrodes 12.

[0099] In pattern 304b of FIG. 14A, which is a single-character pattern, when the first electrode 11 is shared by four pixels 101 that are in contact at one point, all the pixels 101e 11 , 101e 12 , 101d 21 , 102d 22 , …, and the pixel 101e 13 , 101e 14 , 101d 23 , 102d 24 , … in the pixel array portion 111 share one barrier forming electrode 200 row(2) . That is, in pattern 304b, in the pixel array portion 111, every two rows share the barrier forming electrode 200 row(2) .

[0100] Note that in pattern 304b, although the barrier forming electrode 200 row(2) is shown to have no overlapping portion with each of the first electrodes 11 and each of the charge storage electrodes 12, this is not limited to this example. That is, the barrier forming electrode 200 row(2) may have an overlapping portion with each of the first electrodes 11 and each of the charge storage electrodes 12, or may have an overlapping portion with only one of the first electrodes 11 and each of the charge storage electrodes 12.

[0101] In the pattern 304c of FIG. 14A, which is a single-character pattern, when one first electrode 11 is shared with four pixels 101 that are in contact at one point as a sharing unit, across the sharing unit of the pixels, one barrier-forming electrode 200 is shared by a plurality of pixels 101. For example, a first sharing unit that shares one first electrode 11a is the pixels 101e 11 ~102e 14 Let it be. Similarly, a second sharing unit that shares one first electrode 11b is the pixels 101e 21 ~102e 24 Let it be. In this case, across the first sharing unit and the second sharing unit, the pixels 101e 12 、101e 21 、101e 14 And 101e 23 At one point of contact, share one barrier-forming electrode 200 cen .

[0102] The pixels 101e 11 And 101e 13 Similarly, two pixels 101 that are adjacent to the left and in contact at one point (not shown) and, across the sharing unit, share the barrier-forming electrode 200 rht . Also, the pixels 101e 22 And 101e 24 Similarly, two pixels 101 that are adjacent to the right and in contact at one point (not shown) and, across the sharing unit, share the barrier-forming electrode 200 lft .

[0103] Note that in the pattern 304c, for example, the barrier-forming electrode 200 cen Is shown to have an overlapping portion with the first electrodes 11a and 11b and not to have an overlapping portion with the upper and lower charge storage electrodes 12, but this is not limited to this example. For example, the barrier-forming electrode 200cen may have overlapping portions with the first electrodes 11a and 11b and with the upper and lower charge storage electrodes 12, respectively.

[0104] In the pattern 304d of FIG. 14A, which is a single-character pattern, when the first electrode 11 is shared by four pixels 101 that are in contact at one point, all the pixels 101e arranged in two adjacent columns in the pixel array section 111 12 , 101e 14 , 101d 21 , 102d 23 , … share one barrier forming electrode 200 col(a) . That is, in the pattern 304d, in the pixel array section 111, every two columns share the barrier forming electrode 200 col(a) respectively.

[0105] In this case, the barrier forming electrode 200 col(a) has a vertical portion arranged in the column direction between adjacent charge storage electrodes 12, and a protruding portion extending from the vertical portion and arranged in the gap 14 between the first electrode 11 and the charge storage electrode 12 in one pixel 101. This protruding portion becomes a portion that contributes to the generation of a potential barrier at a position corresponding to the gap 14 between the first electrode 11 and the charge storage electrode 12.

[0106] Similarly, for the pixels 101e arranged in one column 11 , 101e 13 , …, each pixel 101 arranged in the column adjacent to the left side of these pixels 101e 11 , 101e 13 , … shares the barrier forming electrode 200 col(c) . Also, for the pixels 101e arranged in one column 22 , 101e 24 , …, each pixel 101 arranged in the column adjacent to the right side of these pixels 101e 22 , 101e 24 , … shares the barrier forming electrode 200 col(b) .

[0107] Note that in the pattern 304d, although it is shown that each protruding portion of the barrier forming electrode 200 col(a) does not have an overlapping portion with each first electrode 11 and each charge storage electrode 12, this is not limited to this example. That is, the barrier forming electrode 200col(a) Each protruding portion may have an overlapping portion with each of the first electrodes 11 and each charge storage electrode 12, or may have an overlapping portion with one of the first electrodes 11 and each charge storage electrode 12.

[0108] FIG. 14B is a diagram showing pixels 101f 11 ~101f 14 in which a pixel separation electrode 220 is arranged with respect to each of the patterns 304a to 304d of FIG. 14A described above, 21 ~101f 24 ~101f

[0109] In each of the patterns 305a to 305d shown in FIG. 14B, the barrier forming electrode 200 row(a) 、200 row(b) 、200 row(2) 、200 cen 、200 rht 、200 lft 、200 col(a) 、200 col(b) and 200 col(c) has an overlapping portion with the pixel separation electrode 220. Since the pixel separation electrode 220 does not contribute to the generation of the potential barrier between the first electrode 11 and the charge storage electrode 12, this overlapping portion can be ignored.

[0110] FIG. 15A is a diagram showing an arrangement example of the barrier forming electrode 200 when a plurality of pixels 101 share one first electrode 11 in the pixel 101 of the corner arrangement pattern. In FIG. 15A, the pattern 306a is four pixels 101g of the corner arrangement pattern respectively 11, 101g 12 , 101g 13 and 101g 14 is an example of sharing one first electrode 11. In pattern 306a, four pixels 101g 11 ~101g 14 that contact at one point are used as the sharing unit of the first electrode 11, and the first electrode 11 is arranged including the points where these four pixels 101g 11 ~101g 14 contact.

[0111] In the example of FIG. 15A, in pattern 306a which is a corner arrangement pattern, the barrier forming electrode 200 is rhombus-shaped by connecting each barrier forming electrode arranged in the gap 14 between the first electrode 11 and each charge storage electrode 12 of the pixels 101g 11 ~101g 14 respectively.

[0112] Note that in pattern 306a, although the barrier forming electrode 200 is shown not to have an overlapping portion with each first electrode 11 and each charge storage electrode 12, this is not limited to this example. That is, the barrier forming electrode 200 may have an overlapping portion with each first electrode 11 and each charge storage electrode 12 respectively, or may have an overlapping portion with only one of each first electrode 11 and each charge storage electrode 12.

[0113] In pattern 306b of FIG. 15A, which is a corner arrangement pattern, when four pixels 101 that contact at one point share the first electrode 11, all the pixels 101g 11 , 101g 12 , 101g 21 , 102g 22 , …, and the pixels 101g 13 , 101g 14 , 101g 23 , 102g 24 , … in the pixel array section 111 share one barrier forming electrode 200 row . That is, in pattern 306b, in the pixel array section 111, every two rows share one barrier forming electrode 200row is shared.

[0114] Here, in pattern 306b, a plurality of barrier forming electrodes 200 arranged in one row, that is, pixel 101g which is a sharing unit of the first electrode 11 11 ~101g 14 to which the barrier forming electrode 200 shared by pixel 101g 21 ~101g 24 to which the barrier forming electrode 200 shared by pixel 101g row ... are connected by wiring or the like to form one barrier forming electrode 200

[0115] In pattern 306c of FIG. 15A, it is a corner arrangement pattern. When the first electrode 11 is shared by four pixels 101 that are in contact at one point, all the pixels 101g 11 、101g 13 、101g 31 、102g 33 、…, and pixel 101g 12 、101g 14 、101g 32 、102g 34 、… in the pixel array section 111 are arranged in two adjacent columns share one barrier forming electrode 200col. That is, in pattern 306c, in the pixel array section 111, every two columns share the barrier forming electrode 200 col is shared.

[0116] Here, in pattern 306c, a plurality of barrier forming electrodes 200 arranged in the column direction, that is, pixel 101g which is a sharing unit of the first electrode 11 11 ~101g 14 to which the barrier forming electrode 200 shared by pixel 101g 31 ~101g 34 to which the barrier forming electrode 200 shared by pixel 101g colIt is configured in this way. Not limited to this, each barrier forming electrode 200 arranged in a column may be extended and connected to each other barrier forming electrode 200.

[0117] In the above-described patterns 306a, 306b, and 306c, the barrier forming electrode 200 is shown not to have an overlapping portion with each of the first electrodes 11 and each charge storage electrode 12, but this is not limited to this example. That is, the barrier forming electrode 200 may have an overlapping portion with each of the first electrodes 11 and each charge storage electrode 12, or may have an overlapping portion with only one of the first electrodes 11 and each charge storage electrode 12.

[0118] FIG. 15B shows pixels 101h 11 ~101h 14 in which the pixel separation electrodes 220 are arranged with respect to the respective patterns 306a to 306c of FIG. 15A described above, 21 ~101h 24 and examples of the pixels 101h

[0119] In addition, in each of the patterns 307b and 307c shown in FIG. 15B, there is an overlapping portion with the pixel separation electrode 220 in the wiring connecting the respective barrier forming electrodes 200. Since the pixel separation electrode 220 does not contribute to the generation of the potential barrier between the first electrode 11 and the charge storage electrode 12, this overlapping portion can be ignored.

[0120] Here, in each of the patterns 307a to 307d, the periphery of the first electrode 11 is a region where the pixel separation electrode 220 is not provided. That is, in each of the patterns 307a to 307d, the pixels 101h sharing the first electrode 1111 ~101h 14 The pixel separation electrode 220 disposed therein has a shape in which the central portion of the grid formed by the outer peripheral portion of the pixel 101h 11 ~101h 14 is notched.

[0121] (2-0-4. Method of applying voltage to barrier formation electrode according to first embodiment) Next, a method of applying a voltage to the barrier formation electrode 200 according to the first embodiment will be described. For example, in each of the patterns 300b to 300e and 301b to 301e formed by a single-character pattern described with reference to FIGS. 12A and 12B, by sharing or connecting the barrier formation electrode 200 with the pixels 101 in each row or column of the pixel array unit 111, it is possible to apply a voltage from the outer peripheral portion of the pixel array unit 111. This also applies to the patterns 304a, 304b, and 304d, and the patterns 305a, 305b, and 305d described with reference to FIG. 14A.

[0122] Also, in each of the patterns 300b to 300e and 301b to 301e, it is also possible to apply a voltage to the barrier formation electrode 200 by providing a through electrode that penetrates the semiconductor substrate 70 and is connected to the wiring layer 62. This also applies to each of the patterns 302b to 302e and 303b to 303e, which are corner arrangement patterns described with reference to FIGS. 13A and 13B.

[0123] Here, a method of applying a voltage when a barrier formation electrode is shared by a plurality of pixels in a corner arrangement pattern will be described. For example, in the case of an arrangement in which four pixels 101h 11 ~101h 14 share the first electrode 11 in the corner arrangement pattern as in the pattern 307a of FIG. 15B, it may be difficult to directly provide a through electrode to the barrier formation electrode 200. An example of a method of applying a voltage to the barrier formation electrode 200 in such a case will be described with reference to FIGS. 16A to 16C.

[0124] FIG. 16A is a diagram schematically showing a first example of a method of applying a voltage to the barrier forming electrode 200 applicable to the first embodiment. In this first example of the voltage application method, the barrier forming electrode 200 and the pixel isolation electrode 220 are connected, and a voltage is applied to the barrier forming electrode 200 from the pixel isolation electrode 220.

[0125] In the arrangement according to pattern 307a of FIG. 15B shown on the left side of FIG. 16A, the barrier forming electrode 200 is disposed on the lower surface side with respect to the pixel isolation electrode 220. Therefore, as shown on the right side of FIG. 16A, the pixel isolation electrode 220 and the barrier forming electrode 200 are connected via a vertical via 221. In the example of FIG. 16A, the end of the pixel isolation electrode 220 cut out along with the arrangement of the first electrode 11 and the end of the barrier forming electrode 200 obliquely disposed between the first electrode 11 and the charge storage electrode 12 are connected via the vertical via 221. A predetermined voltage of a negative bias is applied to the pixel isolation electrode 220 to electrically isolate it from adjacent pixels. Therefore, by this connection via the vertical via 221, a voltage of a negative bias can be applied to the barrier forming electrode 200.

[0126] FIG. 16B is a diagram schematically showing a second example of a method of applying a voltage to the barrier forming electrode 200 applicable to the first embodiment. In this second example of the voltage application method, a wiring 230 is provided above the semiconductor substrate 70, and a voltage is applied to the barrier forming electrode 200 via this wiring 23. This second example can be applied to, for example, patterns 307b and 307c of FIG. 15B described above.

[0127] FIG. 16C is a diagram schematically showing a third example of a method of applying a voltage to the barrier forming electrode 200 applicable to the first embodiment. In this third example of the voltage application method, a through electrode 240 connected to the wiring layer 62 is used to apply a voltage from the wiring layer 62 to the barrier forming electrode 200 via the through electrode 240. In this case, the through electrode 240 is, for example, each pixel 101h that shares the first electrode 11 11 ~101h 14It is provided at a position where the influence on the operation is small, and the barrier forming electrode 200 and the through electrode 240 are connected by the wiring 231. In the example of FIG. 16C, the through electrode 240 is provided at a predetermined position outside the charge storage electrode 12 in each pixel 101h 11 ~101h 14 among.

[0128] Among the first to third examples of the voltage application method described above, the first example is advantageous over the second and third examples because it does not occupy the surface on which the first electrode 11, the charge storage electrode 12, and the pixel isolation electrode 220 are arranged, and the interference with other electrodes is also small.

[0129] Furthermore, a voltage application method in the case where the barrier forming electrode is shared across a plurality of pixels in a single-character pattern and across the shared unit of the first electrode will be described. In the pattern 305c of FIG. 14B described above, for example, the first shared unit (pixels 101f 11 ~101f 14 ) that shares the first electrode 11a and the second shared unit (pixels 101f 21 ~102f 24 ) that shares the first electrode 11b, the barrier forming electrode 200 cen is shared. In this case, it is difficult to apply a voltage to the barrier forming electrode 200 cen from the outer peripheral portion of the pixel array portion 111, for example, as in the patterns 305a, 305b, and 305d of FIG. 14B.

[0130] FIG. 17 is a diagram schematically showing a fourth example of a voltage application method for a barrier forming electrode applicable to the first embodiment for applying a voltage to this barrier forming electrode 200 cen . The pattern 305c' shown in FIG. 17 is provided with a vertical via 232 for connecting the barrier forming electrode 200 cen and the pixel isolation electrode 220 with respect to the pattern 305c of FIG. 14B. The vertical via 232 schematically shown in FIG. 17 is actually, for example, of the pixel isolation electrode 220, pixels 101f 12 and 101f 14 , and pixels 101f 21 and 101f 23and a portion disposed between them, and the barrier forming electrode 200 cen is provided to connect them. By providing the vertical via 232 in this way, the voltage applied to the pixel separation electrode 220 can be applied to the barrier forming electrode 200 cen as well.

[0131] (2-1. First Modification of the First Embodiment) Next, a first modification of the first embodiment will be described. In the above-described first embodiment, the pixel 101 has a structure in which a first photoelectric conversion unit that is a green photoelectric conversion unit, a second photoelectric conversion unit that is a blue photoelectric conversion unit, and a third photoelectric conversion unit that is a red photoelectric conversion unit are stacked. This is not limited to this example, and the technology according to the present disclosure has a first electrode 11 and a charge storage electrode 12, and generates a potential barrier in the gap 14 between the first electrode 11 and the charge storage electrode 12 to accumulate charges. As long as it is a configuration for performing the above, it is applicable to pixels 101 having other configurations as well.

[0132] Using FIGS. 18A to 18C, pixels 101 having other configurations to which the technology according to the present disclosure is applicable will be schematically described.

[0133] FIG. 18A is a diagram schematically showing a pixel configuration of a first example according to a first modification of the first embodiment. This first example is an example in which the first photoelectric conversion unit is made to correspond to panchromatic (panchro). That is, in the example of FIG. 18A, the first photoelectric conversion unit is constituted by a photoelectric conversion layer 15pan using an organic photoelectric conversion material having sensitivity to light having wavelengths in the visible light region. Further, on the semiconductor substrate 70, a photoelectric conversion layer 400 constituting the second photoelectric conversion unit and a photoelectric conversion layer 401 constituting the third photoelectric conversion unit are not provided. By providing a color filter such as red, green, or blue on the light receiving surface, a pixel signal corresponding to the color of the color filter can be output. A configuration in which a color filter is not provided is also possible, and in this case, a monochrome (gray scale) pixel signal can be output.

[0134] Even in the configuration of FIG. 18A, by arranging the barrier forming electrode 200 so as to have an overlapping portion with the gap 14 between the first electrode 11 and the charge storage electrode 12, it becomes possible to secure the accumulated charge amount Qs while maintaining a wide sensitivity region.

[0135] FIG. 18B is a diagram schematically showing the pixel configuration of a second example according to a first modification of the first embodiment. In this second example, the first photoelectric conversion unit remains as the green photoelectric conversion unit, and the second photoelectric conversion unit is an example of a red photoelectric conversion unit. In this case, a color filter CF(RED) that transmits light in the red wavelength region is arranged above the semiconductor substrate 70. Thereby, green and red pixel signals can be output. Further, FIG. 18C is a diagram schematically showing the pixel configuration of a third example according to a first modification of the first embodiment. In this third example, similar to FIG. 18B, the first photoelectric conversion unit remains as the green photoelectric conversion unit, and the second photoelectric conversion unit is an example of a blue photoelectric conversion unit. In this case, a color filter CF(BLUE) that transmits light in the blue wavelength region is arranged above the semiconductor substrate 70. Thereby, green and blue pixel signals can be output.

[0136] In the pixel array unit 111, by arranging the pixel 101 having the configuration shown in FIG. 18B and the pixel 101 having the configuration shown in FIG. 18C in a checkerboard pattern, for example, it becomes possible to support full-color imaging.

[0137] Even in the configurations of FIGS. 18B and 18C, by arranging the barrier forming electrode 200 so as to have an overlapping portion with the gap 14 between the first electrode 11 and the charge storage electrode 12, it becomes possible to secure the accumulated charge amount Qs while maintaining a wide sensitivity region.

[0138] (2-2. Second Modification of the First Embodiment) Next, a second modification of the first embodiment will be described. In the above-described first embodiment and the first modification of the first embodiment, the barrier formation electrode 200 was disposed below the layer in which the first electrode 11 and the charge storage electrode 12 were disposed. In contrast, in the second modification of the first embodiment, as illustrated in FIG. 19, the barrier formation electrode 200 is disposed in the same layer as the layer in which the first electrode 11 and the charge storage electrode 12 are disposed, that is, in the gap 14 between the first electrode 11 and the charge storage electrode 12. Even with the arrangement of FIG. 19, by applying a negative bias voltage to the barrier formation electrode 200, it is possible to generate a higher potential barrier between the first electrode 11 and the charge storage electrode 12. On the other hand, in the configuration of FIG. 19, since the barrier formation electrode 200 is disposed in the same layer as the first electrode 11 and the charge storage electrode 12, the sensitive region becomes narrower by the width of the barrier formation electrode 200.

[0139] [3. Second Embodiment] Next, a second embodiment of the present disclosure will be described. In the above-described first embodiment and each of its modifications, the voltage applied to the barrier formation electrode 200 was fixed. In contrast, in the second embodiment, the barrier formation electrode 200 is driven to change the voltage applied to the barrier formation electrode 200.

[0140] FIG. 20A is a diagram schematically showing the state of the potential barrier in the storage state in which charges are stored in the charge storage electrode 12 according to the second embodiment. Further, FIG. 20B is a diagram schematically showing the state of the potential barrier in the transfer state in which the charges stored in the charge storage electrode 12 are transferred to the first electrode 11 according to the second embodiment.

[0141] In FIG. 20A, it is assumed that the potential Pot(a) is the potential in a state where no voltage is applied to the barrier forming electrode 200, for example. This potential Pot(a) is generated, for example, according to the voltage applied to the second electrode 16. In the storage state, a voltage on the negative bias side is applied to the barrier forming electrode 200 as a storage voltage. As a result, the potential at the position corresponding to the gap 14 is pulled up from the potential Pot(a) to the potential Pot(b), and the potential barrier becomes higher.

[0142] In the transfer state of transferring the charges stored in the charge storage electrode 12 to the first electrode 11, as shown in FIG. 20B, a voltage on the positive bias side is applied to the barrier forming electrode 200 as a transfer voltage. That is, at the time of transfer, a voltage higher than the voltage applied during storage is applied to the barrier forming electrode 200. As a result, the potential at the position corresponding to the gap 14 is pulled down to a potential Pot(c) lower than the potential Pot(b), and the potential barrier becomes lower. At this time, it is preferable that the voltage applied to the barrier forming electrode 200 is a voltage at which the potential Pot(c) is lower than the potential Pot(a).

[0143] At the time of transfer, a transfer voltage is applied to the barrier forming electrode 200, and a voltage lower than that during storage is applied to the charge storage electrode 12. More specifically, a voltage is applied to the charge storage electrode 12 such that the potential corresponding to the charge storage electrode 12 becomes higher than the potential Pot(c). As a result, the potential corresponding to the charge storage electrode 12 becomes higher compared to the potential Pot(c) at the position corresponding to the gap 14, and the charges stored in the charge storage electrode 12 flow into the first electrode 11 over the potential barrier. At this time, since the voltage applied to the barrier forming electrode 200 is controlled so that the potential barrier becomes lower, the voltage applied to the charge storage electrode 12 for transfer can be kept low.

[0144] Note that it is not preferable to apply the second embodiment to an electrode arrangement in which the barrier forming electrode 200 is shared by a plurality of pixels 101. As an example, consider the case where the second embodiment is applied to the pattern 307a shown in FIG. 15B. In this case, since the barrier forming electrode 200 is shared by each pixel 101e 11 ~101e 14 when a transfer voltage is applied to the barrier forming electrode 200, the potential barrier at the position corresponding to the gap 14 between the charge storage electrode 12 and the first electrode 11 becomes low in each pixel 101e 11 ~101e 14 . Therefore, in the plurality of pixels 101e 11 ~101e 14 that are shared, charges are transferred from each charge storage electrode 12 of the pixels 101e 11 other than the pixel (assumed to be the pixel 101e 12 ~101e 14 to be read out) to the first electrode 11.

[0145] [4. Third Embodiment] Next, a third embodiment of the present disclosure will be described. In the first embodiment and its various modifications, and the second embodiment described above, the barrier forming electrode 200 is described as not being connected to the first electrode 11 and the charge storage electrode 12. In contrast, in the third embodiment, the barrier forming electrode 200 is connected to the first electrode 11.

[0146] FIG. 21 is a diagram showing an example of the arrangement of the barrier forming electrode 200 applicable to the second embodiment. As shown in FIG. 21, in the second embodiment, the barrier forming electrode 11ex is connected to the connection portion for connecting the first electrode 11 to the wiring layer 22. More specifically, the pad portion 63 constituting the connection portion for connecting the first electrode 11 to the wiring layer 22 is extended to the position of the gap 14 and used as the barrier forming electrode 11ex. The barrier forming electrode 11ex may have an overlapping portion with the gap 14, but preferably does not reach the position of the charge storage electrode 12.

[0147] FIG. 22 is a diagram schematically showing the state of a potential barrier in an accumulation state in which charges are accumulated in the charge accumulation electrode 12 according to the second embodiment. In the accumulation state, for example, a voltage of 2.7 [V] is applied to the charge accumulation electrode 12, and a voltage of 0 [V] is applied to the first electrode 11. At this time, the potential at the position corresponding to the gap 14 becomes higher than the potential by the first electrode 11 due to the voltage applied to the second electrode 16.

[0148] As a result, a higher potential barrier is generated at the position corresponding to the gap 14 between the first electrode 11 and the charge accumulation electrode 12 as compared with the case where the barrier forming electrode 11ex is not present. Therefore, the amount of accumulated charge Qs accumulated by the charge accumulation electrode 12 increases as compared with the case where the barrier forming electrode 11ex is not present.

[0149] At the time of transferring the charge accumulated in the charge accumulation electrode 12 to the first electrode 11, a voltage of 2.7 [V] is applied to the first electrode 11, and a voltage of 0 [V] is applied to the charge accumulation electrode 12. As a result, the potential by the charge accumulation electrode 12 is pulled up and the potential by the first electrode 11 is pulled down. Further, the potential of the barrier forming electrode 11ex becomes, for example, a potential intermediate between the potential by the charge accumulation electrode 12 and the potential by the first electrode 11 according to the voltage applied to the second electrode 16. Therefore, the charge accumulated by the charge accumulation electrode 12 flows into the first electrode 11 over the potential barrier.

[0150] According to this third embodiment, since the barrier forming electrode 11ex is formed by extending the existing pad portion 63, it is possible to secure the amount of accumulated charge Qs while maintaining a wide sensitivity region without adding a new configuration.

[0151] Note that, for the same reason as in the above-described second embodiment, it is not preferable to apply the third embodiment to an electrode arrangement in which the barrier forming electrode 200 is shared by a plurality of pixels 101.

[0152] [5. Fourth Embodiment] (5-1. Application Examples of the Technology of the Present Disclosure) Next, as a fourth embodiment, application examples of the imaging device according to the first embodiment and its various modifications, and the second and third embodiments of the present disclosure will be described. FIG. 23 is a diagram showing usage examples of using the imaging device according to the above-described first embodiment and its various modifications, and the second embodiment.

[0153] The imaging devices according to the above-described first embodiment and its various modifications, and the second and third embodiments can be used, for example, in various cases of sensing light such as visible light, infrared light, ultraviolet light, X-rays, etc. as follows.

[0154] · Devices for taking pictures of images for appreciation, such as digital cameras and mobile devices with camera functions. · In-vehicle sensors for taking pictures of the front, rear, surroundings, inside the vehicle, etc. of an automobile for safe driving such as automatic stop and recognition of the driver's state, surveillance cameras for monitoring moving vehicles and roads, ranging sensors for ranging between vehicles, etc., devices for traffic use. · Devices for home appliances such as TVs, refrigerators, air conditioners, etc. that take pictures of the user's gestures and perform device operations according to the gestures. · Devices for medical and healthcare use, such as endoscopes and devices for blood vessel imaging by receiving infrared light. · Devices for security use, such as surveillance cameras for crime prevention and cameras for person authentication. · Devices for beauty use, such as skin measuring devices for taking pictures of the skin and microscopes for taking pictures of the scalp. · Devices for sports use, such as action cameras and wearable cameras for sports applications. · Devices for agricultural use, such as cameras for monitoring the state of fields and crops.

[0155] (5-2. Application Example to an Endoscopic Surgery System) The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0156] FIG. 24 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (this technology) can be applied.

[0157] In FIG. 24, a state is illustrated in which an operator (doctor) 11131 is performing a surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As illustrated, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0158] The endoscope 11100 includes a lens barrel 11101 whose tip region of a predetermined length is inserted into the body cavity of the patient 11132, and a camera head 11102 connected to the proximal end of the lens barrel 11101. In the illustrated example, an endoscope 11100 configured as a so-called rigid endoscope having a rigid lens barrel 11101 is illustrated, but the endoscope 11100 may be configured as a so-called flexible endoscope having a flexible lens barrel.

[0159] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel through a light guide extending inside the lens barrel 11101 and irradiated toward an observation target in the body cavity of the patient 11132 through the objective lens. Note that the endoscope 11100 may be a direct-view endoscope, or may be an oblique-view endoscope or a side-view endoscope.

[0160] Inside the camera head 11102, an optical system and an imaging device are provided, and the reflected light (observation light) from the observation target is condensed onto the imaging device by the optical system. The observation light is photoelectrically converted by the imaging device, and an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image is generated. The image signal is transmitted as RAW data to a camera control unit (CCU) 11201.

[0161] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Further, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processes for displaying an image based on the image signal, such as development processing (demosaicing processing), on the image signal.

[0162] The display device 11202 displays an image based on the image signal that has been subjected to image processing by the CCU 11201 under the control of the CCU 11201.

[0163] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies irradiation light for photographing the surgical site or the like to the endoscope 11100.

[0164] The input device 11204 is an input interface for the endoscope surgical system 11000. The user can input various information and instruction inputs to the endoscope surgical system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) by the endoscope 11100.

[0165] The treatment device control device 11205 controls the drive of the energy treatment device 11112 for cauterizing, incising tissue, or sealing blood vessels. The pneumoperitoneum device 11206 injects gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to expand the body cavity for the purpose of securing the visual field by the endoscope 11100 and the working space for the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various forms such as text, images, or graphs.

[0166] Note that the light source device 11203 that supplies irradiation light when photographing the surgical site with the endoscope 11100 can be composed of, for example, an LED, a laser light source, or a white light source composed of a combination thereof. When the white light source is composed of a combination of RGB laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted in the light source device 11203. Further, in this case, the laser light from each of the RGB laser light sources is irradiated to the observation target in a time-division manner, and by controlling the drive of the imaging element of the camera head 11102 in synchronization with the irradiation timing, it is also possible to capture images corresponding to each of RGB in a time-division manner. According to this method, a color image can be obtained without providing a color filter on the imaging element.

[0167] Further, the drive of the light source device 11203 may be controlled so as to change the intensity of the output light every predetermined time. By controlling the drive of the imaging element of the camera head 11102 in synchronization with the timing of the change in the intensity of the light and acquiring images in a time-division manner and synthesizing the images, it is possible to generate a high-dynamic range image without so-called black crush and white blowout.

[0168] In addition, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating narrow-band light compared to the irradiation light (i.e., white light) during normal observation, so-called narrow-band imaging is performed to capture a predetermined tissue such as blood vessels in the mucosal surface layer with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image using fluorescence generated by irradiating excitation light. In fluorescence observation, excitation light may be irradiated to the body tissue to observe the fluorescence from the body tissue (autofluorescence observation), or a reagent such as indocyanine green (ICG) may be locally injected into the body tissue and excitation light corresponding to the fluorescence wavelength of the reagent may be irradiated to the body tissue to obtain a fluorescence image. The light source device 11203 can be configured to supply such narrow-band light and / or excitation light corresponding to special light observation.

[0169] FIG. 25 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG. 24.

[0170] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are communicably connected to each other by a transmission cable 11400.

[0171] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. The observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0172] The imaging unit 11402 is composed of an image sensor. The image sensor constituting the imaging unit 11402 may be one (so-called single-plate type) or a plurality (so-called multi-plate type). When the imaging unit 11402 is configured as a multi-plate type, for example, image signals corresponding to RGB respectively may be generated by each image sensor, and a color image may be obtained by synthesizing them. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for respectively acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. When the imaging unit 11402 is configured as a multi-plate type, a plurality of lens units 11401 may be provided corresponding to each image sensor.

[0173] Also, the imaging unit 11402 does not necessarily have to be provided on the camera head 11102. For example, the imaging unit 11402 may be provided immediately behind the objective lens inside the lens barrel 11101.

[0174] The drive unit 11403 is composed of an actuator, and under the control from the camera head control unit 11405, moves the zoom lens and the focus lens of the lens unit 11401 along the optical axis by a predetermined distance. Thereby, the magnification and focus of the captured image by the imaging unit 11402 can be appropriately adjusted.

[0175] The communication unit 11404 is composed of a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0176] In addition, the communication unit 11404 receives a control signal for controlling the drive of the camera head 11102 from the CCU 11201 and supplies it to the camera head control unit 11405. The control signal includes information related to imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0177] Note that the imaging conditions such as the above frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function are installed in the endoscope 11100.

[0178] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal from the CCU 11201 received via the communication unit 11404.

[0179] The communication unit 11411 is constituted by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0180] In addition, the communication unit 11411 transmits a control signal for controlling the drive of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by telecommunication, optical communication, or the like.

[0181] The image processing unit 11412 performs various image processes on the image signal, which is RAW data transmitted from the camera head 11102.

[0182] The control unit 11413 performs various controls related to imaging of the surgical site and other areas by the endoscope 11100 and display of the captured images obtained by imaging the surgical site and other areas. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0183] Also, based on the image signal processed by the image processing unit 11412, the control unit 11413 causes the display device 11202 to display the captured image in which the surgical site and other areas are reflected. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological parts, bleeding, mist during the use of the energy treatment tool 11112, etc. by detecting the shape, color, etc. of the edges of the objects included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose and display various surgical support information on the image of the surgical site. By superimposing and presenting the surgical support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can surely proceed with the surgery.

[0184] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable corresponding to electrical signal communication, an optical fiber corresponding to optical communication, or a composite cable of these.

[0185] Here, in the illustrated example, communication is performed wired using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0186] The above has described an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the endoscope 11100 or the imaging unit 11402 of the camera head 11102 among the configurations described above. Specifically, the above-described imaging device can be applied to the imaging unit 10112. Since the imaging device according to the present disclosure enables both ensuring a wide sensitivity region (charge storage electrode 12) in each pixel 101 and ensuring the amount of stored charge Qs, a higher-quality captured image can be obtained. Thereby, for example, the surgeon 11131 can proceed with the surgery more reliably.

[0187] Here, an endoscopic surgery system has been described as an example. However, the technology according to the present disclosure may also be applied to, for example, a microsurgery system or the like.

[0188] (5-3. Application Example to a Moving Body) The technology according to the present disclosure may further be applied to devices mounted on various moving bodies such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0189] FIG. 26 is a block diagram showing a schematic configuration example of a vehicle control system which is an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0190] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 26, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an out-of-vehicle information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0191] The drive system control unit 12010 controls the operations of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a driving force generation device for generating the driving force of the vehicle, such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating the braking force of the vehicle.

[0192] The body system control unit 12020 controls the operations of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as a headlamp, a backlamp, a brake lamp, a turn signal, or a fog lamp. In this case, radio waves transmitted from a portable device that replaces the key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these inputs of radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0193] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing, such as for a person, a vehicle, an obstacle, a sign, or characters on the road surface, based on the received image. The vehicle exterior information detection unit 12030, for example, performs image processing on the received image and performs object detection processing and distance detection processing based on the result of the image processing.

[0194] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared light.

[0195] The in-vehicle information detection unit 12040 detects in-vehicle information. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the degree of driver fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0196] Based on the information inside and outside the vehicle acquired by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, the microcomputer 12051 can calculate control target values for the driving force generation device, the steering mechanism, or the braking device, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for realizing functions of an ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, collision warning of the vehicle, or lane departure warning of the vehicle.

[0197] Also, based on the information around the vehicle acquired by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, etc., in which it controls the driving force generation device, the steering mechanism, the braking device, etc., to drive autonomously without relying on the driver's operation.

[0198] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the external information acquired by the vehicle external information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control for the purpose of anti-glare, such as controlling the headlamp according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle external information detection unit 12030 and switching the high beam to the low beam.

[0199] The audio-visual image output unit 12052 transmits at least one output signal of audio and image to an output device capable of notifying information visually or auditorily to the vehicle occupants or outside the vehicle. In the example of FIG. 26, as the output devices, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0200] FIG. 27 is a diagram showing an example of the installation position of the imaging unit 12031. In FIG. 27, the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0201] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose of the vehicle 12100, side mirrors, rear bumper, back door, and the upper part of the front glass inside the vehicle compartment. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the front glass inside the vehicle compartment mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images on the side of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images behind the vehicle 12100. The front images acquired by the imaging units 12101 and 12105 are mainly used for detecting preceding vehicles or pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0202] Note that FIG. 27 shows an example of the imaging ranges of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or the back door. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 seen from above can be obtained.

[0203] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0204] For example, the microcomputer 12051 obtains the distance to each solid object within the imaging ranges 12111 to 12114 and the temporal change of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thus extracts, as the preceding vehicle, the closest solid object on the traveling path of the vehicle 12100 that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more). Further, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control), etc. In this way, cooperative control for the purpose of automatic driving, etc., which autonomously travels without relying on the driver's operation, can be performed.

[0205] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 classifies and extracts solid object data regarding solid objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other solid objects, and can use it for automatic avoidance of obstacles. For example, the microcomputer 12051 discriminates obstacles around the vehicle 12100 into obstacles visible to the driver of the vehicle 12100 and obstacles difficult to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk is equal to or higher than a set value and there is a possibility of collision, it outputs an alarm to the driver via the audio speaker 12061 or the display unit 12062, or performs forced deceleration or avoidance steering via the drive system control unit 12010, thereby providing driving assistance for collision avoidance.

[0206] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. Such recognition of a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras and a procedure of performing pattern matching processing on a series of feature points indicating the outline of an object to discriminate whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio and image output unit 12052 controls the display unit 12062 to superimpose and display a rectangular outline for emphasis on the recognized pedestrian. Further, the audio and image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0207] As described above, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above.

[0208] Specifically, the above-described imaging device can be applied to the imaging unit 12031. Since the imaging device according to the present disclosure enables both ensuring a wide sensitivity region (charge storage electrode 12) in each pixel 101 and ensuring the charge storage amount Qs, a higher-quality captured image can be obtained. As a result, it becomes possible to realize more accurate pedestrian recognition and vehicle control.

[0209] Note that the effects described in this specification are merely illustrative and not limiting, and there may be other effects.

[0210] Note that the present technology can also adopt the following configurations. (1) A photoelectric conversion layer, A first electrode located on the first surface side of the photoelectric conversion layer and electrically connected to the photoelectric conversion layer, A second electrode located on the second surface opposite to the first surface of the photoelectric conversion layer, A charge storage electrode located on the first surface side of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface, A third electrode disposed at a position overlapping a gap between the first electrode and the charge storage electrode in a direction perpendicular to the first surface, An imaging device including a pixel including the above. (2) The third electrode is Not connected to the first electrode and the charge storage electrode, The imaging device according to (1) above. (3) The third electrode is Including a portion overlapping with at least one of the first electrode and the charge storage electrode in a direction perpendicular to the first surface, The imaging device according to (1) or (2) above. (4) The third electrode is Not including a portion overlapping with the first electrode and the charge storage electrode in a direction perpendicular to the first surface, The imaging device according to the above (1) or (2). (5) The third electrode is disposed at a position shared by a plurality of the pixels. The imaging device according to any one of the above (1) to (4). (6) The first electrode is shared with a plurality of the pixels as a sharing unit. The third electrode is disposed at a position shared by a plurality of the pixels across the sharing unit. The imaging device according to any one of the above (1) to (5). (7) A plurality of the pixels are arranged in a matrix array. The third electrode is disposed at a position shared by a plurality of the pixels arranged in one row or one column of the matrix. The imaging device according to any one of the above (1) to (6). (8) A plurality of the pixels are arranged in a matrix array. The third electrode is disposed at a position shared by a plurality of the pixels arranged in two adjacent rows or two adjacent columns of the matrix. The imaging device according to any one of the above (1) to (6). (9) The imaging device further includes a separation electrode for electrically separating the pixel from the pixel adjacent to the pixel. The third electrode is connected to the separation electrode. The imaging device according to any one of the above (1) to (8). (10) The third electrode is connected to the separation electrode via a vertical via. The imaging device according to the above (9). (11) The photoelectric conversion layer, the first electrode, the second electrode, the charge storage electrode, and the third electrode are disposed on the third surface side of the semiconductor substrate. The third electrode Wiring disposed in a wiring layer formed on a fourth surface of the semiconductor substrate opposite to the third surface is connected through the semiconductor substrate, The imaging device according to any one of (1) to (8) above. (12) The pixel has a rectangular shape, The first electrode is disposed along any side of the rectangular shape, The imaging device according to any one of (1) to (11) above. (13) The pixel has a rectangular shape, The first electrode is disposed at any corner of the rectangular shape, The imaging device according to any one of (1) to (11) above. (14) In a first state, a first voltage lower than the voltage applied to the charge storage electrode is applied to the third electrode, In a second state transitioning from the first state, a second voltage higher than the voltage applied to the charge storage electrode and higher than the first voltage is applied to the third electrode, The imaging device according to any one of (1) to (5), (9) to (13) above. (15) The third electrode is connected to the first electrode, The imaging device according to (1) or (3) or (4) or (12) or (13) above. (16) In a first state, a third voltage is applied to the third electrode, and a fourth voltage higher than the third voltage is applied to the charge storage electrode, In a second state transitioning from the first state, the fourth voltage is applied to the third electrode, and the third voltage is applied to the charge storage electrode, The imaging device according to (15) above. (17) A photoelectric conversion layer, A first electrode located on the first surface side of the photoelectric conversion layer and electrically connected to the photoelectric conversion layer, A second electrode positioned on a second surface opposite to the first surface of the photoelectric conversion layer; A charge accumulation electrode disposed on the first surface side of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface; A third electrode disposed at a position overlapping a gap between the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface; An imaging device including a pixel including the above; An image processing unit that executes image processing on a pixel signal based on charges generated by the photoelectric conversion layer to generate image data; A storage unit that stores the image data generated by the image processing unit; An electronic device including the above.

Explanation of Reference Numerals

[0211] 11, 11a, 11b First electrode 11ex, 200, 200 cen , 200 col , 200 col(a) , 200 col(b) , 200 col(c) , 200 lft , 200 rht , 200 row , 200 row(2) , 200 row(a) , 200 row(b) Barrier formation electrode 12 Charge accumulation electrode 14 Gap 15, 15pan Photoelectric conversion layer 16 Second electrode 61 Contact hole portion 63 Pad portion 70 Semiconductor substrate 101, 101a, 101b, 101c, 101d, 101e 11 , 101e 12 , 101e 13 , 101e 14 , 101e 21 , 101e 22 , 101e 23 , 101e 24 , 101f11 , 101f 12 , 101f 13 , 101f 14 , 101f 21 , 101f 22 , 101f 23 , 101f 24 , 101g 11 , 101g 12 , 101g 13 , 101g 14 , 101g 21 , 101g 22 , 101g 23 , 101g 24 , 101h 11 , 101h 12 , 101h 13 , 101h 14 , 101h 21 , 101h 22 , 101h 23 , 101h 24 Pixel 221 Vertical via 220 Pixel isolation electrode 240 Through electrode

Claims

1. A photoelectric conversion layer, a first electrode located on the first surface side of the photoelectric conversion layer and electrically connected to the photoelectric conversion layer, a second electrode located on the second surface opposite to the first surface of the photoelectric conversion layer, a charge storage electrode located on the first surface side of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface, a third electrode disposed at a position overlapping a gap between the first electrode and the charge storage electrode in a direction perpendicular to the first surface, comprising a pixel, the pixel further comprising a separation electrode disposed at an outer edge portion of the pixel for electrically separating the pixel from an adjacent pixel, the pixels are arranged in a matrix array, the first electrode is shared by a plurality of the pixels sharing one vertex in the array, the separation electrode has a shape in which a part including the vertex is cut out from each of two sides including the vertex, the third electrode is disposed obliquely between the first electrode and the charge storage electrode according to each of the cut-out ends of the separation electrode, and is connected to each of the ends of the separation electrode via a vertical via, an imaging device.

2. The third electrode is not connected to the first electrode and the charge storage electrode, The imaging device according to claim 1.

3. The third electrode is including a portion overlapping with at least one of the first electrode and the charge storage electrode in a direction perpendicular to the first surface, The imaging device according to claim 1.

4. The third electrode is not including a portion overlapping with the first electrode and the charge storage electrode in a direction perpendicular to the first surface, The imaging device according to claim 1.

5. The third electrode is disposed at a position shared by a plurality of the pixels, The imaging device according to claim 1.

6. The pixel has a rectangular shape, the first electrode is disposed at any corner of the rectangular shape, The imaging device according to claim 1.

7. A photoelectric conversion layer, a first electrode located on the first surface side of the photoelectric conversion layer and electrically connected to the photoelectric conversion layer, a second electrode located on the second surface opposite to the first surface of the photoelectric conversion layer, a charge storage electrode located on the first surface side of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface, A third electrode disposed at a position having an overlapping portion in a gap between the first electrode and the charge storage electrode in a direction perpendicular to the first surface; including a pixel including the same; the pixel further includes a separation electrode disposed at an outer edge portion of the pixel for electrically separating the pixel from an adjacent pixel; the pixels are arranged in a matrix array; the first electrode is shared by a plurality of the pixels sharing one vertex in the array; the separation electrode has a shape in which a part including the vertex is cut out from each of two sides including the vertex; the third electrode is disposed obliquely between the first electrode and the charge storage electrode according to each of the cut-out ends of the separation electrode, and is connected to each of the ends of the separation electrode via a vertical via; an imaging device; an image processing unit that generates image data by executing image processing on a pixel signal based on charges generated by the photoelectric conversion layer; a storage unit that stores the image data generated by the image processing unit; an electronic device including the same.

Images