Semiconductor device and power conversion device

Abstract

To provide a semiconductor device in which heat dissipation of the semiconductor device is improved.SOLUTION: A semiconductor device has an alternative region where an IGBT region 10 and a diode region 20 are linearly alternately arranged in a plan view, in which a width in a first direction of an IGBT region 10a nearest a center of a cell region in the alternately region of the cell region composed of the IGBT region 10 and the diode region 20 having two or more width types in the first direction along the alternative region in the plan view is a width or less in the first direction of the other IGBT region 10, and the width in the first direction of a diode region 20a nearest the center of the cell region is a width or less in the first direction of the other diode region 20.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a power conversion device.

Background Art

[0002] In recent years, from the perspective of energy conservation, semiconductor devices with low energy loss have been required in the fields of electric railways, in-vehicle devices, industrial machinery, or consumer devices. For example, in a semiconductor device in which an insulated gate bipolar transistor (IGBT) and a diode are provided on one semiconductor substrate, a configuration has been proposed in which the respective regions of the IGBT and the diode are large at the center of the semiconductor device and small on the end side of the semiconductor device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the semiconductor device of Patent Document 1, since the IGBT region and the diode region at the center of the semiconductor device are large, there is a problem that the heat dissipation performance is not excellent.

[0005] The present disclosure has been made to solve the above problems, and an object thereof is to provide a semiconductor device with improved heat dissipation performance of the semiconductor device.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure includes a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface facing the first main surface. equipped withA semiconductor device including an emitter layer of a first conductivity type formed from a first main surface of a semiconductor substrate and penetrating through a base layer of a second conductivity type formed an IGBT region having a trench gate and a collector layer of a second conductivity type provided on a second main surface side of a drift layer, an anode layer of a second conductivity type provided on a first main surface side of the drift layer, and a cathode layer of a first conductivity type provided on a second main surface side of the drift layer When a reflux current flows, it becomes a heat source a diode region composed of an IGBT region and a diode region an alternating region in which the IGBT region and the diode region are alternately arranged linearly in a plan view a cell region having in a first direction along the alternating region to the widths of the IGBT region and the diode region respectively are not constant 、 each each are arranged to have two or more types of widths, and in the alternating region, the width of the IGBT region closest to the center of the cell region in the first direction is less than or equal to the width of other IGBT regions in the first direction, and the width of the diode region closest to the center of the cell region in the first direction is less than or equal to the width of other diode regions in the first direction

Advantages of the Invention

[0007] According to the semiconductor device according to the present disclosure, by making the IGBT region and the diode region closest to the center of the cell region smaller than the peripheral IGBT region and diode region, the heat dissipation performance of the semiconductor device can be improved

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are schematically shown, the sizes and positional relationships can be changed. In the following description, the same or corresponding components may be given the same reference numerals, and repeated descriptions may be omitted.

[0010] Also, in the following description, terms indicating specific positions and directions such as "upper", "lower", and "side" may be used, but these terms are used for convenience in order to facilitate understanding of the content of the embodiments, and do not limit the positions and directions during implementation.

[0011] Also, in the following description, n and p indicate the conductivity types of semiconductors. In the present disclosure, the first conductivity type is described as n-type and the second conductivity type is described as p-type. Also, n- indicates that the impurity concentration is lower than n, and n+ indicates that the impurity concentration is higher than n. Similarly, p- indicates that the impurity concentration is lower than p, and p+ indicates that the impurity concentration is higher than p.

[0012] <Embodiment 1> FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1, and shows a semiconductor device that is an RC-IGBT (Reverse Conducting IGBT). Note that an RC-IGBT is a semiconductor device in which an IGBT region that functions as an IGBT and a diode region that functions as a diode are provided on a single semiconductor substrate. Further, FIG. 2 is a plan view showing a semiconductor device having another configuration according to Embodiment 1, and shows a semiconductor device that is an RC-IGBT having another configuration. The semiconductor device 110 shown in FIG. 1 has an IGBT region 10 and a diode region 20 arranged side by side in a stripe pattern, and may be simply referred to as a "stripe type". As will be described later in Embodiment 2 and subsequent embodiments, for example, the present disclosure may be applied to an "island type" in which the IGBT region 10 is provided around the diode region 20.

[0013] In FIG. 1, the semiconductor device 110 includes an IGBT region 10 (10a, 10b, 10c, 10d) and a diode region 20 (20a, 20b, 20c) in one semiconductor device. In the present disclosure, the IGBT region 10 and the diode region 20 are collectively referred to as a cell region. The IGBT region 10 and the diode region 20 are provided so as to extend from one end side to the other end side of the semiconductor device 110, and are alternately provided in a stripe pattern in a direction orthogonal to the extending direction of the IGBT region 10 and the diode region 20. In FIG. 1, seven IGBT regions 10 (10a, 10b, 10c, 10d) and six diode regions 20 (20a, 20b, 20c) are shown, and all the diode regions 20 are shown in a configuration sandwiched between the IGBT regions 10. However, the numbers of the IGBT region 10 and the diode region 20 are not limited to this, and the number of the IGBT region 10 may be seven or more or seven or less, and the number of the diode region 20 may be six or more or six or less. Further, a configuration in which the positions of the IGBT region 10 and the diode region 20 in FIG. 1 are interchanged may be used, or a configuration in which all the IGBT regions 10 are sandwiched between the diode regions 20 may be used.

[0014] In the present disclosure, a region in which the IGBT regions 10 and the diode regions 20 are arranged alternately in a linear manner is referred to as an alternating region. The first direction is the direction along the alternating region, and in the first direction, the IGBT regions 10 and the diode regions 20 are provided alternately in a linear manner. As shown in FIG. 1, the widths of the IGBT regions 10a, 10b, 10c, 10d in the first direction are W1a, W1b, W1c, W1d, respectively, and the widths in the first direction are different such that W1d > W1c > W1b > W1a. That is, the width of the IGBT region 10a closest to the center of the cell region in the first direction is less than or equal to the widths of the other IGBT regions, and the IGBT regions 10a, 10b, 10c, 10d are provided from the center of the cell region toward the end of the cell region in ascending order of size. That is, in FIG. 1, the widths or areas in the first direction, which is the direction along the alternating region from the center of the cell region toward the end of the cell region, are provided in ascending order in the order of 10a, 10b, 10c, 10d.

[0015] The widths of the diode regions 20a, 20b, 20c in the first direction are W2a, W2b, W2c, respectively, and the widths in the first direction are different such that W2c > W2b > W2a. That is, the width of the diode region 20a closest to the center of the cell in the first direction is less than or equal to the widths of the other diode regions, and the diode regions 20a, 20b, 20c are provided from the center of the cell region toward the end of the cell region in ascending order of size. That is, in FIG. 1, the widths or areas in the first direction, which is the direction along the alternating region from the center of the cell region toward the end of the cell region, are provided in ascending order in the order of 20a, 20b, 20c. Note that although the number of the IGBT regions and the diode regions 20 is described as three or more types, two or more types are sufficient, and it is not limited to the number shown in the drawings.

[0016] In addition, in FIG. 1, the vertical direction of the drawing is shown assuming that the IGBT regions and the diode regions increase from the center to the end of the cell region in the first direction. However, the first direction may be any direction along the alternating region, and the IGBT regions and the diode regions may be provided in the same manner as described above with the left - right direction of the drawing as the first direction, which is perpendicular to the vertical direction of the drawing.

[0017] As shown in FIG. 1, a pad region 40 is provided adjacent to the IGBT region 10d. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 110 is provided. A termination region 30 is provided around the combined region of the cell region and the pad region 40 for maintaining the breakdown voltage of the semiconductor device 110. In the termination region 30, a well-known breakdown voltage maintaining structure can be appropriately selected and provided. The breakdown voltage maintaining structure may be, for example, a FLR (Field Limiting Ring) surrounding the cell region with a p-type terminal well layer of a p-type semiconductor or a VLD (Variation of Lateral Doping) surrounding the cell region with a p-type well layer having a concentration gradient, on the first main surface side which is the front surface side of the semiconductor device 110. The number of ring-shaped p-type terminal well layers used for the FLR and the concentration distribution used for the VLD may be appropriately selected according to the breakdown voltage design of the semiconductor device 110. Also, a p-type terminal well layer may be provided over substantially the entire area of the pad region 40, and IGBT cells or diode cells may be provided in the pad region 40.

[0018] The control pad 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, temperature sense diode pads 41d, 41e. The current sense pad 41a is a control pad for detecting the current flowing through the cell region of the semiconductor device 110. When a current flows through the cell region of the semiconductor device 110, it is a control pad electrically connected to some of the IGBT cells or diode cells in the cell region so that a current of one fraction to one ten-thousandth of the current flowing through the entire cell region flows.

[0019] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for turning on and off the semiconductor device 110 is applied. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected via a p+-type contact layer. The temperature sense diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sense diode provided in the semiconductor device 110. The temperature of the semiconductor device 110 is measured by measuring the voltage between the anode and cathode of a temperature sense diode (not shown) provided in the cell region.

[0020] FIG. 3 is a partially enlarged plan view showing the configuration of the IGBT region of the semiconductor device according to Embodiment 1, and shows the configuration of the IGBT region 10 of the semiconductor device which is an RC-IGBT. FIGS. 4 and 5 are cross-sectional views showing the configuration of the IGBT region of the semiconductor device according to Embodiment 1, and show the configuration of the IGBT region 10 of the semiconductor device which is an RC-IGBT. FIG. 3 shows an enlarged view of the region surrounded by the broken line 82 in the semiconductor device 110 shown in FIG. 1 or the semiconductor device 111 shown in FIG. 2. FIG. 4 is a cross-sectional view taken along the broken line A-A of the semiconductor device 110 shown in FIG. 3, and FIG. 5 is a cross-sectional view taken along the broken line B-B of the semiconductor device 110 shown in FIG. 3.

[0021] As shown in FIG. 3, in the IGBT region 10, an active trench gate 11 and a dummy trench gate 12 are provided in a stripe shape. In the semiconductor device 110, the active trench gate 11 and the dummy trench gate 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 is the longitudinal direction of the active trench gate 11 and the dummy trench gate 12. On the other hand, in the semiconductor device 111, the left-right direction of the drawing may be the longitudinal direction of the active trench gate 11 and the dummy trench gate 12, or the up-down direction of the drawing may be the longitudinal direction of the active trench gate 11 and the dummy trench gate 12.

[0022] The active trench gate 11 has a gate trench electrode 11a in a trench formed in a semiconductor substrate via a gate trench insulating film 11b. The dummy trench gate 12 has a dummy trench electrode 12a in a trench formed in the semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 110 or the semiconductor device 101. That is, the active trench gate 11 can have a gate drive voltage applied thereto, while the dummy trench gate 12 cannot have a gate drive voltage applied thereto.

[0023] The n+-type source layer 13 is provided in contact with the gate trench insulating film 11b on both sides in the width direction of the active trench gate 11. The n+-type source layer 13 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+17 / cm3 to 1.0E+20 / cm3. The n+-type source layer 13 is provided alternately with the p+-type contact layer 14 along the extending direction of the active trench gate 11. The p+-type contact layer 14 is also provided between two adjacent dummy trench gates 12. The p+-type contact layer 14 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+15 / cm3 to 1.0E+20 / cm3.

[0024] As shown in FIG. 3, in the IGBT region 10 of the semiconductor device 110, three active trench gates 11 are arranged side by side, and adjacent to them, three dummy trench gates 12 are arranged. Adjacent to the three dummy trench gates 12, three active trench gates 11 are arranged. The IGBT region 10 is configured such that the sets of active trench gates 11 and the sets of dummy trench gates 12 are arranged alternately in this way. In FIG. 3, the number of active trench gates 11 included in one set of active trench gates 11 is set to 3, but it may be 1 or more. Also, the number of dummy trench gates 12 included in one set of dummy trench gates 12 may be 1 or more, and the number of dummy trench gates 12 may be 0. That is, all the trenches provided in the IGBT region 10 may be active trench gates 11.

[0025] FIG. 4 is a cross-sectional view taken along the dashed line A-A in FIG. 3 of the semiconductor device 110, showing a cross-sectional view of the IGBT region 10. The semiconductor device 110 has an n-type drift layer 1 made of a semiconductor substrate. The n-type drift layer 1 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+12 / cm3 to 1.0E+15 / cm3. The semiconductor substrate is, in FIG. 4, in the range from the n+-type source layer 13 and the p+-type contact layer 14 to the p-type collector layer 16. In FIG. 4, the upper end of the n+-type source layer 13 and the p+-type contact layer 14 on the paper surface is referred to as the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper surface is referred to as the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 110, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 110. The semiconductor device 110 has an n-type drift layer 1 between the first main surface and the second main surface facing the first main surface in the IGBT region 10, which is a cell region.

[0026] As shown in FIG. 4, in the IGBT region 10, an n-type carrier accumulation layer 2 having a higher concentration of n-type impurities than the n-type drift layer 1 is provided on the first main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+13 / cm3 to 1.0E+17 / cm3. Note that in the semiconductor device 110, the n-type drift layer 1 may be provided also in the region of the n-type carrier accumulation layer 2 shown in FIG. 4 without providing the n-type carrier accumulation layer 2. By providing the n-type carrier accumulation layer 2, it is possible to reduce the conduction loss when a current flows through the IGBT region 10. The n-type carrier accumulation layer 2 and the n-type drift layer 1 may be collectively referred to as a drift layer.

[0027] The n-type carrier accumulation layer 2 is formed by ion-implanting an n-type impurity into the semiconductor substrate constituting the n-type drift layer 1 and then diffusing the implanted n-type impurity into the semiconductor substrate which is the n-type drift layer 1 by annealing.

[0028] On the first main surface side of the n-type carrier accumulation layer 2, a p-type base layer 15 is provided. The p-type base layer 15 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm3 to 1.0E+19 / cm3. The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, an n+-type source layer 13 is provided in contact with the gate trench insulating film 11b of the active trench gate 11, and a p+-type contact layer 14 is provided in the remaining region. The n+-type source layer 13 and the p+-type contact layer 14 constitute the first main surface of the semiconductor substrate. Note that the p+-type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15, and when it is necessary to distinguish between the p+-type contact layer 14 and the p-type base layer 15, they may be individually referred to, or the p+-type contact layer 14 and the p-type base layer 15 may be collectively referred to as a p-type base layer.

[0029] Further, in the semiconductor device 110, an n-type buffer layer 3 having a higher concentration of n-type impurities than the n-type drift layer 1 is provided on the second main surface side of the n-type drift layer 1. The n-type buffer layer 3 is provided to suppress the punch-through of the depletion layer extending from the p-type base layer 15 to the second main surface side when the semiconductor device 110 is in the off state. The n-type buffer layer 3 may be formed, for example, by implanting phosphorus (P) or protons (H+), or by implanting both phosphorus (P) and protons (H+). The concentration of n-type impurities in the n-type buffer layer 3 is 1.0E+12 / cm3 to 1.0E+18 / cm3. Note that the semiconductor device 110 may be provided with the n-type drift layer 1 also in the region of the n-type buffer layer 3 shown in FIG. 4 without providing the n-type buffer layer 3. The n-type buffer layer 3 and the n-type drift layer 1 may be collectively referred to as a drift layer.

[0030] On the second main surface side of the n-type buffer layer 3, a p-type collector layer 16 is provided in the semiconductor device 110. That is, the p-type collector layer 16 is provided between the n-type drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+16 / cm3 to 1.0E+20 / cm3. The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region 30, and the portion of the p-type collector layer 16 provided in the termination region 30 constitutes a p-type termination collector layer. Further, a part of the p-type collector layer 16 may protrude from the IGBT region 10 to the diode region 20.

[0031] As shown in FIG. 4, in the semiconductor device 110, a trench is formed that penetrates the p-type base layer 15 from the first main surface of the semiconductor substrate and reaches the n-type drift layer 1. An active trench gate 11 is configured by providing a gate trench electrode 11a in the trench via a gate trench insulating film 11b. The gate trench electrode 11a faces the n-type drift layer 1 via the gate trench insulating film 11b. Also, a dummy trench gate 12 is configured by providing a dummy trench electrode 12a in the trench via a dummy trench insulating film 12b. The dummy trench electrode 12a faces the n-type drift layer 1 via the dummy trench insulating film 12b. The gate trench insulating film 11b of the active trench gate 11 is in contact with the p-type base layer 15 and the n+-type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0032] As shown in FIG. 4, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region where the interlayer insulating film 4 is not provided on the first main surface of the semiconductor substrate and on the interlayer insulating film 4. The barrier metal 5 may be a conductor containing, for example, titanium (Ti), may be, for example, titanium nitride, or may be TiSi in which titanium and silicon (Si) are alloyed.

[0033] As shown in FIG. 4, the barrier metal 5 makes ohmic contact with the n+-type source layer 13, the p+-type contact layer 14, and the dummy trench electrode 12a, and is electrically connected to the n+-type source layer 13, the p+-type contact layer 14, and the dummy trench electrode 12a. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 may be formed of an aluminum alloy such as an aluminum-silicon alloy (Al—Si alloy), or may be an electrode composed of a plurality of metal films formed by electroless plating or electrolytic plating to form a plating film on the electrode formed of the aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film.

[0034] In FIG. 4, a configuration is shown in which a contact hole 19 is provided without providing the interlayer insulating film 4 on the dummy trench electrode 12a of the dummy trench gate 12, but the interlayer insulating film 4 may be formed on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a may be electrically connected in another cross section.

[0035] When the width of the contact hole 19 provided in the interlayer insulating film 4 is narrow and good embedding cannot be obtained with the emitter electrode 6, tungsten having better embedding properties than the emitter electrode 6 may be disposed in the contact hole 19, and the emitter electrode 6 may be provided on the tungsten. Note that the emitter electrode 6 may be provided on the n+-type source layer 13, the p+-type contact layer 14, and the dummy trench electrode 12a without providing the barrier metal 5. Further, the barrier metal 5 may be provided only on the n-type semiconductor layer such as the n+-type source layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as an emitter electrode.

[0036] On the second main surface side of the p-type collector layer 16, a collector electrode 7 is provided. Similar to the emitter electrode 6, the collector electrode 7 may be composed of an aluminum alloy or an aluminum alloy and a plating film. Also, the collector electrode 7 may have a configuration different from that of the emitter electrode 6. The collector electrode 7 makes an ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0037] FIG. 5 is a cross-sectional view taken along the dashed line B-B in FIG. 3 of the semiconductor device 110 and is a cross-sectional view of the IGBT region 10. It is different from the cross-sectional view taken along the dashed line A-A shown in FIG. 4 in that the n+-type source layer 13 provided on the first main surface side of the semiconductor substrate in contact with the active trench gate 11 is not seen in the cross-section along the dashed line B-B in FIG. 5. That is, as shown in FIG. 3, the n+-type source layer 13 is selectively provided on the first main surface side of the p-type base layer. Here, the p-type base layer mentioned here refers to the p-type base layer that collectively refers to the p-type base layer 15 and the p+-type contact layer 14.

[0038] FIG. 6 is a partially enlarged plan view showing the configuration of the diode region of the semiconductor device according to Embodiment 1 and shows the configuration of the diode region of the semiconductor device that is an RC-IGBT. FIGS. 7 and 8 are cross-sectional views showing the configuration of the diode region of the semiconductor device according to Embodiment 1 and show the configuration of the diode region of the semiconductor device that is an RC-IGBT. FIG. 6 is an enlarged view of the region surrounded by the dashed line 83 in the semiconductor device 110 shown in FIG. 1. FIG. 7 is a cross-sectional view taken along the dashed line C-C of the semiconductor device 110 shown in FIG. 6. FIG. 8 is a cross-sectional view taken along the dashed line D-D of the semiconductor device 110 shown in FIG. 6.

[0039] The diode trench gate 21 extends from one end side to the opposite end side of the diode region 20, which is a cell region, along the first main surface of the semiconductor device 110 or the semiconductor device 101. The diode trench gate 21 has a diode trench electrode 21a in a trench formed in the semiconductor substrate of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a faces the n- type drift layer 1 via the diode trench insulating film 21b. A p+ type contact layer 24 and a p type anode layer 25 are provided between two adjacent diode trench gates 21. The p+ type contact layer 24 is a semiconductor layer having, for example, boron or aluminum as a p type impurity, and the concentration of the p type impurity is 1.0E+15 / cm3 to 1.0E+20 / cm3. The p type anode layer 25 is a semiconductor layer having, for example, boron or aluminum as a p type impurity, and the concentration of the p type impurity is 1.0E+12 / cm3 to 1.0E+19 / cm3. The p+ type contact layer 24 and the p type anode layer 25 are alternately provided in the longitudinal direction of the diode trench gate 21.

[0040] Figure 7 is a cross-sectional view taken along the broken line C-C in FIG. 6 of the semiconductor device 110 and is a cross-sectional view of the diode region 20. The semiconductor device 110 has an n- type drift layer 1 made of a semiconductor substrate also in the diode region 20, similar to the IGBT region 10. The n- type drift layer 1 in the diode region 20 and the n- type drift layer 1 in the IGBT region 10 are continuously and integrally formed and are constituted by the same semiconductor substrate. In FIG. 7, the semiconductor substrate is in the range from the p+ type contact layer 24 to the n+ type cathode layer 26. In FIG. 7, the upper end of the p+ type contact layer 24 on the paper surface is called the first main surface of the semiconductor substrate, and the lower end of the n+ type cathode layer 26 on the paper surface is called the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are the same surface, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are the same surface.

[0041] As shown in FIG. 7, in the diode region 20 as well as in the IGBT region 10, an n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, and an n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 have the same configuration as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. Note that it is not always necessary to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20. Even when the n-type carrier accumulation layer 2 is provided in the IGBT region 10, it may be configured not to provide the n-type carrier accumulation layer 2 in the diode region 20. Also, similar to the IGBT region 10, the n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as a drift layer.

[0042] A p-type anode layer 25 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is provided between the n-type drift layer 1 and the first main surface. The p-type anode layer 25 may have the same p-type impurity concentration as the p-type base layer 15 of the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously. Also, they may be formed at the same depth in the direction toward the second main surface. Further, the p-type impurity concentration of the p-type anode layer 25 may be made lower than the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10 so as to reduce the amount of holes flowing into the diode region 20 during diode operation. By reducing the amount of holes flowing in during diode operation, the recovery current during diode operation can be reduced.

[0043] On the first main surface side of the p-type anode layer 25, a p+-type contact layer 24 is provided. The concentration of p-type impurities in the p+-type contact layer 24 may be the same as that of the p-type impurities in the p+-type contact layer 14 in the IGBT region 10, or may be different. The p+-type contact layer 24 constitutes the first main surface of the semiconductor substrate. Note that the p+-type contact layer 24 is a region with a higher concentration of p-type impurities than the p-type anode layer 25, and when it is necessary to distinguish between the p+-type contact layer 24 and the p-type anode layer 25, they may be individually named, or the p+-type contact layer 24 and the p-type anode layer 25 may be collectively referred to as the p-type anode layer.

[0044] In the diode region 20, an n+-type cathode layer 26 is provided on the second main surface side of the n-type buffer layer 3. The n+-type cathode layer 26 is provided between the n−-type drift layer 1 and the second main surface. The n+-type cathode layer 26 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+16 / cm3 to 1.0E+21 / cm3. As shown in FIG. 2, the n+-type cathode layer 26 is provided in part or all of the diode region 20. The n+-type cathode layer 26 constitutes the second main surface of the semiconductor substrate. Although not shown, in the region where the n+-type cathode layer 26 is formed as described above, p-type impurities may be selectively implanted further to provide a p-type cathode layer with a part of the region where the n+-type cathode layer 26 is formed being a p-type semiconductor.

[0045] As shown in FIG. 7, in the diode region 20 of the semiconductor device 110, a trench is formed that penetrates the p-type anode layer 25 from the first main surface of the semiconductor substrate and reaches the n−-type drift layer 1. By providing a diode trench electrode 21a in the trench of the diode region 20 via a diode trench insulating film 21b, a diode trench gate 21 is formed. The diode trench electrode 21a faces the n−-type drift layer 1 via the diode trench insulating film 21b.

[0046] As shown in FIG. 7, a barrier metal 5 is provided on the diode trench electrode 21a and the p+ type contact layer 24. The barrier metal 5 makes an ohmic contact with the diode trench electrode 21a and the p+ type contact layer 24, and is electrically connected to the diode trench electrode and the p+ type contact layer 24. The barrier metal 5 may have the same configuration as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. Note that, similar to the case of the IGBT region 10, the emitter electrode 6 may be brought into ohmic contact with the diode trench electrode 21a and the p+ type contact layer 24 without providing the barrier metal 5.

[0047] In FIG. 7, a configuration is shown in which a contact hole 19 is provided without providing an interlayer insulating film 4 on the diode trench electrode 21a of the diode trench 21, but the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in another cross section.

[0048] A collector electrode 7 is provided on the second main surface side of the n+ type cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 in the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 makes an ohmic contact with the n+ type cathode layer 26 and is electrically connected to the n+ type cathode layer 26.

[0049] FIG. 8 is a cross-sectional view taken along the dashed line D-D in FIG. 6 of the semiconductor device 110 and is a cross-sectional view of the diode region 20. It is different from the cross-sectional view taken along the dashed line C-C shown in FIG. 7 in that a p+-type contact layer 24 is not provided between the p-type anode layer 25 and the barrier metal 5, and the p-type anode layer 25 constitutes the first main surface of the semiconductor substrate. That is, the p+-type contact layer 24 shown in FIG. 7 is selectively provided on the first main surface side of the p-type anode layer 25.

[0050] FIG. 9 is a cross-sectional view showing the configuration of the termination region of a semiconductor device that is an RC-IGBT. FIG. 10(a) is a cross-sectional view taken along the dashed line E-E in FIG. 1 or FIG. 2 and is a cross-sectional view from the IGBT region 10 to the termination region 30. Further, FIG. 10(b) is a cross-sectional view taken along the dashed line F-F in FIG. 1 and is a cross-sectional view from the diode region 20 to the termination region 30.

[0051] As shown in FIGS. 9(a) and 9(b), the termination region 30 of the semiconductor device 110 has an n-type drift layer 1 between the first main surface and the second main surface of the semiconductor substrate. The first main surface and the second main surface of the termination region 30 are the same surfaces as the first main surface and the second main surface of the IGBT region 10 and the diode region 20, respectively. Also, the n-type drift layer 1 of the termination region 30 has the same configuration as the n-type drift layer 1 of the IGBT region 10 and the diode region 20 and is continuously and integrally formed.

[0052] On the first main surface side of the n-type drift layer 1, that is, between the first main surface of the semiconductor substrate and the n-type drift layer 1, a p-type terminal well layer 31 is provided. The p-type terminal well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+14 / cm3 to 1.0E+19 / cm3. The p-type terminal well layer 31 is provided so as to surround the cell region including the IGBT region 10 and the diode region 20. The p-type terminal well layer 31 is provided in a plurality of ring shapes, and the number of the p-type terminal well layers 31 provided is appropriately selected according to the breakdown voltage design of the semiconductor device 110. Further, an n+-type channel stopper layer 32 is provided on the outer edge side of the p-type terminal well layer 31, and the n+-type channel stopper layer 32 surrounds the p-type terminal well layer 31.

[0053] A p-type terminal collector layer 16a is provided between the n-type drift layer 1 and the second main surface of the semiconductor substrate. The p-type terminal collector layer 16a is continuously and integrally formed with the p-type collector layer 16 provided in the cell region. Therefore, it may be called the p-type collector layer 16 including the p-type terminal collector layer 16a. Further, in the configuration in which the diode region 20 is provided adjacent to the terminal region 30 as in the semiconductor device 110 shown in FIG. 1, as shown in FIG. 9(b), the p-type terminal collector layer 16a is provided such that the end on the diode region 20 side protrudes into the diode region 20 by a distance U2. In this way, by providing the p-type terminal collector layer 16a to protrude into the diode region 20, the distance between the n+-type cathode layer 26 of the diode region 20 and the p-type terminal well layer 31 can be increased, and the operation of the p-type terminal well layer 31 as an anode of the diode can be suppressed. The distance U2 may be, for example, 100 μm.

[0054] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is continuously and integrally formed from the cell region including the IGBT region 10 and the diode region 20 to the terminal region 30. On the other hand, an emitter electrode 6 continuous from the cell region and a terminal electrode 6a separated from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the terminal region 30.

[0055] The emitter electrode 6 and the terminal electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, sinSiN (semi-insulating Silicon Nitride). The terminal electrode 6a, the p-type terminal well layer 31, and the n+-type channel stopper layer 32 are electrically connected via a contact hole formed in the interlayer insulating film 4 provided on the first main surface of the terminal region 30. Further, a terminal protection film 34 is provided in the terminal region 30 to cover the emitter electrode 6, the terminal electrode 6a, and the semi-insulating film 33. The terminal protection film 34 may be formed of, for example, polyimide.

[0056] Next, a method for manufacturing the semiconductor device according to Embodiment 1 will be described. In the following description of the manufacturing method, the manufacturing method of the cell region is described, and the manufacturing methods of the terminal region 30 and the pad region 40 formed in an arbitrary structure are omitted.

[0057] FIGS. 10 to 15 are diagrams showing a method for manufacturing a semiconductor device that is an RC-IGBT. FIGS. 10 to 13 are diagrams showing a process of forming the front surface side of the semiconductor device 110, and FIGS. 14 and 15 are diagrams showing a process of forming the back surface side of the semiconductor device 110.

[0058] First, as shown in Fig. 10(a), a semiconductor substrate constituting the n-type drift layer 1 is prepared. For the semiconductor substrate, for example, a so-called FZ wafer manufactured by the FZ (Floating Zone) method or a so-called MCZ wafer manufactured by the MCZ (Magnetic applied CZochralki) method may be used, and it may be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the semiconductor device to be manufactured. For example, in a semiconductor device with a breakdown voltage of 1200V, the concentration of the n-type impurities is adjusted so that the resistivity of the n-type drift layer 1 constituting the semiconductor substrate is about 40 to 120 Ω·cm. As shown in Fig. 10(a), in the step of preparing the semiconductor substrate, the entire semiconductor substrate is the n-type drift layer 1. However, from the first main surface side or the second main surface side of such a semiconductor substrate, p-type or n-type impurity ions are implanted, and then diffused into the semiconductor substrate by heat treatment or the like to form a p-type or n-type semiconductor layer, and the semiconductor device 110 is manufactured.

[0059] As shown in Fig. 10(a), the semiconductor substrate constituting the n-type drift layer 1 includes regions that will become the IGBT region 10 and the diode region 20. Although not shown, a region that will become the termination region 30 is provided around the regions that will become the IGBT region 10 and the diode region 20. Hereinafter, the manufacturing method of the configurations of the IGBT region 10 and the diode region 20 of the semiconductor device 110 will be mainly described, but the termination region 30 of the semiconductor device 110 may be manufactured by a well-known manufacturing method. For example, when forming an FLR having a p-type termination well layer 51 as a breakdown voltage holding structure in the termination region 30, p-type impurity ions may be implanted and formed before processing the IGBT region 10 and the diode region 20 of the semiconductor device 110, or p-type impurity ions may be implanted and formed simultaneously when p-type impurities are ion-implanted into the IGBT region 10 or the diode region 20 of the semiconductor device 110.

[0060] Next, as shown in FIG. 10(b), an n-type impurity such as phosphorus (P) is implanted from the first main surface side of the semiconductor substrate to form an n-type carrier accumulation layer 2. Further, a p-type impurity such as boron (B) is implanted from the first main surface side of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by diffusing impurity ions by heat treatment after implanting impurity ions into the semiconductor substrate. Since the n-type impurity and the p-type impurity are ion-implanted after performing a mask process on the first main surface of the semiconductor substrate, they are selectively formed on the first main surface side of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20 and are connected to the p-type terminal well layer 51 in the termination region 30. Note that the mask process refers to a process of forming a mask on the semiconductor substrate in order to apply ion implantation or etching to a predetermined region of the semiconductor substrate through an opening formed in a predetermined region of the resist by applying a resist on the semiconductor substrate and using photolithography technology.

[0061] The p-type base layer 15 and the p-type anode layer 25 may be formed by simultaneously ion-implanting a p-type impurity. In this case, the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 are the same and have the same configuration. Further, the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 may be made different by ion-implanting p-type impurities separately into the p-type base layer 15 and the p-type anode layer 25 by a mask process.

[0062] Further, the p-type terminal well layer 51 formed in another cross section may be formed by ion-implanting p-type impurities simultaneously with the p-type anode layer 25. In this case, the depth and the p-type impurity concentration of the p-type terminal well layer 51 and the p-type anode layer 25 can be the same, enabling the same configuration. Also, it is possible to form the p-type terminal well layer 51 and the p-type anode layer 25 by simultaneously ion-implanting p-type impurities and set the p-type impurity concentrations of the p-type terminal well layer 51 and the p-type anode layer 25 to different concentrations. In this case, either one or both masks may be a mesh-shaped mask, and the aperture ratio may be changed. Also, by separately ion-implanting p-type impurities into the p-type terminal well layer 51 and the p-type anode layer 25 through mask processing, the depth and the p-type impurity concentration of the p-type terminal well layer 51 and the p-type anode layer 25 may be made different. The p-type terminal well layer 51, the p-type base layer 15, and the p-type anode layer 25 may be formed by simultaneously ion-implanting p-type impurities.

[0063] Next, as shown in FIG. 11(a), an n+-type source layer 13 is formed by selectively implanting n-type impurities into the first main surface side of the p-type base layer 15 of the IGBT region 10 through mask processing. The n-type impurities to be implanted may be, for example, arsenic (As) or phosphorus (P). Also, through mask processing, a p+-type contact layer 14 is formed by selectively implanting p-type impurities into the first main surface side of the p-type base layer 15 of the IGBT region 10, and a p+-type contact layer 24 is formed by selectively implanting p-type impurities into the first main surface side of the p-type anode layer 25 of the diode region 20. The p-type impurities to be implanted may be, for example, boron (B) or aluminum (Al). Next, as shown in FIG. 11(b), a trench 8 is formed that penetrates the p-type base layer 15 and the p-type anode layer 25 from the first main surface side of the semiconductor substrate and reaches the n-type drift layer 1. In the IGBT region 10, the side wall of the trench 8 that penetrates the n+-type source layer 13 constitutes a part of the n+-type source layer 13. The trench 8 may be formed by depositing an oxide film such as SiO2 on the semiconductor substrate, forming an opening in the oxide film of the portion where the trench 8 is to be formed by a masking process, and etching the semiconductor substrate using the oxide film with the opening as a mask. In FIG. 12(b), the pitch of the trench 8 is formed to be the same in the IGBT region 10 and the diode region 20, but the pitch of the trench 8 may be made different between the IGBT region 10 and the diode region 20. The pattern of the pitch of the trench 8 in a plan view can be appropriately changed by the mask pattern of the masking process.

[0064] Next, as shown in FIG. 12(a), the semiconductor substrate is heated in an atmosphere containing oxygen to form an oxide film 9 on the inner wall of the trench 8 and the first main surface of the semiconductor substrate. Among the oxide films 9 formed on the inner wall of the trench 8, the oxide film 9 formed in the trench 8 of the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. Also, the oxide film 9 formed in the trench 8 of the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed in a later process.

[0065] Next, as shown in FIG. 12(b), polysilicon doped with an n-type or p-type impurity is deposited in the trench 8 having the oxide film 9 formed on its inner wall by CVD (chemical vapor deposition) or the like to form the gate trench electrode 11a, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0066] Next, as shown in FIG. 13(a), after forming the interlayer insulating film 4 on the gate trench electrode 11a of the active trench gate 11 of the IGBT region 10, the oxide film 9 formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 4 may be, for example, SiO2. Then, contact holes are formed in the interlayer insulating film 4 deposited by mask processing. The contact holes are formed on the n+-type source layer 13, the p+-type contact layer 14, the p+-type contact layer 24, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0067] Next, as shown in FIG. 13(b), a barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by depositing titanium nitride by PVD (physical vapor deposition) or CVD.

[0068] The emitter electrode 6 may be formed, for example, by depositing an aluminum-silicon alloy (Al-Si-based alloy) on the barrier metal 5 by PVD such as sputtering or evaporation. Further, a nickel alloy (Ni alloy) may be formed on the formed aluminum-silicon alloy by electroless plating or electroplating to form the emitter electrode 6. When the emitter electrode 6 is formed by plating, a thick metal film can be easily formed as the emitter electrode 6, so that the heat capacity of the emitter electrode 6 can be increased and the heat resistance can be improved. When a nickel alloy is further formed by plating after forming the emitter electrode 6 made of an aluminum-silicon alloy by PVD, the plating process for forming the nickel alloy may be performed after processing on the second main surface side of the semiconductor substrate.

[0069] Next, as shown in FIG. 14(a), the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined thickness designed. The thickness of the ground semiconductor substrate may be, for example, 80 μm to 200 μm.

[0070] Next, as shown in FIG. 14(b), n-type impurities are implanted from the second main surface side of the semiconductor substrate to form an n-type buffer layer 3. Further, p-type impurities are implanted from the second main surface side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, and the termination region 30, or may be formed only in the IGBT region 10 or the diode region 20.

[0071] The n-type buffer layer 3 may be formed, for example, by implanting phosphorus (P) ions. Also, it may be formed by implanting protons (H+). Further, it may be formed by implanting both protons and phosphorus. Protons can be implanted from the second main surface of the semiconductor substrate to a deep position with relatively low acceleration energy. Also, the depth of proton implantation can be changed relatively easily by changing the acceleration energy. Therefore, when forming the n-type buffer layer 3 with protons, if implanted multiple times while changing the acceleration energy, an n-type buffer layer 3 wider in the thickness direction of the semiconductor substrate than when formed with phosphorus can be formed.

[0072] Also, since phosphorus can increase the activation rate as an n-type impurity compared to protons, forming the n-type buffer layer 3 with phosphorus can more surely suppress the punch-through of the depletion layer even in a thinned semiconductor substrate. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus. In this case, the protons are implanted at a deeper position from the second main surface than phosphorus.

[0073] The p-type collector layer 16 may be formed, for example, by implanting boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the second main surface side of the semiconductor substrate, the second main surface is irradiated with a laser and laser annealed, so that the implanted boron is activated and the p-type collector layer 16 is formed. At this time, the phosphorus for the n-type buffer layer 3 implanted at a relatively shallow position from the second main surface of the semiconductor substrate is also simultaneously activated. On the other hand, since protons are activated at a relatively low annealing temperature such as 350°C to 500°C, it is necessary to pay attention that the entire semiconductor substrate does not reach a temperature higher than 350°C to 500°C except for the process for activating protons after proton implantation. Since laser annealing can heat only the vicinity of the second main surface of the semiconductor substrate to a high temperature, it can be used for activating n-type impurities and p-type impurities even after proton implantation.

[0074] Next, as shown in FIG. 15(a), an n+-type cathode layer 26 is formed in the diode region 20. The n+-type cathode layer 26 may be formed, for example, by implanting phosphorus (P). As shown in FIG. 15(a), phosphorus is selectively implanted from the second main surface side by a mask process so that the boundary between the p-type collector layer 16 and the n+-type cathode layer 26 is located at a position of a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20 side. The implantation amount of the n-type impurity for forming the n+-type cathode layer 26 is larger than the implantation amount of the p-type impurity for forming the p-type collector layer 16. In FIG. 5 (a), the depths of the p-type collector layer 16 and the n+-type cathode layer 26 from the second main surface are shown to be the same, but the depth of the n+-type cathode layer 26 is equal to or greater than the depth of the p-type collector layer 16. In the region where the n+-type cathode layer 26 is formed, since it is necessary to implant an n-type impurity into the region where the p-type impurity is implanted to make it an n-type semiconductor, the concentration of the implanted p-type impurity is made higher than the concentration of the n-type impurity in all of the region where the n+-type cathode layer 26 is formed.

[0075] Next, as shown in FIG. 15(b), a collector electrode 7 is formed on the second main surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surfaces of the IGBT region 10, the diode region 20, and the termination region 30 on the second main surface. Further, the collector electrode 7 may be formed over the entire surface of the second main surface of the n-type wafer which is the semiconductor substrate. The collector electrode 7 may be formed by depositing an aluminum silicon alloy (Al—Si based alloy), titanium (Ti), etc. by PVD such as sputtering or vapor deposition, or may be formed by laminating a plurality of metals such as an aluminum silicon alloy, titanium, nickel, or gold. Furthermore, an electroless plating or an electrolytic plating may be performed on the metal film formed by PVD to further form a metal film as the collector electrode 7.

[0076] The semiconductor device 110 is fabricated through the above-described steps. Since a plurality of semiconductor devices 110 are fabricated in a matrix pattern on a single n-type wafer, the semiconductor device 110 is completed by cutting it into individual semiconductor devices 110 by laser dicing or blade dicing.

[0077] Next, the operation of the semiconductor device according to Embodiment 1 will be described.

[0078] FIG. 16 is a cross-sectional view showing the configuration of the boundary between the IGBT region and the diode region of the semiconductor device according to Embodiment 1. FIG. 16 is a cross-sectional view taken along the dashed line H-H in the semiconductor device 110 shown in FIG. 1.

[0079] The diode operation of the RC-IGBT will be described. During the diode operation, a positive voltage is applied to the emitter electrode 6 as compared with the collector electrode 7, and no gate drive voltage is applied to the active trench gate electrode 11a. By applying a positive voltage to the emitter electrode 6 as compared with the collector electrode 7, holes flow into the drift layer 1 from the anode layer 25 and the p-type base layer 15, and the flowing holes move toward the cathode layer 26. In the diode region 20a near the boundary with the IGBT region 10a, in addition to the holes from the anode layer 25, holes also flow in from the IGBT region 10a, so that the hole density is higher than that in the diode region 20a away from the IGBT region 10a. During the diode operation, a circulating current flows in the direction from the emitter electrode 6 toward the collector electrode 7.

[0080] As shown in Fig. 16, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10a protrudes by a distance U1 toward the diode region 20a from the boundary between the IGBT region 10a and the diode region 20a. In Fig. 16, a configuration is shown in which it protrudes by a distance U1 toward the diode region 20a on the right side of the drawing from the boundary between the IGBT region 10a and the diode region 20a on the right side of the drawing sheet, but it may also protrude by a distance U1 toward the diode region 20a on the left side of the drawing sheet from the boundary between the IGBT region 10a and the diode region 20a on the left side of the drawing sheet. Thus, by providing the p-type terminal collector layer 16 to protrude into the diode region 20a, the distance between the n+-type cathode layer 26 of the diode region 20a and the active trench gate 11 can be increased. Even when a gate drive voltage is applied to the active trench gate electrode 11a during the diode operation, it is possible to suppress the current from flowing from the channel formed adjacent to the active trench gate 11 of the IGBT region 10a to the n+-type cathode layer 26. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 110 which is an RC-IGBT, the distance U1 may be zero or a distance smaller than 100 μm. In Fig. 16, the boundary between the IGBT region 10a and the diode region 20a is described, but the same applies to the boundary between the IGBT regions 10 (10b, 10c, 10d) and the diode regions (20a, 20b, 20c).

[0081] Next, the IGBT operation of the RC-IGBT will be described. During IGBT operation, a negative voltage is applied to the emitter electrode 6 compared to the collector electrode 7, and a gate drive voltage is applied to the active trench gate electrode 11a, so that an inversion layer of the first conductivity type is partially formed in the p-type base layer 15 of the second conductivity type. Electrons flow from the n+-type source layer 13 into the n--type drift layer 1, and the flowing electrons move toward the p-type collector layer 16. That is, a main current flows in the direction from the collector electrode 16 toward the emitter electrode 6. When switching to the diode operation, the holes that were moving toward the n+-type cathode layer 26 change their moving direction and move in the direction toward the p-type anode layer 25. That is, a circulating current flows in the direction from the emitter electrode 6 toward the collector electrode 7.

[0082] When the main current and the reflux current flow, the semiconductor device generates heat. In the RC-IGBT, the reflux current flows during the diode operation, and the diode becomes the main heat generation source. During the IGBT operation, the main current flows, and the IGBT becomes the main heat generation source. If the IGBT region 10 and the diode region 20, which are cell regions, are all formed with the same size, the heat dissipation efficiency will be the same within the cell region, so the temperature rise at the center of the cell region with large heat interference will increase. On the other hand, as shown in FIG. 1, in the semiconductor device of Embodiment 1, the IGBT region 10a and the diode region 20a are provided at the positions closest to the center of the cell region. The IGBT region 10a is a region with a smaller size compared to the surrounding IGBT regions 10b, 10c, and 10d, and the diode region 20a is a region with a smaller size compared to the surrounding diode regions 20b and 20c.

[0083] Therefore, by reducing the size of the IGBT region and the diode region, which are heat sources at the center of the cell region, it is possible to promote heat diffusion not only in the substrate thickness direction but also in the first direction, and improve the heat dissipation from the heat sources during IGBT operation and diode operation. Thereby, the temperature rise at the center of the cell region can be suppressed, and the temperature uniformity of the semiconductor device can be improved. Note that the smallest region 10a in the IGBT region 10 and the smallest region 20a in the diode region 20 may be provided at the position closest to the center of the cell region. In the vicinity of each region, the IGBT region 10b or 10c may be the largest region in the IGBT region, and the diode region 20b may be the largest region in the diode region.

[0084] In addition, the configuration and operation of the semiconductor device of the comparative example will be described with reference to FIG. 17. When the size of the diode region 20a is larger than that of the IGBT region 10a and the heat generation amount of the diode region 20a is larger than that of the IGBT region 10a, there is a concern that the heat interference between the regions will increase. Appropriate heat interference promotes heat diffusion in the first direction and improves heat dissipation, but excessive heat interference leads to heat accumulation and causes local temperature rise. Note that the semiconductor device of the comparative example is different from the semiconductor device of Embodiment 1 in that the size of the IGBT region 10a located between the two diode regions 20a is smaller than that of the semiconductor device 110 of Embodiment 1.

[0085] When a main current and a reflux current flow through the IGBT region 10a and the diode region 20a respectively, and the semiconductor device generates heat, the generated heat diffuses in the semiconductor substrate and is mainly radiated to the outside through the collector electrode 7. As shown in FIG. 17, for example, when the diode region 20a on the right side of the paper surface generates heat, in the direction parallel to the semiconductor substrate surface, the heat generated on the semiconductor substrate surface diffuses in the semiconductor substrate so that the heat radiation distance becomes LD1 until it reaches the collector electrode 7. At this time, the angle at which the heat diffuses is about 45°, and the heat radiation distance LD1 is approximately equal to the thickness of the semiconductor substrate. When the size of the IGBT region 10a located between the two diode regions 20a is smaller than the above-described heat radiation distance LD1 in a plan view, for example, the heat generated from the diode region 20a on the right side of the paper surface diffuses through the IGBT region 10a to the diode region 20a.

[0086] On the other hand, as shown in FIG. 16, in the semiconductor device of Embodiment 1, since the IGBT region 10a is larger than the substrate thickness in a plan view, excessive heat interference between the diode regions 20a adjacent to the IGBT region 10a due to heat diffusion can be suppressed. In particular, in order to suppress heat interference from the diode regions 20a located on both sides of the IGBT region 10a, it is desirable that the size of the IGBT region 10a is larger than 2× the heat radiation distance LD1. That is, by being larger than twice the substrate thickness in a plan view, heat interference can be further suppressed. Although it has been described above that the IGBT region 10a is equal to or greater than the thickness of the semiconductor substrate, the same applies to the diode region 20a. For example, when the IGBT region 10a is adjacent to the diode region 20a, excessive heat interference between the adjacent IGBT regions 10a can be suppressed by the diode region 20a being equal to or greater than the thickness of the semiconductor substrate.

[0087] FIG. 18 is a cross-sectional view showing the configuration of the boundary between the IGBT region and the diode region of the semiconductor device 110 according to Embodiment 1, and is a cross-sectional view taken along the broken line J-J in the semiconductor device 110 shown in FIG. 1. As shown in FIG. 18, in the semiconductor device of Embodiment 1, the IGBT region 10d and the diode region 20c are provided adjacent to each other at a position closest to the end of the cell region on the side. The IGBT region 10d is a region larger in size than the IGBT regions 10a, 10b, and 10c, and is the largest region among the IGBT regions 10. The IGBT region 10a is a region smaller in size than the IGBT regions 10b, 10c, and 10d, and is the smallest region among the IGBT regions 10. And, as shown in FIG. 18, the 10d which is the largest region among the IGBT regions is desirably larger than the heat dissipation distance LD1 compared to the 10a which is the smallest region among the IGBT regions in order to improve the temperature uniformity of the RC-IGBT. For example, since the IGBT region 10d is larger than the substrate thickness compared to the IGBT region 10a, heat diffusion from the diode region 20c to the control pad 41 can be suppressed.

[0088] In the semiconductor device according to Embodiment 1, the IGBT region 10a and the diode region 20a are provided at a position closest to the center of the cell region. In the first direction, the width of the IGBT region 10a is equal to or less than the widths of the surrounding IGBT regions 10b, 10c, and 10d, and the width of the diode region 20a is equal to or less than the widths of the surrounding diode regions 20b and 20c. By adopting such a configuration, the heat dissipation can be enhanced by increasing the heat interference at the center of the cell region compared to the periphery, and the temperature rise at the center of the cell can be suppressed.

[0089] <Embodiment 2> The configuration of the semiconductor device according to Embodiment 2 will be described with reference to FIG. 2. FIG. 2 is a cross-sectional view showing the semiconductor device according to Embodiment 2. In Embodiment 2, the same components as those described in Embodiment 1 are denoted by the same reference numerals, and the description thereof is omitted.

[0090] In FIG. 2, the semiconductor device 111 is of the island type, and includes an IGBT region 10 (10a, 10b, 10c, 10d, 10e, 10f, 10g) and a diode region 20 (20a, 20b, 20c) within one semiconductor device. In the semiconductor device 110 according to Embodiment 1 shown in FIG. 1, a stripe-shaped semiconductor device in which the IGBT region 10 and the diode region 20 are linearly arranged alternately in a direction orthogonal to the extending direction of the IGBT region 10 and the diode region 20 is shown. However, in the semiconductor device 111 according to Embodiment 2 shown in FIG. 2, although the stripes of the IGBT region 10 (10a, 10b, 10c, 10d) are maintained, the stripe portion of the diode region 20 is divided into a plurality of regions by the IGBT region 10, and the plurality of diode regions 20 are arranged in an island shape, each being covered by a continuous IGBT region 10. Such an island-like arrangement is also called an island-type semiconductor device, etc. Even in the island type, a region in which the IGBT region 10 and the diode region 20 are linearly arranged alternately is called an alternating region. For example, it has an alternating region in which the IGBT region 10 and the diode region 20 are linearly arranged alternately on a virtual line including the H-H cross section and further extending the H-H cross section.

[0091] In the semiconductor device 110, the IGBT region 10c and the IGBT region 10d are connected by the IGBT region 10g, and the IGBT region 10g is arranged alternately with the diode region 20c in the direction in which the IGBT region 10c extends. The IGBT region 10b and the IGBT region 10c are connected by the IGBT region 10f, and the IGBT region 10f is arranged linearly alternately with the diode region 20b in the direction in which the IGBT region 10b extends. The IGBT region 10a and the IGBT region 10b are connected by the IGBT region 10e, and the IGBT region 10e is arranged alternately with the diode region 20a in the direction in which the IGBT region 10a extends.

[0092] As shown in FIG. 2, in the semiconductor device 111, the IGBT region 10a and the diode region 20a are provided at positions closest to the center of the cell region. The IGBT region 10a is a region where the width W1a in the first direction along the alternating region is smaller than those of the peripheral IGBT regions 10b, 10c, and 10d. The diode region 20a is a region where the width W2a in the first direction is smaller than those of the peripheral diode regions 20b and 20c. With such a configuration, by enhancing the heat dissipation at the center of the cell region compared to the periphery, the temperature rise at the center can be suppressed.

[0093] In addition, as another modification example of the second embodiment, as shown in FIGS. 19 and 20, the diode region 20 may be triangular or circular, and if it is island-shaped, it may be a polygon such as a triangle, an ellipse, or the like. Further, as shown in FIG. 19, the apex of the triangle may be arranged facing the center of the cell region, and by being provided such that the width in the direction parallel to the bottom surface of the triangle narrows from the end side of the cell region toward the center of the cell region, the thermal resistance at the center of the cell region can be reduced compared to the periphery, suppressing the temperature rise at the center, and improving the temperature uniformity of the cell region.

[0094] In FIGS. 2, 19, and 20, the diode region 20 is provided in an island shape, but the IGBT region 10 may also be in an island shape, and it is sufficient that either the diode region 20 or the IGBT region 10 is provided in an island shape. The number of diode regions 20 may be two or more, and is not limited to the numbers shown in FIGS. 2, 19, and 20. In addition, not only the target arrangement centered on a specific location, but also an arrangement that makes the temperature of the cell region uniform may be provided asymmetrically. Further, it may be provided such that the area is the smallest at the center of the cell region and gradually increases as it approaches the end from the center of the cell region. By reducing the thermal resistance at the center of the cell region compared to the periphery, the temperature rise at the center of the cell region can be suppressed, and the heat dissipation can be improved.

[0095] Therefore, in Embodiment 2, either the IGBT region 10 or the diode region 20 is island-shaped, the width of the IGBT region 10a in the first direction is equal to or less than the widths of the surrounding IGBT regions 10b, 10c, and 10d, and the width of the diode region 20a is equal to or less than the widths of the surrounding diode regions 20b and 20c. With such a configuration, heat dissipation can be enhanced by increasing the thermal interference at the center of the cell region compared to the periphery, and the temperature rise at the center of the cell can be suppressed.

[0096] <Embodiment 3> The configuration of the semiconductor device according to Embodiment 3 will be described with reference to FIG. 21. FIG. 21 is a cross-sectional view showing the semiconductor device according to Embodiment 3. In Embodiment 3, the same components as those described in Embodiments 1 and 2 are denoted by the same reference numerals, and the description thereof is omitted. The descriptions of the H-H cross-section and the J-J cross-section shown in FIG. 21 are omitted because they are the same as those in other embodiments.

[0097] As shown in FIG. 21, in the semiconductor device 114, the IGBT region 10 and the diode region 20, which are cell regions, are alternately arranged radially from the center of the cell region toward the end of the cell region. With such a configuration, the width is narrow at the center of the IGBT region 10 and the diode region 20 and becomes wider toward the end, so the temperature rise at the center can be suppressed by reducing the thermal resistance at the center of the cell region compared to the periphery, and the temperature uniformity of the cell region can be improved. Although the widths at the ends of the cell regions of the IGBT regions 10 are shown to be the same in a plurality of IGBT regions as shown in FIG. 21, the widths at the ends of the cell regions may be different in the plurality of IGBT regions, and the same applies to the diode region 20.

[0098] In the semiconductor device according to Embodiment 3, for example, it has an alternating region in which the IGBT region 10 and the diode region 20 are linearly arranged alternately on a virtual line including the H-H cross section and further extending the H-H cross section. In this alternating region, the width in the first direction along the alternating region of the IGBT region closest to the center of the cell region is less than or equal to the width in the first direction of the other IGBT regions, and the width in the first direction of the diode region closest to the center of the cell region is less than or equal to the width in the first direction of the other diode regions.

[0099] Therefore, in Embodiment 3, the IGBT region 10 and the diode region 20, which are cell regions, are alternately arranged radially from the center of the cell region toward the end of the cell region, and have a structure in which the width is narrow at the center of the IGBT region 10 and the diode region 20 and wide toward the end. Also, in the alternating region, the width in the first direction along the alternating region of the IGBT region closest to the center of the cell region is less than or equal to the width in the first direction of the other IGBT regions, and the width in the first direction of the diode region closest to the center of the cell region is less than or equal to the width in the first direction of the other diode regions. By adopting such a configuration, the heat dissipation can be enhanced by increasing the thermal interference at the center of the cell region compared to the periphery, and the temperature rise at the center of the cell can be suppressed.

[0100] <Embodiment 4> The configuration of the semiconductor device according to Embodiment 4 will be described with reference to FIG. 22. FIG. 22 is a cross-sectional view showing the semiconductor device according to Embodiment 4. In Embodiment 4, the same components as those described in Embodiments 1 to 3 are denoted by the same reference numerals and the description thereof is omitted.

[0101] As shown in FIG. 22, in the semiconductor device 115, the outer perimeters of the IGBT region 10 and the diode region 20 are each square-shaped, and the respective square shapes are concentric squares having the same center. The semiconductor device is arranged such that the centers of the square shapes, that is, the concentric positions, are alternately provided toward the end of the cell region. Note that the center of the concentric squares does not necessarily have to coincide with the center of the cell region and may be arranged within the cell region, and it is sufficient that the width of each region increases from the center of the concentric squares toward the end of the cell region. Note that the outer perimeters of the IGBT region 10 and the diode region 20 may be polygonal or circular instead of square-shaped.

[0102] The IGBT region 10 and the diode region 20 are alternately arranged in concentric squares, and the concentric squares are arranged within the cell region. The central region is island-shaped, and the rest is provided in an annular shape. The IGBT region 10 and the diode region 20 of each region whose outer perimeter is arranged in concentric squares are provided in concentric squares such that the width is the narrowest at the center of the cell region and increases toward the end of the cell region. That is, the width W1a of the IGBT region 10a is equal to or less than the widths of the peripheral IGBT regions 10b, 10c, 10d, and the width W2a of the diode region 20a is equal to or less than the widths of the peripheral diode regions 20b, 20c.

[0103] With such a configuration, by increasing the thermal interference at the center of the cell region compared to the periphery, the temperature rise at the center can be suppressed, and the temperature uniformity of the cell region can be improved. As another modification of Embodiment 4, as shown in FIG. 23, the diode regions 20 may be scattered within the region of the concentric squares represented by the dotted line, and the IGBT regions 10a, 10b, 10c, 10d may be connected by the IGBT regions 10e, 10f, 10g, respectively.

[0104] For example, the concentric rectangular IGBT region 10c and the concentric rectangular IGBT region 10d are connected by the IGBT region 10g, and the IGBT regions 10g are alternately arranged with the diode regions 20c that are scattered in a concentric rectangular pattern. The concentric rectangular IGBT region 10b and the concentric rectangular IGBT region 10c are connected by the IGBT region 10f, and the IGBT regions 10f are alternately arranged with the diode regions 20b that are scattered in a concentric rectangular pattern. The IGBT region 10a, which is an island, and the concentric rectangular IGBT region 10b are connected by the IGBT region 10e, and the IGBT regions 10e are alternately arranged with the diode regions 20a that are scattered in a concentric rectangular pattern. Note that the concentric rectangle may be a round concentric rectangle with rounded corners. In other words, in the plurality of diode regions 20 provided in an island shape, when a virtual line connecting adjacent island-shaped regions along the end of the cell region is drawn, a plurality of virtual lines can be drawn, and the plurality of virtual lines form a concentric rectangular shape having a center within the cell region. For example, a first island group composed of a plurality of island-shaped diode regions 20a arranged at a first distance from the end of an annular cell region is surrounded by a first virtual line formed by connecting in a ring the virtual lines drawn in contact with the portion of the diode region 20a closest to the end of the cell region and a second virtual line formed by connecting in a ring the virtual lines drawn in contact with the portion of the diode region 20a farthest from the end of the cell region. A second island group composed of a plurality of island-shaped diode regions 20b arranged at a second distance from the end of the annular cell region is surrounded by a third virtual line formed by connecting in a ring the virtual lines drawn in contact with the portion of the diode region 20b closest to the end of the cell region and a fourth virtual line formed by connecting in a ring the virtual lines drawn in contact with the portion of the diode region 20b farthest from the end of the cell region. A third island group composed of a plurality of island-shaped diode regions 20c arranged at a third distance from the end of the annular cell region is surrounded by a fifth virtual line formed by connecting in a ring the virtual lines drawn in contact with the portion of the diode region 20c closest to the end of the cell region and a sixth virtual line formed by connecting in a ring the virtual lines drawn in contact with the portion of the diode region 20c farthest from the end of the cell region.The region surrounded by the first virtual line and the second virtual line, the region surrounded by the third virtual line and the fourth virtual line, and the region surrounded by the fifth virtual line and the sixth virtual line have the same center. Note that although three types of island groups are described, two or more types are sufficient.

[0105] Furthermore, as shown in FIGS. 24 and 25, the diode region 20 may be triangular or circular, and if it is an island-shaped island type, it may be a polygon such as a triangle, an ellipse, or the like. Also, as shown in FIG. 24, the vertices of the triangle may be arranged facing the center of the cell region, and by providing it so that the width in the direction parallel to the bottom surface of the triangle becomes narrower from the end side of the cell region toward the center of the cell region, the thermal resistance at the center of the cell region can be reduced compared to the periphery, suppressing the temperature rise at the center and improving the temperature uniformity of the cell region. Note that in FIGS. 22 to 25, the diode region 20 is provided in an island shape, but the IGBT region 10 may also be in an island shape, and as long as either the diode region 20 or the IGBT region 10 is provided in an island shape.

[0106] Note that the number of diode regions 20 may be two or more, and is not limited to the numbers shown in FIGS. 22 to 25. Note that it may be provided asymmetrically as long as it is an arrangement that not only arranges objects centered on a specific location but also equalizes the temperature of the cell region. Also, it may be provided such that the area is the smallest at the center of the cell region and gradually increases as it approaches the end from the center of the cell region, suppressing the temperature rise at the center of the cell region by reducing the thermal resistance at the center of the cell region compared to the periphery and improving the heat dissipation performance.

[0107] In the semiconductor device according to Embodiment 4, for example, it has an alternating region in which the IGBT region 10 and the diode region 20 are arranged linearly and alternately on a virtual line including the H-H cross section and further extending the H-H cross section. In this alternating region, the width in the first direction along the alternating region of the IGBT region closest to the center of the cell region is less than or equal to the width in the first direction of the other IGBT regions, and the width in the first direction of the diode region closest to the center of the cell region is less than or equal to the width in the first direction of the other diode regions.

[0108] Therefore, in Embodiment 4, the IGBT region 10 and the diode region 20 are alternately arranged in a concentric square shape centered on the center of the cell region, and the IGBT region 10 and the diode region 20 are provided in a concentric square shape such that the width is narrow at the center of the cell region and becomes wider toward the end of the cell region. Thus, by reducing the thermal resistance at the center of the cell region compared to the periphery, the temperature rise at the center can be suppressed, and the heat dissipation performance can be improved.

[0109] In Embodiment 4, as shown in FIG. 22, a configuration in which the IGBT region 10 and the diode region 20 are provided in a concentric square shape is shown. However, it is not necessary for the shape to be square as long as it is concentric, and it may be a polygon such as a triangle or an octagon, or it may be a circular shape.

[0110] <Embodiment 5> This embodiment applies the semiconductor device according to the above-described Embodiments 1 to 4 to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, hereinafter, as Embodiment 5, a case where the present disclosure is applied to a three-phase inverter will be described.

[0111] FIG. 26 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0112] The power conversion system shown in FIG. 26 includes a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source and supplies DC power to the power conversion device 200. The power source 100 can be configured by various things. For example, it can be configured by a DC system, a solar cell, a storage battery, or it may be configured by a rectifier circuit or an AC / DC converter connected to an AC system. Further, the power source 100 may be configured by a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0113] The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300. It converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. As shown in FIG. 26, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals for driving the switching elements of the main conversion circuit 201, and a control circuit 203 that outputs control signals for controlling the drive circuit 202 to the drive circuit 202.

[0114] The load 300 is a three-phase motor driven by the AC power supplied from the power conversion device 200. Note that the load 300 is not limited to a specific application and is a motor mounted on various electrical devices. For example, it is used as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0115] Hereinafter, the details of the power conversion device 200 will be described. The main conversion circuit 201 includes switching elements (not shown). By switching the switching elements, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300. There are various specific circuit configurations of the main conversion circuit 201. The main conversion circuit 201 according to the present embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements. The semiconductor devices according to any of the above-described Embodiments 1 to 4 are applied to each switching element of the main conversion circuit 201. The six switching elements are connected in series in pairs of two switching elements to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Then, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0116] The drive circuit 202 generates a drive signal for driving the switching elements of the main conversion circuit 201 and supplies it to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with the control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of each switching element. When maintaining the switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

[0117] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that a desired amount of power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time (on-time) during which each switching element of the main conversion circuit 201 should be in the on state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state and an off signal is output to the switching element that should be in the off state at each point in time. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrodes of each switching element in accordance with this control signal.

[0118] In the power conversion device according to the present embodiment, since the semiconductor devices according to Embodiments 1 to 4 are applied as the switching elements of the main conversion circuit 201, the temperature rise at the center can be suppressed by reducing the thermal resistance at the center of the cell region compared to the periphery, and the heat dissipation performance can be improved.

[0119] In this embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described. However, the present disclosure is not limited to this and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but it may also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, the present disclosure may be applied to a single-phase inverter. Further, when supplying power to a DC load or the like, it is also possible to apply the present disclosure to a DC / DC converter or an AC / DC converter.

[0120] In addition, the power conversion device to which the present disclosure is applied is not limited to the case where the above-described load is an electric motor. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power feeding system. Furthermore, it can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

[0121] In the above embodiment, the switching element is shown as being formed of silicon, but it may be formed of a wide bandgap semiconductor having a larger bandgap than silicon. Examples of the wide bandgap semiconductor include silicon carbide, gallium nitride-based materials, or diamond.

[0122] The switching element formed of such a wide bandgap semiconductor has high breakdown voltage and high allowable current density, so that the switching element can be miniaturized. By using these miniaturized switching elements, it is possible to miniaturize the semiconductor module incorporating these elements.

[0123] In addition, since it also has high heat resistance, it is possible to miniaturize the heat dissipation fins of the heat sink and to air-cool the water-cooled part, so that the semiconductor device can be further miniaturized.

[0124] Furthermore, since the power loss is low, it is possible to improve the efficiency of the switching element, and by extension, it is possible to improve the efficiency of the semiconductor device.

[0125] Although some embodiments of the present disclosure have been described, these embodiments are presented by way of example. Various omissions, replacements, and changes can be made without departing from the gist. Also, the embodiments can be combined with each other.

[0126] Hereinafter, aspects of the present disclosure will be collectively described as appendices.

[0127] (Appendix 1) A semiconductor device including a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface facing the first main surface, a trench gate provided penetrating through the emitter layer of the first conductivity type and the base layer of the second conductivity type from the first main surface of the semiconductor substrate, and an IGBT region having a collector layer of the second conductivity type provided on the second main surface side of the drift layer; a diode region having an anode layer of the second conductivity type provided on the first main surface side of the drift layer and a cathode layer of the first conductivity type provided on the second main surface side of the drift layer; a cell region including an alternating region configured by the IGBT region and the diode region, in which the IGBT region and the diode region are alternately arranged linearly in a plan view; In a first direction along the alternating region, the widths of the IGBT region and the diode region are not constant respectively, and are arranged to have two or more types of widths respectively; In the alternating region, the width of the IGBT region closest to the center of the cell region in the first direction is less than or equal to the widths of the other IGBT regions in the first direction, and the width of the diode region closest to the center of the cell region in the first direction is less than or equal to the widths of the other diode regions in the first direction. A semiconductor device. (Appendix 2) The semiconductor device according to Additional Note 1, wherein in the alternating region, the width of the IGBT region in the first direction gradually increases from the IGBT region closest to the center of the cell region to the IGBT region closest to the end of the cell region in the first direction. (Additional Note 3) The semiconductor device according to Additional Note 1 or 2, wherein in the alternating region, the width of the diode region in the first direction gradually increases from the diode region closest to the center of the cell region to the diode region closest to the end of the cell region in the first direction. (Additional Note 4) The semiconductor device according to Additional Note 1, wherein in the alternating region, the width of the other IGBT regions in the first direction, excluding the IGBT region closest to the center of the cell region and the IGBT region closest to the end of the cell region in the first direction, is the widest among the widths of the IGBT regions in the first direction, and the width of the other diode regions in the first direction, excluding the diode region closest to the center of the cell region and the diode region closest to the end of the cell region in the first direction, is the widest among the widths of the diode regions in the first direction. (Additional Note 5) The semiconductor device according to any one of Additional Notes 1 to 4, wherein in the alternating region, the width of the IGBT region closest to the center of the cell region in the first direction is equal to or greater than the thickness of the semiconductor substrate. (Additional Note 6) The semiconductor device according to any one of Additional Notes 1 to 5, wherein in the alternating region, the width of the diode region closest to the center of the cell region in the first direction is equal to or greater than the thickness of the semiconductor substrate. (Additional Note 7) The semiconductor device according to any one of Additional Notes 1 to 6, wherein the IGBT region and the diode region are provided to extend in a direction orthogonal to the first direction, and are alternately provided along the first direction in the alternating region. (Additional Note 8) The semiconductor device according to any one of Appendices 1 to 6, wherein the IGBT region and the diode region are provided radially such that the width in the first direction increases from the center of the cell region toward the end of the cell region. (Appendix 9) In a plan view, the IGBT region and the diode region each have an outer periphery that is polygonal or circular, and the polygonal or circular shapes have the same center, and the IGBT region and the diode region are alternately provided from the same center toward the end of the cell region. The semiconductor device according to any one of Appendices 1 to 6. (Appendix 10) The semiconductor device according to any one of Appendices 1 to 6, wherein one of the IGBT region and the diode region is divided into a plurality of island-shaped regions surrounded by the other region in a plan view. (Appendix 11) The semiconductor device according to Appendix 10, wherein the island-shaped region is provided in a polygonal or circular shape in a plan view. (Appendix 12) A first island group composed of a plurality of the island-shaped regions arranged at a first distance from the end of the annular cell region, A second island group composed of a plurality of the island-shaped regions arranged at a second distance from the end of the annular cell region, A first virtual line formed by connecting in a ring a virtual line drawn in contact with the portion of the island-shaped regions belonging to the first island group that is closest to the end of the cell region, A second virtual line formed by connecting in a ring a virtual line drawn in contact with the portion of the island-shaped regions belonging to the first island group that is farthest from the end of the cell region, A third virtual line formed by connecting in a ring a virtual line drawn in contact with the portion of the island-shaped regions belonging to the second island group that is closest to the end of the cell region, A fourth virtual line formed by connecting in a ring a virtual line drawn in contact with the portion of the island-shaped regions belonging to the second island group that is farthest from the end of the cell region, and comprising The semiconductor device according to Appendix 10 or 11 having the same center, wherein one region is surrounded by the first virtual line and the second virtual line, and the other region is surrounded by the third virtual line and the fourth virtual line. (Appendix 13) A power conversion device having the semiconductor device according to Appendices 1 to 12, and including a main conversion circuit configured to convert input power and output the converted power, a drive circuit configured to output a drive signal for driving the semiconductor device to the semiconductor device, and a control circuit configured to output a control signal for controlling the drive circuit to the drive circuit.

Description of Reference Numerals

[0128] 1 n-type drift layer 2 n-type carrier accumulation layer 3 n-type buffer layer 4 interlayer insulating film 5 barrier metal 6 emitter electrode 7 collector electrode 10 (10a, 10b, 10c, 10d) IGBT region 11 active trench gate 11a gate trench electrode 11b gate trench insulating film 11c bottom surface of active trench gate 11d side wall of active trench gate 12 dummy trench gate 12a dummy trench electrode 12b dummy trench insulating film 13 n+-type source layer 14 p+-type contact layer 15 p-type base layer 16 p-type collector layer 19 contact hole 20 (20a, 20b, 20c) diode region 21 diode trench gate 21a diode trench electrode ​21b Diode trench insulating film 21c Bottom surface of diode trench gate 21d Side wall of diode trench gate 24 p+ type contact layer 25 p type anode layer 26 n+ type cathode layer 30 Terminal region 31 p type terminal well layer 51 Boundary trench gate 51a Boundary trench gate electrode 51b Boundary trench gate insulating film 51c Bottom surface of boundary trench gate 51d Side wall of boundary trench gate 52 Back surface dummy trench gate 52a Back surface dummy trench gate electrode 52b Back surface dummy trench gate insulating film 52c Bottom surface of back surface dummy trench gate 52d Side wall of back surface dummy trench gate 100 Power supply 110~118 Semiconductor device 200 Power conversion device 201 Main conversion circuit 202 Drive circuit 203 Control circuit 300 Load

Claims

1. A semiconductor device including a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface facing the first main surface, a trench gate provided penetrating through an emitter layer of the first conductivity type and a base layer of a second conductivity type from the first main surface of the semiconductor substrate, and an IGBT region having a collector layer of the second conductivity type provided on the second main surface side of the drift layer, a diode region having an anode layer of the second conductivity type provided on the first main surface side of the drift layer and a cathode layer of the first conductivity type provided on the second main surface side of the drift layer, and becoming a heat source when a reflux current flows, a cell region including an alternating region formed of the IGBT region and the diode region, and in a plan view, the IGBT region and the diode region are alternately arranged linearly, in a first direction along the alternating region, the widths of the IGBT region and the diode region are not constant respectively, and are arranged to have two or more types of widths respectively, in the alternating region, the width of the IGBT region in the first direction closest to the center of the cell region is less than or equal to the width of the other IGBT regions in the first direction, and the width of the diode region in the first direction closest to the center of the cell region is less than or equal to the width of the other diode regions in the first direction. A semiconductor device.

2. The semiconductor device according to claim 1, wherein in the alternating region, the width of the IGBT region in the first direction gradually increases from the IGBT region closest to the center of the cell region toward the IGBT region closest to the end of the cell region in the first direction.

3. The semiconductor device according to claim 1, wherein in the alternating region, the width of the diode region in the first direction gradually increases from the diode region closest to the center of the cell region toward the diode region closest to the end of the cell region in the first direction.

4. In the alternating region, the width in the first direction of the other IGBT regions excluding the IGBT region closest to the center of the cell region and the IGBT region closest to the end of the cell region in the first direction is the widest among the widths in the first direction of the IGBT regions, and the width in the first direction of the other diode regions excluding the diode region closest to the center of the cell region and the diode region closest to the end of the cell region in the first direction is the widest among the widths in the first direction of the diode regions. The semiconductor device according to claim 1, characterized in that.

5. In the alternating region, the width in the first direction of the IGBT region closest to the center of the cell region is equal to or greater than the thickness of the semiconductor substrate. The semiconductor device according to claim 1, characterized in that.

6. In the alternating region, the width in the first direction of the diode region closest to the center of the cell region is equal to or greater than the thickness of the semiconductor substrate. The semiconductor device according to claim 1, characterized in that.

7. The IGBT region and the diode region are provided so as to extend in a direction orthogonal to the first direction, and are alternately provided along the first direction in the alternating region. The semiconductor device according to claim 1, characterized in that.

8. The IGBT region and the diode region are provided in a radial shape in which the width in the first direction becomes wider from the center of the cell region toward the end of the cell region. The semiconductor device according to claim 1, characterized in that.

9. In a plan view, the outer peripheries of the IGBT region and the diode region are each polygonal or circular, and the polygonal or circular shapes each have the same center, and the IGBT region and the diode region are alternately provided from the same center toward the end of the cell region. The semiconductor device according to claim 1, characterized in that.

10. Either one of the IGBT region and the diode region is provided by being divided into a plurality of island-shaped regions surrounded by the other region in a plan view. The semiconductor device according to claim 1, characterized in that.

11. The island-shaped region is provided in a polygonal or circular shape in a plan view. The semiconductor device according to claim 10, characterized in that.

12. A first island group including a plurality of the island-shaped regions arranged at a first distance from an end of the annular cell region; A second island group including a plurality of the island-shaped regions arranged at a second distance from an end of the annular cell region; A first virtual line formed by connecting in a ring shape virtual lines drawn in contact with a portion of the island-shaped regions belonging to the first island group that is closest to the end of the cell region; A second virtual line formed by connecting in a ring shape virtual lines drawn in contact with a portion of the island-shaped regions belonging to the first island group that is farthest from the end of the cell region; A third virtual line formed by connecting in a ring shape virtual lines drawn in contact with a portion of the island-shaped regions belonging to the second island group that is closest to the end of the cell region; A fourth virtual line formed by connecting in a ring shape virtual lines drawn in contact with a portion of the island-shaped regions belonging to the second island group that is farthest from the end of the cell region, the semiconductor device according to claim 10, comprising: A region surrounded by the first virtual line and the second virtual line and a region surrounded by the third virtual line and the fourth virtual line have the same center.

13. A main conversion circuit that has the semiconductor device according to claims 1 to 12 and converts and outputs input power; A drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; A control circuit that outputs a control signal for controlling the drive circuit to the drive circuit; A power conversion device comprising:

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