Selective Interconnection in the Wiring Process of an Integrated Circuit Metallization Stack

Abstract

To provide interconnect structures and fabrication methods for integrating multiple functions within an IC.SOLUTION: An integrated circuit die structure 100 comprises a host chip 102, which has a device layer 104 and one or more first metallization levels over adjacent first and second regions of the device layer. The first metallization levels are interconnected with the device layer. An interconnect chiplet 101 is over the first metallization levels within the first region. The interconnect chiplet comprises a plurality of second metallization levels, and a plurality of third metallization levels over the first metallization levels within the second region and adjacent to the interconnect chiplet. An interconnect feature dimension and / or composition differs between one of the second metallization levels and an adjacent one of the third metallization levels.SELECTED DRAWING: Figure 1

Description

Background Art

[0001] Monolithic manufacturing methods can introduce certain constraints on device architecture that can limit the performance of integrated circuit (IC) devices. Heterogeneous integration in which multiple independently manufactured IC dies are integrated within the same package (according to multi-chip packaging technology, wafer stacking technology, or die stacking technology) can have high manufacturing costs, lower insertion efficiency, and large Z-height problems. Currently, depending on the type of IC device (e.g., CPU, GPU, FPGA, RFIC, etc.), the choice of design rules for the thickness and dimensions of the interconnect layers within the metallization stack wiring process (BEOL) of the integrated circuit is affected. Often, an IC chip manufacturing facility will provide a set of design rules for a particular technology node that has the ability to meet a given performance goal. However, when multiple functions are integrated within an IC according to current semiconductor processing methods, the performance or cost of certain functional blocks may be sub-optimal within the resulting integrated circuit device.

Brief Description of the Drawings

[0002] Multiple embodiments of the present disclosure will be more fully understood from the forms for carrying out the invention given below and from the accompanying drawings of the various embodiments of the present disclosure. However, these should not be construed as limiting the present disclosure to specific embodiments, but are for illustrative and understanding purposes only. Figures classified as "cross-sectional", "profile", "plan", and "isometric" correspond to orthogonal planes within an orthogonal coordinate system. Thus, cross-sectional and profile views are interpreted as the x-z plane, plan views are interpreted as the x-y plane, and isometric views are interpreted as a three-dimensional orthogonal coordinate system (x-y-z). Where necessary, the drawings are classified by axes indicating the direction of the figure.

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DETAILED DESCRIPTION OF THE INVENTION

[0012] References to "an embodiment", "one embodiment", "some embodiments", or "other embodiments" in this specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least some embodiments, but not necessarily all embodiments. The various expressions "an embodiment", "one embodiment", or "some embodiments" do not necessarily all refer to the same embodiment. When the specification states that a component, mechanism, structure, or characteristic "may", "might", or "could" be included, it is not essential that the particular component, mechanism, structure, or characteristic be included. When the specification or claims refer to "a" or "an" element, this does not mean that there is only one such element. When the specification or claims refer to "additional" elements, this does not preclude the presence of more than one additional element.

[0013] The term "microprocessor" generally refers to an integrated circuit (IC) package that includes a central processing unit (CPU) or a microcontroller. The microprocessor package is referred to as a "microprocessor" in this disclosure. A microprocessor socket houses the microprocessor and electrically couples it to a printed circuit board (PCB).

[0014] As used herein, the term "backend of line (BEOL)" generally refers to the operations after device fabrication on a semiconductor wafer. After forming active and passive devices in a circuit layer on a semiconductor wafer in a substrate fabrication process (e.g., a substrate process or FEOL), a series of operations in which a metal structure is formed over the semiconductor device (metallization) comprises the BEOL portion of the fabrication process.

[0015] As used herein, the term "chiplet" generally refers to a small and thin die that is embedded in the BEOL metallization of a larger host die. In the various embodiments described, a chiplet comprises at least an interconnect metallization stack and is thus referred to herein as an "interconnect chiplet". Such interconnect chiplets may or may not include a semiconductor substrate. As such, interconnect chiplets need not include active devices, but may include active devices. Interconnect chiplets may hold, for example, dedicated integrated circuits such as clock circuits, active repeater banks for long-distance on-die interconnects, etc.

[0016] The meanings of "a", "an", and "the" include references to the plural form. The meaning of "in" includes "in" and "on". The vertical direction is in the z-direction, and it is understood that descriptions of "top", "bottom", "above", "over", and "below" refer to relative positions in the z-dimension in the ordinary sense. Generally, "top", "above", and "over" refer to upper positions in the z-dimension, while "bottom", "below", and "under" refer to lower positions in the z-dimension. The term "on" is used in the present disclosure to indicate that one mechanism or object is in an upper position relative to a lower mechanism or object and is in direct contact with them. However, it is understood that the various embodiments are not necessarily limited to the directions or configurations shown in the figures.

[0017] The terms "substantially", "close", "approximately", "near", and "about" generally (unless otherwise specified) refer to within + / - 10% of the target value. Unless otherwise specified, the use of ordinal adjectives such as "first", "second", and "third" merely indicates that different instances of like objects are being referred to in order to describe a common object, and is not intended to imply that the objects so described must be in a given order, either temporally, spatially, or in any other manner, whether sequential or otherwise.

[0018] For purposes of the present disclosure, the terms "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of the present disclosure, the term "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0019] An integrated circuit (IC) device structure of a composite material is described herein that comprises one or more interconnected chiplets selectively embedded within a host wiring process (BEOL) metallization level on a host chip (die). According to multiple embodiments disclosed herein, the interconnected chiplets provide a stack-shaped and material set of selective interconnections to an integrated circuit on the host die, optimizing the performance of the host integrated circuit. By the interconnected chiplets, the host integrated circuit may comprise a composite material of multiple functional sub-circuits or circuit portions. Next, each sub-circuit of the host circuit may have a set of design rules for the shape of the optimal interconnections for optimal performance. According to multiple embodiments of the present disclosure, an appropriate interconnected chiplet may be selected to meet a set of design rules for multiple interconnections that can be selectively integrated into the BEOL stack above the corresponding sub-circuit of the host chip. As an example, the design rules for a first sub-circuit dedicated to signal transmission may require a high-density interconnect shape satisfied by a first interconnected chiplet, while the design rules for an adjacent second sub-circuit dedicated to processing or memory may require a high-performance interconnect stack shape satisfied by the interconnect stack of the host BEOL or the interconnect stack of another chiplet. The selective placement of the chiplets can thus optimize the vertical interconnections between the block of the integrated circuit below the chiplets and the first-level interconnect (FLI) interface layer of the interconnect stack of the host BEOL. Next, the FLI interface layer can be coupled to any FLI architecture typical of an IC chip in signal and power transmission to a package or interposer substrate.

[0020] According to some embodiments disclosed herein, an IC device structure of a composite material has a laterally heterogeneous BEOL metallization stack. Each of one or more interconnected chiplets embedded in a host BEOL metallization stack generally has an interconnect shape and / or a dielectric material different from that of the host BEOL metallization stack. In some embodiments, the interconnected chiplets comprise a functional material interleaved with a dielectric such as, but not limited to, a magnetic material or a piezoelectric material. In some embodiments, one or more interlayer dielectric materials of the embedded chiplets are different from the native interlayer dielectric of the host BEOL metallization stack. As an example, a chiplet having a high-density interconnect shape may comprise an interlayer dielectric having a lower relative dielectric constant or dielectric constant (k) than the dielectric of the host BEOL stack. A low-k dielectric can reduce the capacitance between electrodes between the dense wiring and other metallization mechanisms in the interconnect stack of the chiplet, enabling high-density transmission of high-speed data signals.

[0021] According to multiple embodiments of the present disclosure, the interconnected chiplets are integrated at any layer of the host BEOL metallization stack by hybrid bonding. The interconnected chiplets may each have a multi-level metallization stack having a top-level metallization that interfaces with a lower metallization layer in the host BEOL stack. The pitch and dimensions of the mechanisms in the interfaced metal layers may be adapted to the metal bonding of substantially overlapping opposing structures. In some embodiments, a diffusion bond is formed between the interfaced metal mechanisms resulting from the hybrid bonding process, enabling the chiplet to be directly bonded to the host BEOL stack.

[0022] The hybrid bonding process may include placing the chiplet within the BEOL metallization stack and subsequently performing a bonding thermal anneal. Opposing metallization structures are placed in direct contact at the bonding interface. The interface die is then subjected to a thermal anneal that enables the interdiffusion of metal atoms between the interfaced metal structures. Molecular bonding between interfaced dielectrics having a similar surface chemistry or molecular structure may be present simultaneously. For example, opposing surface silanol groups of silicate-containing dielectrics may be joined together by a condensation reaction. The resulting structure of the chiplet-host chip composite material may be processed as a monolithic composite material chip and may then be assembled into a package using standard package assembly tools and procedures.

[0023] The interconnect chiplet may be manufactured partially or fully separately from the host chip. The partially or fully manufactured chiplet may be separated from the donor wafer and placed on the host chip wafer by any suitable technique (e.g., a pick-and-place operation) at any appropriate stage of the BEOL metallization of the host IC. The pick-and-place process may be performed using a die-wafer bonding apparatus having an alignment accuracy of 200 nm or less. Such an apparatus may have an ISO 3 or better cleanliness to ensure the placement and bonding of selected interconnect chiplets with high yield. Any misalignment inaccuracies may be compensated for by the metallization stack on the interconnect chiplet. For example, the critical dimensions of the mechanism may increase from the internal (lower) metallization level to the external (upper) metallization level to critical dimensions suitable for the alignment tolerance of subsequent processing needs. The coarser mechanism of the outermost metallization level of the interconnect chiplet may thus match the pitch of the mechanism within the host BEOL stack, allowing for some offset between the chiplet and the interconnect mechanism of the host die.

[0024] FIG. 1 shows a cross-sectional view in the x-z plane of a composite die structure 100 according to some embodiments of the present disclosure.

[0025] The die structure 100 of the composite material comprises an interconnect chiplet 101 integrated (depicted by the dashed enclosure) within a common metallization stack (BEOL stack 102) on the host chip 103. The BEOL metallization stack 102 comprises a plurality of metallization levels from M1 to Mx coupled to the device layer 104. The substrate 105 comprises a semiconductor material, and the upper 50 - 1000 nm thereof may comprise, for example, a plurality of transistors and / or other active devices and passive devices within the device layer 104. In some embodiments, the substrate 105 comprises one or more semiconductor materials such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium phosphide (GaP), gallium nitride (GaN), gallium indium nitride (GaInN), or indium phosphide (InP). In some embodiments, the substrate 105 is a silicon on insulator (SOI) chip having a buried oxide (BOX) layer several microns below the surface. The device layer 104 may be formed in the semiconductor material above the BOX layer. The device layer 104 may have a thickness ranging from 100 to 1000 nm and is integral with the substrate 105 having a thickness ranging up to 775 microns. In other embodiments, the substrate 105 is a bulk silicon substrate and the device layer 104 is merely the upper portion of the bulk substrate.

[0026] In some embodiments, the host chip device layer 104 comprises active devices, passive devices, or a combination of active and passive devices. The active devices may include an array of field effect transistors (FETs) or bipolar junction transistors disposed in a logic circuit. The pitch of the mechanism defined as the distance between similar interconnect terminals above the gate region, source region, or drain region of an individual transistor may vary between 20 and 1000 nanometers (nm). For example, the gate - to - gate pitch may be between 40 and 80 nm.

[0027] The host chip BEOL metallization stack 102 includes one or more conductive layers 106 embedded in the interlayer dielectric (ILD) 107. The first metallization level M1 of the BEOL stack includes an interconnect mechanism (e.g., via 108) coupled to the gate terminal, source terminal, and drain terminal. The via 108 can have a pitch that varies, for example, between 40 and 1000 nm. The via 108 can be interconnected to the metallization mechanism 120 within level M2. In the illustrated embodiment, four BEOL conductive layers 106 (represented as metallization levels M1 - M4) are shown below the interconnect chiplet 101, although the interconnect chiplet 101 can be attached at any suitable level within the BEOL metallization stack 102.

[0028] In some embodiments, the conductive layer 106 comprises metals such as, but not limited to, copper, aluminum copper alloy, aluminum, silver, gold, nickel, indium, cobalt, tungsten, tantalum, and titanium. The interlayer dielectric (ILD) layer 107 comprises, but is not limited to, silicon oxide (e.g., Si x O 1-x ), silicon nitride (e.g., Si x N( 1-x ))), silicon oxynitride (e.g., SiO x N( 1-x ))), silicon carbide (e.g., SiC) and silicon carbonitride (e.g., SiC x N 1-x) It includes materials such as aluminum oxide and aluminum nitride. In some embodiments, the ILD layer 107 comprises a low-k material having a relative dielectric constant lower than that of SiO2 (e.g., k ≤ 3.9). The ILD layer 107 may comprise any of the above-described materials, or without being limited thereto, fluorosilicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BSG), or undoped silicate glass (USG), organosilicate glass (OSG, e.g., carbon-doped oxide CDO), porous OSG, and silicate glasses such as porous silicon dioxide. In some embodiments, one or more of the ILD layers 107 may comprise low-k organic polymer materials such as polyimide, hydrogen silsesquioxane, and methylsilsesquioxane. The above-described dielectric materials may be formed by spin coating methods (e.g., spin-on glass, SOG), chemical vapor deposition (CVD), or sol-gel technology.

[0029] The thicknesses of both the conductive layer 106 and the dielectric layer 107 can vary from 50 nm or less at the lower levels proximal to the substrate 105 to 5 microns or more at the upper layers closest to the top of the BEOL metallization level 106. The metallization mechanism within the conductive layer 106 may include, for example, horizontal wiring. In the figure, the metallization mechanisms (e.g., mechanisms 114, 115, 116) are represented as wiring shown in cross-section. Interlayer vias (not shown) may extend through the dielectric layer (ILD) 107 between the conductive layers 106. In some embodiments, the size and pitch of the smallest mechanisms can fan out from the device layer 104 (e.g., increase with increasing distance). The topmost metallization level (e.g., the highest level within the stack) may have a maximum pitch indicated by pitch P3 (greater than P1, P2, P4, and P5).

[0030] The first-level interconnect (FLI) interface metallization level Mx is shown above the lower levels of the host BEOL stack 102. To emphasize that Mx can be attached to the BEOL stack 102 above M10 or any higher level not shown in the figure, the figure shows the level Mx floating above the lower levels of the BEOL stack 102. The FLI interface 121 comprises FLI pads or posts 122 and solder bumps 123. The pads 122 may extend from a metallization mechanism 117 (e.g., wiring) within the level Mx. The solder bumps 123 are an example of FLI metallization that may be coupled to the FLI pads 122. The solder mask layer 124 may optionally be between the FLI pads 122 above the ILD 107 of the topmost level Mx. Any other FLI metallization suitable for interconnecting the ICs may be selectively applied.

[0031] An exemplary embodiment of the interconnected chiplet 101 is also shown in the inset of FIG. 1 separated from the composite material die structure 100 to more clearly illustrate the mechanisms being referenced. In some embodiments, the chiplet 101 comprises one or more metallization stack levels having a different structure than the host chip BEOL stack 102. The chiplet 101 is interleaved with the chiplet's interlayer dielectric (ILD) 110 and comprises the chiplet's metallization levels 109 classified from M'1 to M'2. Although two metallization levels are shown, the chiplet 101 may comprise any number of metallization levels. Referring now to the composite material die structure 100, the sidewalls 111 of the interconnected chiplet 101 form discontinuities with the layers 106 and 107 in the BEOL metallization stack 102. In some embodiments, a fill dielectric 112 is incorporated between the sidewalls 111 of the chiplet and interfaces with the sidewalls 113 of the BEOL stack. The fill dielectric 112 may fill the gap between the sidewalls 111 of the interconnected chiplet 101 and the host BEOL stack 102. Here, the sidewalls 113 define a recess within the BEOL stack 102 into which the interconnected chiplet 101 is inserted. In some embodiments, the metallization layer 109 (e.g., M'1 - M'2) of the interconnected chiplet has a thickness t2 similar to the thickness t1 of the conductive layer 106 of the host BEOL stack that varies between 100 nm and 5 microns (5000 nm). In some embodiments, the metallization layer 109 of the chiplet is substantially aligned with the conductive layer 106 of the host BEOL stack. As an example, in the illustrated embodiment, the chiplet's metallization levels M'1 - M'2 are substantially co-planar with the levels M5 - M6 within the host BEOL stack 102. Here, the chiplet level M'1 is in the same plane as the host BEOL stack level M5, and the chiplet level M'2 is in the same plane as the host BEOL stack level M6.

[0032] In some embodiments, the interconnect chiplet 101 has a higher interconnect density than the adjacent host BEOL metallization. For example, the interconnect chiplet 101 can be integrated above a region of the device layer 104 that requires a higher density of signal-carrying wiring than that required by adjacent regions of the device layer 104 at the underlying metallization level it covers. In the illustrated embodiment, the metallization density of at least some of the underlying metallization levels of the interconnect chiplet 101 is different from the adjacent metallization density at adjacent levels within the host BEOL metallization stack 102. For example, the metallization mechanisms 114 within the metallization levels M'1 and M'2 of the chiplet have a minimum mechanism pitch P1 that is smaller than the minimum mechanism pitch P2 of the adjacent metallization mechanisms 115 within the BEOL stack levels M4 and M5. Both the chiplet and the host BEOL level metallization mechanisms 114 and 115 can be wiring paths, as shown in cross-section. Embedded pads and vias can also be included as metallization mechanisms, although not shown in the figure. The smaller mechanism pitch P1 (and other critical dimensions of the mechanism, such as the width and / or thickness of the mechanism, CD) at at least some of the metallization levels can enable the chiplet 101 to have a higher density of interconnects at the underlying metallization level of the chiplet stack than those of the adjacent host metallization level 106. For example, the mechanism 115 of the host BEOL level metallization has a minimum mechanism pitch P2 that can be substantially greater than the minimum mechanism pitch P1 between the metallization mechanism 114 of the chiplet of the interconnect chiplet 101 and the metallization mechanism 120 at the underlying metallization level.

[0033] A common host stack metallization is above the level of dielet 101 (starting, for example, at M7), such that dielet 101 is embedded within the host stack. A higher metallization level of the host BEOL stack 102 above dielet 101 can include any damascene type of interconnect structure that follows set design rules that can define the CD and layer thickness within the host BEOL stack 102 as well as the pitch of the structures. The decrease in interconnect density associated with the simultaneous increase in the pitch and size of the structures within the higher metallization level can enable a transition from the sub-micron pitch of the structures at the device layer (e.g., the pitch of transistor gates of 100 nm or less) to a micron or greater pitch at the topmost level of the metallization stack (e.g., the FLI interface 121 within level Mx in the host BEOL stack).

[0034] As shown in FIG. 1, the structures 114 within dielet levels M'1 and M'2 have a decreased pitch of the structures as compared to the adjacent common host metallization. For example, the minimum pitch P1 of the metallization structures 114 of the dielet is substantially smaller than the minimum pitch P2 of the corresponding structures 115 within the adjacent host BEOL stack levels M5 and M6. The minimum pitch P2 is also common at host BEOL levels M7 and M8 above dielet 101 and can scale to increase from the pitch P1 within dielet levels M'1 and M'2, as well as scale to the increased pitch P3 within host level M8.

[0035] For clarity, vertical interconnects such as vias-in-layer extending from the wiring within each metallization layer or the embedded pads are not shown. In some embodiments, exposed pads (not shown) that terminate vias-in-layer at the bottom of dielet 101 within M'1 are bonded to exposed pads within host metallization level M3. In some embodiments, an offset exists between the bonded pads and other bonded interface structures such as wiring. In some embodiments, the native material is substantially the same in both interconnect dielet 101 and host BEOL stack 102. In some embodiments, the native stack material is substantially different in two multi-level interconnect structures.

[0036] Integrating dielet 101 into host BEOL stack 102 interrupts the common stack design rules above a selected portion of device layer 104 by selectively replacing segments of host conductive layer 106 with dielet segments having a higher interconnect density than the laterally adjacent host metallization that may be sufficient for adjacent circuits. The circuit performance of device layer 104 underlying dielet 101 may be optimized by the higher interconnect density to which it is connected. Multiple dielets may be integrated elsewhere within host BEOL stack 102 above circuits that require high-density interconnect metallization to optimize performance.

[0037] In FIG. 1, it is shown that the thickness of the metallization layer of the dielet (e.g., thickness t2) is substantially the same as the thickness of the host BEOL metallization level (e.g., thickness t1). There may be a large difference between the thicknesses of laterally adjacent layers, and generally, the dielet and host layers may not be in the same plane as shown in the example of FIG. 1. In other embodiments, dielet 101 may have a lower metallization density than the adjacent host BEOL layers, as described below.

[0038] In some embodiments, the material compositions of the conductive layer 106 and the dielectric layer 110 are substantially the same as those described above for the BEOL metallization level 106. For example, the thicknesses of the layer 115 and the layer 116 can vary from 10 to 100 nm at the lowest level (e.g., level M'1) to 8 microns at the highest level. The size and pitch of the structures can increase from level to level, as described above, from a minimum pitch of 10 to 100 nm for the interconnections of the transistors within the level M'1 (when directly attached to the device layer 104) to a pitch of 10 microns (e.g., pitch P3).

[0039] In some embodiments, the interconnect chiplet 101 is hybrid bonded to the BEOL metallization stack 102 (e.g., at the metallization level M3). As a result, the metallization mechanism 120 within the host BEOL level M3 and the chiplet metallization mechanism 114 within the chiplet metallization level M'1 can be fused by diffusion bonding. As will be described below, some offsets of adjacent metallization mechanisms can exist within the interconnect structure of the composite material resulting from joining the two interconnect mechanisms due to inaccuracies in the chiplet-host position. An externally applied adhesive or solder need not be utilized to effect such a bond.

[0040] Diffusion bonding can be characterized by the mutual diffusion of metal atoms between adjacent pads. Similarly, the adjacent dielectric layer 107 of the BEOL metallization stack 102 and the dielectric layer 110 of the chiplet metallization mechanism 114 are fused, for example, by forming a covalent bond (e.g., Si-O-Si bond) between the dielectric layer 107 and the dielectric layer 110.

[0041] A high-speed I / O data signal can be transmitted from a package substrate or an interposer (not shown) through the FLI pads 122 and solder bumps 123 of the top-layer metallization. The chiplet 101 can be inserted into and integrated with the host BEOL stack 102 above a circuit portion in the device layer 104 that requires high-density transmission to optimize performance. The circuit can have a high transistor density. High-density transmission may be necessary for signal transmission that conforms to the underlying circuits in the region of the device layer 104 below the chiplet 101.

[0042] In some embodiments, the filled dielectric layer 112 can fully surround the sidewalls 111 of the chiplet and embed the chiplet 101 within the dielectric material. The filled dielectric 112 can fill the gap between the sidewalls of a well structure formed within the host BEOL stack 102 and accommodate the interconnecting chiplet 101. The footprint of the well (described below) is generally larger in area (is a footprint) than the footprint of the interconnecting chiplet 101 to accommodate the insertion of the chiplet. The filled dielectric layer 112 can refill any gaps remaining after the insertion of the chiplet 101. The filled dielectric 112 can comprise a material having a different composition than the ILD107. As an example, the filled dielectric 112 can comprise a material having a higher dielectric constant (k) than the ILD107. In some embodiments, the filled dielectric 112 comprises an inorganic dielectric material such as amorphous silicon oxide and polycrystalline silicon oxide, which may have a higher k than the ILD material in some cases, although not limited thereto. In some other embodiments, the filled dielectric layer 112 comprises an organic material such as an epoxy resin and a composite material of an epoxy resin, although not limited thereto. As will be described later, the filled dielectric can also be located below the interconnecting chiplet 101 (e.g., between M'1 and M3 of the BEOL stack 102). The chiplet 101 can be bonded to the filled dielectric 112.

[0043] FIG. 2 shows a cross-sectional view in the x-z plane of a composite die structure 200 according to some embodiments of the present disclosure.

[0044] The die structure 200 of the composite material includes an interconnect chiplet 201 integrated within the host BEOL metallization stack 102. An interconnect chiplet 201 having four metallization levels M'1 - M'2 is shown, but it is understood that any number of suitable metallization levels may be utilized. The materials and dimensions utilized in forming the ILD 110 and the metallization layer 109 may be as described above.

[0045] An isolated view of the interconnect chiplet 201 is shown in the inset of FIG. 2 to more clearly illustrate the mechanisms being referenced. The metallization structure 202 of the chiplet's metallization layer 203 is embedded within the ILD 110. In some embodiments, the metallization structure is horizontal wiring. The metallization layer 203 comprises the metallization levels M'1 and M'2 of the chiplet having a minimum feature pitch of P3.

[0046] Referring again to the die structure 200 of the composite material, the chiplet 201 is embedded within the common host BEOL stack 102 at levels M7 and M8. The pitch P3 of the chiplet's metallization mechanism 202 is greater than the pitch P2 of a more dense host metallization structure (e.g., host metallization structure 115) horizontally adjacent within the host BEOL stack levels M6 and M7. The adjacent host metallization structures 115 have a smaller CD than the chiplet's metallization structure 202, which is shown to have a greater thickness than the structure 115. The pitch P3 may be substantially the same size as, or smaller than, the minimum feature pitch of the vertically adjacent metallization mechanism within a higher host level above the chiplet 201 (e.g., the metallization structure 116 within level M9). In the illustrated embodiment, the host BEOL metallization structure 116 has a minimum feature pitch P3 that is substantially the same as the minimum feature pitch of the chiplet's metallization mechanism 202. In alternative embodiments, other functional CDs and pitches may be utilized.

[0047] Accordingly, the metallization density of the interconnect chiplet 201 is lower than that of the adjacent host BEOL metallization. Here, the metallization mechanism may have a larger CD compared to the CD of the mechanism 115 within the adjacent host BEOL metallization level (see the inserted figure). As an example, the metallization mechanism 202 has a minimum mechanism pitch P3 that is larger than the pitch P2 of the common metallization mechanism directly adjacent to the chiplet 201. The chiplet 201 can be integrated above a circuit within the device layer 104 that requires a high current-carrying capacity. The larger CD and lower density of the metallization mechanism such as the wiring shown in FIG. 2 can comply with the design rules for the circuits interconnected by the chiplet 201. As described above, the interconnects to the device layer 104 are fewer within circuit portions having a high transistor density to support a large signal density. In an implementation, the chiplet 201 can have a role in power transmission from the FLI interface layer (e.g., the host BEOL level Mx) to the device layer 104.

[0048] FIG. 3 shows a cross-sectional view in the x-z plane of a die structure 300 of a composite material according to some embodiments of the present disclosure.

[0049] The die structure 300 of the composite material includes an interconnect chiplet 101 and an interconnect chiplet 301 embedded in the host BEOL metallization stack 102 of the host chip 103. In the illustrated embodiment, the interconnect chiplet 301 is shown to be directly adjacent to the interconnect chiplet 101. In alternative embodiments, the interconnect chiplets may be distributed above non-adjacent portions of the host chip 103. Referring to the inset, the interconnect chiplet 301 comprises a stack of five metallization levels M'1 - M'5 having metallization mechanisms 302 and 303 embedded in the ILD 304 within levels M'1 - M'3 and levels M'4 - M'5, respectively. In some embodiments, the ILD 304 comprises substantially the same dielectric material utilized for the native host ILD 107. The metallization mechanisms 302 and 303 may have substantially the same CD and pitch (e.g., pitches P3 and P4) as the metallization mechanisms 116 and 117 within the host BEOL stack 102, respectively. In the die structure 300 of the composite material, the interconnect chiplet 301 is attached to the five levels below the top host level Mx such that the chiplet level M'5 forms part of the top metallization host level Mx. The level Mx indicates that the host BEOL stack 102 comprises more than one layer above M9, and the host stack 102 may terminate at Mx. Here, Mx is M10. In alternative embodiments, the interconnect chiplet 301 may be integrated into the host BEOL stack 102 at any suitable level, including level M1 adjacent to the device layer 104.

[0050] The interconnect chiplet 101 includes a stack of two metallization levels and is embedded deeper than the interconnect chiplet 301 that extends up to the top level Mx of the host stack within the host BEOL stack 102. The interconnect chiplet is embedded within the fill dielectric 112 and fills the gap between the sidewalls 111 and 113 of the chiplet in the excavated portion of the host BEOL stack 102. Further, the fill dielectric 112 is above the chiplet 101 and replaces a portion of the ILD dielectric layer 107 within level M6. In the illustrated embodiment, the fill dielectric 112 may have a lateral extent within M6 only over the entire host substrate 105 or above a portion thereof. The fill dielectric 112 is formed above level M5 of the host BEOL stack 102 after the interconnect chiplet 101 is attached and may fill the gap between the sidewalls 111 and 113. The thickness t1 of the layer of the fill dielectric 112 may be adjusted to match the thickness of the layer of M6 according to the design rules. In some embodiments, incorporating the fill dielectric 112 within M6 is an alternative to completely removing the excess fill dielectric 112 up to M5 and then depositing the native ILD 107. As described below, the metallization mechanism 115 may be formed in the fill dielectric 305 within M6 and any native ILD 107 on the same plane by damascene processing.

[0051] The host metallization mechanism 115 embedded in the layer of the fill dielectric 305 within level M6 may follow design rules (e.g., the same CD and minimum mechanism pitch P2) that are substantially the same as those followed by the metallization mechanisms 115 within levels M4, M5, and M7. The metallization mechanism 114 of the interconnect chiplet 101 may have a minimum mechanism pitch P1 that is substantially the same as the smaller metallization mechanism pitch with respect to the mechanism 120 within the lower levels of the host stack 102.

[0052] Although the interconnect chiplet 301 appears to be proximal to the interconnect chiplet 101 in the figure, it can be selectively integrated at a more distant location within the host BEOL stack 102. The interconnect chiplet 301 can be inserted into a recess within the host BEOL stack 102 that extends from the topmost level Mx to the bottom of the recess at level M5 (described below). As described below, the dielectric and metallization mechanism 302 at the lowermost level M'1 of the interconnect chiplet 301 can be directly bonded to the native ILD 107 and to the metal mechanism 115 within the host level M5. An externally applied adhesive or solder need not be utilized to effect such bonding.

[0053] A second fill dielectric 305 is incorporated between the sidewall 306 of the interconnect chiplet 301 and the sidewall 113 of the recess (described below) within the BEOL stack 102. In some embodiments, the fill dielectric 305 comprises substantially the same material as that utilized for the fill dielectric 112. In some embodiments, the fill dielectric 305 comprises substantially the same material as that utilized for the native ILD 107. In some embodiments, the fill dielectric 305 comprises substantially the same material as that utilized for the chiplet ILD 304. In some embodiments, the fill dielectric 305 comprises a dielectric material of lower performance than that utilized for the ILD 107. For example, the fill dielectric 305 can be given a higher dielectric constant than the native ILD 107. The higher dielectric constant can be sufficient within the upper stack layers since capacitive coupling between larger metallization mechanisms can be reduced as compared to those within lower stack levels having smaller feature pitches. The fill dielectric 305 can be incorporated into the host level Mx by a process similar to that utilized to incorporate the fill dielectric 112 at level M6.

[0054] The filling dielectric 305 extends horizontally above level M9 from the sidewall 306 of the chiplet 301 and can be continuous with the filling dielectric 112 incorporated between the sidewall 306 and the sidewall 113. The filling dielectric 305 can form at least part of the ILD at Mx. In some embodiments, the filling dielectric 305 has a thickness t4 that can follow the common design rules for the host BEOL stack 102. The top host metallization mechanism 117 can be formed in the filling dielectric 305 by damascene processing (as described below).

[0055] In the illustrated embodiment, the top metallization level M'5 of the interconnect chiplet 301 is substantially aligned with the host level Mx and has a size (e.g., CD) that is substantially the same as the size of the adjacent host metallization mechanism 117 and a pitch (e.g., P4) that is the same as the pitch of the adjacent host metallization mechanism 117, and includes a metallization mechanism 303.

[0056] As shown, the interconnect chiplet 301 has a lower interconnect density than the adjacent common host stack metallization and enables greater power handling (and thus higher performance) for the interconnected circuits in the device layer 104 directly below the chiplet 301. The mechanism 114 in the interconnect chiplet 101 replaces the common host metallization mechanism 115 in M4 and M5 that has a larger size and pitch than the mechanism 114. Conversely, the interconnect chiplet 101 provides a higher density of interconnects for the circuits in the device layer 104 interconnected to the chiplet 101 and enables optimized performance of the interconnected circuits that require a high density of interconnects.

[0057] Figures 4A - 4D show partial cross-sectional views in the x-z plane of functional chiplets 400A - D according to some embodiments of the present disclosure.

[0058] The interconnected chiplets disclosed herein (e.g., chiplet 101, chiplet 201, and chiplet 301) can have functional materials in addition to the ILD dielectric and conductive layer structures. In FIG. 4A, a portion of the interconnected chiplet 400A is shown in cross-section. Chiplet 400A can have a neutral ILD dielectric 107. ILD dielectric 106 can have a silicate material or a polymer material as described above for interconnected chiplet 101, interconnected chiplet 201, and interconnected chiplet 301. ILD 106 can have the sole function of providing electrical insulation to metal structures 114 and metal structure 401. Since the metallization density may be relatively low, the dielectric material utilized can have a relatively high dielectric constant (k or relative permittivity of 3.9 or higher). Design rules for the metallization density may not include the need for a low-k dielectric material having a relative permittivity of 3.9 or less.

[0059] In FIG. 4B, a portion of the interconnected chiplet 400B is shown in cross-section. The interconnected chiplet 400B includes a high-density metallization structure 402 embedded in a low-k dielectric (e.g., k less than 3.9). The high-density metallization structure 402 can have a pitch P6 less than 1000 nm. Due to the close proximity of the metallization structures 402, a high degree of dielectric insulation may be required. ILD 403 can have a low-k dielectric such as fluorosilicate glass (FSG), carbon-doped oxide, porous organosilicate glass, and porous silicon dioxide.

[0060] In FIG. 4C, a part of the interconnected chiplet 400C is shown in cross-section. The interconnected chiplet 400C includes a magnetic layer 404 sandwiched between two non-magnetic dielectric layers 107. The magnetic layer 404 can have a magnetic dielectric such as a ferrite material, a (dilute) magnetic semiconductor, or a material comprising powdered iron oxide. In some embodiments, the magnetic layer comprises ferrite or a dielectric rare-earth material dispersed in a non-magnetic dielectric matrix. In some embodiments, the magnetic layer 404 comprises a metallic magnetic material such as, but not limited to, the transition metals cobalt, iron, and nickel, and rare-earth metals such as, but not limited to, neodymium, dysprosium, and samarium. In some embodiments, the magnetic layer 404 is a sheet of magnetic material sandwiched between a dielectric layer 107 or a semiconductor layer doped with magnetic dopant atoms. A metal mechanism 405 may optionally be present within the magnetic layer 404, and the use of a conductive magnetic material may be omitted. In some embodiments, the metal mechanism 405 is an inductor winding embedded in a magnetic core formed by the magnetic layer 404.

[0061] In FIG. 4D, a part of the interconnected chiplet 400D is shown in cross-section. The interconnected chiplet 400D includes an embedded piezoelectric element 406. A metallization layer 407 can be sandwiched between piezoelectric layers 408. The metallization layer 407 can be in close contact with both piezoelectric layers 408 and function as a contact electrode to the piezoelectric element 406. The piezoelectric layer 408 may be confined within a single metallization layer or may extend over a plurality of metallization layers. The material used for the piezoelectric layer 408 can be replaced with a non-functional ILD material used for the ILD107 and can comprise, but is not limited to, a piezoelectric polycrystalline ceramic material such as barium titanate, lead titanate, lead zirconate titanate, potassium niobate, bismuth ferrite, lithium tantalate, and sodium tungstate. The piezoelectric element 406 can be utilized as an actuator, a surface acoustic wave sensor and transducer, and an integrated piezoelectric element for clocks and oscillators.

[0062] FIG. 5A and FIG. 5B show cross-sectional views in the x-z plane of a die structure 500A of a composite material and a die structure 500B of a composite material comprising a chiplet having a functional material integrated with an interconnect chiplet in BEOL, according to some embodiments of the present disclosure.

[0063] In FIG. 5A, the die structure 500A of the composite material comprises an interconnect chiplet 501 with a magnetic layer 404 depicted by the dashed enclosure. Similar to the interconnect chiplet 101, interconnect chiplet 201, and interconnect chiplet 301 described above, the chiplet 501 is integrated into the host BEOL stack 102 above the host chip device layer 104 and the substrate 105. The magnetic layer 404 may be confined within a single metallization layer or may extend over multiple metallization layers, as shown in the illustrated embodiment. In some embodiments, the fill dielectric 112 may at least partially surround the chiplet 501 and fill the space between the sidewall 111 of the chiplet and the sidewall 113 of the host BEOL stack. The chiplet 501 may be hybrid bonded to the host BEOL stack 102 at level M3.

[0064] The chiplet 501 may comprise an inductor structure inserted into the BEOL stack 102 that is electrically coupled to the lower portion of the integrated circuit within the device layer 104. The magnetic layer 404 may improve the performance index of the inductor. In the illustrated embodiment, the chiplet 501 comprises metallization layers from M'1 to M'5. The magnetic layer 404 is within M'2 and may occupy the layer wholly or partially. The magnetic layer 404 may extend over multiple metallization layers. As such, the chiplet 501 can be manufactured, singulated, and integrated into a wide range of host IC structures at the wafer level without requiring a host IC manufacturing process to accommodate the complexity of the magnetic structure.

[0065] In FIG. 5B, the die structure 500B of the composite material includes a (depicted) dielet 502 with a piezoelectric element 406 and a (depicted) interconnect dielet 503 adjacent to the dielet 502. The sidewall 113 of the host BEOL stack is adjacent to the sidewall 111 of the dielet 502 located on the side of the fill dielectric 112 (on the right side of the figure). In some embodiments, the fill dielectric 112 at least partially surrounds the dielet 502. The dielet 503 is a passive interconnect stack to the surrounding native host BEOL stack 102, providing a region of high or low interconnect density compared to the surrounding native host BEOL stack 102, and connecting circuit portions within the device layer 104 that require a low-density, high-performance metallization stack to the topmost FLI level (similar to the FLI level Mx in FIGS. 1, 2, and 3 but not shown in FIGS. 5A or 5B). The piezoelectric element 406 can be coupled through the host BEOL level metallization layers M1 - M3 to an integrated circuit portion within the device layer 104 below the dielet 502. In some implementations, the circuit coupled to the piezoelectric element 406 can activate the piezoelectric motion of the piezoelectric layer 408 for vibrations required for functions such as clock functions, radio frequency (rf) generation, etc. In some implementations, the piezoelectric element 406 may provide sensing functions such as acceleration sensing and may enable active capacitor tuning. As such, the dielet 502 can be manufactured, singulated, and integrated into a wide range of host IC structures without requiring a host IC manufacturing process adapted to the complexity of the piezoelectric structure.

[0066] An interconnect dielet 503 adjacent to the dielet 502 is shown, and the sidewall 504 of the dielet 503 is separated from the sidewall 111 of the dielet 502 by the fill dielectric 112. In some embodiments, the interconnect dielet 503 is integrated at a greater distance from the dielet 502. The sidewall 111 of the dielet 502 and the sidewall 504 of the dielet 503 can be directly adjacent to the sidewall of the host BEOL stack (e.g., the sidewall 113 of the BEOL stack).

[0067] Figures 6A and 6B show plan views of the x-y planes of a plurality of chiplets integrated into a host BEOL stack in a die structure 600A of a composite material and a die structure 600B of a composite material, according to some embodiments of the present disclosure.

[0068] In FIG. 6A, a partial plan view of a die structure 600A of a composite material is shown. The host BEOL stack 102 includes a plurality of interconnected chiplets 601, 602, and 603 arranged in an adjacent configuration. The three chiplets 601-603 are directly adjacent to each other. Although three chiplets are shown in the illustrated embodiment, any suitable number of a plurality of chiplets can be configured in a two-dimensional arrangement as shown in FIG. 6A. In some embodiments, the chiplets 601-603 are laterally separated such that sidewalls (e.g., sidewall 111) are adjacent to sidewalls (e.g., sidewall 113) of the host BEOL stack. The arrangement can be any suitable arrangement of the chiplets 601-603 in the X and Y ranges. The chiplets 601-603 are classified as "high performance", "dense", and "low cost", respectively reflecting their metallization density. The label "high performance" of chiplet 601 can indicate a low density and thick (e.g., large CD) metallization compared to the host BEOL level metallization for high power and high-speed transmission requirements, similar to chiplet 201 in FIG. 2. The label "dense" of chiplet 602 can indicate a high density and small CD metallization compared to the host BEOL level metallization for high-density data transmission requirements. The label "low cost" of chiplet 603 can indicate a metallization with a compromised performance.

[0069] In FIG. 6B, the die structure 600B of the composite material includes a magnetic chiplet 604 and a piezoelectric chiplet 605 in addition to the interconnect chiplet 602. In the illustrated embodiment, the chiplets 602, 604, and 605 are disposed in different portions of the host BEOL stack 102 and have the native stack 102 between their sidewalls. As shown in the example, the chiplets 604 and 605 may have any polygonal shape, including a circular (or generally curved) shape rather than a rectangular shape. Non-rectangular shapes may serve functional purposes. As an example, the circular shape of a piezoelectric layer (e.g., piezoelectric layer 408, FIG. 4D) may enhance certain vibration modes. The magnetic chiplet may not be rectangular in order to conform to a particular shape of an inductor or for optimal magnetic shielding of a host circuit portion. The chiplets 602, 604, and 605 may thus have any suitable shape. Additionally, non-rectangular functional layers may be formed on chiplets having a rectangular outer perimeter.

[0070] FIGS. 7A-7H illustrate an exemplary processing flow of a die structure 300 of a composite material according to some embodiments of the present disclosure.

[0071] In FIG. 7A, a host die wafer 103 of the manufacturing process is housed at level M5 after completion of the BEOL stack 102, for example, according to any suitable damascene manufacturing technique. Levels M1-M3 include a relatively high-density metallization structure 120 having a pitch P1. A coarser pitch (e.g., pitch P2 greater than P1) separates the larger metallization features 115 within levels M4 and M5.

[0072] The substrate 105 of the wafer 701 of the chiplet may be made of a suitable semiconductor material such as, but not limited to, silicon, silicon germanium, germanium, gallium arsenide, indium gallium arsenide, or gallium nitride. In some embodiments, the substrate 105 is a silicon-on-insulator (SOI) wafer having a BOX layer below the device layer 104. The device layer 104 may comprise highly integrated MOSFET transistors composed of various n-MOS, p-MOS, CMOS, or other types of digital logic circuits and analog circuits. In some embodiments, the device layer may comprise passive devices such as resistors, capacitors, diodes, and inductors. Local metallization may be provided within the device layer 104 to form transistor terminals and interconnect vias. The transistor terminals may have a pitch of a mechanism that can vary between 10 and 500 nm and may be, for example, as small as about 1 to 10 nm. In some embodiments, an embedded metallization layer is formed below the gate region, source region, and drain region of the back contact. In some embodiments, the transistor layer is present within the BEOL stack 102. Metallization may be present above and below the BEOL stack integrated transistor layer, which may extend above and below the transistor layer and have interconnect vias and through-silicon vias (TSVs) that interconnect with the metallization on both sides of the stack integrated transistor layer.

[0073] In FIG. 7B, recess 701 is formed in host BEOL stack 102 by etching the back ILD associated with metallization layers M3, M4, and M5. In some embodiments, recess 701 can be formed by a high aspect ratio anisotropic etching process such as deep reactive ion etching (DRIE, e.g., the Bosch process) through an etching mask defined by lithography having a via pattern corresponding to the dielet positions. The dry etching process can produce substantially straight sidewalls 113. Recess 701 can be hundreds of microns to several millimeters in the lateral direction and hundreds of nanometers to several microns or dozens of microns in depth. In the illustrated embodiment, recess 704 is etched to level M3. In some embodiments, an etch stop layer can be deposited to a predetermined level after completion of host BEOL stack 102 to avoid uncontrolled etching of the ILD surrounding the underlying host metallization layer.

[0074] In FIG. 7C, interconnect dielet 101 is attached to host BEOL stack 102 at the wafer level by inserting dielet 101 into recess 701. Multiple interconnect dielets 101 can be separated from a dielet wafer (not shown) in a separate manufacturing process. The separate process of dielet manufacturing allows for the production of multiple interconnect dielets having different interconnect densities. As an example, high-density interconnect dielets (e.g., interconnect dielet 101) and high-performance dielets having a lower interconnect density (e.g., dielet 201) can be manufactured according to different sets of design rules compatible with the various circuits within device layer 104 as described above. At the wafer level, the completed dielets can be pre-inspected for functionality and quality, allowing only reliable units. Multiple dielets having acceptable reliability can be integrated at the wafer level into the host chip metallization to form a composite structure (e.g., composite die structure 100) comprising the host chip and the embedded dielets.

[0075] The interconnected chiplet 101 includes two metallization levels M'1 and M'2 with a conductive layer 109 embedded in the ILD 110. The metallization levels M'1 and M'2 form the interconnect stack of the chiplet. As will be described below, forming the metallization layer 109 can be performed by a damascene metallization process that creates the metallization layer 109 as utilized in the formation of the ILD 110 and the host BEOL stack 102. Above M'2, there is no further metallization. A relatively thick processing substrate 705, which may include, for example, single-crystalline silicon, a dielectric, or any other material, through which interconnects can be formed or moved, can facilitate the processing of the chiplet. After a partially completed metallization stack (e.g., the host BEOL metallization stack 102) is prepared for chiplet attachment, the completed chiplet (e.g., the interconnected chiplet 101) can be separated from the wafer and introduced into the host wafer BEOL processing line (see, for example, FIG. 7B). In the embodiment shown in FIG. 7B, as shown in FIG. 7C, the host BEOL stack 102 is built up to level M5, and then the ILD is selectively etched at level M3 to expose the metal structures.

[0076] Proper attachment processing of the chiplet may comprise a pick-and-place operation and inserting the chiplet 101 into the recess 701. In alternative embodiments, forming the recess 701 may be omitted, and / or the chiplet 101 may be attached directly to an unetched portion of the exposed metallization level of the BEOL stack 102. Individual chiplets 101 may be placed, or multiple chiplets up to hundreds at a time may be inserted simultaneously into the etched recesses 701 at multiple positions above the partially completed BEOL metallization stack on the host wafer. In some embodiments, the singulated chiplet 101 is accommodated in the wiring process (BEOL) metallization process of the host chip wafer 103. In some embodiments, the singulated chiplet die may be attached to a processing tool (not shown) for mechanical support.

[0077] The recess 701 may be etched to have a footprint slightly larger than the interconnecting chiplet 101, such that a gap remains between the sidewall 111 and the sidewall 113. The bottom metallization mechanism 114 may have a slight misalignment in arrangement with respect to the metallization mechanism in M5, changing the distance between the sidewall 111 and the sidewall 113.

[0078] The wafer-level chiplet attachment process may include a hybrid bonding process to the top metallization level of the host die completed before chiplet attachment. In this example, level M3 is exposed at the bottom of the recess 701. Here, the metallization mechanism 120 within level M3 is joined to the lowest-level interconnect (e.g., metallization mechanism 114) on the chiplet's metallization stack (e.g., level M'1) by diffusing and bonding the metal to the metal contact during hybrid bonding. The ILD layers (e.g., host ILD 107 and chiplet ILD 110) are adhered by covalent bonding (e.g., condensation bonding between surface silanol groups). Multiple chiplet dies may be attached to a single host die at the wafer level and at more than one level within the BEOL stack on the host die.

[0079] After insertion and bonding of the chiplet 101, the processing substrate 705 may protrude by a distance above M5 of the host BEOL stack 102. As shown in FIG. 7C, M'1 and M'2 are fixed within the recess 704 below M5 and may be substantially in the same plane as the host metallization levels M4 and M5.

[0080] As described above, the chiplet 101 is joined to the host stack metal structure 702 and ILD 107 at the bottom of the recess 704. A filler dielectric (e.g., filler dielectric 112) may be deposited at the wafer level in the gap between the chiplet 101 and the host BEOL stack. The filler dielectric may be a composite material of a PECVD dielectric, spin-on glass (e.g., sol-gel glass or organosilicate glass), or an organic polymer resin such as an epoxy resin. The filler dielectric 112 may stabilize the bonded chiplets on the host wafer by potting the chiplets, enhancing adhesion to the host die. The chiplet 101 may be planarized before and after applying the filler dielectric 112, and / or the processing substrate 705 may otherwise be removed. For example, the planarization operation may be performed by chemical mechanical processing or etching, or a combination thereof.

[0081] In FIG. 7D, the fill dielectric 112 is deposited above the top of the chiplet 101 and the host BEOL stack 102. The gap between sidewall 111 and sidewall 113 is filled back to enhance the adhesion of the chiplet 101 to the host stack. The layer of fill dielectric 112 above M5 can be deposited to any suitable thickness and can be planarized back to a predetermined thickness. For example, the fill dielectric 112 can be polished back to a thickness t1, which is consistent with the thicknesses of levels M4 and M5. The fill dielectric 112 can cover the entire BEOL stack 102. Optionally, the material of the native ILD 107 can be utilized to fill back the gap between the chiplet 101 and the native BEOL stack, and an ILD can be formed within level M6. The material used for the ILD 107 can be a dielectric with higher performance than the fill dielectric 112. For example, the native ILD 107 can have a lower dielectric constant (k) than the fill dielectric 112, reducing the capacitance between metallization structures. In some embodiments, incorporating the fill dielectric 112 within M6 is an alternative to completely removing the excess fill dielectric 112 up to M5 and then depositing the native ILD 107. The metallization mechanism 115 can be formed in the fill dielectric 305 within M6 and any native ILD 107 on the same plane by damascene processing.

[0082] In FIG. 7E, after bonding the chiplet 101, any suitable damascene metallization process is continued to form the upper layers of the host BEOL stack 102. The host BEOL metallization levels M6, M7, M8, and M9 (within the fill dielectric 112) can be successively added. The host metallization process can include forming an ILD layer 107 and a metallization layer 106 above the fill dielectric M6. In some embodiments, the ILD layer 107 (and subsequent ILD layers) can comprise inorganic crystalline dielectric materials such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, oxycarbide silicon, aluminum oxide, and aluminum nitride.

[0083] In some embodiments, ILD 107 includes, but is not limited to, undoped silicate glass (USG) and fluorosilicate glass (FSG) deposited by CVD techniques, or amorphous silicate materials such as spin-on glass (SOG). In some embodiments, ILD 107 includes, but is not limited to, organic dielectrics such as epoxy resin, polyimide, polynorbornene, benzocyclobutene, polytetrafluoroethylene (PTFE), hydrogen silsesquioxane, and methylsilsesquioxane. The ILD layer 107 can be deposited to a thickness of 1000 nm or less (e.g., 200 - 500 nm) to support the formation of high-density interconnects to transistors within the device layer 104. The deposition of these materials can be performed by methods including, but not limited to, RF sputtering, atomic layer deposition, chemical vapor deposition, and wet chemical methods such as TEOS (tetraethyl orthosilicate) treatment. Also included is spin coating technology (e.g., spin-on glass, SOG). ILD 107 and the fill dielectric 112 can be deposited by chemical vapor deposition processes such as plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD). The thickness of the layer can vary between 50 nm and several microns.

[0084] Generally, the thickness of the layer can gradually increase as the number of stack levels increases. The number of levels within the host BEOL metallization stack 102 can depend on the minimum feature pitch (e.g., pitch P2 in FIG. 1) within the interface layer of the chiplet of the BEOL metallization stack of the host chip, which is required to substantially match. For the relatively large interconnect sizes and pitches that may exist in a particular BEOL layer within the host chip metallization stack (e.g., BEOL metallization stack 102) to which the chiplet is attached, more metallization levels may be required to expand the CD and pitch of the fine features proximal to the chiplet, e.g., from pitch P1 to P2 of device layer 104 at the chiplet-host wafer interface (see FIG. 1).

[0085] A plurality of suitable metal deposition processes can be utilized to fabricate the metallization mechanism (e.g., 115 - 117). The metal deposition can be performed by electroplating a metal such as copper, gold, or nickel onto an etched mechanism and can be utilized in a damascene metallization process. Prior to electroplating, first a barrier layer and subsequently an electroplating seed layer can be deposited onto the etched mechanism as thin films. The barrier layer can comprise, for example, a conformal titanium, titanium nitride, or tantalum nitride film that directly contacts the dielectric to prevent diffusion and contamination by atoms of the metallization metal. For example, the barrier layer can be 1 - 5 nm thick. The seed layer can comprise the same metal as that to be plated, such as copper. The barrier layer and the seed layer can be deposited by any suitable physical deposition technique such as RF and / or DC sputtering or by evaporation of the metal in a vacuum. In some other embodiments, the metal structure can be formed by electroless deposition.

[0086] Damascene metallization includes etching trenches and via holes (not shown) in the ILD layer by the above-described etching process. The trenches and via holes can form a base for deposition for metallization mechanisms such as pads and wiring, and for interlayer vias (not shown). In a single damascene process, metal is deposited into the etched via openings and trenches by repeating the single damascene process twice continuously or by a dual damascene process. In the first repetition of the single damascene, either a via or a trench is formed, then filled by the first metal deposition, and the overcoat layer (e.g., overfill) is removed and planarized (e.g., by chemical mechanical polishing, CMP) to make the metallization flush with the dielectric surface. The second damascene process follows the first damascene process. Here, if a via was formed first, a trench is formed and vice versa. The second etched mechanism is filled by the second metal deposition, and then a second planarization is performed to remove any overcoat layer. Thus, the metal mechanism is embedded below the ILD level, enabling a low z-direction height for the multi-level stack. In the dual damascene process, via holes and wiring and / or pad trenches are formed prior to metallization. A single metal deposition is utilized to fill both the via holes and trenches simultaneously.

[0087] In FIG. 7F, the ILD material of the host BEOL adjacent to the chiplet 101 is removed by an etching process to form a recess 702 adjacent to the chiplet 101. The sidewall 111 of the chiplet 101 is exposed. A part of the metallization level M5 is exposed as a well to form the bottom of the recess 702. The interconnect mechanism within M5 becomes part of the attachment surface for the integration of the second chiplet. A second sidewall of the recess 702 (e.g., sidewall 113) is not shown but is implied. The etching process can be substantially the same as that described above for forming the recess 701. As an example, a DRIE (e.g., Bosch) process can be utilized for a through-mask etching process to form the recess 702 defined by lithography. The Bosch process can be optimal for forming straight sidewalls (e.g., sidewall 113 not shown). The recess 702 can be etched to produce a footprint larger than the interconnect chiplet 301.

[0088] FIG. 7G shows the attachment of the interconnect chiplet 301. In some embodiments, the attachment of the chiplet 301 can be performed by a wafer-level pick-and-place operation. The individual chiplets 301 can be attached to the host BEOL stack 102 by inserting the chiplets 301 into the recesses 702 formed in the host BEOL stack 102. The pick-and-place operation can have an accuracy tolerance in the tens to hundreds of nanometers and can introduce some alignment offset between the metallization mechanism 114 of the chiplet and the BEOL metallization stack pad 115. In some embodiments, the chiplet 301 is hybrid bonded to level M5 within the host BEOL level metallization 102. The hybrid bonding can be performed by a pick-and-place operation followed by thermal annealing of an assembly comprising the chiplet 301 (and 101) and the host chip wafer 103. The chiplet 301 can have a metallization density that is substantially different from the host BEOL level metallization density. In the illustrated embodiment, the chiplet 301 is an interconnect stack with a relatively low density and a larger CD that is optimal for high-performance circuits in the device layer 104 portion below the chiplet 201.

[0089] In the illustrated embodiment, the number of layers of the interconnect chiplet 301 is greater than the number of host layers removed to create the recesses 702. As a result, the interconnect chiplet 301 is not planar with the host BEOL stack. The chiplet 301 introduces an incomplete metallization layer that extends above the host level M9.

[0090] In FIG. 7H, a second fill dielectric material 305 is deposited above the host level M9 to fill the gap between the sidewall 306 of the chiplet 301 and the sidewall 113 of the recess 702. By depositing the fill dielectric 305, an ILD layer is formed above the host level M9, which can be polished to make the host BEOL stack 102 flush with the interconnect chiplet 301. In some embodiments, the fill dielectric 305 comprises substantially the same material as the fill dielectric 112. In some embodiments, the fill dielectric comprises a native ILD dielectric. The fill dielectric 305 can then be planarized to the level of the interconnect level at which the chiplet 301 is held. A CMP operation can be utilized to polish the fill dielectric 305 until it is flush with the topmost portion of the chiplet 301.

[0091] The operation on the host chip wafer 103 can be terminated by forming the FLI interface layer 121 (including the interconnect pads 122 and the solder bumps 123) as the final metallization and ILD formation operations. The interconnect pads 121 are grown above the metallization mechanism 117 within level M10. Vertical connections from levels M9 and M10 can be created by the vias (not shown). Subsequently, for example, singulation of the host chip, reconfiguration, and application of the FLI solder bumps 123 via a solder mask (or passivation) 124, or conversely, application of the FLI solder bumps using the passivation 124, singulation, and attachment to the package, followed by the assembly operation can continue. FIG. 8 shows a system 800 comprising a die structure 300 of a composite material coupled to a package or an interposer substrate 801 according to some embodiments of the present disclosure. The system 800 comprises a die structure 300 of a composite material bonded to the package substrate or interposer 801 by FLI solder bonding 802 to the substrate pads 803. As described with reference to FIGS. 7A - 7H, the interconnect chiplets 101 and the interconnect chiplets 301 are integrated adjacent to the die structure 300 of the composite material. The chiplets 101 and 301 can be coupled to paths within the substrate 801 that transmit high - speed or high - density signals to the integrated circuit portions underlying each chiplet, and signals are optimally transmitted through the host BEOL stack 102 to the target circuits within the device layer 104.

[0092] FIG. 9 shows a block diagram of a computing device 900 as part of a system - on - chip (SoC) package comprising a die of a composite material (e.g., any of die structure 100, die structure 200, die structure 300, or die structure 700 of the composite material) disclosed herein in the implementation of a computing device according to some embodiments of the present disclosure.

[0093] According to some embodiments, computing device 900 represents, but is not limited to, a server, a desktop workstation, or a mobile workstation such as a laptop computer, a computing tablet, a cellular phone or smartphone, a wireless-enabled e-book reader, or other wireless mobile device. The IC package includes, but is not limited to, a microprocessor such as a single-core microprocessor or a multi-core microprocessor (e.g., representing a central processing unit). In some embodiments, the IC package includes a die structure of a composite material (e.g., any one of the die structures of composite material 100, die structure of composite material 200, die structure of composite material 300, or die structure of composite material 700) including a chiplet die (e.g., any one of chiplet die 101, chiplet die 201, chiplet die 301, chiplet die 501, chiplet die 502, chiplet die 601, chiplet die 602, chiplet die 603, chiplet die 604, or chiplet die 605) according to multiple embodiments of the present disclosure.

[0094] In some embodiments, the computing device has a wireless connection (e.g., Bluetooth®, WiFi, and 5G network). It will be understood that certain components are generally shown and not all components of such a device are shown in computing device 1100.

[0095] Various embodiments of the present disclosure may also include a network interface within 970, such as a wireless interface, so that system embodiments can be incorporated into a wireless device, such as a cellular phone or a personal digital assistant. The wireless interface includes a millimeter-wave generator and an antenna array.

[0096] According to some embodiments, processor 910 represents a CPU or GPU and may include one or more physical devices such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. The processing operations executed by processor 910 include executing an operating platform or operating system on which the functions of the application and / or device are executed. The processing operations include operations related to I / O (input / output) with a human user or with other devices, operations related to power management, and / or operations related to connecting computing device 900 to other devices. The processing operations may also include operations related to audio I / O and / or display I / O.

[0097] In one embodiment, computing device 900 includes an audio subsystem 920 that represents hardware (e.g., audio hardware and audio circuits) components and software (e.g., drivers, codecs) components related to providing audio functionality to the computing device. The audio functionality may include output of speakers and / or headphones and input of a microphone. Devices for such functionality may be integrated into computing device 900 or connected to computing device 900. In one embodiment, the user interacts with computing device 900 by providing audio commands received and processed by processor 910.

[0098] The display subsystem 930 represents hardware (e.g., a display device) components and software (e.g., a driver) components that provide a visual display and / or a tactile display for a user to interact with the computing device 900. The display subsystem 930 includes a display interface 932 that includes a specific screen or hardware device used to provide the display to the user. In one embodiment, the display interface 932 includes logic separated from the processor 910 for performing at least some of the processing related to the display. In one embodiment, the display subsystem 930 includes a touch screen (or touch pad) device that provides both output and input to the user.

[0099] The I / O controller 940 represents hardware devices and software components related to user interaction. The I / O controller 940 is operable to manage hardware that is part of the audio subsystem 920 and / or the display subsystem 930. Further, the I / O controller 940 indicates connection points for additional devices connected to the computing device 900 through which the user can interact with the system. For example, devices that can be attached to the computing device 900 can include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices for use with specific applications such as a card reader or other device.

[0100] As described above, the I / O controller 940 can interact with the audio subsystem 920 and / or the display subsystem 930. For example, input via a microphone or other audio device can provide input or commands to one or more applications or functions of the computing device 900. Additionally, audio output can be provided instead of, or in addition to, the display output. In other examples, if the display subsystem 930 includes a touch screen, the display device can also function as an input device that is at least partially managed by the I / O controller 940. Additional buttons or switches may also be present on the computing device 900 to provide I / O functions managed by the I / O controller 940.

[0101] In one embodiment, the I / O controller 940 manages devices such as an accelerometer, camera, light sensor or other environmental sensor, or other hardware that may be included in the computing device 900. This input can be part of providing environmental input to the system to affect its operation (such as filtering against noise, adjusting the display for brightness detection, applying a flash to the camera, or other functions) as well as for direct interaction by the user.

[0102] In one embodiment, computing device 900 includes a power management unit 950 that manages functions related to battery power utilization, battery charging, and power-saving operations. Memory subsystem 960 includes a memory device for storing information in computing device 900. The memory may include a non-volatile (state does not change when power to the memory device is cut off) memory device and / or a volatile (state is uncertain when power to the memory device is cut off) memory device. Memory subsystem 960 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to executing the applications and functions of computing device 900.

[0103] Elements of multiple embodiments are also provided as a machine-readable medium (e.g., memory 960) for storing computer-executable instructions. The machine-readable medium (e.g., memory 960) may include, but is not limited to, flash memory, optical disk, CD-ROM, DVDROM, RAM, EPROM, EEPROM, magnetic or optical card, phase change memory (PCM), or other types of machine-readable media suitable for storing computer-executable instructions. For example, multiple embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS) that can be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by a data signal via a communication link (e.g., a modem or network connection).

[0104] The connection via network interface 970 includes a hardware device (e.g., a wireless and / or wired connector, and communication hardware) and a software component (e.g., a driver, a protocol stack) to enable computing device 900 to communicate with an external device. Computing device 900 can be another computing device, a separate device such as a wireless access point or a base station, and a peripheral device such as a headset, a printer, or another device.

[0105] Network interface 970 can include a plurality of different types of connections. For generalization, computing device 900 is shown as having a cellular connection 972 and a wireless connection 974. Cellular connection 972 generally refers to a connection to a cellular network provided by a wireless carrier such as GSM (registered trademark) (Global System for Mobile Communications) or a modification or derivative thereof, CDMA (Code Division Multiple Access) or a modification or derivative thereof, TDM (Time Division Multiplexing) or a modification or derivative thereof, or other mobile phone service standards. Wireless connection (or wireless interface) 974 refers to a wireless connection that is not cellular and can include a personal area network (such as Bluetooth (registered trademark), Near Field Communication, etc.), a local area network (such as Wi-Fi, etc.), and / or a wide area network (such as WiMax, etc.), or other wireless communications.

[0106] The peripheral connection 980 includes a hardware interface and connector for making a peripheral connection, as well as software components (e.g., drivers, protocol stacks). It will be understood that computing device 900 can be a peripheral device ( "to" 982) to another computing device and can simultaneously have a peripheral device ( "from" 984) connected thereto. Computing device 900 generally has a "docking" connector for connecting to other computing devices for purposes such as managing content on computing device 900 (e.g., downloading and / or uploading, modifying, synchronizing). Further, the docking connector can enable computing device 900 to connect to certain peripheral devices that enable computing device 900 to control the output of content to, for example, an audio visual or other system.

[0107] In addition to a dedicated docking connector or other dedicated connection hardware, computing device 900 can form peripheral connection 980 via a common or standard - based connector. Common types can include Universal Serial Bus (USB) connectors (which can include any number of different hardware interfaces), display ports including Mini DisplayPort (MDP), High - Definition Multimedia Interface (HDMI (registered trademark)), FireWire, or other types.

[0108] Furthermore, certain features, structures, functions, or characteristics can be combined in any suitable manner in one or more embodiments. For example, wherever the specific features, structures, functions, or characteristics associated with two embodiments are not mutually exclusive, the first embodiment can be combined with the second embodiment.

[0109] Although the present disclosure has been described with specific embodiments, many alternative, modified, and varied forms of such embodiments will be apparent to those skilled in the art in view of the above description. The various embodiments of the present disclosure are intended to embrace all such alternatives, modifications, and variations so as to be included within the broad scope of the appended claims.

[0110] Furthermore, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the drawings presented so as to simplify the illustration and description and not obscure the present disclosure. Further, to avoid obscuring the present disclosure and considering the fact that the details regarding the implementation of the configuration of such block diagrams depend heavily on the platform implementing the present disclosure, the configuration may be shown in the form of block diagrams (i.e., such details should be well within the purview of those skilled in the art). While specific details (e.g., circuits) have been described to illustrate exemplary embodiments of the present disclosure, it should be apparent to those skilled in the art that the present disclosure may be practiced with or without such specific details. Accordingly, the description is to be regarded as illustrative rather than limiting.

[0111] The following examples relate to further embodiments. The details in the examples may be used anywhere in one or more embodiments. Any and all features of the apparatus described herein may also be implemented with respect to a method or process.

[0112] (Example 1) A host chip having a device layer and one or more first metallization levels above an adjacent first region and a second region of the device layer, wherein the plurality of first metallization levels are interconnected to the device layer, a host chip, an interconnect chiplet above the plurality of first metallization levels in the first region, the interconnect chiplet having a plurality of second metallization levels, and a plurality of third metallization levels above the plurality of first metallization levels in the second region and adjacent to the interconnect chiplet, wherein at least one of the dimensions or composition of the interconnect mechanism is different between one of the plurality of second metallization levels and an adjacent one of the plurality of third metallization levels, an integrated circuit (IC) device structure comprising the plurality of third metallization levels.

[0113] (Example 2) Including all features of Example 1, wherein a dielectric material is between one or more sidewalls of the chiplet and the plurality of third metallization levels.

[0114] (Example 3) Including all features of Example 2, wherein the dielectric material surrounds the outer periphery of the chiplet.

[0115] (Example 4) Including all features of any one of Examples 1 to 3, further comprising one or more top metallization levels extending above both the plurality of second metallization levels and the plurality of third metallization levels.

[0116] (Example 5) Including all features of any one of Examples 1 to 4, wherein a first mechanism of the plurality of first metallization layers is in direct contact with a second mechanism of the plurality of second metallization levels, and a dielectric material surrounding the first mechanism is in direct contact with a dielectric material surrounding the second mechanism.

[0117] (Example 6) Including all the features of Example 5, the second mechanism of the plurality of first metallization layers is in direct contact with the third mechanism of the plurality of third metallization levels, and the lateral offset between the sidewall of the first mechanism of the plurality of second metallization levels and the sidewall of the second mechanism is larger than the lateral offset between the sidewall of the second mechanism of the plurality of first metallization levels and the sidewall of the third mechanism.

[0118] (Example 7) Including all the features of any one of Examples 1 to 6, one of the plurality of second metallization levels or the plurality of third metallization levels mainly contains Cu, and the other of the plurality of second metallization levels or the plurality of third metallization levels mainly contains other than Cu.

[0119] (Example 8) Including all the features of any one of Examples 1 to 7, the plurality of second metallization levels are separated by a first dielectric material having a relative permittivity different from that of the second dielectric material separating the plurality of third metallization levels.

[0120] (Example 9) Including all the features of any one of Examples 1 to 8, the interconnecting chiplet is a first chiplet, the second interconnecting chiplet has the plurality of third metallization levels, and the dielectric material is between the sidewalls of the first chiplet and the sidewalls of the second chiplet.

[0121] (Example 10) Including all the features of Example 9, the one or more first metallization levels include one or more lower metallization levels above both the first region and the second region of the device layer and one or more upper metallization levels above only the second region of the device layer, the first mechanism of the plurality of second metallization levels is in direct contact with the first mechanism of the plurality of lower metallization levels, and the first mechanism of the plurality of third metallization levels is in direct contact with the first mechanism of the plurality of upper metallization levels.

[0122] (Example 11) Including all the features of Example 10, further comprising a second dielet above the third region of the device layer, the second dielet having a plurality of fourth metallization levels, at least one of the pitch, composition, or thickness of the interconnect mechanism being different between one of the plurality of fourth metallization levels and an adjacent one of the plurality of second metallization levels or the plurality of third metallization levels.

[0123] (Example 12) Including all the features of Example 11, further comprising one or a plurality of top metallization levels extending above two or more of the plurality of second metallization levels, the plurality of third metallization levels, and the plurality of fourth metallization levels.

[0124] (Example 13) Including all the features of Example 12, further comprising a first-level interconnect that contacts the top one of the plurality of top metallization levels.

[0125] (Example 14) Including all the features of any one of Examples 1 to 13, the dielet having a magnetic material between two interconnect mechanisms at one of the plurality of second metallization levels or between two of the plurality of second metallization levels.

[0126] (Example 15) Including all the features of any one of Examples 1 to 14, the dielet having a piezoelectric material between two interconnect mechanisms at one of the plurality of second metallization levels or between two of the plurality of second metallization levels.

[0127] (Example 16) A microprocessor chip, including a plurality of transistors within a first region and an adjacent second region of the chip, one or more first metallization levels above the first region and the second region and interconnected to the plurality of transistors, an interconnect chiplet above the plurality of first metallization levels within the first region, the interconnect chiplet having a plurality of second metallization levels, a plurality of third metallization levels above the plurality of first metallization levels within the second region and adjacent to the interconnect chiplet, at least one of the dimensions or composition of the interconnect mechanism being different between one of the plurality of second metallization levels and an adjacent one of the plurality of third metallization levels, a plurality of third metallization levels, and one or more top metallization levels extending above the plurality of second metallization levels and the plurality of third metallization levels; a system comprising a first level of interconnect that contacts the top one of the plurality of top metallization levels and contacts another chip or a host substrate.

[0128] (Example 17) Including all the features of Example 16, further comprising a power supply coupled to supply power to the microprocessor chip.

[0129] (Example 18) Forming one or more first metallization levels above a first region and a second region of a device layer; placing an interconnect chiplet on the one or more first metallization levels, the interconnect chiplet having a plurality of second metallization levels; bonding a structure of the plurality of second metallization levels to a structure of a lower one of the plurality of first metallization levels; and forming one or more top metallization levels above the interconnect chiplet and above a top one of the plurality of first metallization levels within the second region of the device layer. A method of forming an IC device structure comprising these steps.

[0130] (Example 19) Including all features of Example 18, the step of placing an interconnect chiplet on the one or more first metallization levels includes first forming a cavity within at least a top one of the plurality of first metallization levels, the cavity exposing a lower one of the plurality of first metallization levels between the first region of the device layer and the top metallization layer.

[0131] (Example 20) Including all features of Example 19, the step of forming the cavity includes etching a dielectric material between structures of a top one of the plurality of first metallization levels to a first depth, the interconnect chiplet having a z-direction height approximately equal to the first depth. The step of forming the one or more top metallization levels further includes planarizing the dielectric material and performing a damascene metallization process.

[0132] It is understood that the abstract is presented without limiting the scope or meaning of the claims. The following claims are incorporated herein into the mode for carrying out the invention, and each claim stands on its own as a separate embodiment. [Other possible claims] [Item 1] A host chip having a device layer and one or more first metallization levels above adjacent first and second regions of the device layer, the plurality of first metallization levels being interconnected to the device layer, the host chip; An interconnect chiplet above the plurality of first metallization levels within the first region, the interconnect chiplet having a plurality of second metallization levels; A plurality of third metallization levels above the plurality of first metallization levels within the second region and adjacent to the interconnect chiplet, at least one of the dimensions or composition of the interconnect mechanism being different between one of the plurality of second metallization levels and an adjacent one of the plurality of third metallization levels; An integrated circuit (IC) device structure comprising. [Item 2] The IC device structure according to item 1, wherein a dielectric material is between one or more sidewalls of the chiplet and the plurality of third metallization levels. [Item 3] The IC device structure according to item 2, wherein the dielectric material surrounds the outer periphery of the chiplet. [Item 4] The IC device structure according to item 1, further comprising one or more top metallization levels extending above both the plurality of second metallization levels and the plurality of third metallization levels. [Item 5] The IC device structure according to item 1, wherein a first mechanism of the plurality of first metallization layers is in direct contact with a second mechanism of the plurality of second metallization levels, and a dielectric material surrounding the first mechanism is in direct contact with a dielectric material surrounding the second mechanism. [Item 6] The second mechanism of the plurality of first metallization layers is in direct contact with the third mechanism of the plurality of third metallization levels, and a lateral offset between a sidewall of the first mechanism of the plurality of second metallization levels and a sidewall of the second mechanism is greater than a lateral offset between a sidewall of the second mechanism of the plurality of first metallization levels and a sidewall of the third mechanism. The IC device structure according to item 5. [Item 7] One of the plurality of second metallization levels or the plurality of third metallization levels mainly contains Cu, and the other of the plurality of second metallization levels or the plurality of third metallization levels mainly contains other than Cu. The IC device structure according to item 1. [Item 8] The plurality of second metallization levels are separated by a first dielectric material having a relative permittivity different from that of a second dielectric material that separates the plurality of third metallization levels. The IC device structure according to item 1. [Item 9] The interconnect chiplet is a first chiplet, A second interconnect chiplet has the plurality of third metallization levels, The dielectric material is between a sidewall of the first chiplet and a sidewall of the second chiplet. The IC device structure according to item 1. [Item 10] The one or more first metallization levels include one or more lower metallization levels above both the first region and the second region of the device layer and one or more upper metallization levels above only the second region of the device layer. A first mechanism of the plurality of second metallization levels is in direct contact with a first mechanism of the plurality of lower metallization levels, and a first mechanism of the plurality of third metallization levels is in direct contact with a first mechanism of the plurality of upper metallization levels. The IC device structure according to item 9. [Item 11] Further comprising a second die above the third region of the device layer, the second die having a plurality of fourth metallization levels, wherein at least one of the pitch, composition, or thickness of the interconnect mechanism is different between one of the plurality of fourth metallization levels and an adjacent one of the plurality of second metallization levels or the plurality of third metallization levels. The IC device structure according to item 10. [Item 12] The IC device structure according to item 11, further comprising two or more of the plurality of second metallization levels, the plurality of third metallization levels, and one or more top metallization levels extending above two or more of them. [Item 13] The IC device structure according to item 12, further comprising a first-level interconnect in contact with the top one of the plurality of top metallization levels. [Item 14] The IC device structure according to item 1, wherein the die has a magnetic material between two interconnect mechanisms at one of the plurality of second metallization levels or between two of the plurality of second metallization levels. [Item 15] The IC device structure according to item 1, wherein the die has a piezoelectric material between two interconnect mechanisms at one of the plurality of second metallization levels or between two of the plurality of second metallization levels. [Item 16] A microprocessor chip, A plurality of transistors within a first region and an adjacent second region of the chip, One or more first metallization levels above the first region and the second region and interconnected to the plurality of transistors, An interconnect chiplet above the plurality of first metallization levels within the first region, the interconnect chiplet having a plurality of second metallization levels, and A plurality of third metallization levels above the plurality of first metallization levels within the second region and adjacent to the interconnect chiplet, wherein at least one of the dimensions or composition of the interconnect mechanism is different between one of the plurality of second metallization levels and an adjacent one of the plurality of third metallization levels, and One or more top metallization levels extending above the plurality of second metallization levels and the plurality of third metallization levels A microprocessor chip having A first level of interconnect that contacts the top one of the plurality of top metallization levels and contacts another chip or a host substrate A system comprising [Item 17] The system according to item 16, further comprising a power supply coupled to supply power to the microprocessor chip [Item 18] Forming one or more first metallization levels above a first region and a second region of a device layer; and Placing an interconnect chiplet on the one or more first metallization levels, the interconnect chiplet having a plurality of second metallization levels; and Bonding the mechanism of the plurality of second metallization levels to the mechanism of the lower one of the plurality of first metallization levels; and Forming one or more top metallization levels above the interconnect chiplet and above the top one of the plurality of first metallization levels within the second region of the device layer A method of forming an IC device structure, comprising. [Item 19] The step of placing the interconnect chiplets on the one or more first metallization levels includes first forming a cavity within at least the uppermost one of the plurality of first metallization levels, the cavity exposing a lower one of the plurality of first metallization levels between the first region of the device layer and the uppermost metallization layer, the method of item 18 having the step. [Item 20] The step of forming the cavity includes etching a dielectric material between the mechanisms of the uppermost one of the plurality of first metallization levels to a first depth, the interconnect chiplets further including a step having a z-direction height substantially equal to the first depth, and the step of forming the plurality of uppermost metallization levels further includes planarizing the dielectric material and performing a damascene metallization process, the method of item 19.

Claims

1. A host chip having a device layer and a plurality of first metallization layers above the device layer, wherein the plurality of first metallization layers are interconnected to the device layer, and the host chip; An interconnect chiplet above the plurality of first metallization layers, wherein the interconnect chiplet has a plurality of second metallization layers, and the interconnect chiplet is interconnected to the plurality of first metallization layers, and the interconnect chiplet; A plurality of third metallization layers above the plurality of first metallization layers and adjacent to the interconnect chiplet, wherein at least one of the dimensions or compositions of the conductive layers included in the metallization layer is different between the plurality of second metallization layers and the plurality of third metallization layers, and the plurality of third metallization layers; A plurality of fourth metallization layers extending above both the plurality of second metallization layers and the plurality of third metallization layers; An interconnect pad connecting the topmost layer of the plurality of fourth metallization layers and the interposer substrate An integrated circuit (IC) device structure comprising.

2. The IC device structure according to claim 1, wherein a dielectric material is between the sidewall of the interconnect chiplet and the plurality of third metallization layers.

3. The IC device structure according to claim 2, wherein the dielectric material surrounds the sidewall of the interconnect chiplet, and the interconnect chiplet is interconnected to the plurality of first metallization layers via through-silicon vias.

4. The IC device structure according to any one of claims 1 to 3, wherein one of the plurality of second metallization layers or the plurality of third metallization layers mainly contains Cu, and the other of the plurality of second metallization layers or the plurality of third metallization layers mainly contains other than Cu.

5. The IC device structure according to any one of claims 1 to 3, wherein the conductive layers included in each layer of the plurality of second metallization layers are separated by a first dielectric layer having a relative permittivity different from the relative permittivity of a second dielectric layer separating the conductive layers included in each layer of the plurality of third metallization layers.

6. The interconnect chiplet is a first chiplet, The second interconnected chiplet has a plurality of fourth metallization layers, and the second interconnected chiplet is interconnected to the plurality of third metallization layers. The dielectric material is between the sidewalls of the first chiplet and the sidewalls of the second interconnected chiplet. The IC device structure according to any one of claims 1 to 3.

7. The IC device structure according to claim 6, wherein the plurality of first metallization layers include one or more lower metallization layers and one or more upper metallization layers located above the one or more lower metallization layers.

8. The IC device structure according to claim 7, wherein at least one of the pitch, composition, or thickness of the conductive layers included in the metallization layer is different between the plurality of fourth metallization layers and the plurality of second metallization layers or the plurality of third metallization layers.

9. The IC device structure according to claim 8, wherein the plurality of fourth metallization layers are a plurality of topmost metallization layers extending above the plurality of second metallization layers and the plurality of third metallization layers.

10. A host chip having a device layer and a plurality of first metallization layers above the device layer, wherein the plurality of first metallization layers are interconnected to the device layer, a host chip, An interconnected chiplet above the plurality of first metallization layers, wherein the interconnected chiplet has a plurality of second metallization layers, and the interconnected chiplet is interconnected to the plurality of first metallization layers, an interconnected chiplet, A plurality of third metallization layers above the plurality of first metallization layers and adjacent to the interconnected chiplet, wherein at least one of the dimensions or composition of the conductive layers included in the metallization layer is different between the plurality of second metallization layers and the plurality of third metallization layers, a plurality of third metallization layers Comprising The interconnected chiplet is a first chiplet. The second interconnected chiplet has a plurality of fourth metallization layers, and the second interconnected chiplet is interconnected to the plurality of third metallization layers. The dielectric material is between the sidewalls of the first chiplet and the sidewalls of the second interconnect chiplet, the plurality of first metallization layers include one or more lower metallization layers and one or more upper metallization layers located above the one or more lower metallization layers, at least one of the pitch, composition, or thickness of the conductive layers included in the metallization layer is different between the plurality of fourth metallization layers and the plurality of second metallization layers or the plurality of third metallization layers, the plurality of fourth metallization layers are a plurality of topmost metallization layers extending above the plurality of second metallization layers and the plurality of third metallization layers, an integrated circuit (IC) device structure. **Claim 11** The IC device structure according to claim 10, further comprising an interconnect pad connecting the topmost layer of the plurality of fourth metallization layers and the interposer substrate. **Claim 12** The IC device structure according to any one of claims 1 to 3, wherein the interconnect chiplet has a magnetic layer between two of the plurality of second metallization layers. **Claim 13** A host chip having a device layer and a plurality of first metallization layers above the device layer, wherein the plurality of first metallization layers are interconnected to the device layer, a host chip, an interconnect chiplet above the plurality of first metallization layers, wherein the interconnect chiplet has a plurality of second metallization layers, and the interconnect chiplet is interconnected to the plurality of first metallization layers, an interconnect chiplet, a plurality of third metallization layers above the plurality of first metallization layers and adjacent to the interconnect chiplet, wherein at least one of the dimensions or composition of the conductive layers included in the metallization layer is different between the plurality of second metallization layers and the plurality of third metallization layers, a plurality of third metallization layers, comprising the interconnect chiplet has a magnetic layer between two of the plurality of second metallization layers, an integrated circuit (IC) device structure. **Claim 14** The IC device structure according to any one of claims 1 to 3, wherein the interconnected chiplet has a piezoelectric layer between two of the plurality of second metallization layers.

15. A microprocessor chip, including a plurality of transistors within the microprocessor chip, a plurality of first metallization layers above the plurality of transistors and interconnected to the plurality of transistors, an interconnected chiplet above the plurality of first metallization layers, the interconnected chiplet having a plurality of second metallization layers, and the interconnected chiplet being interconnected to the plurality of first metallization layers, a plurality of third metallization layers above the plurality of first metallization layers and adjacent to the interconnected chiplet, wherein at least one of the dimensions or compositions of the conductive layers included in the metallization layer is different between the plurality of second metallization layers and the plurality of third metallization layers, and a plurality of fourth metallization layers extending above the plurality of second metallization layers and the plurality of third metallization layers A microprocessor chip having and an interconnect pad connecting the topmost layer of the plurality of fourth metallization layers and the interposer substrate A system comprising

16. A microprocessor chip, including a plurality of transistors within the microprocessor chip, a plurality of first metallization layers above the plurality of transistors and interconnected to the plurality of transistors, an interconnected chiplet above the plurality of first metallization layers, the interconnected chiplet having a plurality of second metallization layers, and the interconnected chiplet being interconnected to the plurality of first metallization layers, A plurality of third metallization layers above the plurality of first metallization layers and adjacent to the interconnect chiplets, wherein at least one of the dimensions or composition of the conductive layers included in the metallization layer is different between the plurality of second metallization layers and the plurality of third metallization layers, the plurality of third metallization layers, and A second interconnect chiplet having a plurality of fourth metallization layers, wherein the second interconnect chiplet is interconnected to the plurality of third metallization layers, the second interconnect chiplet and A microprocessor chip having Comprising The interconnect chiplet is a first chiplet, The dielectric material is between the sidewalls of the first chiplet and the sidewalls of the second interconnect chiplet, The plurality of first metallization layers includes one or more lower metallization layers and one or more upper metallization layers located above the one or more lower metallization layers, At least one of the pitch, composition, or thickness of the conductive layers included in the metallization layer is different between the plurality of fourth metallization layers and the plurality of second metallization layers or the plurality of third metallization layers, The plurality of fourth metallization layers are a plurality of topmost metallization layers extending above the plurality of second metallization layers and the plurality of third metallization layers, System.

17. A microprocessor chip, A plurality of transistors within the microprocessor chip, and A plurality of first metallization layers above the plurality of transistors and interconnected to the plurality of transistors, and An interconnect chiplet above the plurality of first metallization layers, wherein the interconnect chiplet has a plurality of second metallization layers, and the interconnect chiplet is interconnected to the plurality of first metallization layers, the interconnect chiplet, A plurality of third metallization layers above the plurality of first metallization layers and adjacent to the interconnect chiplets, wherein at least one of the dimensions or compositions of the conductive layers included in the metallization layer is different between the plurality of second metallization layers and the plurality of third metallization layers, the plurality of third metallization layers and A microprocessor chip having Comprising The interconnect chiplets have a magnetic layer between two of the plurality of second metallization layers. System

18. The system according to any one of claims 15 to 17, further comprising a power supply coupled to supply power to the microprocessor chip.

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