Semiconductor device

Abstract

To provide a semiconductor device with which it is possible to suppress on-resistance from increasing.SOLUTION: Trenches 15 adjacent to each other are formed at such an interval that when a prescribed voltage is applied to a gate electrode 17, channel regions formed in base layers 13 that are in contact with the respective trenches 15 are connected. The trenches 15 are tapered, with side faces inclined with respect to the normal to a surface direction of a semiconductor substrate 10, and when a length in a direction intersecting the longitudinal direction and parallel to the surface direction of the semiconductor substrate 10 is assumed to be a width, the base layers 13 are constituted to include a portion between the adjacent trenches 15, where impurity concentration in a wide width portion is lower than impurity concentration in a narrow width portion.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a trench gate structure and composed of a wide bandgap semiconductor material.

Background Art

[0002] Conventionally, a semiconductor device having a trench gate structure and composed of a wide bandgap semiconductor material has been proposed (see, for example, Patent Document 1). Specifically, this semiconductor device is composed of silicon carbide (hereinafter also referred to as SiC) as a wide bandgap semiconductor material, and a MOSFET (abbreviation for Metal Oxide Semiconductor Field Effect Transistor) is formed. More specifically, in this semiconductor device, an n + -type substrate has an n - -type drift layer formed thereon, and a p-type base layer is formed on the drift layer. An n + -type source region is formed in the surface layer portion of the base layer. A plurality of trenches are formed so as to penetrate the source region and the base layer, and a gate insulating film and a gate electrode are sequentially formed in each trench. Thereby, a trench gate structure is formed.

[0003] + -type substrate, and a second electrode is formed so as to be connected to the n

[0004] In such a semiconductor device, when a voltage equal to or higher than a predetermined threshold voltage is applied to the gate electrode, an n-type inversion layer (i.e., a channel region) is formed in a portion of the base layer that contacts the trench. Then, in the semiconductor device, electrons are supplied from the source region to the drift layer through the inversion layer, causing a current to flow between the first electrode and the second electrode and turning the device on. Also, in this semiconductor device, by preventing a voltage equal to or higher than a predetermined threshold voltage from being applied to the gate electrode, the inversion layer formed in the base layer disappears, turning the device off.

[0005] And in a semiconductor device configured using such a wide-bandgap semiconductor material, it has been reported that the electron mobility may decrease due to the influence of interface states or the like, increasing the on-resistance. For this reason, in the above semiconductor device, when in the on state, the interval between adjacent trenches is adjusted so that an inversion layer is formed over the entire base layer located between adjacent trenches. In other words, in the above semiconductor device, when in the on state, in the base layer located between adjacent trenches, the interval between adjacent trenches is adjusted so that the inversion layer formed in a portion contacting one trench and the inversion layer formed in a portion contacting the other trench are connected.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] However, when actually forming the trenches included in the semiconductor device described above, it is difficult to make the side surfaces completely parallel to the normal direction with respect to the surface direction of the semiconductor substrate due to manufacturing errors or the like, and the side surfaces become tapered and inclined with respect to the normal direction. And the base layer varies in width along the depth direction (that is, the thickness direction of the semiconductor substrate) in the portion located between adjacent trenches. For this reason, if the impurity concentration of the base layer is made constant along the depth direction, in the portion where the width is wide, it becomes difficult for the inversion layer to connect to the portion where the width is narrow, and the electron mobility tends to decrease. Therefore, in the semiconductor device described above, there is a possibility that the on-resistance increases.

[0008] In view of the above points, an object of the present invention is to provide a semiconductor device capable of suppressing an increase in on-resistance.

Means for Solving the Problems

[0009] Claim 1 for achieving the above object and 4A semiconductor device having a trench gate structure, which is composed of a wide bandgap semiconductor material, includes a base layer (13) of a first conductivity type, a first impurity region (14) of a second conductivity type disposed on the surface layer portion of the base layer, and a second impurity region (11, 21) of the first conductivity type or the second conductivity type disposed apart from the first impurity region. A semiconductor substrate (10) has a surface on the surface layer portion side of the base layer as one surface (10a) and a surface on the opposite side of the one surface as the other surface (10b). A plurality of trenches (15) are formed from one surface side of the semiconductor substrate with one direction in the plane direction of the semiconductor substrate as the longitudinal direction. The semiconductor device further includes a plurality of trench gate structures each having a gate insulating film (16) disposed on the wall surface of the trench (15) and a gate electrode (17) disposed on the gate insulating film, a first electrode (19) electrically connected to the first impurity region and the base layer, and a second electrode (20) electrically connected to the second impurity region. When a predetermined voltage is applied to the gate electrode, a channel region is formed in a portion of the base layer in contact with the trench, and a current flows between the first electrode and the second electrode. Adjacent trenches are formed at intervals such that channel regions formed in the base layer in contact with the respective trenches are connected when a predetermined voltage is applied to the gate electrode. The trenches are tapered such that the side surfaces are inclined with respect to the normal direction to the plane direction of the semiconductor substrate. When the length in the direction intersecting the longitudinal direction and along the plane direction of the semiconductor substrate is defined as the width, the base layer is configured to include a portion where the impurity concentration in the wide-width portion is lower than the impurity concentration in the narrow-width portion at a portion located between adjacent trenches. And in claim 1, the trench has portions with different opening widths along the longitudinal direction, and the base layer is configured to include a portion where the impurity concentration in the wider-width portion is lower than that in the narrower-width portion in the longitudinal direction. In claim 4, the first electrode and the second electrode are disposed on one surface side of the semiconductor substrate, and current flows along the surface direction of the semiconductor substrate.

[0010] According to this, the impurity concentration in the wide-width portion of the base layer is lower than that in the narrow-width portion. Therefore, when the semiconductor device is in the on state in which current flows, the inversion layers formed in the portions in contact with the adjacent trenches are easily connected even in the wide-width portion of the base layer. Accordingly, it is possible to suppress a decrease in the electron density and a decrease in the electron mobility even in the wide-width portion, so that the channel resistance can be sufficiently reduced and an increase in the on-resistance can be suppressed.

[0011] Note that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 6A

Figure 6B

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Modes for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals and described together.

[0014] (First Embodiment) The first embodiment will be described with reference to the drawings. Note that the semiconductor device of this embodiment is preferably applied as a semiconductor device mounted on a vehicle such as an automobile and used to drive various vehicle-mounted electronic devices. In this embodiment, a semiconductor device in which an inversion-type MOSFET having a trench gate structure is formed will be described.

[0015] As shown in FIG. 1, the semiconductor device of this embodiment is configured using a semiconductor substrate 10. The semiconductor substrate 10 is made of a wide bandgap semiconductor material, and in this embodiment, it is made of SiC. Hereinafter, in this embodiment, a SiC semiconductor device in which the semiconductor substrate 10 is made of SiC will be described as an example. However, the semiconductor substrate 10 may be made of a wide bandgap semiconductor material, and for example, it may be made of gallium nitride, diamond, or the like.

[0016] The semiconductor substrate 10 of this embodiment is formed by disposing an n-type drift layer 12 and a p-type base layer 13 on an n-type substrate 11 made of SiC. And an n-type source region 14 is formed in the surface layer portion of the base layer 13. + type substrate 11, an n - type drift layer 12 and a p-type base layer 13 are arranged and configured. And an n + type source region 14 is formed in the surface layer portion of the base layer 13.

[0017] Although not particularly shown, in a cross section different from that in FIG. 1, the semiconductor device of this embodiment has a contact region with a higher impurity concentration than the base layer 13 formed in the surface layer portion of the base layer 13 so as to be exposed from one surface 10a of the semiconductor substrate 10. Specifically, in this embodiment, the source region 14 and the contact region are alternately formed along the longitudinal direction of a trench 15 described later.

[0018] The substrate 11 has, for example, an n-type impurity concentration of 1.0×10 19 / cm 3 and its surface is a (0001) Si plane. In this embodiment, the substrate 11 constitutes the drain region in the MOSFET. The base layer 13 is the portion where the channel region is formed, and the impurity concentration distribution will be described later. The source region 14 has a higher impurity concentration than the drift layer 12. And in this embodiment, the substrate 11 corresponds to the second impurity region, and the source region 14 corresponds to the first impurity region.

[0019] A plurality of trenches 15 extending in one direction in the plane direction of the semiconductor substrate 10 with the longitudinal direction along one direction in the plane direction of the semiconductor substrate 10 are formed in the semiconductor substrate 10 so as to penetrate the base layer 13 and the source region 14 from the one surface 10a side and reach the drift layer 12. In this embodiment, each trench 15 is formed in a stripe shape with the depth direction in FIG. 1 as the longitudinal direction. And the base layer 13 and the source region 14 are formed so as to be in contact with the side surfaces of the trenches 15 because the trenches 15 are formed as described above. Note that the contact regions are formed in a cross section different from FIG. 1 as described above and are alternately formed with the source region 14 along the longitudinal direction of the trenches 15.

[0020] A gate insulating film 16 is formed on the inner wall surface of the trench 15. A gate electrode 17 made of doped Poly-Si is formed on the surface of the gate insulating film 16. Thereby, a trench gate structure is formed in the semiconductor substrate 10.

[0021] Here, the trench 15 of the present embodiment is formed by anisotropic etching such as RIE (abbreviation for Reactive Ion Etching). Specifically, as will be described later, the side surface is tapered. Further, the trench of the present embodiment, specifically as will be described later, when the semiconductor device is in the on state, the channel region (that is, the bulk channel region) is formed in the entire base layer 13 located between adjacent trenches 15, and the interval is adjusted. In the present embodiment, the adjacent trenches 15 are formed such that the width of the longest portion of the base layer 13 located between the adjacent trenches 15 is 0.1 μm or less.

[0022] An interlayer insulating film 18 is formed on one surface 10a of the semiconductor substrate 10. And a contact hole 18a for exposing the source region 14 and a contact region (not shown) is formed in the interlayer insulating film 18.

[0023] A first electrode 19 electrically connected to the source region 14 and the base layer 13 through the contact hole 18a is formed on the interlayer insulating film 18. Note that the first electrode 19 is electrically connected to the base layer 13 by being electrically connected to a contact region formed in the surface layer portion of the base layer 13 in a cross section different from that of FIG. 1.

[0024] In the present embodiment, the first electrode 19 is composed of, for example, a plurality of metals such as Ni / Al. And the portion in contact with the portion constituting the n-type SiC (that is, the source region 14) among the plurality of metals is composed of a metal capable of forming an ohmic contact with the n-type SiC. Further, at least the portion in contact with the p-type SiC (that is, the contact region) among the plurality of metals is composed of a metal capable of forming an ohmic contact with the p-type SiC.

[0025] A second electrode 20 electrically connected to the substrate 11 is formed on the other surface 10b side of the substrate 11. In the present embodiment, with such a structure, an n-channel type inversion-mode trench gate structure MOSFET is configured.

[0026] Next, the shape of the trench 15 and the impurity concentration of the base layer 13 in the present embodiment will be specifically described. Hereinafter, the stacking direction of the substrate 11, the drift layer 12, and the base layer 13 is also referred to as the depth direction. Note that the depth direction can also be said to be the thickness direction of the semiconductor substrate 10. Further, hereinafter, the length in the direction parallel to the plane direction of the semiconductor substrate 10 and intersecting the longitudinal direction of the trench 15 is defined as the width. For example, in FIG. 1 and the like, the length in the left-right direction of the paper surface is the width.

[0027] The trench 15 is formed by performing dry etching such as RIE on the semiconductor substrate 10, and as shown in FIGS. 1 and 2, the side surface has a tapered shape inclined with respect to the normal direction to one surface 10a of the semiconductor substrate 10. Specifically, the trench 15 in the present embodiment has a forward taper shape in which the opening width becomes narrower from the one surface 10a side toward the other surface 10b side. Therefore, the base layer 13 located between adjacent trenches 15 has an inverted taper shape in which the width becomes wider from the one surface 10a side toward the other surface 10b side.

[0028] And, in the base layer 13, in the portion located between adjacent trenches 15, in the portion where the width is wide, the impurity concentration is made lower than that in the portion where the width is narrow. That is, in the present embodiment, in the base layer 13, the impurity concentration of the portion located on the other surface 10b side is made lower than the impurity concentration of the portion located on the one surface 10a side. In this case, the base layer 13 may be adjusted so that the impurity concentration continuously decreases from the one surface 10a side toward the other surface 10b side, or may be adjusted so that the impurity concentration decreases stepwise. In the present embodiment, the base layer 13 is adjusted so that the impurity concentration continuously decreases from the one surface 10a side toward the other surface 10b side.

[0029] Note that such a base layer 13 is configured by adjusting the impurity concentration when performing ion implantation when the base layer 13 is formed by ion implantation. When the base layer 13 is formed by epitaxial growth, it is configured by adjusting the concentration of the impurity added during epitaxial growth.

[0030] Further, the trench 15 of the present embodiment is in a tapered shape as described above. As shown in FIG. 3, when the angle formed between the side surface and the virtual plane S along the plane direction of the semiconductor substrate 10 is θ1, the formed angle θ1 is adjusted as follows. That is, in the semiconductor device as described above, a source region 14 and a contact region are formed on one surface 10a side of the semiconductor substrate 10. In this case, considering the variations when forming the source region 14 and the contact region, the source region 14 and the contact region have a thickness of 0.3 μm or more. Further, the base layer 13 is a portion where a channel region is formed, and has a thickness of 0.2 μm or more so that threshold voltage variations are less likely to occur. That is, in the present embodiment, the length L1 from one surface 10a of the semiconductor substrate 10 to the portion on the other surface 10b side of the base layer 13 is 0.5 μm or more. Note that the portion on the other surface 10b side of the base layer 13 is, in other words, the interface between the base layer 13 and the drift layer 12.

[0031] Also, the width d of the longest portion of the base layer 13 located between adjacent trenches 15 is 0.1 μm or less as described above so that a channel region is formed throughout the base layer 13. And the formed angle θ1 is adjusted to be 84.3° or more and less than 90° so that one surface 10a of the semiconductor substrate 10 (that is, the source region 14 and the contact region) remains between adjacent trenches 15.

[0032] The above is the configuration of the semiconductor device in the present embodiment. Note that in the present embodiment, the n + -type and n - -type correspond to the first conductivity type, and the p - -type, p-type, and p + -type correspond to the second conductivity type. Further, in the present embodiment, by being configured as described above, the semiconductor substrate 10 includes a substrate 11, a drift layer 12, a base layer 13, a source region 14, and the like.

[0033] Next, the operation and effects of the semiconductor device will be described. In the semiconductor device, while the second electrode 20 is set to a higher potential than the first electrode 19, when a voltage equal to or higher than a predetermined threshold voltage is applied to the gate electrode 17, an n-type inversion layer (i.e., a channel region) is formed in the portion of the base layer 13 that contacts the trench 15. Then, electrons are supplied from the source region 14 to the drift layer 12 through the inversion layer, causing a current to flow between the first electrode 19 and the second electrode 20 and turning the device on. That is, in the semiconductor device of the present embodiment, when a voltage equal to or higher than a predetermined threshold voltage is applied to the gate electrode 17, a current flows along the thickness direction of the semiconductor substrate 10.

[0034] At this time, in the present embodiment, the width d of the longest portion of the base layer 13 located between adjacent trenches 15 is set to 0.1 μm or less. Therefore, when a voltage equal to or higher than a predetermined threshold voltage is applied to the gate electrode 17, the inversion layers formed in the portions of the base layer 13 that contact each trench 15 are more likely to be connected. That is, in the base layer 13 located between adjacent trenches 15, a channel region (i.e., a bulk channel region) is more likely to be formed as a whole. Therefore, the on-resistance of the semiconductor device can be reduced.

[0035] Here, as shown in FIG. 4, a semiconductor device in which the impurity concentration of the base layer 13 is constant along the depth direction is used as a comparative semiconductor device. In other words, a semiconductor device in which the impurity concentration in the narrow-width portion of the base layer 13 is equal to the impurity concentration in the wide-width portion is used as a comparative semiconductor device. In this case, in the comparative semiconductor device, in the wide-width portion, it is more difficult for the inversion layers formed in the portions contacting the adjacent trenches 15 to be connected than in the narrow-width portion. Therefore, as shown in FIGS. 5A and 5B, in the wide-width portion, the electron density is smaller than in the narrow-width portion. For this reason, in the comparative semiconductor device, as shown in FIG. 4, the electron mobility in the wide-width portion is low. Therefore, in the comparative semiconductor device, the current may be reduced in the wide-width portion as indicated by arrow B, and the channel resistance may not be sufficiently reduced.

[0036] In contrast, as shown in FIG. 2, in the base layer 13 of the present embodiment, in the wide-width portion, the impurity concentration is made lower than that in the narrow-width portion. Therefore, even in the wide-width portion of the base layer 13, it becomes easier for the inversion layers formed in the portions in contact with the adjacent trenches 15 to be connected to each other. Accordingly, as shown in FIGS. 6A and 6B, it is possible to suppress a decrease in electron density even in the wide-width portion, and as shown in FIG. 2, it is possible to suppress a decrease in electron mobility even in the wide-width portion. Thereby, it is possible to suppress a decrease in current in the wide-width portion as indicated by the arrow A. That is, according to the semiconductor device of the present embodiment, the channel resistance can be sufficiently reduced, and an increase in the on-resistance can be suppressed.

[0037] Note that FIGS. 5A and 6A show the electron density at the interface between the base layer 13, the source region 14, and the contact region. FIGS. 5B and 6B are diagrams showing the electron density at the interface between the base layer 13 and the drift layer 12.

[0038] According to the present embodiment described above, in the base layer 13, in the wide-width portion, the impurity concentration is made lower than that in the narrow-width portion. Therefore, when the base layer 13 is in the on state, even in the wide-width portion, it becomes easier for the inversion layers formed in the portions in contact with the adjacent trenches 15 to be connected to each other. Accordingly, it is possible to suppress a decrease in electron density and a decrease in electron mobility even in the wide-width portion, so that the channel resistance can be sufficiently reduced, and an increase in the on-resistance can be suppressed.

[0039] (1) In the present embodiment, the trench 15 is formed at an angle θ1 of 84.3° or more and less than 90°. Therefore, it is possible to suppress disappearance of one surface 10a of the semiconductor substrate 10 between the adjacent trenches 15. Accordingly, it is possible to suppress occurrence of a connection failure between the first electrode 19 and one surface 10a of the semiconductor substrate 10 (that is, the source region 14 and the contact region).

[0040] (Second Embodiment) A description will be given of the second embodiment. This embodiment is different from the first embodiment in that the shape of the trench 15 and the impurity concentration distribution of the base layer 13 are changed. Since other aspects are the same as those of the first embodiment, the description thereof will be omitted here.

[0041] In the semiconductor device of this embodiment, as shown in FIG. 7, the trench 15 has an inverted taper shape in which the opening width becomes wider from one surface 10a side toward the other surface 10b side. For this reason, the base layer 13 located between adjacent trenches 15 has a forward taper shape in which the width becomes narrower from the one surface 10a side toward the other surface 10b side. And the impurity concentration of the portion of the base layer 13 located on the one surface 10a side is made lower than the impurity concentration of the portion located on the other surface 10b side. Note that the base layer 13 may be adjusted so that the impurity concentration continuously decreases from the other surface 10b side toward the one surface 10a side, or may be adjusted so that the impurity concentration decreases stepwise. In this embodiment, the base layer 13 is adjusted so that the impurity concentration continuously decreases from the other surface 10b side toward the one surface 10a side.

[0042] In addition, the trench 15 has the inverted taper shape as described above, and as shown in FIG. 8, the angle θ2 formed with the virtual plane S is adjusted as follows. That is, in the semiconductor device as described above, the thickness of the base layer 13 is set to 0.2 μm or more, and the trench 15 is formed so as to penetrate the base layer 13. For this reason, in this embodiment, the length L2 from the portion of the base layer 13 located on the one surface 10a side to the bottom of the trench 15 is set to 0.2 μm or more. Further, the width d of the widest portion of the base layer 13 located between adjacent trenches 15 is set to 0.1 μm or less as described above. And the angle θ2 is set to be greater than 90° and less than 104° so that the root portion located between adjacent trenches 15 does not have a complete apex angle. In other words, the angle θ2 is set to be greater than 90° and less than 104° so that the bottoms of adjacent trenches 15 are not connected.

[0043] Note that for such a trench 15, the etching process and the protective film forming process may be repeated by dry etching so that the protective film disposed on the side surface on the other surface 10b side becomes thinner in the protective film forming process.

[0044] According to the present embodiment described above, since the base layer 13 has a lower impurity concentration in the wider portion than in the narrower portion, the same effects as those of the first embodiment can be obtained.

[0045] (1) In the present embodiment, the trench 15 has an angle θ2 formed thereby greater than 90° and less than 104°. Therefore, it is possible to suppress the disappearance of the root portion sandwiched between the bottoms of adjacent trenches 15 between adjacent trenches 15.

[0046] (Third Embodiment) The third embodiment will be described. This embodiment combines the shapes of the trenches 15 of the first embodiment and the second embodiment. Since the other aspects are the same as those of the first embodiment, the description is omitted here.

[0047] In the semiconductor device of the present embodiment, as shown in FIG. 9, the trench 15 has a reverse tapered shape on the one surface 10a side and a forward tapered shape on the other surface 10b side. That is, the trench 15 of the present embodiment includes a reversely tapered portion and a forward tapered portion.

[0048] And the base layer 13 has a lower impurity concentration in the portion located between adjacent trenches 15 in the wider portion than in the narrower portion. In the present embodiment, the base layer 13 has a higher impurity concentration in the portion located at the same depth as the portion where the reversely tapered trench 15 and the forward tapered trench 15 are connected, and the impurity concentration decreases from this portion toward the one surface 10a side and the other surface 10b side.

[0049] According to the present embodiment described above, since the impurity concentration in the wide portion of the base layer 13 is lower than that in the narrow portion, the same effects as those of the first embodiment can be obtained.

[0050] In the semiconductor device of the present embodiment, the trench 15 may have a forward-tapered portion on the one surface 10a side and a reverse-tapered portion on the other surface 10b side. In this case, the impurity concentration of the portion of the base layer 13 located at the same depth as the portion where the trench 15 having a reverse-tapered shape and the trench 15 having a forward-tapered shape are connected is lowered, and the impurity concentration increases from this portion toward the one surface 10a side and the other surface 10b side.

[0051] (Fourth Embodiment) The fourth embodiment will be described. This embodiment is a lateral semiconductor device in which current flows in the plane direction of the semiconductor substrate 10 with respect to the second embodiment. Since other aspects are the same as those of the second embodiment, the description is omitted here.

[0052] As shown in FIG. 10, the semiconductor substrate 10 of the present embodiment is configured by disposing a p + -type base layer 13 on a p-type substrate 11. On the surface layer portion of the base layer 13, an n + -type source region 14 and an n + -type drain region 21 are formed so as to be separated from each other. In the present embodiment, the semiconductor substrate 10 is configured as described above. The semiconductor substrate 10 includes the base layer 13, the source region 14, the drain region 21, etc., and one surface 10a is formed, and the other surface 10b is formed by the substrate 11. Although omitted in FIG. 10, actually, an interlayer insulating film 18, a first electrode 19, and a second electrode 20 are disposed on the one surface 10a side of the semiconductor substrate 10. The first electrode 19 is connected to the source region 14 and the base layer 13, and the second electrode 20 is connected to the drain region 21. In the present embodiment, the drain region 21 corresponds to the second impurity region.

[0053] In the semiconductor substrate 10, a trench 15 is formed so as to penetrate the base layer 13, the source region 14, and the drain region 21 and reach the substrate 11. That is, the source region 14 and the drain region 21 are formed in contact with the trench 15. And in the trench 15, a gate insulating film 16 and a gate electrode 17 are embedded in the same manner as in the first embodiment.

[0054] Note that in FIG. 10, only one trench 15 is shown, but actually, a plurality of trenches 15 are formed in a stripe shape to constitute a semiconductor device.

[0055] Also, the trench 15 of the present embodiment has an inverted tapered shape in which the opening width becomes wider from the one surface 10a side toward the other surface 10b side, as in the second embodiment. For this reason, the base layer 13 located between adjacent trenches 15 has a tapered shape in which the width becomes narrower from the one surface 10a side toward the other surface 10b side. And the base layer 13 has a lower impurity concentration in the wider portion than in the narrower portion in the portion located between adjacent trenches 15, as in the second embodiment.

[0056] The above is the configuration of the semiconductor device in the present embodiment. And in the semiconductor device of the present embodiment, when a voltage equal to or higher than a predetermined threshold voltage is applied to the gate electrode 17, a current flows along the plane direction of the semiconductor substrate 10.

[0057] According to the present embodiment described above, since the base layer 13 has a lower impurity concentration in the wider portion than in the narrower portion, the same effect as that of the first embodiment can be obtained. And such a configuration of the base layer 13 can also be applied to a semiconductor device in which a current flows along the plane direction of the semiconductor substrate 10.

[0058] (Fifth Embodiment) The fifth embodiment will be described. This embodiment is different from the fourth embodiment in that the width along the longitudinal direction of the trench 15 is changed. Since other aspects are the same as those of the fourth embodiment, the description thereof will be omitted here.

[0059] In the semiconductor device of this embodiment, as shown in FIG. 11, the trench 15 varies in width along the longitudinal direction. In this embodiment, the trench 15 is formed such that the opening width increases from the source region 14 side toward the drain region 21 side. Note that such a trench 15 can be formed due to manufacturing errors or the like. And the base layer 13 located between adjacent trenches 15 has a lower impurity concentration from the drain region 21 side toward the base layer 13 side.

[0060] According to the embodiment described above, since the impurity concentration of the base layer 13 is lower in the wider portion than in the narrower portion, the same effect as that of the first embodiment can be obtained.

[0061] (Other Embodiments) Although the present disclosure has been described in accordance with the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and variations within the equivalent scope. In addition, various combinations and forms, and further other combinations and forms including only one element, more than one element, or less than one element thereof, fall within the scope and spirit of the present disclosure.

[0062] For example, in each of the above embodiments, a semiconductor device in which an n-channel type trench gate structure MOSFET with the first conductivity type being n-type and the second conductivity type being p-type is formed has been described. However, this is merely an example. For example, a semiconductor device may be configured by forming a p-channel type trench gate structure MOSFET in which the conductivity types of the respective components are inverted with respect to the n-channel type. Furthermore, in addition to the MOSFET, the semiconductor device may be configured to have a structure in which an IGBT having the same structure is formed. In the case of an IGBT, for example, in the first embodiment above, other than changing the n + type substrate 11 to a p + type substrate 11, it is the same as the MOSFET described in the first embodiment. Furthermore, in the semiconductor device of each of the above embodiments, another semiconductor element such as a diode element may be integrally formed.

[0063] In each of the above embodiments, a n-type semiconductor layer having a higher impurity concentration than the drift layer 12 is provided between the drift layer 12 and the base layer 13. + A carrier diffusion layer may be formed on the semiconductor device to further reduce the on-resistance.

[0064] Furthermore, in each of the above embodiments, the impurity concentration of a part of the base layer 13 located between adjacent trenches 15 may be adjusted as described above, and the impurity concentration of the remaining base layer 13 may be constant along the depth direction. That is, in the semiconductor device of each of the above embodiments, the impurity concentration of all of the base layers 13 located between adjacent trenches 15 may not be adjusted, but the impurity concentration of a part of the base layer 13 may be adjusted as in each of the above embodiments.

[0065] The above embodiments may be combined as appropriate. For example, the first embodiment may be combined with the fourth or fifth embodiment, and the trench 15 may be tapered so that the opening width narrows from the one surface 10a toward the other surface 10b. The third embodiment may be combined with the fourth or fifth embodiment, and the trench 15 may be configured to include a forward tapered portion and a reverse tapered portion. [Explanation of symbols]

[0066] 10. Semiconductor Substrate 10a one side 10b Other side 11 Substrate (second impurity region) 13 Base Layer 14 Source region (first impurity region) 15. Trench 16 Gate insulating film 17 Gate electrode 19 1st electrode 20 2nd electrode

Claims

1. A semiconductor device having a trench gate structure, composed of a wide bandgap semiconductor material, having a base layer (13) of a first conductivity type, a first impurity region (14) of a second conductivity type disposed on the surface layer portion of the base layer, and a second impurity region (11, 21) of a first conductivity type or a second conductivity type disposed apart from the first impurity region, and using a surface on the surface layer portion side of the base layer as one surface (10a) and a surface on the opposite side of the one surface as the other surface (10b), a semiconductor substrate (10); a plurality of trench gate structures each having a trench (15) formed from one surface side of the semiconductor substrate with one direction in the plane direction of the semiconductor substrate as the longitudinal direction, a gate insulating film (16) disposed on the wall surface of the trench (15), and a gate electrode (17) disposed on the gate insulating film; a first electrode (19) electrically connected to the first impurity region and the base layer; a second electrode (20) electrically connected to the second impurity region; wherein a channel region is formed in a portion of the base layer in contact with the trench when a predetermined voltage is applied to the gate electrode, and a current flows between the first electrode and the second electrode; adjacent trenches are formed at intervals such that channel regions formed in the base layer in contact with the respective trenches are connected when a predetermined voltage is applied to the gate electrode; the trench is tapered such that its side surface is inclined with respect to the normal direction to the plane direction of the semiconductor substrate; when the length in the direction along the plane direction of the semiconductor substrate and intersecting the longitudinal direction is taken as the width, the base layer is configured to include a portion where the impurity concentration of a wide-width portion is lower than the impurity concentration of a narrow-width portion in a portion located between adjacent trenches; the trench has portions with different opening widths along the longitudinal direction; a semiconductor device, wherein the base layer is configured to include a portion where the impurity concentration of a wide-width portion is lower than the impurity concentration of a narrow-width portion in the longitudinal direction.

2. the first electrode is disposed on one surface side of the semiconductor substrate, the second electrode is disposed on the other surface side of the semiconductor substrate, The semiconductor device according to claim 1, wherein the current flows along the thickness direction of the semiconductor substrate.

3. the first electrode and the second electrode are disposed on one surface side of the semiconductor substrate, The semiconductor device according to claim 1, wherein the current flows along the plane direction of the semiconductor substrate.

4. A semiconductor device having a trench gate structure, composed of a wide bandgap semiconductor material, having a base layer (13) of a first conductivity type, a first impurity region (14) of a second conductivity type disposed on the surface layer portion of the base layer, and a first or second impurity region (11, 21) of a first conductivity type or a second conductivity type disposed apart from the first impurity region, with a semiconductor substrate (10) having a surface on the surface layer portion side of the base layer as one surface (10a) and a surface on the opposite side of the one surface as the other surface (10b), a plurality of trenches (15) are formed from one surface side of the semiconductor substrate with one direction in the plane direction of the semiconductor substrate as the longitudinal direction, and having a gate insulating film (16) disposed on the wall surface of the trench (15) and a gate electrode (17) disposed on the gate insulating film, a first electrode (19) electrically connected to the first impurity region and the base layer, a second electrode (20) electrically connected to the second impurity region, when a predetermined voltage is applied to the gate electrode to form a channel region in a portion of the base layer in contact with the trench, a current flows between the first electrode and the second electrode, adjacent trenches are formed at intervals such that channel regions formed in the base layer in contact with the respective trenches are connected when a predetermined voltage is applied to the gate electrode, the trench is tapered with a side surface inclined with respect to the normal direction to the plane direction of the semiconductor substrate, when the length in the direction along the plane direction of the semiconductor substrate is defined as the width in a direction intersecting the longitudinal direction, the base layer includes a portion where the impurity concentration in a wide-width portion is lower than the impurity concentration in a narrow-width portion in a portion located between adjacent trenches, the first electrode and the second electrode are disposed on one surface side of the semiconductor substrate, a semiconductor device in which the current flows along the plane direction of the semiconductor substrate.

5. the trench has a portion tapered in a forward taper shape with an opening width decreasing from the one surface side toward the other surface side, the semiconductor device according to any one of claims 1 to 4, wherein the angle (θ1) formed by the virtual plane (S) along the plane direction of the semiconductor substrate and the side surface of the forward taper-shaped portion is 84.2° or more and less than 90°.

6. The trench has a portion with an inverted taper shape in which the opening width widens from the one surface side toward the other surface side. The semiconductor device according to any one of claims 1 to 5, wherein the portion with the inverted taper shape has an angle (θ2) formed between a virtual plane (S) along the plane direction of the semiconductor substrate and the side surface that is greater than 90° and less than 104°.

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