Semiconductor device

Abstract

To provide a semiconductor device.SOLUTION: A semiconductor device comprises: a first type semiconductor structure that includes a first lattice constant, and includes a first side and a second side that is opposite to the first side; an active structure that is positioned on the first side, and emits a radial ray, of which a peak wavelength is 1000nm to 2000nm; and a first contact layer that is positioned to the second side, includes a second lattice constant, and contains a first dopant having a first doping concentration that is larger than 1*1018 / cm3. A difference between the second lattice constant and the first lattice constant is at least 0.5%.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices having a lattice constant difference.

Background Art

[0002] With the rapid progress of science and technology, semiconductor devices play a very important role in fields such as information transmission and energy conversion, and research and development of related materials are continuously carried out. For example, semiconductor materials can be applied to various optoelectronic devices, such as light emitting diodes (LEDs), laser diodes (LDs), solar cells, power devices, acoustic wave sensors, etc., and can also be applied to fields such as lighting, display, communication, detection, and power systems.

[0003] The principle of light emission of a light emitting diode is to convert electrical energy into light energy by applying a current to combine electrons in the N-type semiconductor layer and holes in the P-type semiconductor layer. Since light emitting diodes have advantages such as low power consumption and long service life, they are widely applied in traffic signal lights, backlight modules, various lighting, medical devices, etc. instead of conventional light sources. Light emitting diodes that emit infrared light also have a large market and potential in the fields of detection systems, recognition systems, monitoring systems, and in-vehicle light sources.

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a semiconductor device having a lattice constant difference.

Means for Solving the Problems

[0005] According to some embodiments of the present invention, a semiconductor device is provided, which a first type semiconductor structure having a first lattice constant and having a first side and a second side opposite the first side; an active structure, located on a first side of the first type semiconductor structure, emitting radiation, the peak wavelength of the radiation being between 1000 nm and 2000 nm; and a first contact layer located on a second side of the first-type semiconductor structure, the first contact layer having a second lattice constant and a lattice constant greater than or equal to 1×10 18 / cm 3 a first dopant having a first doping concentration greater than wherein the difference between the second lattice constant and the first lattice constant is at least 0.5%. [Brief description of the drawings]

[0006] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the drawings, in which various features are not drawn to scale, but are merely illustrative, and in which the dimensions of elements may be arbitrarily increased or decreased to more clearly illustrate the features of the present invention.

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 5

Figure 6

Figure 7

Figure 8

[0007] The following describes several embodiments to enable those skilled in the art to more easily understand the present invention. It should be noted that these embodiments are merely illustrative and do not limit the present invention. Also, those skilled in the art may adjust the embodiments described below according to their needs. For example, they may change the order of the processes and / or increase or decrease some steps.

[0008] Also, based on the embodiments described below, other elements or steps may be added. For example, descriptions such as "forming a second layer / structure on a first layer / structure" may include embodiments where the first layer / structure is in direct contact with the second layer / structure, and may also include embodiments where the first layer / structure is not in direct contact with the second layer / structure due to having other elements between them. The relative spatial relationship between the first layer / structure and the second layer / structure may also change depending on the operation or use of the device in different orientations. In addition, in the present invention, numbers and / or letters as reference signs may be used repeatedly in different embodiments, and such repeated use is for simplification and clarification, not to represent the relationship between different embodiments. Furthermore, in this specification, expressions such as "a layer substantially composed of X material" indicate that the main composition of the layer is X material, but do not exclude the inclusion of dopants and inevitable impurities.

[0009] In the embodiments of the present invention, unless otherwise specifically explained, chemical formulas may include "stoichiometric compounds" and "non-stoichiometric compounds". Among them, "stoichiometric compounds" refer to, for example, the total amount of group 3 elements being the same as the total amount of group 5 elements, and "non-stoichiometric compounds" refer to, for example, the total amount of group 3 elements being different from the total amount of group 5 elements. For example, a chemical formula being AlGaAs means it contains group 3 elements Al and / or Ga, and also contains group 5 element As. Among them, the total amount of group 3 elements (Al and / or Ga) may be the same as or different from the total amount of group 5 element (As).

[0010] Also, when each compound represented by a chemical formula is a stoichiometric compound, AlGaAs represents Al x1 Ga (1-x1) As, where 0 < x1 < 1, AlInP represents Al x2 In (1-x2) P, where 0 < x2 < 1, AlGaInP represents (Al y1 Ga (1-y1) ) 1-x3 In x3 P, where 0 < x3 < 1 and 0 < y1 < 1, AlGaInAs represents (Al y2 Ga (1-y2) ) 1-x4 In x4 As, where 0 < x4 < 1 and 0 < y2 < 1, AlGaN represents Al x5 Ga (1-x5) N, where 0 < x5 < 1, AlAsSb represents AlAs x6 Sb (1-x6) and 0 < x6 < 1, InGaP represents In x7 Ga 1-x7 P, where 0 < x7 < 1, InGaAsP represents In x8 Ga 1-x8 As 1-y3 P y3 where 0 < x8 < 1 and 0 < y3 < 1, InGaAsN represents In x9 Ga 1-x9 As 1-y4 N y4 where 0 < x9 < 1 and 0 < y4 < 1, AlGaAsP represents Al x10 Ga 1-x10 As 1-y5 P y5 where 0 < x10 < 1 and 0 < y5 < 1, InGaAs represents In x11 Ga 1-x11 As, where 0 < x11 < 1.

[0011] For the sake of convenience in explanation, the present invention will be described below by taking a set of four (i.e., composed of four elements) light-emitting diodes as an example, but the present invention is not limited thereto. The present invention can also be applied to other types of semiconductor devices, for example, a set of two (composed of two elements), a set of three (composed of three elements) light-emitting diodes or other semiconductor devices. Also, the two electrodes of the semiconductor device may be located on both sides of the semiconductor device respectively, or may be located on the same side of the semiconductor device. Here, the “set of four” (i.e., quaternary), “set of three” (i.e., ternary), and “set of two” (i.e., binary) respectively mean that the semiconductor stack layer of the light-emitting diode contains compounds composed of four, three, and two types of elements.

[0012] Hereinafter, a semiconductor device will be described based on some embodiments of the present invention, which is particularly applicable to a light-emitting device that emits near-infrared rays (NIR). In this embodiment, when a semiconductor device is provided and the semiconductor device is a light-emitting diode, a contact layer and / or a window layer close to the light-emitting surface use a material that does not absorb light (hereinafter referred to as a light non-absorbing material). Since the absorption wavelength of this light non-absorbing material is different from the emission wavelength of the active structure, it does not absorb the light emitted by the active structure and can improve the luminous efficiency. Also, since there is no need to remove the contact layer in an additional step in the subsequent process, the manufacturing steps can be reduced. Also, by performing a roughening process on the contact layer and / or the window layer, the luminance of the semiconductor device can be further improved. In some embodiments, the material of the active structure may include a set of four compound semiconductors, for example, AlInGaAs or InGaAsP, and the light non-absorbing material may include a set of two compound semiconductors, for example, GaAs or InP. In another embodiment, the active structure is AlInGaAs or substantially composed of AlInGaAs, the light non-absorbing material is substantially composed of GaAs or InP, and in other embodiments, the active structure is InGaAsP or substantially composed of InGaAsP, and the light non-absorbing material is substantially composed of GaAs or InP.

[0013] FIG. 1 is a cross-sectional view of a semiconductor device 100 in an embodiment. The semiconductor device 100 includes a base 102 and a semiconductor stack layer S located on the base 102. The semiconductor stack layer S includes a first contact layer 104, a first window layer 106, a buffer layer 108, a first-type semiconductor structure 110, an active structure 112, a second-type semiconductor structure 114, a second window layer 116, and a second contact layer 118.

[0014] In some embodiments, the semiconductor stack layer S can be grown or connected to the base 102 by an epitaxial method, i.e., the base 102 can be a growth substrate or a non-growth substrate. The base 102 is used to support the semiconductor stack layer S and other layers or structures thereon, and the base 102 can be transparent, translucent, or opaque to the light emitted by the active structure 112, and can also be a conductor, a semiconductor, or an insulator. In this embodiment, since the semiconductor element 100 is in a vertical form, the base 102 is a conductive material and includes a metal material, a metal alloy material, a metal oxide material, a semiconductor material, or a carbon-containing material. The metal material includes Cu, Al, Cr, Sn, Au, Ni, Ti, Pt, Pb, Zn, Cd, Sb, or Co, the metal alloy material is an alloy including these metal materials, the semiconductor material may include, but is not limited to, group IV semiconductors or group III-V semiconductors, such as Si, Ge, SiC, GaN, GaP, GaAs, AsGaP, InP, etc., the metal oxide material may include, but is not limited to, ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, IWO, ZnO, or IZO, and the carbon-containing material may include, but is not limited to, DLC (Diamond-Like carbon) or Graphene. In another embodiment, when the semiconductor element 100 is in a non-vertical form, the base 102 may include an insulating material, such as sapphire, glass, insulating nitride (e.g., SiN), insulating oxide (e.g., SiO2), etc. In this embodiment, the semiconductor element is a near-infrared light-emitting element, and the material of the base 102 includes InP or GaAs. For example, the material of the base 102 is InP or GaAs, or consists essentially of InP or GaAs.

[0015] In some embodiments, the formation of the second contact layer 118, the second window layer 116, the second-type semiconductor structure 114, the active structure 112, the first-type semiconductor structure 110, the buffer layer 108, the first window layer 106, and the first contact layer 104 can be sequentially grown on the base 102 or a growth substrate (not shown) by an epitaxial method, and the epitaxial method includes MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), similar methods, or combinations thereof.

[0016] In some embodiments, the materials of the first contact layer 104, the first window layer 106, the first-type semiconductor structure 110, the active structure 112, the second-type semiconductor structure 114, the second window layer 116, and the second contact layer 118 may each independently include a Group 3, 5 (also referred to as "III-V") compound semiconductor material, for example, AlGaInAs, AlGaAs, AlInAs, GaInAs, AlAs, GaAs, InAs, AlGaInP, AlGaP, AlInP, GaInP, AlP, GaP, InP, AlInGaN, AlInN, AlGaN, InGaN, AlAsSb, AlSb, AsSb, InGaAsP, InAsP, GaAsP, InGaAsN, InAsN, GaAsN, InN, AlGaAsP, AlAsP, or a similar Group 3, 5 compound semiconductor material.

[0017] As shown in FIG. 1, the active structure 112 is located between a first-type semiconductor structure 110 and a second-type semiconductor structure 114. When the semiconductor device 100 according to the present invention is a light-emitting device, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 are, for example, a cladding layer and / or a confinement layer, respectively, providing electrons and holes, and having an energy gap larger than that of the active layer, thereby improving the probability that electrons and holes combine and emit light in the active structure 112. The active structure 112 can emit radiation. For example, for a near-infrared light-emitting device, the radiation has a peak wavelength between 1000 nm and 2000 nm, preferably a peak wavelength between 1200 nm and 1800 nm, for example, 1250 nm to 1650 nm.

[0018] The semiconductor device 100 may include a SH (single heterostructure), DH (double heterostructure), DDH (double-side double heterostructure), or MQW (multiple quantum wells) structure. In some embodiments, the active structure 112 is an MQW structure, which includes a plurality of barrier layers and a plurality of well layers stacked alternately, and the barrier layer has an energy gap higher than that of the well layer. In some embodiments, the barrier layer and the well layer may each independently include a set of four materials or a set of three materials. In some embodiments, the active structure 112 may include Al, Ga, In, P, or As, and preferably is a set of four compounds without N, such as AlGaInAs, InGaAsP.

[0019] As shown in FIG. 1, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 are respectively located on both sides of the active structure 112. The first-type semiconductor structure 110 and the second-type semiconductor structure 114 may be single-layer or multi-layer, and have an energy gap larger than that of the active structure 112, confine carriers in the active structure 112, and effectively prevent carrier overflow in the active structure 112, and / or are respectively used to provide electrons and holes to the active structure 112. In some embodiments, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 may include Group 3 and 5 semiconductor materials. Since the preferred examples are as described above, the detailed description thereof is omitted here. In some embodiments, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 preferably include Al, Ga, As, P, In, or a combination thereof, and are preferably a ternary or binary compound that does not contain N, for example, InAlAs or InP.

[0020] In some embodiments, the first-type semiconductor structure 110 has a first conductivity type, and the second-type semiconductor structure 114 has a second conductivity type, where the first conductivity type is different from the second conductivity type. For example, the first conductivity type and the second conductivity type may be P-type and N-type, respectively, or may be N-type and P-type, respectively. The first-type semiconductor structure 110 and the second-type semiconductor structure 114 have different conductivity types by adding different dopants, for example, the first-type semiconductor structure 110 has a first dopant, and the second-type semiconductor structure 114 has a second dopant different from the first dopant of the first-type semiconductor structure 110. Specifically, these dopants may include Mg, Zn, Si, Te, etc. In some embodiments, doping of the first-type semiconductor structure 110 and the second-type semiconductor structure 114 can be performed by performing in-situ doping during the epitaxial growth period and / or by performing an implanting process using a P-type or N-type dopant after the epitaxial growth. For example, in this embodiment, the dopant of the first-type semiconductor structure 110 is Zn, and the dopant of the second-type semiconductor structure 114 is Si.

[0021] In one embodiment, the doping concentration of the dopant in the first-type semiconductor structure 110 and the doping concentration of the dopant in the second-type semiconductor structure 114 are each independently in the range of 1×10 16 / cm 3 ~5×10 18 / cm 3 In one embodiment, the doping concentration of the dopant in the first-type semiconductor structure 110 may be greater than the doping concentration of the dopant in the second-type semiconductor structure 114. For example, the doping concentration of the dopant in the first-type semiconductor structure 110 is 1×10 17 / cm 3 ~1×10 18 / cm 3 and preferably 3×10 17 / cm 3 ~8×10 17 / cm 3and the doping concentration of the dopant in the second-type semiconductor structure 114 is 3×10 16 / cm 3 ~1×10 18 / cm 3 and preferably 5×10 16 / cm 3 ~9×10 17 / cm 3 In some embodiments, the thickness of the first-type semiconductor structure 110 and the thickness of the second-type semiconductor structure 114 may each independently be in the range of 100 nm to 1200 nm, for example, both in the range of 200 nm to 1000 nm.

[0022] The description of the embodiments of the present invention takes as an example the case where the first contact layer 104 and the first window layer 106 contain the same light non-absorbing material, and the light non-absorbing material is GaAs, and the first-type semiconductor structure 110, the active structure 112, the second-type semiconductor structure 114, the second window layer 116, and the second contact layer 118 may each independently contain any suitable material, but the present invention is not limited thereto. In another embodiment, the first contact layer 104 and the first window layer 106 may each independently contain different light non-absorbing materials, for example, GaAs and InP, respectively. Also, the second contact layer 118 and the second window layer 116 may contain the same or different light non-absorbing materials, and the first contact layer 104 and the first window layer 106 may each independently contain any suitable material. Alternatively, in other embodiments, the first contact layer 104, the first window layer 106, the second contact layer 118, and the second window layer 116 contain light non-absorbing materials, and these light non-absorbing materials may be the same or different.

[0023] As shown in FIG. 1, the semiconductor device 100 includes a first contact layer 104 located above the first-type semiconductor structure 110, with the first-type semiconductor structure 110 positioned between the first contact layer 104 and the base 102. Specifically, the first-type semiconductor structure 110 includes a first side S1 and a second side S2 opposite to the first side S1, and the second side S2 is farther from the base 102 than the first side S1. The active structure 112 is disposed on the first side S1, and the first contact layer 104 is disposed on the second side S2. The energy gap of the first contact layer 104 is larger than the energy gaps of the active structure 112 and the first-type semiconductor structure 110, thereby avoiding a reduction in the efficiency of the semiconductor device 100 due to the first contact layer 104 absorbing light. In one embodiment, the difference between the energy gap of the first contact layer 104 and the energy gap of the active structure 112 is 0.3 eV to 0.8 eV, preferably 0.4 eV to 0.7 eV.

[0024] Also, the first-type semiconductor structure 110 has a first lattice constant, and the first contact layer 104 has a second lattice constant, where the first lattice constant is different from the second lattice constant, that is, the first-type semiconductor structure 110 and the first contact layer 104 have a lattice mismatch. When the first-type semiconductor structure 11 is a single layer, the lattice constant of the single layer is defined as the first lattice constant. When the first-type semiconductor structure 11 is composed of multiple layers, the average value (arithmetic mean) of the lattice constants of these multiple layers is defined as the first lattice constant. In some embodiments, the difference between the second lattice constant and the first lattice constant is at least 0.5%, for example, in the range of 1% to 6%, preferably 2% to 5%, and more preferably 3% to 4.5%. The difference D1 between the above-mentioned second lattice constant and the first lattice constant is calculated by the following formula (1), where d1 represents the first lattice constant and d2 represents the second lattice constant.

[0025] Difference D1 = ((d2 - d1) / d2)×100%... Formula (1) In this embodiment, the material of the first-type semiconductor structure 110 is In 0.53 Al 0.47It is As or substantially In 0.53 Al 0.47 It consists of As. The first lattice constant is 5.848. The material of the first contact layer 104 is GaAs or substantially consists of GaAs. The second lattice constant is 5.653. The difference between the second lattice constant and the first lattice constant is 3.45%. Also, the lattice constant may be obtained by any appropriate method. For example, the lattice constants of the first semiconductor structure 110 and the first contact layer 104 may be analyzed using a diffraction pattern by TEM (transmission electron microscopy), or the lattice constant information may be obtained by XRD (X-ray diffraction) at a temperature of 300 K. In the content of the present invention, the "lattice constant" is defined as the lattice constant a0 of an unstrained layer.

[0026] In one embodiment, the thickness of the first contact layer 104 may be in the range of 5 nm to 100 nm, for example, 50 nm. Also, the surface of the first contact layer 104 may selectively have a roughened structure, whereby the probability of total reflection of the light emitted by the active structure 112 in the semiconductor stack layer S is reduced, the light extraction efficiency is improved, and the luminance of the semiconductor element 100 can be further improved.

[0027] As shown in FIG. 1, the first window layer 106 is provided between the first contact layer 104 and the first-type semiconductor structure 110. The first window layer 106 is used to increase the light extraction efficiency of the semiconductor device 100 and / or to uniformly disperse current in the semiconductor stack layer S. In one embodiment, the first window layer 106 and the first contact layer 104 are of the same material, i.e., the first window layer 106 and the first contact layer 104 have the same lattice constant (both having a second lattice constant), and the difference from the first lattice constant of the first-type semiconductor structure 110 is at least 0.5%. For example, the materials of the first contact layer 104 and the first window layer 106 are both GaAs or substantially composed of GaAs. In another embodiment, the first contact layer 104 and the first window layer 106 have different materials, and the first window layer 106 may have a lattice constant with a difference from the first lattice constant less than 0.5%. In other embodiments, the material of the first window layer 106 may be the same as the material of the base 102. For example, the first contact layer 104 is GaAs or substantially composed of GaAs, and the first window layer 106 and the base 102 are both InP or substantially composed of InP.

[0028] Also, the conductivity type of the first contact layer 104 and the first window layer 106 may be the same as the conductivity type of the first-type semiconductor structure 110. For example, the conductivity types of the first contact layer 104, the first window layer 106, and the first-type semiconductor structure 110 are all P-type, and the first contact layer 104, the first window layer 106, and the first-type semiconductor structure 110 all have the same dopant, such as Zn. The doping of the first contact layer 104 and the first window layer 106 is performed by in-situ doping during the epitaxial growth period and / or by implanting dopants after epitaxial growth. The doping concentration of the dopant in the first contact layer 104 is greater than the doping concentration of the first-type semiconductor structure 110 and 1×10 18 / cm 3Larger than, thereby enabling a relatively low resistance value to be provided between the first contact layer 104 and the electrode structure thereon. Preferably, the doping concentration of the dopant in the first contact layer 104 is, for example, 2×10 18 / cm 3 ~5×10 19 / cm 3 within the range of. The first window layer 106 has a thickness greater than that of the first-type semiconductor structure 110, and / or a relatively low doping concentration, thereby enabling the light extraction efficiency to be increased or the lateral current dispersion ability to be improved.

[0029] The doping concentration of the dopant in the first contact layer 104 is different from the doping concentration of the dopant in the first window layer 106. In some embodiments, the doping concentration of the dopant in the first window layer 106 is smaller than the doping concentration of the dopant in the first contact layer 104. In one embodiment, the doping concentration of the dopant in the first window layer 106 may be within the range of 2×10 16 / cm 3 ~1×10 19 / cm 3 , for example, it may be 4×10 16 / cm 3 ~8×10 18 / cm 3 .

[0030] In some embodiments, the thickness of the first window layer 106 may be greater than the thickness of the first contact layer 104. In one embodiment, the thickness of the first window layer 106 may be within the range of 300 nm to 10,000 nm, preferably within the range of 500 nm to 8000 nm. In this embodiment, for example, it is 7000 nm.

[0031] As shown in FIG. 1, the buffer layer 108 is disposed between the first window layer 106 and the first-type semiconductor structure 110 to reduce the energy level difference between the first-type semiconductor structure 110 and the first window layer 106. Specifically, there is a valence band energy gap (Ev) difference between the valence band energy level of the first window layer 106 and the valence band energy level of the first-type semiconductor structure 110, and there is a conduction band energy gap (Ec) difference between the conduction band energy level of the first window layer 106 and the conduction band energy level of the first-type semiconductor structure 110. When the valence band energy gap difference and / or the conduction band energy gap difference is too large, it is necessary to provide an additional voltage difference to transmit carriers, which may cause a high forward voltage (Vf) difference in the semiconductor device, resulting in problems such as a decrease in the saturation current or premature failure of the semiconductor device. Therefore, by disposing the buffer layer 108 between the first window layer 106 and the first-type semiconductor structure 110, such problems can be avoided. The buffer layer 108 has a valence band energy level between the valence band energy level of the first-type semiconductor structure 110 and the valence band energy level of the first window layer 106, and the buffer layer 108 has a conduction band energy level between the conduction band energy level of the first-type semiconductor structure 110 and the conduction band energy level of the first contact layer 104, thereby reducing the energy level difference between the first-type semiconductor structure 110 and the first window layer 106 and improving the reliability of the semiconductor device 100. In another embodiment, the first window layer 106 may be selectively disposed. When the semiconductor device 100 does not include the first window layer 106, the buffer layer 108 is disposed between the first contact layer 104 and the first-type semiconductor structure 110 and can be in direct contact with the first contact layer 104 and the first-type semiconductor structure 110. As described above, the buffer layer 108 can reduce the energy level difference between the first contact layer 104 and the first-type semiconductor structure 110.

[0032] In some embodiments, the material of the buffer layer 108 may include a quaternary semiconductor compound, such as AlGaInAs or InGaAsP. When the first contact layer 104 is GaAs or substantially consists of GaAs, and the first-type semiconductor structure 110 is InAlAs or substantially consists of InAlAs, the material of the buffer layer 108 is (Al x Ga 1-x ) 0.47 In 0.53 As (0 < x < 1), or substantially consists of (Al x Ga 1-x ) 0.47 In 0.53 As (0 < x < 1). In another embodiment, when the first contact layer 104 is GaAs or substantially consists of GaAs, and the first-type semiconductor structure 110 is InP or substantially consists of InP, the material of the buffer layer 108 is InGaAsP or substantially consists of InGaAsP.

[0033] When the buffer layer 108 is located between the first-type semiconductor structure 110 and the first window layer 106 (or the first contact layer 104), the buffer layer 108 has the same conductivity type as the first-type semiconductor structure 110 and the first window layer 106 (or the first contact layer 104), and the three may include the same dopant. In one embodiment, the doping concentration of the dopant in the buffer layer 108 may be in the range of 5×10 16 / cm 3 ~2×10 18 / cm 3 , for example, 5×10 17 / cm 3 ~1×10 18 / cm 3 . Also, the thickness of the buffer layer 108 may be in the range of 10 nm to 200 nm, for example, 100 nm.

[0034] The buffer layer 108 is optional. In some embodiments, the buffer layer 108 may not be provided, that is, the first window layer 106 is in direct contact with the first type semiconductor structure 110. Also, the position and quantity of the buffer layer 108 may be adjusted according to the characteristics of the actual product. In some other embodiments, two or more buffer layers may be provided, and these buffer layers may have the same or different materials and / or doping concentrations. For example, in some embodiments, an additional buffer layer (not shown) may be provided between the second type semiconductor structure 114 and the second window layer 116.

[0035] As shown in FIG. 1, the second window layer 116 is provided between the second type semiconductor structure 114 and the base 102, and the second window layer 116 is away from the second side S2 of the first type semiconductor structure 110. In some embodiments, the material of the second window layer 116 may include Group 3 and 5 semiconductor materials. In some embodiments, the material of the second window layer 116 may include a transparent conductive material. For example, the material of the second window layer 116 may include, but is not limited to, a metal oxide material or a semiconductor material. The metal oxide may include, but is not limited to, ITO, InO (indium oxide), SnO (tin oxide), CTO (chromium titanium oxide), ATO (antimony tin oxide), AZO (aluminum-doped zinc oxide), ZTO (zinc tin oxide), GZO (gallium doped zinc oxide), IWO (indium tungsten oxide), ZnO, MgO (magnesium oxide), or IZO. The semiconductor material may include, but is not limited to, InP, GaAs, AlGaAs, GaP, etc. The material of the first window layer 106 may refer to the material of the second window layer 116. In one embodiment, the material of the second window layer 116 is the same as the material of the first window layer 106. For example, all are InP or substantially consist of InP. In other embodiments, the material of the second window layer 116 is different from the material of the first window layer 106, and each is InP and GaAs, or each substantially consists of InP and GaAs.

[0036] The second window layer 116 has a third lattice constant that is different from the second lattice constant of the first contact layer 104. In some embodiments, the difference between the third lattice constant and the second lattice constant is at least 0.5%, for example, in the range of 1% to 6%, preferably 2% to 5%, and more preferably 3% to 4.5%. As described above, the third lattice constant of the second window layer 116 can be analyzed in any suitable manner. In some embodiments, the difference between the third lattice constant and the first lattice constant is 0.5% or less. In another embodiment, the difference between the third lattice constant and the first lattice constant is less than 0.2% and greater than 0. The difference D2 between the above-mentioned third lattice constant and the first lattice constant is calculated by the following formula (2), where d1 represents the first lattice constant and d3 represents the third lattice constant.

[0037] Difference D2 = ((d3 - d1) / d3) × 100% … Formula (2) In one embodiment, the doping concentration of the dopant in the second window layer 116 may be greater than 1×10 16 / cm 3 For example, it may be in the range of 2×10 16 / cm 3 ~1×10 18 / cm 3 In some embodiments, the thickness of the second window layer 116 may be smaller than the thickness of the first window layer 106. In another embodiment, the thickness of the second window layer 116 is greater than the thickness of the second-type semiconductor structure 114, or the second window layer 116 has a relatively low doping concentration compared to the second-type semiconductor structure 114, thereby increasing the light extraction rate or improving the lateral current dispersion ability. In some embodiments, the thickness of the second window layer 116 may be in the range of 100 nm to 1000 nm, for example, 500 nm.

[0038] As shown in FIG. 1, a second contact layer 118 may be selectively disposed between the second window layer 116 and the base 102, and the second contact layer 118 is separated from the second side S2 of the first-type semiconductor structure 110. The material of the second contact layer 118 may include group 3 and 5 semiconductor materials. Since suitable examples are as described above, the detailed description thereof is omitted here. The conductivity types of the second contact layer 118 and the second window layer 116 are the same as the conductivity type of the second-type semiconductor structure 114. For example, the conductivity types of the second contact layer 118, the second window layer 116, and the second-type semiconductor structure 114 are all N-type, and the second contact layer 118, the second window layer 116, and the second-type semiconductor structure 114 all contain the same dopant, for example, Si. The doping concentration of the dopant in the second contact layer 118 is different from the doping concentration of the dopant in the second window layer 116. In some embodiments, the doping concentration of the dopant in the second contact layer 118 is greater than the doping concentration of the dopant in the second window layer 116. In one embodiment, the doping concentration of the dopant in the second contact layer 118 may be greater than 5×10 17 / cm 3 , whereby the resistance value between the second contact layer 118 and the base 102 is relatively low. For example, the doping concentration of the dopant in the second contact layer 118 is 1×10 18 / cm 3 ~1×10 20 / cm 3 in the range of.

[0039] The semiconductor device 100 includes a first electrode 122 and a second electrode 120 located on opposite sides of the semiconductor device 100, respectively. For example, in this embodiment, the first contact layer 104 is located between the first-type semiconductor structure 110 and the first electrode 122, and the base 102 is located between the second electrode 120 and the second-type semiconductor structure 114, thereby forming the vertical semiconductor device 100. It should be noted that the present invention is not limited thereto. In some other embodiments, the first electrode 122 and the second electrode 120 may be located on the same side of the base 102 to form a horizontal semiconductor device. In one embodiment, the first contact layer 104 is formed between the first-type semiconductor structure 110 and the first electrode 122 and corresponds only to the position of the first electrode 122.

[0040] Both the first electrode 122 and the second electrode 120 are all connected to an external power source and used to introduce current into the semiconductor device 100. In some embodiments, the material of the first electrode 122 and the material of the second electrode 120 may each independently include a metal material, an alloy material, a metal oxide material, or a carbon-containing material. For example, the metal material may include, but is not limited to, Al, Cr, Cu, Sn, Au, Ni, Ti, Pt, Pb, Zn, Cd, Sb, or Co. The alloy material includes alloys combined from these metals. The metal oxide material may include, but is not limited to, ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, IWO, ZnO, or IZO. The carbon-containing material may include, but is not limited to, DLC or graphene.

[0041] FIG. 2 is a cross-sectional view of the semiconductor device 200 in one embodiment, and FIG. 3 is a top view of the semiconductor device 200 in one embodiment. FIG. 2 corresponds to a cross-sectional view taken along line AA' of FIG. 3. In FIG. 2, the same elements as those in FIG. 1 are denoted by the same reference numerals, and since the materials and characteristics of these elements are the same as those described above, the detailed description thereof is omitted here. The semiconductor device 200 of this embodiment has undergone one chip connection process compared to the semiconductor device 100 shown in FIG. 1, so the order of the semiconductor stack layer S is reversed from that in FIG. 1, and the first-type semiconductor structure 110 is located between the base 102 and the active structure 112. Further, after the connection process, since the second contact layer 118 and the second window layer 116 are located in the light propagation path emitted by the active structure 112, the second contact layer 118 and the second window layer 116 can use a light non-absorbing material to make the energy gaps of the second contact layer 118 and the second window layer 116 larger than the energy gap of the active structure 112, respectively. For example, InP is used as the light non-absorbing material. The chip connection process will be described later.

[0042] Compared with the semiconductor device 100 in FIG. 1, in addition to the base 102, the semiconductor stack layer S, the first electrode 122, and the second electrode 120, the semiconductor device 200 further includes a reflective structure 130, a conductive structure 140, and a connection layer 124 located between the base 102 and the semiconductor stack layer S. Also, in this embodiment, the first contact layer 104 may be selectively omitted, and the characteristics such as the lattice constant, energy gap difference, doping concentration, and thickness of the second contact layer 118, the second window layer 116, and the second-type semiconductor structure 114 may also refer to the relationships of the first contact layer 104, the first window layer 106, and the first-type semiconductor structure 110 shown in FIG. 1, respectively. In this embodiment, as shown in FIGS. 2 to 3, the second electrode 122 includes an electrode pad 1221 located at a substantially central position on the upper surface of the semiconductor stack layer S, and a plurality of extended electrodes 1222 connected to the electrode pad 1221 and extending in a direction away from the electrode pad 1221. The extended electrodes 1222 are used to uniformly diffuse current into the semiconductor stack layer S.

[0043] Specifically, the semiconductor element 200 includes a connection layer 124 positioned between the reflective structure 130 and the base 102, whereby the reflective structure 130 and the base 102 can be connected. In some embodiments, the connection layer 124 may include a plurality of sub-layers (not shown), and the material of the connection layer 124 may include a conductive material, for example, a metal oxide material, a semiconductor material, a metal material, a metal alloy material, or a carbon-containing material. By way of example, the metal oxide may include, but is not limited to, ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, ZnO, ICO (indium cerium oxide), IWO, ITiO (indium titanium oxide), IZO, IGO (indium gallium oxide), or GAZO (gallium and aluminum codoped zinc oxide). The semiconductor material may include, but is not limited to, GaP. The metal material may include, but is not limited to, Cu, Al, Sn, Au, Ag, Pb, Ti, Ni, Pt, or W. The metal alloy material is an alloy containing these metal materials. The carbon-containing material may include, but is not limited to, Graphene.

[0044] The reflective structure 130 is disposed between the base 102 and the semiconductor stack layer S, and is used to reflect the light emitted by the active structure 112 to increase the light extraction efficiency (LEE) of the semiconductor element 200. In some embodiments, the material of the reflective structure 130 may include, but is not limited to, a metal material or a metal alloy material. The metal material may include, but is not limited to, Cu, Al, Sn, Au, Ag, Pt, or W, and the metal alloy material is an alloy containing these metal materials.

[0045] In some embodiments, as shown in FIG. 2, the reflective structure 130 may include a third contact layer 132, a barrier layer 134 positioned on the third contact layer 132, a reflective connection (adhesive) layer 136 positioned on the barrier layer 134, and a reflective layer 138 positioned on the reflective connection layer 136. The third contact layer 132 can form a low-resistance contact with the underlying connection layer 124. The barrier layer 134 can maintain the reflectivity of the reflective layer 138 by preventing the destruction of the structure of the reflective layer 138 due to the diffusion of the material of the connection layer 124 into the reflective layer 138 during the process. The reflective connection layer 136 is used to connect the reflective layer 138 and the barrier layer 134. The reflective layer 138 can reflect the light emitted by the active structure 112. It should be noted that the present invention is not limited thereto. For example, the reflective structure 130 may include more structures, and the materials of the third contact layer 132, the barrier layer 134, the reflective connection layer 136, and the reflective layer 138 may each independently include the same or different metal materials or metal alloy materials. The metal material may include, but is not limited to, Cu, Al, Sn, Au, Ag, Pb, Ti, Ni, Pt, or W, and the metal alloy material is an alloy containing these metal materials.

[0046] The conductive structure 140 is positioned between the reflective structure 130 and the first contact layer 104. The conductive structure 140 is transparent to the light emitted by the active structure 112 and is used to improve the conduction and diffusion of current between the first contact layer 104 and the reflective structure 130. In some embodiments, the conductive structure 140 and the reflective structure 130 can jointly form an ODR (Omni-Directional Reflector) to further increase the light extraction efficiency (LEE) of the semiconductor device 200. In some embodiments, the material of the conductive structure 140 may include a metal oxide material, a carbon-containing material, or a combination of these materials. The metal oxide material may include, but is not limited to, ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, ZnO, ICO, IWO, ITiO, IZO, IGO, or GAZO. The carbon-containing material may include, but is not limited to, graphene.

[0047] In some embodiments, as shown in FIG. 2, the conductive structure 140 includes a first conductive layer 142 located above the reflective structure 130 and a second conductive layer 144 located between the semiconductor stack layer S and the first conductive layer 142. In some embodiments, the material of the first conductive layer 142 may be different from the material of the second conductive layer 144. Specifically, at least one element of the material of the first conductive layer 142 is different from that of the second conductive layer 144. For example, the material of the first conductive layer 142 is IZO, and the material of the second conductive layer 144 is ITO.

[0048] In some embodiments, as shown in FIG. 2, an insulating layer 146 is provided between the second conductive layer 144 and the first contact layer 104, and the insulating layer 146 is in direct contact with the second conductive layer 144. In some embodiments, the material of the insulating layer 146 may be selected such that the transmittance of the light emitted by the active structure 112 is greater than 90%. Also, the material of the insulating layer 146 may include an oxide insulating material or a non-oxide insulating material. For example, the oxide insulating material may include SiOx or a similar material, and the non-oxide insulating material may include SiNx, BCB (benzocyclobutene), COC (cyclo olefin copolymer), or a fluorocarbon polymer. In some other embodiments, the material of the insulating layer 146 may include a halide or a compound of Group IIA and Group VII, such as CaF2 (calcium fluoride) or MgF2 (magnesium fluoride). In one embodiment, the material of the insulating layer 146 has a refractive index less than 1.6.

[0049] In some embodiments, the insulating layer 146 includes a plurality of holes 141 penetrating the insulating layer 146, so that the conductive structure 140 can be in direct contact with the semiconductor stack layer S through these holes 141 for electrical connection.

[0050] In some embodiments, as shown in FIG. 2, a roughening process is performed on the top surface of the second contact layer 118 and / or the second window layer 116 to give it a roughened surface, thereby scattering the light emitted by the active structure 112 and improving the light extraction efficiency of the semiconductor device 200.

[0051] Figures 4A-4B are cross-sectional views of the steps in manufacturing a semiconductor device in one embodiment, for explaining the chip connection process. In this embodiment, the base 102 is a non-growing substrate. As shown in FIG. 4A, the semiconductor stack layer S is epitaxially grown on the growth substrate 101, and a sacrificial layer 103 may be selectively provided between the semiconductor stack layer S and the growth substrate 101. Also, by removing the sacrificial layer 103 in the subsequent process shown in FIG. 4B, the first contact layer 104, the first window layer 106, the buffer layer 108, the first-type semiconductor structure 110, the active structure 112, the second-type semiconductor structure 114, the second window layer 116, and the second contact layer 118 can be made to detach from the growth substrate 101. In some embodiments, a sacrificial layer 103 may be formed on the growth substrate 101 before forming the second contact layer 118. In some embodiments, the semiconductor device may not have a sacrificial layer 103 and the second contact layer 118 may be formed directly on the growth substrate 101. In some other embodiments, a buffer structure (not shown) may be further provided between the second contact layer 118 and the growth substrate 101 to reduce the lattice defects of the second contact layer 118 and the layers thereon and improve the epitaxial quality of the semiconductor stack layer S. In other embodiments, the semiconductor device does not have a sacrificial layer 103 but includes an etching stop layer (not shown) located between the growth substrate 101 and the second contact layer 118. Then, when the growth substrate 101 is etched and removed by etching, the etching stop layer has the function of protecting the semiconductor stack layer S, thereby avoiding damage to the semiconductor stack layer S during the etching process. For example, the material of the etching stop layer is InGaAs or InGaP, or consists essentially of InGaAs or InGaP.

[0052] Also, in some embodiments, the sacrificial layer 103 includes a material having an etching selectivity different from that of the material of the second contact layer 118, for example, AlAs (aluminum arsenide). In some embodiments, the removal of the sacrificial layer 103 may use an etching process, a dry etching process, a laser lift-off (LLO) process, or a combination thereof.

[0053] FIG. 4B is a cross-sectional view of a manufacturing stage of a semiconductor device in an embodiment. By a substrate transfer technique, a first contact layer 104, a first window layer 106, a buffer layer 108, a first-type semiconductor structure 110, an active structure 112, a second-type semiconductor structure 114, a second window layer 116, and a second contact layer 118 are bonded to a non-growth substrate (base 102) with an adhesive layer (not shown), and the adhesive layer is located between the first contact layer 104 and the non-growth substrate. Subsequently, by removing the sacrificial layer 103, the second contact layer 118 is detached from the growth substrate 101, but the present invention is not limited thereto. By inverting top to bottom, the arrangement of the first contact layer 104, the first window layer 106, the buffer layer 108, the first-type semiconductor structure 110, the active structure 112, the second-type semiconductor structure 114, the second window layer 116, and the second contact layer 118 on the non-growth substrate is opposite to the arrangement on the growth substrate 101 in FIG. 4A. Specifically, as shown in FIG. 4A, before inverting top to bottom, the active structure 112 is located between the first-type semiconductor structure 110 and the growth substrate 101, and as shown in FIG. 4B, after inverting top to bottom, the first-type semiconductor structure 110 is located between the non-growth substrate and the active structure 112.

[0054] Further, the growth substrate 101 may include, but is not limited to, semiconductor materials such as SiC (silicon carbide), GaAs (gallium arsenide), GaP (gallium phosphide), GaAsP (gallium arsenide phosphide), ZnSe (zinc selenide), InP (indium phosphide), etc. In some embodiments, the material of the growth substrate 101 may include, but is not limited to, sapphire. The material of the non-growth substrate and the material of the growth substrate 101 may be the same or different. In many embodiments, the non-growth substrate has different properties from the growth substrate 101. For example, compared with the growth substrate 101, the non-growth substrate has higher thermal conductivity, electrical conductivity, transparency, or mechanical strength.

[0055] FIG. 5 is a diagram showing the relationship between the concentration and depth of elements in a partial range of a semiconductor device and the doping concentration and depth of a dopant in one embodiment. Specifically, FIG. 5 is a mass spectrometry diagram obtained by secondary ion mass spectrometer (SIMS) of a partial structure in the semiconductor device 100 of FIG. 1. Note that the present invention is not limited thereto, and a diagram showing the relationship between the concentration and depth of elements in a partial range of the semiconductor device 100 may be obtained using other techniques. Here, the aforementioned depth refers to the depth in the direction from the side away from the base 102 to the side close to the base 102, that is, the closer to the base 102, the deeper the depth.

[0056] As shown in FIG. 5, according to the depth and order of each layer in the semiconductor device 100, the mass spectrometry diagram can generally be divided into seven regions A-G. Region A substantially corresponds to the position of the first contact layer 104, region B substantially corresponds to the position of the first window layer 106, region C substantially corresponds to the position of the buffer layer 108, region D substantially corresponds to the position of the first-type semiconductor structure 110, region E substantially corresponds to the position of the active structure 112, region F substantially corresponds to the position of the second-type semiconductor structure 114, and region G substantially corresponds to the position of the second window layer 116.

[0057] As shown in FIG. 5, the mass spectrometry diagram includes a first dopant 302, a second dopant 304, a first element 306, a second element 308, and a third element 310. The first contact layer 104, the first window layer 106, the buffer layer 108, and the first-type semiconductor structure 110 have the first dopant 302, and the first dopant 302 can make the conduction type of these layers P-type. The first dopant is Zn. The second-type semiconductor structure 114 and the second window layer 116 have the second dopant 304, and the second dopant 304 can make the conduction type of these layers N-type. The second dopant is Si. The first element, the second element, and the third element are elements that constitute the host of each layer, and may be group 3 elements or group 5 elements. In FIG. 5, the first element is indium, the second element is aluminum, and the third element is gallium. All are group 3 elements. The atomic weight of the first element is greater than that of the third element, and the atomic weight of the second element is smaller than that of the third element. The concentrations of the first dopant 302 and the second dopant 304 are shown on the left vertical axis, and the contents of the first element 306, the second element 308, and the third element 310 are shown on the right vertical axis. The content of the element shown on the right vertical axis indicates the relative relationship of the content of a single element in each layer.

[0058] In region A, the first dopant 302 (Zn) has the highest concentration, and the concentration is 1×10 18 / cm 3Larger than, the concentration of the first dopant 302 decreases with the increase of depth. Specifically, the Zn dopant in the A region has the first doping concentration, the Zn dopant in the C region has the second doping concentration, and the second doping concentration is smaller than the first doping concentration. Also, the Zn dopant in the E region has the third doping concentration, and the second doping concentration is between the first doping concentration and the third doping concentration. The Zn dopant in the B region has the fourth doping concentration, and the fourth doping concentration is between the first doping concentration and the second doping concentration. In some embodiments, the ratio of the first doping concentration to the second doping concentration (first doping concentration / second doping concentration) is 10 to 100.

[0059] As shown in FIG. 5, the second dopant 304 (Si) in the G region has the highest doping concentration, and the concentration is about 1×10 18 / cm 3 . Specifically, the Si dopant in the G region has the fifth doping concentration, the Si dopant in the F region has the sixth doping concentration, and the fifth doping concentration is larger than the sixth doping concentration. In some embodiments, the ratio of the fifth doping concentration to the sixth doping concentration is about 2 to about 100.

[0060] As shown in FIG. 5, the first element 306 (In) in the G region has the largest content, and the content of the first element 306 increases with the increase of depth. Specifically, since the C region, the D region, the E region, and the F region contain substantially the same content of In 306, and the ratios of the In contents in the C region, the D region, the E region, and the F region to the In content in the A region are all larger than 1000, the A region can be regarded as not containing In. Here, "not containing" refers to "unintentionally added".

[0061] As shown in Fig. 5, the content of the second element 308 (Al) in the D region and the F region is greater than the content of the second element 308 in the E region. The D region and the F region contain substantially the same content of Al 308, and the ratios of the Al content in the D region and the F region respectively to the Al content in the A region are all greater than 1000, so the A region can be regarded as not containing Al. Similarly, since the ratios of the Al content in the D region and the F region respectively to the Al content in the G region are all greater than 1000, the G region can also be regarded as not containing Al.

[0062] The third element 310 (Ga) in the A region and the B region has the highest content, and the Ga content in the E region is less than the Ga content in the A region and the B region. Compared with the Ga content in the A region and the B region, the Ga content in the D region, the F region, and the G region is extremely small. Specifically, since the ratios of the Ga content in the A region to the Ga content in the D region, the F region, and the G region are all greater than 1000, the D region, the F region, and the G region can be regarded as not containing Ga.

[0063] FIG. 6 is a cross-sectional view of a conductor element 300 in another embodiment. For convenience, the same or similar structures are denoted by the same reference numerals. Since the formation method and materials of these structures are the same as those described above, the detailed description thereof is omitted here. In this embodiment, compared with the semiconductor element 100, the semiconductor element 300 does not include a second-type semiconductor structure 114, a second contact layer 118, and a buffer layer 108. Further, the semiconductor element 300 has a double heterostructure (DH), the material of the active structure 112 is a four-component compound semiconductor, for example, InGaAsP, and the material of the first contact layer 104 is a two-component compound semiconductor, for example, GaAs. In one embodiment, the material of the first window layer 106 may be the same as the material of the second window layer 116 and different from the material of the first-type semiconductor structure 110. For example, the materials of both the first window layer 106 and the second window layer 116 are InP, or substantially consist of InP. In another embodiment, the first contact layer 104 and the first window layer 106 include the same material, for example, GaAs, and are different from the material of the second window layer 116, and the material of the second window layer is, for example, InP. Also, the doping concentration of the dopant in the second window layer 116 of the semiconductor element 300 may be less than 8×10 17 / cm 3 , for example, in the range of 1×10 16 / cm 3 ~5×10 17 / cm 3 .

[0064] FIG. 7 is a cross-sectional view of a semiconductor element 400 in another embodiment. For convenience, the same or similar structures are denoted by the same reference numerals. Since the formation method and materials of these structures are the same as those described above, the detailed description thereof is omitted here. In this embodiment, the first electrode 122 and the second electrode 120 are located on the same side of the base 102 to form a horizontal semiconductor element 400. In another embodiment, optionally, a connection layer 126 may be provided between the semiconductor stack layer S and the base 102. The material of the connection layer 126 may include an insulating material. For example, the insulating material may include, but is not limited to, SiO2, Al2O3, AlN, BCB, etc. In these embodiments, the above-described base 102 can be made to emit light from the base 102 side by using a material that is transparent to the light emitted by the active structure 112, and the semiconductor element can be connected to the circuit board with the first electrode 122 and the second electrode 120 facing downward in a flip-chip manner.

[0065] FIG. 8 is a package structure diagram of a semiconductor device in an embodiment. As shown in FIG. 8, the package structure 500 includes a semiconductor device 100, a package plate 51, a mounting body 53, connection lines 55, a contact structure 56, and a package material 58. The package plate 51 may include a ceramic or glass material. The package plate 51 has a plurality of through holes 52. By filling the through holes 52 with a conductive material, such as metal, etc., it can assist in conduction and / or heat dissipation. The mounting body 53 is located on one surface of the package plate 51b and includes a conductive material, such as metal. The contact structure 56 is located on the other surface of the package plate 51. In this embodiment, the contact structure 56 includes a contact pad 56a and a contact pad 56b, and the contact pad 56a and the contact pad 56b can be electrically connected to the mounting body 53 through the through holes 52. In one embodiment, the contact structure 56 may further include a heat dissipation pad (not shown), which is located, for example, between the contact pad 56a and the contact pad 56b. The semiconductor device 100 is located on the mounting body 53 and may be a semiconductor device described in any embodiment of the present invention. In this embodiment, the mounting body 53 includes a first portion 53a and a second portion 53b, and the semiconductor device 100 is electrically connected to the second portion 53b of the mounting body 53 by the connection lines 55. In another embodiment, the semiconductor device 100 is not installed on the mounting body 53, but is directly installed on the package plate 51 and can form an electrical connection with the contact structure 56.

[0066] The material of the connection line 55 may include a metal, for example, gold, silver, copper, aluminum, or an alloy containing at least any one of these elements. The package material 58 covers the semiconductor element 100 and has the effect of protecting the semiconductor element 100. Specifically, the package material 58 may include a resin material, for example, an epoxy resin, a silicone resin, etc. The package material 58 may further include a plurality of wavelength conversion particles (not shown) that convert the first light emitted by the semiconductor element 50 into second light. The wavelength of the second light is greater than the wavelength of the first light. In other embodiments, the semiconductor element 100 in the above-described package structure 500 may be the semiconductor element 200 or 300, or in some embodiments, the package structure 500 includes a plurality of semiconductor elements 100, 200, and / or 300, and these semiconductor elements 100, 200, and / or 300 may be connected in series, in parallel, or in series-parallel.

[0067] In some embodiments of the present invention, a semiconductor element is provided, and one or more contact layers and / or window layers in this semiconductor element use a material whose absorption wavelength is different from the emission wavelength of the active structure, thereby avoiding the light emitted by the active structure being absorbed by the contact layer and / or window layer, improving the light emission efficiency, and also omitting the step of removing the contact layer and / or window layer that affects the luminance. Furthermore, by performing a roughening process on the contact layer, the light emission efficiency can be further improved.

[0068] Also, in some embodiments of the present invention, by providing a buffer layer between the contact layer and the semiconductor structure in the semiconductor element, the difference in valence band energy level and / or conduction band energy level between the contact layer and the first-type semiconductor structure or the second-type semiconductor structure is alleviated, avoiding problems such as a decrease in the saturation current or early failure of the semiconductor element, and improving the reliability of the semiconductor element.

[0069] The semiconductor device according to the present invention can be applied to products in fields such as lighting, display, communication, detection, power supply systems, etc., for example, lighting fixtures, monitors, mobile phones, tablet computers, in-vehicle instrument panels, televisions, detectors, computers, wearable devices (such as wristwatches, bracelets, necklaces, etc.), traffic signal lights, outdoor displays, etc.

[0070] As described above, the preferred embodiments of the present invention have been explained. However, the present invention is not limited to these embodiments, and all changes to the present invention belong to the technical scope of the present invention as long as they do not depart from the spirit of the present invention.

Explanation of Reference Numerals

[0071] 100, 200, 300, 400: Semiconductor device 101: Growth substrate 102: Base 103: Sacrificial layer 104: First contact layer 106: First window layer 108: Buffer layer 110: First-type semiconductor structure 112: Active structure 114: Second-type semiconductor structure 116: Second window layer 118: Second contact layer 122: First electrode 120: Second electrode 124: Connection layer 130: Reflection structure 132: Third contact layer 134: Barrier layer 136: Reflection connection layer 138: Reflection layer 140: Conductive structure 141: Hole 142: First conductive layer 144: Second conductive layer 146: Insulating layer 302: First dopant 304: Second dopant 306: First element 308: Second element 310: Third element 500: Package structure 51: Package plate 52: Through hole 53: Mounting body 53a: First part 53b: Second part 55: Connection line 56: Contact structure 56a, 56b: Contact pads 58: Package material S: Semiconductor stack layer S1: First side S2: Second side

Claims

1. A semiconductor device, A semiconductor stack layer, A first-type semiconductor structure including a first side and a second side opposite to the first side; An active structure located on the first side, including a quaternary compound semiconductor and emitting radiation, wherein a peak wavelength of the radiation is between 1000 nm and 2000 nm; and A first contact layer located on the second side and including a III-V compound semiconductor material Including a semiconductor stack layer; A first window layer located between the first contact layer and the first-type semiconductor structure; A second-type semiconductor structure, wherein the active structure is located between the second-type semiconductor structure and the first-type semiconductor structure; and A second window layer, wherein the second-type semiconductor structure is located between the active structure and the second window layer; A reflective structure located under the semiconductor stack layer; A conductive structure located between the reflective structure and the semiconductor stack layer; and An insulating layer located between the conductive structure and the semiconductor stack layer Including, A semiconductor device, wherein a material of the second window layer is the same as a material of the first window layer.

2. The semiconductor device according to Claim 1, Further including a buffer layer, The buffer layer is located between the first contact layer and the first-type semiconductor structure. A semiconductor device.

3. The semiconductor device according to Claim 1, The quaternary compound semiconductor is AlInGaAs or InGaAsP. A semiconductor device.

4. The semiconductor device according to Claim 1, An energy gap of the first contact layer is larger than energy gaps of the active structure and the first-type semiconductor structure. A semiconductor device.

5. The semiconductor device according to Claim 1, The first-type semiconductor structure includes a ternary or binary compound not containing nitrogen (N). A semiconductor device.

6. The semiconductor device according to Claim 1, The first contact layer and the first window layer include different materials. A semiconductor device.

7. The semiconductor device according to Claim 1, The first contact layer includes GaAs, InGaAs or InGaAsP. A semiconductor device.

8. The semiconductor device according to Claim 1, The material of the second window layer and the material of the first window layer include InP. A semiconductor device.

9. The semiconductor device according to Claim 1, Further including a first electrode and a second electrode, The first electrode and the second electrode are semiconductor elements located on opposite sides of the semiconductor stack layer. **Claim 10** The semiconductor element according to claim 1, wherein the reflective structure includes a barrier layer, a reflective adhesive layer located on the barrier layer, and a reflective layer located on the reflective adhesive layer.

Images