Semiconductor device, imaging device

Abstract

Provided are a semiconductor device, a method for manufacturing the semiconductor device, and an image-capturing device that are capable of suppressing variations in transistor characteristics. The semiconductor device comprises: a semiconductor substrate; and a field effect transistor provided on a first principal surface-side of the semiconductor substrate. The field effect transistor has: a semiconductor region in which a channel is formed; a gate electrode that covers the semiconductor region; and a gate insulating film disposed between the semiconductor region and the gate electrode. The semiconductor region has: a top surface; and a first side surface located on one side of the top surface in the gate-width direction of the gate electrode. The gate electrode has: a first part that faces the top surface with the gate insulating film interposed therebetween; and a second part that faces the first side surface with the gate insulating film interposed therebetween. A first end surface of the first part and a second end surface of the second part are flush at least on one end of the gate electrode in the gate-length direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a method of manufacturing a semiconductor device, and an imaging device.

Background Art

[0002] As a semiconductor device used in a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a non-planar transistor is known (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The gate electrode of the non-planar transistor disclosed in Patent Document 1 has a horizontal gate electrode and a vertical gate electrode connected to the horizontal gate electrode. The vertical gate electrode is formed by embedding a gate electrode material in a recess provided in a semiconductor substrate layer. The horizontal gate electrode is formed by etching the gate electrode material using a mask pattern. Since the shape and arrangement of the vertical gate electrode depend on the recess and the shape and arrangement of the horizontal gate electrode depend on a mask pattern different from the recess, a positional deviation may occur between the vertical gate electrode and the horizontal gate electrode.

[0005] The drain region (or source region) of the non-planar transistor is self-alignedly formed by ion implantation using a horizontal gate electrode as a mask. Therefore, there is no misalignment between the horizontal gate electrode and the drain region (or source region). However, the vertical gate electrode is not used as a mask for this ion implantation. Therefore, if misalignment occurs between the horizontal gate electrode and the vertical gate electrode, the distance between the vertical gate electrode and the drain region (or source region) may vary.

[0006] If the distance between the vertical gate electrode and the drain region (or source region) varies, transistor characteristics such as the gate-drain capacitance (Cgd) may vary, and the performance of the CMOS image sensor may deteriorate.

[0007] The present disclosure has been made in view of such circumstances, and an object thereof is to provide a semiconductor device, a method of manufacturing a semiconductor device, and an imaging device capable of suppressing variations in transistor characteristics.

Means for Solving the Problems

[0008] A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate and a field effect transistor provided on a first main surface side of the semiconductor substrate. The field effect transistor has a semiconductor region in which a channel is formed, a gate electrode covering the semiconductor region, and a gate insulating film disposed between the semiconductor region and the gate electrode. The semiconductor region has an upper surface and a first side surface located on one side of the upper surface in the gate width direction of the gate electrode. The gate electrode has a first portion facing the upper surface via the gate insulating film and a second portion facing the first side surface via the gate insulating film. At at least one end in the gate length direction of the gate electrode, a first end surface of the first portion and a second end surface of the second portion are flush.

[0009] According to this, at one end of the gate electrode in the gate length direction, the position of the first end face of the first part and the position of the second end face of the second part are aligned. Thereby, the semiconductor device can suppress variations in the distance between the drain region (or source region) formed using the first part as a mask and the second part. Thereby, the semiconductor device can suppress variations in transistor characteristics such as gate-drain capacitance (Cgd).

[0010] A method of manufacturing a semiconductor device according to an aspect of the present disclosure is a method of manufacturing a semiconductor device including a field effect transistor on a first main surface side of a semiconductor substrate, the method including: etching the first main surface side of the semiconductor substrate to form a first trench at a position adjacent to a semiconductor region that becomes a channel of the field effect transistor; forming a gate insulating film on an upper surface of the semiconductor region and a first side surface of the semiconductor region facing the first trench; forming an electrode member on the first main surface side on which the gate insulating film is formed to fill the first trench; and etching the electrode member to form a gate electrode. The gate electrode has a first part facing the upper surface via the gate insulating film and a second part disposed in the first trench and facing the first side surface via the gate insulating film. In the step of forming the gate electrode, the electrode member is etched such that the first end face of the first part and the second end face of the second part are flush with each other at at least one end of the gate electrode in the gate length direction.

[0011] According to this, at one end of the gate electrode in the gate length direction, the position of the first end face of the first part and the position of the second end face of the second part are aligned. Thereby, the above manufacturing method can manufacture a semiconductor device in which variations in the distance between the drain region (or source region) and the second part 32 are suppressed and variations in transistor characteristics such as Cgd are suppressed.

[0012] An imaging device according to an aspect of the present disclosure includes a photoelectric conversion element and a semiconductor device for transmitting an electrical signal photoelectrically converted by the photoelectric conversion element. The semiconductor device includes a semiconductor substrate and a field effect transistor provided on the first main surface side of the semiconductor substrate. The field effect transistor has a semiconductor region in which a channel is formed, a gate electrode covering the semiconductor region, and a gate insulating film disposed between the semiconductor region and the gate electrode. The semiconductor region has an upper surface and a first side surface located on one side of the upper surface in the gate width direction of the gate electrode. The gate electrode has a first portion facing the upper surface through the gate insulating film and a second portion facing the first side surface through the gate insulating film. At at least one end in the gate length direction of the gate electrode, a first end surface of the first portion and a second end surface of the second portion are flush.

[0013] According to this, the semiconductor device can suppress variations in transistor characteristics such as gate-drain capacitance (Cgd). The imaging device can suppress variations in charge conversion efficiency by using the field effect transistor of this semiconductor device as an amplification transistor for amplifying an electrical signal. Thereby, the imaging device can improve imaging performance, for example, by reducing fixed pattern noise.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 5A

Figure 5B

Figure 5C

Figure 6A

Figure 6B

Figure 6C

Figure 7A

Figure 7B

Figure 7C

Figure 8A

Figure 8B

Figure 8C

Figure 9A

Figure 9B

Figure 9C

Figure 10A

Figure 10B

Figure 10C

Figure 11A

Figure 11B

Figure 11C

Figure 12A

Figure 12B

Figure 12C

Figure 13A

Figure 13B

Figure 13C

Figure 14A

Figure 14B

Figure 15A

Figure 15B

Figure 16A

Figure 16B

Figure 16C

Figure 17A

Figure 17B

Figure 18A

Figure 18B

Figure 19A

Figure 19B

Figure 20A

Figure 20B

Figure 21A

Figure 21B

Figure 22A

Figure 22B

Mode for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Also, it goes without saying that there are portions where the dimensional relationships and ratios are different between the drawings.

[0016] The definitions of the directions such as up and down in the following description are merely for convenience of explanation and do not limit the technical idea of the present disclosure. For example, if the object is rotated by 90° and observed, up and down are read as left and right, and if it is rotated by 180° and observed, up and down are read in reverse.

[0017] In the following description, the directions may be described using the terms of the X-axis direction, the Y-axis direction, and the Z-axis direction. For example, the X-axis direction and the Y-axis direction are directions parallel to the surface 10a of the semiconductor substrate 10. The X-axis direction is the gate length direction of the gate electrode 30, and the Y-axis direction is the gate width direction of the gate electrode 30. The X-axis direction and the Y-axis direction are also referred to as the horizontal direction. The Z-axis direction is a direction perpendicular to the surface 10a of the semiconductor substrate 10. The X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

[0018] In the following description, the case where the first conductivity type is N-type and the second conductivity type is P-type will be exemplarily described. However, the conductivity types may be selected in the reverse relationship, i.e., the first conductivity type may be P-type and the second conductivity type may be N-type.

[0019] <Embodiment 1> (Configuration Example of Imaging Device) FIG. 1 is a diagram showing a configuration example of an imaging device 200 according to Embodiment 1 of the present disclosure. As shown in FIG. 1, the imaging device 200 is, for example, an image sensor using CMOS (Complementary Metal Oxide Semiconductor) (hereinafter referred to as a CMOS image sensor). The imaging device 200 takes in incident light (image light) from a subject via an optical lens system (not shown), converts the amount of incident light imaged on the imaging surface into an electrical signal in pixel units, and outputs it as a pixel signal.

[0020] In FIG. 1, the imaging device 200 includes a pixel array unit 211, a vertical drive unit 212, a column readout circuit unit 213, a column signal processing unit 214, a horizontal drive unit 215, a system control unit 216, a signal processing unit 217, and a data storage unit 218.

[0021] The pixel array unit 211, the vertical drive unit 212, the column readout circuit unit 213, the column signal processing unit 214, the horizontal drive unit 215, the system control unit 216, the signal processing unit 217, and the data storage unit 218 are formed on the same semiconductor substrate (chip) or a plurality of stacked semiconductor substrates (chips) electrically connected to each other. In the pixel array unit 211, pixels are two-dimensionally arranged in a matrix. Each pixel has a photodiode (an example of the "photoelectric conversion element" of the present disclosure) that can photoelectrically convert the amount of charge corresponding to the incident light amount, accumulate it inside, and output it as an electrical signal.

[0022] Note that the pixel array unit 211 may include a region in which, in addition to effective pixels (hereinafter referred to as effective pixels), dummy pixels having a structure without a photodiode and light-shielding pixels having a structure that shields the light-receiving surface to block light incident from the outside are two-dimensionally arranged in a matrix.

[0023] In the pixel array unit 211, pixel drive lines 231 are further formed for each row of the matrix-like pixel array along the left-right direction of the figure (the pixel arrangement direction of the pixel row), and vertical pixel wirings 232 are formed for each column along the up-down direction of the figure (the pixel arrangement direction of the pixel column). One end of the pixel drive line 231 is connected to the output end corresponding to each row of the vertical drive unit 212.

[0024] The column readout circuit unit 213 includes a circuit that supplies a constant current to the selected row pixels in the pixel array unit 211 for each column, a current mirror circuit that constitutes a high-gain amplifier, and a readout mode switching switch. The column readout circuit unit 213 forms an amplifier together with the transistors in the selected pixels in the pixel array unit 211, converts the charge signal into a voltage signal, and outputs it to the vertical pixel wiring 232.

[0025] The vertical drive unit 212 is a pixel drive unit that drives each pixel of the pixel array unit 211 simultaneously for all pixels or in units of rows. The vertical drive unit 212 is composed of a shift register, an address decoder, and the like.

[0026] The pixel signals output from each pixel of the pixel row selected and scanned by the vertical drive unit 212 are supplied to the column signal processing unit 214 through each of the vertical pixel wirings 232. The column signal processing unit 214 performs predetermined signal processing on the pixel signals output from each pixel of the selected row through the vertical pixel wiring 232 for each pixel column of the pixel array unit 211, and temporarily holds the pixel signals after the signal processing.

[0027] The horizontal drive unit 215 sequentially selects the unit circuits corresponding to the pixel columns of the column signal processing unit 214. By the selective scanning by the horizontal drive unit 215, the pixel signals processed by the column signal processing unit 214 are sequentially output to the signal processing unit 217. The horizontal drive unit 215 is composed of a shift register, an address decoder, and the like.

[0028] The system control unit 216 is composed of a timing generator or the like that generates various timing signals. Based on the various timing signals generated by the timing generator, the system control unit 216 performs drive control of the vertical drive unit 212, the column signal processing unit 214, the horizontal drive unit 215, and the like.

[0029] The imaging device 200 further includes a signal processing unit 217 and a data storage unit 218. The signal processing unit 217 performs various signal processes such as addition processing on the pixel signals output from the column signal processing unit 214. The data storage unit 218 temporarily stores the data necessary for the processing when performing the signal processing in the signal processing unit 217. The signal processing unit 217 and the data storage unit 218 may be provided in an external signal processing unit, for example, a DSP (Digital Signal Processor), which is provided on a substrate different from the imaging device 200, or may be processed by software. Further, the signal processing unit 217 and the data storage unit 218 may be provided on the same substrate (for example, the semiconductor substrate 10 described later) as the imaging device 200.

[0030] (Configuration example of pixels) Next, a circuit configuration example of the pixels two-dimensionally arranged in a matrix in the pixel array unit 211 will be described. FIG. 2 is a circuit diagram showing a configuration example of the pixel PU according to Embodiment 1 of the present disclosure. As shown in FIG. 2, the pixel PU has a photodiode PD, a transfer transistor TR, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. The pixel PU also has a floating diffusion region FD.

[0031] The anode of the photodiode PD is grounded, and the cathode of the photodiode is connected to the source of the transfer transistor TR. The drain of the transfer transistor TR is connected to the source of the reset transistor RST and the gate of the amplification transistor AMP, respectively, and this connection point constitutes the floating diffusion region FD.

[0032] Also, the drain of the reset transistor RST is connected to the vertical reset input line 261, and the source of the amplification transistor AMP is connected to the vertical current supply line 262. The drain of the amplification transistor AMP is connected to the source of the selection transistor SEL, and the drain of the selection transistor SEL is connected to the vertical signal line VSL. The vertical reset input line 261, the vertical current supply line 262, and the vertical signal line VSL are each part of the vertical pixel wiring 232 (see FIG. 1).

[0033] The gates of the transfer transistor TR, the reset transistor RST, and the selection transistor SEL are each connected to the vertical driving unit 212 (see FIG. 1) via the driving lines TR-L, RST-L, SEL-L, respectively, and pulses as driving signals are supplied thereto. The driving lines TR-L, RST-L, SEL-L are each part of the pixel driving line 231 (see FIG. 1).

[0034] (Configuration example of differential pixel readout circuit) FIG. 3 is a circuit diagram showing a configuration example of the differential readout circuit 150 according to Embodiment 1 of the present disclosure. As shown in FIG. 3, the differential readout circuit 150 includes a readout pixel PUS that reads a charge signal, a reference pixel PUR that provides a reference voltage without a charge signal, a current mirror circuit 151 composed of PMOS transistors, and a load MOS circuit 152 that supplies a constant current to the pixel. The readout pixel PUS and the reference pixel PUR each have the same configuration as the pixel PU shown in FIG. 2.

[0035] In the readout pixel PUS, the drain of the reset transistor RST is connected to the readout-side vertical reset input line 261S. The source of the amplification transistor AMP is connected to the readout-side vertical current supply line 262S. The drain of the amplification transistor AMP is connected to the source of the selection transistor SEL. The drain of the selection transistor SEL is connected to the readout-side vertical signal line VSLS.

[0036] In the read pixel PUS, the gates of the transfer transistor TR, the reset transistor RST, and the selection transistor SEL are connected to the vertical drive unit 212 (see FIG. 1) via the pixel drive line 231 (see FIG. 1). From the vertical drive unit 212, drive signals for reading are respectively supplied to the gates of the transfer transistor TR, the reset transistor RST, and the selection transistor SEL via the pixel drive line 231.

[0037] The vertical signal line VSLS on the read side is connected to the vertical reset input line 261S on the read side, the drain of the PMOS transistor 153S on the read side included in the current mirror circuit 151, and the output terminal Vout of the differential read circuit 150. When the reset transistor RST on the read side is on, the vertical reset input line 261S is connected to the floating diffusion region FD, and the output signal of the read circuit 150 is negatively feedback.

[0038] In the reference pixel PUR, the drain of the reset transistor RST is connected to the vertical reset input line 261R on the reference side. The source of the amplifier transistor AMP is connected to the vertical current supply line 262R on the reference side. The drain of the amplifier transistor AMP is connected to the source of the selection transistor SEL. The drain of the selection transistor SEL is connected to the vertical signal line VSLR on the reference side.

[0039] In the reference pixel PUR, the gates of the transfer transistor TR, the reset transistor RST, and the selection transistor SEL are connected to the vertical drive unit 212 (see FIG. 1) via the pixel drive line 231 (see FIG. 1). From the vertical drive unit 212, drive signals for reference are respectively supplied to the gates of the transfer transistor TR, the reset transistor RST, and the selection transistor SEL via the pixel drive line 231.

[0040] The vertical signal line VSLR on the reference side is connected to the drain and gate of the PMOS transistor 153R on the reference side included in the current mirror circuit 151, and the gate of the PMOS transistor 153S on the read side, respectively.

[0041] The vertical reset input line 261R on the reference side is connected to the power supply Vrst. At the time of reset, an arbitrary input voltage signal is applied through the vertical reset input line 261R to the input terminal of the amplification transistor AMP of the selected reference pixel PUR.

[0042] The vertical current supply line 262S on the read side and the vertical current supply line 262R on the reference side are connected to each other at the connection point Vcom and then connected to the load MOS circuit 152 which is a constant current source. In the differential read circuit 150, the amplification transistor AMP of the read pixel PUS and the amplification transistor AMP of the reference pixel PUR constitute a differential amplifier (differential amplification circuit), and a voltage signal corresponding to the charge signal detected by the photodiode PD of the read pixel PUS is output via the output terminal Vout.

[0043] (Configuration example of semiconductor device) Next, a semiconductor device constituting the pixel array unit 211 shown in FIG. 1 will be described. FIG. 4A is a plan view showing a configuration example of a semiconductor device 100 according to Embodiment 1 of the present disclosure. FIGS. 4B to 4D are cross-sectional views showing a configuration example of the semiconductor device 100 according to Embodiment 1 of the present disclosure. Specifically, FIG. 4B shows a cross-section obtained by cutting the plan view shown in FIG. 4A along the line A4 - A'4 parallel to the X-axis. FIG. 4C shows a cross-section obtained by cutting the plan view shown in FIG. 4A along the line B4 - B'4 parallel to the X-axis. FIG. 4D shows a cross-section obtained by cutting the plan view shown in FIG. 4A along the line C4 - C'4 parallel to the Y-axis.

[0044] As shown in FIGS. 4A to 4D, the semiconductor device 100 includes a semiconductor substrate 10, a plurality of MOS (Metal Oxide Semiconductor) transistors 1A, 1B (an example of the "field effect transistor" of the present disclosure) provided on the semiconductor substrate 10, and an element isolation layer 13 provided on the semiconductor substrate 10.

[0045] The semiconductor substrate 10 is made of, for example, single-crystalline silicon. The semiconductor substrate 10 has a surface 10a (an example of the "first main surface" of the present disclosure) and a back surface 10b located on the side opposite to the surface 10a. MOS transistors 1A and 1B are provided on the surface 10a side of the semiconductor substrate 10. The element isolation layer 13 is an insulating film for electrically isolating adjacent elements in a horizontal direction parallel to the surface 10a, and is composed of, for example, a silicon oxide film (SiO2 film).

[0046] The MOS transistors 1A and 1B are transistors of the first conductivity type (for example, N-type). For example, the MOS transistor 1A is an amplification transistor AMP (see FIGS. 2 and 3), and the MOS transistor 1B is a selection transistor SEL (see FIGS. 2 and 3). The MOS transistors 1A and 1B are connected in series with each other.

[0047] The MOS transistors 1A and 1B each include a semiconductor region 11 of the second conductivity type (for example, P-type) in which a channel is formed, a gate insulating film 20, a gate electrode 30, a sidewall 39, and impurity diffusion layers 41 and 42 of the second conductivity type provided in the semiconductor substrate 10.

[0048] One of the impurity diffusion layers 41 and 42 is a source region, and the other is a drain region. For example, in the MOS transistor 1A, the impurity diffusion layer 41 is the source region, and the impurity diffusion layer 42 is the drain region. In the MOS transistor 1B, the impurity diffusion layer 41 is the drain region, and the impurity diffusion layer 42 is the source region. FIG. 4B illustrates a mode in which the MOS transistors 1A and 1B share the impurity diffusion layer 42.

[0049] The semiconductor region 11 is, for example, a part of the semiconductor substrate 10 and is made of single-crystalline silicon. The semiconductor region 11 is a portion formed by etching a part of the surface 10a side of the semiconductor substrate 10, and its shape is, for example, a fin shape.

[0050] The semiconductor region 11 has a shape that is long in the X-axis direction and short in the Y-axis direction. For example, the length of the semiconductor region 11 in the X-axis direction is 150 nm or more and 700 nm or less. The length (width) of the semiconductor region 11 in the Y-axis direction is 15 nm or more and 1000 nm or less. The length (depth) of the semiconductor region 11 in the Z-axis direction is 100 nm or more and 1000 nm or less.

[0051] In the Y-axis direction, a trench H1 (an example of the "first trench" of the present disclosure) is provided on one side of the semiconductor region 11, and a trench H2 (an example of the "second trench" of the present disclosure) is provided on the other side of the semiconductor region 11. The second part 32 of the gate electrode 30 is disposed in the trench H1. The third part 33 of the gate electrode 30 is disposed in the trench H2. The second part 32 and the third part 33 will be described later. The semiconductor region 11 is sandwiched in the Y-axis direction by the second part 32 disposed in the trench H1 and the third part 33 disposed in the trench H2.

[0052] The gate insulating film 20 is provided so as to cover the upper surface 11a, the first side surface 11b, and the second side surface 11c of the semiconductor region 11. The upper surface 11a of the semiconductor region 11 is a part of the surface 10a of the semiconductor substrate 10. The first side surface 11b is located on one side of the upper surface 11a in the Y-axis direction. The second side surface 11c is located on the other side of the upper surface 11a in the Y-axis direction. The gate insulating film 20 is composed of, for example, a SiO2 film.

[0053] The gate electrode 30 covers the semiconductor region 11 with the gate insulating film 20 interposed therebetween. For example, the gate electrode 30 includes a first part 31 facing the upper surface 11a of the semiconductor region 11 with the gate insulating film 20 interposed therebetween, a second part 32 facing the first side surface 11b of the semiconductor region 11 with the gate insulating film 20 interposed therebetween, and a third part 33 facing the second side surface 11c of the semiconductor region 11 with the gate insulating film 20 interposed therebetween. The second part 32 and the third part 33 are respectively connected to the lower surface of the first part 31. Note that the first part 31 may be referred to as a horizontal gate electrode. The second part 32 and the third part 33 may be respectively referred to as vertical gate electrodes.

[0054] As a result, the gate electrode 30 can apply a gate voltage to the upper surface 11a, the first side surface 11b, and the second side surface 11c of the semiconductor region 11 simultaneously. That is, the gate electrode 30 can apply the gate voltage to the semiconductor region 11 simultaneously from three directions, i.e., the upper side and the left and right sides. As a result, the gate electrode 30 can completely deplete the semiconductor region 11. The gate electrode 30 is formed of, for example, a polysilicon (Poly-Si) film.

[0055] The sidewall 39 is provided around the gate electrode 30. The sidewall 39 is formed of, for example, a silicon nitride (SiN) film.

[0056] The impurity diffusion layers 41 and 42 are provided on the surface 10a of the semiconductor substrate 10 and in the vicinity thereof, respectively. In the X-axis direction, the impurity diffusion layer 41 is connected to one side of the semiconductor region 11, and the impurity diffusion layer 42 is connected to the other side of the semiconductor region 11. The impurity diffusion layers 41 and 42 are of the first conductivity type (e.g., N-type), respectively.

[0057] The MOS transistor 1A according to the embodiment of the present disclosure may be called a MOS transistor having a trench gate structure because the second part 32 and the third part 33 of the gate electrode 30 are arranged in the trenches H1 and H2. Alternatively, since the semiconductor region 11 has a fin shape, the MOS transistor 1A may be called a fin field effect transistor (FinFET). Alternatively, the MOS transistor 1A may be called a trench FinFET from the above two shapes. Similarly, the MOS transistor 1B may also be called a MOS transistor having a trench gate structure, a finFET, or a trench FinFET.

[0058] In each of the MOS transistors 1A and 1B, the gate electrode 30 has an end face 30d on one end side in the X-axis direction (for example, the impurity diffusion layer 42 side), and an end face 30e on the other end side in the X-axis direction (for example, the impurity diffusion layer 41 side). The end face 30d includes the end face 31d of the first portion 31 (an example of the "first end face" of the present disclosure), the end face 32d of the second portion 32 (an example of the "second end face" of the present disclosure), and the end face 33d of the third portion 33 (an example of the "third end face" of the present disclosure). The end face 30e includes the end face 31e of the first portion 31, the end face 32e of the second portion 32, and the end face 33e of the third portion 33.

[0059] In the semiconductor device 100 according to Embodiment 1, there is no (or almost no) step between the end face 31d and the end face 32d, and between the end face 31d and the end face 33d. The end faces 31d, 32d, and 33d are flush. On the other hand, there are steps between the end face 31e and the end face 32e, and between the end face 31e and the end face 33e. The end faces 31e, 32e, and 33e are not flush.

[0060] (Method for manufacturing a semiconductor device) Next, a method for manufacturing the semiconductor device 100 according to Embodiment 1 of the present disclosure will be described. The semiconductor device 100 is manufactured using various devices such as a film forming device (including a CVD (Chemical Vapor Deposition) device, a thermal oxidation furnace, a sputtering device, and a resist coating device), an exposure device, an ion implantation device, an annealing device, an etching device, and a CMP (Chemical Mechanical Polishing) device. Hereinafter, these devices will be collectively referred to as manufacturing devices.

[0061] Figures 5A to 12C are diagrams showing the manufacturing method of the semiconductor device 100 according to Embodiment 1 of the present disclosure in the order of steps. In Figures 5A to 12C, A in each figure is a plan view, B in each figure is a cross-sectional view obtained by cutting A in each figure along the line A-A', and C in each figure is a cross-sectional view obtained by cutting A in each figure along the line B-B'.

[0062] In FIGS. 5A to 5C, the manufacturing apparatus sequentially forms a silicon oxide film (SiO2 film) 15 and a silicon nitride film (SiN film) 17 on the surface 10a of the semiconductor substrate 10 using the CVD method. Next, the manufacturing apparatus partially removes the silicon nitride film 17, the silicon oxide film 15, and the semiconductor substrate 10 in the dug-in region using photolithography and etching techniques. Thereby, the manufacturing apparatus forms a trench H11 in the dug-in region.

[0063] Next, the manufacturing apparatus forms a silicon oxide film above the semiconductor substrate 10 using the CVD method to fill the trench H11. Next, the manufacturing apparatus performs CMP processing on the silicon oxide film to planarize it. In this CMP processing, the silicon nitride film 17 functions as a polishing stop layer. Thereby, the element isolation layer 13 is formed from the silicon oxide film.

[0064] Next, as shown in FIGS. 6A to 6C, the manufacturing apparatus forms a resist pattern RP1 above the semiconductor substrate 10. The resist pattern RP1 has a shape that opens the regions where trenches H1 and H2 (see FIG. 4D) are formed and the region sandwiched between the trenches H1 and H2, and covers the other regions. Next, the manufacturing apparatus etches and removes the element isolation layer 13 using the resist pattern RP1 and the silicon nitride film 17 as masks. Thereby, as shown in FIGS. 7A to 7C, the trenches H1 and H2 are formed. Thereafter, the manufacturing apparatus removes the resist pattern RP1.

[0065] Next, as shown in FIGS. 8A to 8C, the manufacturing apparatus removes the silicon nitride film 17. In the step of removing the silicon nitride film 17, the silicon oxide film 15 functions as an etching stop layer. Next, the manufacturing apparatus removes the silicon oxide film 15. Thereby, the surface 10a of the semiconductor substrate 10 is exposed from under the silicon oxide film 15.

[0066] Next, the manufacturing apparatus thermally oxidizes the semiconductor substrate 10. As a result, as shown in FIGS. 9A to 9C, a gate insulating film 20 is formed on the surface 10a of the semiconductor substrate 10. The gate insulating film 20 is formed on the upper surface 11a, the first side surface 11b, and the second side surface 11c of the semiconductor region 11 sandwiched between the trenches H1 and H2.

[0067] Next, as shown in FIGS. 10A to 10C, the manufacturing apparatus forms a polysilicon film 30' (an example of the "electrode member" of the present disclosure) above the semiconductor substrate 10 using the CVD method and fills the trenches H1 and H2. Next, the manufacturing apparatus forms a resist pattern (not shown) on the polysilicon film 30'. The resist pattern has a shape that covers the region where the gate electrode is to be formed and opens the other regions. Next, the manufacturing apparatus uses the resist pattern as a mask to etch and remove the polysilicon film 30'. As a result, as shown in FIGS. 11A to 11C, the manufacturing apparatus forms the gate electrode 30.

[0068] In the etching process for forming the gate electrode 30, overetching with respect to the polysilicon film 30' is sufficiently performed to separate the gate electrodes 30 from each other. Since the upper surface 11a, the first side surface 11b, and the second side surface 11c of the semiconductor region 11 are covered with the gate insulating film 20, the semiconductor region 11 remains without being etched even in the region AR1 where the polysilicon film 30' is overetched. Thereafter, the manufacturing apparatus removes the resist pattern.

[0069] Next, the manufacturing apparatus forms a silicon nitride film above the semiconductor substrate 10. Next, the manufacturing apparatus etchbacks the silicon nitride film. As a result, as shown in FIGS. 12A to 12C, the manufacturing apparatus forms sidewalls 39 around the gate electrode 30.

[0070] Next, the manufacturing apparatus uses the gate electrode 30 and the sidewall 39 as masks to ion-implant impurities of the first conductivity type on the surface 10a side of the semiconductor substrate 10. Then, the manufacturing apparatus performs an annealing process on the semiconductor substrate 10 into which the impurities have been ion-implanted to activate the impurities. Thereby, the manufacturing apparatus forms impurity diffusion layers 41 and 42 (see FIGS. 4A and 4B) that will become source regions or drain regions on the surface 10a side of the semiconductor substrate 10.

[0071] Through the above steps, the semiconductor device 100 having the trench gate structure MOS transistors 1A and 1B is completed.

[0072] As described above, the semiconductor device 100 according to Embodiment 1 of the present disclosure includes a semiconductor substrate 10 and MOS transistors 1A and 1B provided on the surface 10a side of the semiconductor substrate 10. The MOS transistors 1A and 1B include a semiconductor region 11 in which a channel is formed, a gate electrode 30 covering the semiconductor region 11, and a gate insulating film 20 disposed between the semiconductor region 11 and the gate electrode 30. The semiconductor region 11 has an upper surface 11a and a first side surface 11b located on one side of the upper surface 11a in the gate width direction (for example, the Y-axis direction) of the gate electrode 30. The gate electrode 30 has a first portion 31 facing the upper surface 11a via the gate insulating film 20 and a second portion 32 facing the first side surface 11b via the gate insulating film 20. At one end in the gate length direction (for example, the X-axis direction) of the gate electrode 30, the end surface 31d of the first portion 31 and the end surface 32d of the second portion 32 are flush.

[0073] According to this, at one end in the X-axis direction, the position of the end face 31d of the first part 31 and the position of the end face 32d of the second part 32 are aligned. Thereby, the semiconductor device 100 can suppress the variation in the distance between the drain region (or source region) formed using the first part 31 as a mask and the second part 32. For example, the semiconductor device 100 can suppress the variation in the distance between the impurity diffusion layer 42 serving as the drain region and the second part 32 of the gate electrode 30 in the MOS transistor 1A. Thereby, the semiconductor device 100 can suppress the variation in transistor characteristics such as the gate-drain capacitance (Cgd).

[0074] Further, the semiconductor region 11 further has a second side surface 11c located on the other side of the upper surface 11a in the Y-axis direction. The gate electrode 30 further has a third part 33 facing the second side surface 11c with the gate insulating film 20 interposed therebetween. At one end of the gate electrode 30 in the X-axis direction, the end face 31d of the first part 31 and the end face 33d of the third part 33 are flush.

[0075] According to this, at one end in the X-axis direction, the position of the end face 31d of the first part 31 and the position of the end face 33d of the third part 33 are aligned. Thereby, the semiconductor device 100 can suppress the variation in the distance between the drain region (or source region) formed using the first part 31 as a mask and the third part 33. Thereby, the semiconductor device 100 can further suppress the variation in transistor characteristics such as Cgd.

[0076] The manufacturing method of the semiconductor device 100 according to Embodiment 1 of the present disclosure is a method for manufacturing a semiconductor device including MOS transistors 1A and 1B on the surface 10a side of the semiconductor substrate 10, and includes a step of etching the surface 10a side of the semiconductor substrate 10 to form a trench H1, a step of forming a gate insulating film 20 on the upper surface 11a of the semiconductor region 11 adjacent to the trench H1 and on the first side surface 11b facing the trench H1 in the semiconductor region 11, a step of forming a polysilicon film 30' on the surface 10a side where the gate insulating film 20 is formed to fill the trench H1, and a step of etching the polysilicon film 30' to form a gate electrode 30. The gate electrode 30 has a first portion 31 facing the upper surface 11a through the gate insulating film 20 and a second portion 32 disposed in the trench H1 and facing the first side surface 11b through the gate insulating film 20. In the step of forming the gate electrode 30, the polysilicon film 30' is etched so that the end face 31d of the first portion 31 and the end face 32d of the second portion 32 are flush at one end of the gate electrode 30 in the X-axis direction.

[0077] According to this, at one end in the X-axis direction, the position of the end face 31d of the first portion 31 and the position of the end face 32d of the second portion 32 are aligned. Thereby, the manufacturing method can manufacture a semiconductor device in which the variation in the distance between the drain region (or source region) and the second portion 32 is suppressed, and the variation in transistor characteristics such as Cgd is suppressed.

[0078] The imaging device 200 according to the embodiment of the present disclosure includes a photodiode PD and a semiconductor device 100 for transmitting an electrical signal photoelectrically converted by the photodiode PD. The semiconductor device 100 can suppress variations in transistor characteristics such as Cgd. The imaging device 200 can suppress variations in charge conversion efficiency by using the MOS transistor 1A of this semiconductor device 100 as an amplification transistor for amplifying an electrical signal. Thereby, the imaging device 200 can improve imaging performance, for example, by reducing fixed pattern noise.

[0079] <Embodiment 2> In the above-described Embodiment 1, it was explained that at one end of the gate electrode 30 in the X-axis direction, the end faces are flush. However, the embodiments of the present disclosure are not limited to this. In the embodiments of the present disclosure, not only at one end of the gate electrode 30, but also at the other end, the end faces may be flush. That is, at both ends of the gate electrode 30 in the X-axis direction, the end faces may be flush with each other.

[0080] FIG. 13A is a plan view showing a configuration example of a semiconductor device 100A according to Embodiment 2 of the present disclosure. FIGS. 13B and 13C are cross-sectional views showing configuration examples of the semiconductor device 100A according to Embodiment 2 of the present disclosure. Specifically, FIG. 13B shows a cross-section obtained by cutting the plan view shown in FIG. 13A along line A13-A'13 parallel to the X-axis. FIG. 13C shows a cross-section obtained by cutting the plan view shown in FIG. 13A along line B13-B'13 parallel to the X-axis.

[0081] As shown in FIGS. 13A to 13B, the semiconductor device 100A according to Embodiment 2 includes MOS transistors 1A and 1B. In each of the MOS transistors 1A and 1B, the gate electrode 30 has an end face 30d on one end side in the X-axis direction and an end face 30e on the other end side in the X-axis direction. The end face 30d includes an end face 31d of the first portion 31 (an example of the "first end face" of the present disclosure), an end face 32d of the second portion 32 (an example of the "second end face" of the present disclosure), and an end face 33d of the third portion 33 (an example of the "third end face" of the present disclosure). The end face 30e includes an end face 31e of the first portion 31 (another example of the "first end face" of the present disclosure), an end face 32e of the second portion 32 (another example of the "second end face" of the present disclosure), and an end face 33e of the third portion 33 (another example of the "third end face" of the present disclosure).

[0082] In the semiconductor device 100A, there is no (or almost no) step between the end face 31d and the end face 32d, and between the end face 31d and the end face 33d. The end faces 31d, 32d, and 33d are flush. Similarly, there is no (or almost no) step between the end face 31e and the end face 32e, and between the end face 31e and the end face 33e. The end faces 31e, 32e, and 33e are flush. That is, at both ends of the gate electrode 30 in the X-axis direction, the end faces are flush with each other.

[0083] With such a configuration, the semiconductor device 100A exhibits the same effects as the semiconductor device 100 according to Embodiment 1. Further, in the semiconductor device 100A, also at the other end in the X-axis direction, the positions of the end faces 31e of the first part 31, the positions of the end faces 32e of the second part 32, and the positions of the end faces 33e of the third part 33 are aligned. Thereby, in each of the MOS transistors 1A and 1B of the semiconductor device 100, variations in the gate-drain capacitance (Cgd) and variations in the gate-source capacitance (Cgs) can be suppressed respectively.

[0084] Next, a method for manufacturing the semiconductor device 100A will be described. FIGS. 14A to 15B are cross-sectional views showing the method for manufacturing the semiconductor device 100A according to Embodiment 2 of the present disclosure in the order of steps. In FIGS. 14A to 15B, A in each figure shows the manufacturing process of the cross-section shown in FIG. 13B, and B in each figure shows the manufacturing process of the cross-section shown in FIG. 13C. Note that, in the method for manufacturing the semiconductor device 100A, up to the step of forming the polysilicon film 30' shown in FIGS. 10A to 10C, it is the same as the method for manufacturing the semiconductor device 100 described in Embodiment 1.

[0085] After the formation of the polysilicon film 30', the manufacturing apparatus forms a resist pattern (not shown) on the polysilicon film 30'. The resist pattern has a shape that covers the region where the gate electrode is to be formed and opens the other regions. Next, the manufacturing apparatus uses the resist pattern as a mask to etch and remove the polysilicon film 30'. Thereby, as shown in FIGS. 14A and 14B, the manufacturing apparatus forms the gate electrode 30. Thereafter, the manufacturing apparatus removes the resist pattern.

[0086] In the process of forming the gate electrode 30 shown in FIGS. 14A and 14B, not only on one end side of the gate electrode 30 in the X-axis direction but also on the other end side, following the first part 31, the second part 32 and the third part 33 are etched. For this reason, the end faces 31e, 32e, 33e on the other end side of the gate electrode 30 are flush. Also, a gap S1 is generated between the end faces 32e, 33e of the gate electrode 30 and the element isolation layer 13 in the trench H11 due to etching of the polysilicon film 30' in the trench H11.

[0087] Next, the manufacturing apparatus forms a silicon nitride film above the semiconductor substrate 10. The above-mentioned gap S1 is filled with the silicon nitride film. Next, the manufacturing apparatus etch-backs the silicon nitride film. Thereby, as shown in FIGS. 15A and 15B, the manufacturing apparatus forms sidewalls 39 around the gate electrode 30. In the semiconductor device 100A, the end faces 32e, 33e facing the gap S1 also have a structure covered with the sidewalls 39.

[0088] In the manufacturing method of the semiconductor device 100A, the subsequent processes are the same as those of the manufacturing method of the semiconductor device 100 according to Embodiment 1. The manufacturing apparatus uses the gate electrode 30 and the sidewalls 39 as masks to ion-implant impurities and perform an annealing process on the semiconductor substrate 10. Thereby, the manufacturing apparatus forms impurity diffusion layers 41, 42 (see FIGS. 13A and 13B) that will become the source region or the drain region. Through the above processes, the semiconductor device 100A having the recessed gate structure MOS transistors 1A, 1B is completed.

[0089] <Embodiment 3> In the above-described Embodiment 1, it was explained that the gate insulating film 20 is made of an SiO2 film and the gate electrode 30 is made of a polysilicon film. However, in the embodiments of the present disclosure, the materials of the gate insulating film and the gate electrode are not limited to this. For example, the gate insulating film may be made of a high dielectric constant film (High-k insulating film) having a higher dielectric constant than the SiO2 film. Also, the gate electrode may be made of a metal material. An insulating film (hereinafter, thermal oxide film) formed by thermally oxidizing the semiconductor substrate may be disposed between the high dielectric constant film and the semiconductor substrate.

[0090] FIG. 16A is a plan view showing a configuration example of a semiconductor device 100B according to Embodiment 3 of the present disclosure. FIGS. 16B to 16D are cross-sectional views showing a configuration example of the semiconductor device 100B according to Embodiment 3 of the present disclosure. Specifically, FIG. 16B shows a cross-section obtained by cutting the plan view shown in FIG. 16A along line A16-A'16 parallel to the X axis. FIG. 16C shows a cross-section obtained by cutting the plan view shown in FIG. 16A along line B16-B'16 parallel to the X axis. FIG. 16D shows a cross-section obtained by cutting the plan view shown in FIG. 16A along line C16-C'16 parallel to the Y axis.

[0091] As shown in FIGS. 16A to 16D, the semiconductor device 100B according to Embodiment 3 includes MOS transistors 1A and 1B. Each of the MOS transistors 1A and 1B has a high dielectric constant film 70 as a gate insulating film. The high dielectric constant film 70 is made of, for example, hafnium oxide or the like.

[0092] Also, each of the MOS transistors 1A and 1B has a metal gate 60 as a gate electrode. Similar to the gate electrode 30 described in Embodiment 1, the metal gate 60 has a first portion 61 facing the upper surface 11a of the semiconductor region 11 via the high-k dielectric film 70, a second portion 62 facing the first side surface 11b (see FIG. 4D) of the semiconductor region 11 via the high-k dielectric film 70, and a third portion 63 facing the second side surface 11c (see FIG. 4D) of the semiconductor region 11 via the high-k dielectric film 70. The second portion 62 and the third portion 63 are each connected to the lower surface of the first portion 61. The metal gate 60 is made of, for example, titanium nitride, tungsten, or the like.

[0093] Note that FIGS. 16B and 16C show an embodiment in which a thermal oxide film 20A (e.g., SiO2 film) is disposed between the semiconductor substrate 10 and the high-k dielectric film 70, but this is merely an example. The thermal oxide film 20A may not be disposed between the semiconductor substrate 10 and the high-k dielectric film 70.

[0094] In each of the MOS transistors 1A and 1B, the metal gate 60 has an end face 60d on one end side in the X-axis direction (e.g., the impurity diffusion layer 42 side) and an end face 60e on the other end side in the X-axis direction (e.g., the impurity diffusion layer 41 side). The end face 60d includes an end face 61d of the first portion 61 (an example of the "first end face" in the present disclosure), an end face 62d of the second portion 62 (an example of the "second end face" in the present disclosure), and an end face 63d of the third portion 63 (an example of the "third end face" in the present disclosure). The end face 60e includes an end face 61e of the first portion 61, an end face 62e of the second portion 62, and an end face 63e of the third portion 63.

[0095] In the semiconductor device 100B according to Embodiment 3, there is no (or almost no) step between the end face 61d and the end face 62d, and between the end face 61d and the end face 63d. The end faces 61d, 62d, and 63d are flush.

[0096] Even with such a configuration, the semiconductor device 100B exhibits the same effects as the semiconductor device 100 according to Embodiment 1. Further, by using the high-k dielectric film 70 for the gate insulating film, it becomes possible to increase the gate capacitances of the MOS transistors 1A and 1B respectively, and it becomes possible to increase the film thickness of the gate insulating film without impairing the gate capacitance.

[0097] Next, a manufacturing method of the semiconductor device 100B will be described. FIGS. 17A to 22B are cross-sectional views showing the manufacturing method of the semiconductor device 100B according to Embodiment 3 of the present disclosure in order of steps. In FIGS. 17A to 22B, A in each figure shows the manufacturing process of the cross-section shown in FIG. 16B, and B in each figure shows the manufacturing process of the cross-section shown in FIG. 16C. In the manufacturing method of the semiconductor device 100B, up to the step of forming the sacrificial gate electrode 30A, it is the same as the manufacturing method of the semiconductor device 100 described in Embodiment 1. Note that the shape and size of the sacrificial gate electrode 30A are, for example, the same as those of the gate electrode 30 described in Embodiment 1. The sacrificial gate electrode 30A can be formed by the same method as the gate electrode 30. The thermal oxide film 20A can be formed by the same method as the gate insulating film 20 described in Embodiment 1.

[0098] As shown in FIGS. 17A and 17B, after forming the sacrificial gate electrode 30A, the manufacturing apparatus forms a silicon oxide film (SiO2) film 50 over the entire upper surface of the semiconductor substrate 10 using the CVD method. The sacrificial gate electrode 30A is covered by the silicon oxide film 50. Next, as shown in FIGS. 18A and 18B, the manufacturing apparatus performs a CMP process on the silicon oxide film 50 to expose the surface of the sacrificial gate electrode 30A. In this CMP process, the sacrificial gate electrode 30A functions as a polishing stop layer.

[0099] Next, the manufacturing apparatus etches and removes the sacrificial gate electrode 30A. The sacrificial gate electrode 30A is made of, for example, a polysilicon film. The manufacturing apparatus etches the sacrificial gate electrode 30A using process conditions under which the polysilicon film is easily etched sufficiently with respect to the silicon oxide film and the silicon nitride film (that is, the etching selectivity is high). When the sacrificial gate electrode 30A is removed, as shown in FIGS. 19A and 19B, trenches H31 to H33 appear. The trenches H31, H32, and H33 have the same shapes as the first portion 31, the second portion 32, and the third portion 33 (see FIGS. 4A to 4D), respectively.

[0100] Next, as shown in FIGS. 20A and 20B, the manufacturing apparatus forms a high-k dielectric film 70 over the entire upper surface of the semiconductor substrate 10. The inner surfaces and the bottom surfaces of the trenches H31, H32, and H33 are covered with the high-k dielectric film 70.

[0101] Next, as shown in FIGS. 21A and 21B, the manufacturing apparatus forms a metal film 60' over the entire upper surface of the semiconductor substrate 10. The metal film 60' is made of, for example, tungsten. The metal film 60' is formed by, for example, a CVD method. The trenches H31, H32, and H33 are filled with the metal film 60'.

[0102] Next, as shown in FIGS. 22A and 22B, the manufacturing apparatus performs a CMP process on the metal film 60' to expose the surface of the silicon oxide film 50. In this CMP process, the silicon oxide film 50 functions as a polishing stop layer. By this CMP process, a metal gate 60 is formed from the metal film 60'.

[0103] Through the above steps, a semiconductor device 100B having trench gate structure MOS transistors 1A and 1B is completed.

[0104] <Other Embodiments> As described above, although the present disclosure has been described by way of embodiments and modifications, it should not be understood that the descriptions and drawings forming a part of this disclosure limit the present disclosure. Various alternative embodiments, examples, and operation techniques will become apparent to those skilled in the art from this disclosure. Of course, the present technology includes various embodiments and the like not described herein. At least one of various omissions, substitutions, and changes of components can be made without departing from the gist of the above-described embodiments and modifications. Further, the effects described in this specification are merely examples and are not limiting, and there may be other effects.

[0105] Note that the present disclosure can also have the following configuration. (1) A semiconductor substrate, and a field effect transistor provided on the first main surface side of the semiconductor substrate. The field effect transistor has a semiconductor region in which a channel is formed, a gate electrode covering the semiconductor region, and a gate insulating film disposed between the semiconductor region and the gate electrode. The semiconductor region has an upper surface and a first side surface located on one side of the upper surface in the gate width direction of the gate electrode. The gate electrode has a first portion facing the upper surface through the gate insulating film, and a second portion facing the first side surface through the gate insulating film. A semiconductor device in which, at at least one end in the gate length direction of the gate electrode, a first end surface of the first portion and a second end surface of the second portion are flush. (2) The semiconductor region further has a second side surface located on the other side of the upper surface in the gate width direction, and the gate electrode further has a third portion facing the second side surface through the gate insulating film. At at least one end in the gate length direction of the gate electrode, the first end face and the third end face of the third part are flush. The semiconductor device according to (1) above. (3) The semiconductor substrate A first trench provided on the first main surface side, A second trench provided on the first main surface side and adjacent to the first trench with the semiconductor region therebetween, The second part is disposed in the first trench, The third part is disposed in the second trench. The semiconductor device according to (2) above. (4) The gate electrode is made of polysilicon. The semiconductor device according to any one of (1) to (3) above. (5) The gate electrode is made of metal. The semiconductor device according to any one of (1) to (3) above. (6) A method of manufacturing a semiconductor device including a field effect transistor on the first main surface side of a semiconductor substrate, Etching the first main surface side of the semiconductor substrate to form a first trench at a position adjacent to a semiconductor region that becomes a channel of the field effect transistor; Forming a gate insulating film on the upper surface of the semiconductor region and a first side surface of the semiconductor region facing the first trench; Forming an electrode member on the first main surface side on which the gate insulating film is formed to fill the first trench; Etching the electrode member to form a gate electrode, The gate electrode A first part facing the upper surface through the gate insulating film, A second part disposed in the first trench and facing the first side surface through the gate insulating film, In the step of forming the gate electrode, A method of manufacturing a semiconductor device, wherein the electrode member is etched such that at at least one end in the gate length direction of the gate electrode, a first end surface of the first portion and a second end surface of the second portion are flush. (7) A photoelectric conversion element, and a semiconductor device for transmitting an electric signal photoelectrically converted by the photoelectric conversion element. The semiconductor device includes a semiconductor substrate, and a field effect transistor provided on the first main surface side of the semiconductor substrate. The field effect transistor has a semiconductor region in which a channel is formed, a gate electrode covering the semiconductor region, and a gate insulating film disposed between the semiconductor region and the gate electrode. The semiconductor region has an upper surface and a first side surface located on one side of the upper surface in the gate width direction of the gate electrode. The gate electrode has a first portion facing the upper surface through the gate insulating film, and a second portion facing the first side surface through the gate insulating film. An imaging device, wherein at at least one end in the gate length direction of the gate electrode, a first end surface of the first portion and a second end surface of the second portion are flush.

Description of Reference Numerals

[0106] 1A, 1B MOS transistors 10 Semiconductor substrate 10a Surface 10b Back surface 11 Semiconductor region 11a Upper surface 11b First side surface 11c Second side surface 13 Element isolation layer 15, 50 Silicon oxide film 17 Silicon nitride film 20 Gate insulating film 20A Thermal oxide film 30 gate electrodes 30’ polysilicon film 30A sacrificial gate electrode 30d, 30e, 31d, 31e, 32d, 32e, 33d, 33e, 61d, 61e, 62d, 62e, 63d, 63e end faces 31, 61 first part 32, 62 second part 33, 63 third part 39 sidewall 41, 42 impurity diffusion layer 60 metal gate 60’ metal film 70 high-k dielectric film 100, 100A, 100B semiconductor device 150 readout circuit 151 current mirror circuit 152 load MOS circuit 153R PMOS transistor 153S PMOS transistor 200 imaging device 211 pixel array section 212 vertical drive section 213 circuit section 214 column signal processing section 215 horizontal drive section 216 system control section 217 signal processing section 218 data storage section 231 pixel drive line 232 vertical pixel wiring 261 vertical reset input line 261R reference side vertical reset input line 261S readout side vertical reset input line 262 vertical current supply line 262R reference side vertical current supply line 262S readout side vertical current supply line AMP amplification transistor FD floating diffusion region H1, H2, H11, H31, H32, H33 trench PD Photodiode PU Pixel PUR Reference Pixel PUS Readout Pixel RP1 Resist Pattern RST Reset Transistor RST-L Drive Line S1 Gap SEL Selection Transistor SEL-L Drive Line TR Transfer Transistor TR-L Drive Line Vcom Connection Point Vout Output Terminal Vrst Power Supply VSL Vertical Signal Line VSLR Reference-Side Vertical Signal Line VSLS Readout-Side Vertical Signal Line

Claims

1. A semiconductor substrate, and a field-effect transistor provided on the first main surface side of the semiconductor substrate, wherein the field-effect transistor has a semiconductor region in which a channel is formed, a gate electrode covering the semiconductor region, and a gate insulating film disposed between the semiconductor region and the gate electrode, wherein the semiconductor region has an upper surface and a first side surface located on one side of the upper surface in the gate width direction of the gate electrode, wherein the gate electrode has a first portion facing the upper surface via the gate insulating film, and a second portion facing the first side surface via the gate insulating film, at one end in the gate length direction of the gate electrode, a first end surface of the first portion and a second end surface of the second portion are flush, and at the other end in the gate length direction, the first end surface and the second end surface are not flush, in the gate width direction of the gate electrode, the width of the gate insulating film is shorter than the width of the first portion, the field-effect transistor includes a first field-effect transistor and a second field-effect transistor, and the first field-effect transistor and the second field-effect transistor are connected in series on the one end side. A semiconductor device.

2. further comprising an element isolation layer provided on the first main surface side of the semiconductor substrate, wherein the element isolation layer is located on the opposite side of the semiconductor region across the gate insulating film and the second portion in the gate width direction of the gate electrode, and has a first element isolation layer adjacent to the second portion, and the first element isolation layer is provided to a deeper position from the first main surface than the second portion. The semiconductor device according to claim 1.

3. wherein the semiconductor region further has a second side surface located on the other side of the upper surface in the gate width direction, wherein the gate electrode further has a third portion facing the second side surface via the gate insulating film, at one end in the gate length direction of the gate electrode, the first end surface and a third end surface of the third portion are flush, and at the other end in the gate length direction, the first end surface and the third end surface are not flush. The semiconductor device according to claim 1 or 2.

4. further comprising an element isolation layer provided on the first main surface side of the semiconductor substrate, wherein the element isolation layer In the gate width direction of the gate electrode, a second element isolation layer is provided on the opposite side of the semiconductor region with the gate insulating film and the third part interposed therebetween, and adjacent to the third part. The semiconductor device according to claim 3, wherein the second element isolation layer is provided to a deeper position from the first main surface than the third part.

5. The semiconductor substrate has a first trench provided on the first main surface side, and a second trench provided on the first main surface side and adjacent to the first trench with the semiconductor region interposed therebetween. The second part is disposed in the first trench. The semiconductor device according to claim 3, wherein the third part is disposed in the second trench.

6. The semiconductor device according to claim 1, wherein the gate electrode is made of polysilicon.

7. The semiconductor device according to claim 1, wherein the gate electrode is made of metal.

8. A semiconductor substrate, and a field effect transistor provided on the first main surface side of the semiconductor substrate. The field effect transistor has a semiconductor region in which a channel is formed, a gate electrode covering the semiconductor region, and a gate insulating film disposed between the semiconductor region and the gate electrode. The semiconductor region has an upper surface and a first side surface located on one side of the upper surface in the gate width direction of the gate electrode. The gate electrode has a first part facing the upper surface through the gate insulating film, and a second part facing the first side surface through the gate insulating film. At one end in the gate length direction of the gate electrode, a first end surface of the first part and a second end surface of the second part are flush, and at the other end in the gate length direction, the first end surface and the second end surface are not flush. The semiconductor substrate further includes an element isolation layer provided on the first main surface side. The element isolation layer has a first element isolation layer located on the opposite side of the semiconductor region with the gate insulating film and the second part interposed therebetween in the gate width direction of the gate electrode, and adjacent to the second part. The first element isolation layer is provided to a deeper position from the first main surface than the second part. The field effect transistor includes a first field effect transistor and a second field effect transistor. The first field effect transistor and the second field effect transistor are connected in series on the one end side with respect to each other. Semiconductor device.

9. A photoelectric conversion element A semiconductor device for transmitting an electrical signal photoelectrically converted by the photoelectric conversion element, and the like. The semiconductor device is a semiconductor substrate, and a field effect transistor provided on the first main surface side of the semiconductor substrate. The field effect transistor is a semiconductor region in which a channel is formed, a gate electrode covering the semiconductor region, and a gate insulating film disposed between the semiconductor region and the gate electrode. The semiconductor region has an upper surface and a first side surface located on one side of the upper surface in the gate width direction of the gate electrode. The gate electrode has a first portion facing the upper surface via the gate insulating film, and a second portion facing the first side surface via the gate insulating film. At one end in the gate length direction of the gate electrode, a first end surface of the first portion and a second end surface of the second portion are flush, and at the other end in the gate length direction, the first end surface and the second end surface are not flush. In the gate width direction of the gate electrode, the width of the gate insulating film is shorter than the width of the first portion. The field effect transistor includes a first field effect transistor and a second field effect transistor. The first field effect transistor and the second field effect transistor are connected in series on the one end side of each other, an imaging device.

Images