Semiconductor device, semiconductor package, and method for manufacturing the same

Abstract

A semiconductor device comprising: a semiconductor layer having a first main surface on one side and a second main surface on the other side; a first main surface electrode that includes a first electrode, which covers the first main surface, and a second electrode, which has a hardness greater than that of the first electrode and covers the first electrode; and an oxide layer that covers the first main surface electrode.

Description

Technical Field

[0001] This application corresponds to Japanese Patent Application No. 2020-082702 filed with the Japan Patent Office on May 8, 2020, and the entire disclosure of this application is incorporated herein by reference. The present invention relates to a semiconductor device, a semiconductor package, and methods for manufacturing them.

Background Art

[0002] Patent Document 1 discloses a technique related to a vertical semiconductor device using a SiC semiconductor substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment of the present invention provides a semiconductor device, a semiconductor package, and methods for manufacturing them, which can improve mechanical strength.

Means for Solving the Problems

[0005] One embodiment of the present invention is a semiconductor device including a vertical power semiconductor device, having a first main surface and a second main surface opposite to the first main surface, a semiconductor layer containing SiC as a main component, a first electrode layer formed on the first main surface side of the semiconductor layer, a second electrode layer formed on the first electrode layer and electrically connected to a first terminal of the vertical power semiconductor device, the second electrode layer being harder than the first electrode layer, a third electrode layer formed on the second main surface side of the SiC semiconductor layer and electrically connected to a second terminal of the vertical power semiconductor device, and an oxide layer formed on the surface of the second electrode layer.

[0006] One embodiment of the present invention is a method for manufacturing a semiconductor device including a vertical power semiconductor device, the method including: forming a first electrode layer on a first main surface side of a semiconductor layer containing SiC as a main component; forming, on the first electrode layer, a second electrode layer that is electrically connected to a first terminal of the vertical power semiconductor device and is harder than the first electrode layer; and connecting a bonding wire to the second electrode layer.

[0007] One embodiment of the present invention provides a semiconductor device including: a semiconductor layer having a first main surface on one side and a second main surface on the other side; a first electrode covering the first main surface; and a first main surface electrode including a second electrode that has a higher hardness than the first electrode and covers the first electrode; and an oxide layer covering the first main surface electrode.

[0008] One embodiment of the present invention provides a method for manufacturing a semiconductor device, the method including: preparing a semiconductor layer having a main surface; forming a first electrode on the main surface; and forming a second electrode having a higher hardness than the first electrode on the first electrode, thereby forming a first main surface electrode including the first electrode and the second electrode on the main surface; and forming an oxide layer covering an outer surface of the first main surface electrode.

[0009] The above-described or further other objects, features, and effects of the present invention will become apparent from the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 3E

Figure 3F

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Figure 6

DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. Each of the embodiments described below shows an inclusive or specific example. The numerical values, shapes, materials, components, arrangement positions of components, connection forms of components, steps, order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present disclosure. Among the components in the following embodiments, the components not described in the independent claims are described as optional components.

[0012] Each of the accompanying drawings is a schematic diagram and is not necessarily drawn precisely. Therefore, for example, scales etc. do not necessarily match in the accompanying drawings. Substantially the same configurations in the accompanying drawings are denoted by the same reference numerals, and overlapping explanations are omitted or simplified.

[0013] In this specification, terms indicating the relationship between elements such as vertical and horizontal, terms indicating the shape of elements such as rectangular, and numerical ranges are not expressions representing only a strict meaning, but are expressions meaning including substantially equivalent ranges.

[0014] Also, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute space recognition, but are used as terms defined by the relative positional relationship based on the stacking order in the stacked structure. Specifically, in this specification, one main surface side of the semiconductor layer is described as the upper side (above), and the other main surface side is described as the lower side (below). When the semiconductor device (vertical transistor) is actually used, the first main surface side may be the lower side (below), and the second main surface side may be the upper side (above). Alternatively, the semiconductor device (vertical transistor) may be used in a posture where the first main surface and the second main surface are inclined or orthogonal to the horizontal plane.

[0015] Also, the terms "upper" and "lower" are applicable not only when the two components are spaced apart from each other with another component intervening between them, but also when the two components are arranged in close contact with each other.

[0016] Hereinafter, the configuration of the semiconductor device according to this embodiment will be described. FIG. 1 is a plan view showing a semiconductor device 101 according to this embodiment. The semiconductor device 101 includes a power semiconductor device (power semiconductor element) as an example of a functional device. Hereinafter, an example in which the semiconductor device 101 includes a vertical transistor is shown.

[0017] Referring to FIG. 1, the semiconductor device 101 has a SiC semiconductor layer 102 including a SiC (silicon carbide) single crystal as an example of a wide bandgap semiconductor. In this embodiment, the SiC semiconductor layer 102 is formed in a rectangular parallelepiped chip shape. The SiC semiconductor layer 102 includes a first main surface 103 on one side and a second main surface 104 on the other side. The first main surface 103 is a device surface on which the main structure of the functional device is formed. The second main surface 104 may be a mounting surface facing the connection target when the semiconductor device 101 is connected to the connection target.

[0018] The length of one side of the SiC semiconductor layer 102 may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). In the SiC semiconductor layer 102, an active region 106 and an outer region 107 are set. The active region 106 is a region where a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed. The outer region 107 is a region outside the active region 106.

[0019] The semiconductor device 101 includes a gate electrode 108, a gate finger 109, and a source electrode 110 that are respectively formed on the first main surface 103 of the SiC semiconductor layer 102. The gate electrode 108 and the source electrode 110 are respectively formed as an example of the first main surface electrodes. The gate electrode 108 may be referred to as a gate pad, and the source electrode 110 may be referred to as a source pad. In FIG. 1, the gate electrode 108, the gate finger 109, and the source electrode 110 are shown by hatching for clarity. The gate electrode 108, the gate finger 109, and the source electrode 110 may contain aluminum or copper.

[0020] The gate electrode 108 is formed in a rectangular shape in plan view. The gate electrode 108 is drawn from the outer region 107 into the active region 106 so as to cross the boundary region between the outer region 107 and the active region 106 in plan view. The gate finger 109 is formed in the outer region 107. The gate finger 109 is drawn from the gate electrode 108 and extends in a strip shape in the outer region 107.

[0021] The source electrode 110 is formed in the active region 106 at a distance from the gate electrode 108 and the gate fingers 109. The source electrode 110 is formed in a concave shape in plan view so as to cover the concave region partitioned by the gate electrode 108 and the gate fingers 109. A gate voltage is applied to the gate electrode 108 and the gate fingers 109. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source electrode 110. The source voltage may be a reference voltage (for example, GND voltage).

[0022] FIG. 2 is a cross-sectional view of the SiC semiconductor layer 102 and is a cross-sectional view of the MISFET in the first direction X in the active region 106. The first direction X is an arbitrary direction along the first main surface 103 (second main surface 104) of the SiC semiconductor layer 102. Referring to FIG. 2, in this embodiment, the SiC semiconductor layer 102 has a stacked structure including an n + -type SiC semiconductor substrate 121 and an n-type SiC epitaxial layer 122. The SiC semiconductor substrate 121 is formed as the drain region of the MISFET. The SiC epitaxial layer 122 is formed as the drift region of the MISFET.

[0023] The SiC semiconductor substrate 121 forms the second main surface 104 of the SiC semiconductor layer 102. The SiC epitaxial layer 122 forms the first main surface 103 of the SiC semiconductor layer 102. The second main surface 104 of the SiC semiconductor layer 102 may be a ground surface. The thickness of the SiC semiconductor substrate 121 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 121 is preferably 150 μm or less.

[0024] The thickness of the SiC epitaxial layer 122 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 122 is preferably 15 μm or less or 10 μm or less. The n-type impurity concentration of the SiC epitaxial layer 122 is equal to or less than the n-type impurity concentration of the SiC semiconductor substrate 121. The n-type impurity concentration of the SiC epitaxial layer 122 is 1.0×10 15cm -3 1.0×10 or more above 18 cm -3 It may be below this value.

[0025] In this form, the SiC epitaxial layer 122 has a plurality of regions having different n-type impurity concentrations along the normal direction Z of the first main surface 103 of the SiC semiconductor layer 102. Specifically, the SiC epitaxial layer 122 includes a high-concentration region 122a having a relatively high n-type impurity concentration and a low-concentration region 122b having an n-type impurity concentration lower than that of the high-concentration region 122a.

[0026] The high-concentration region 122a is formed in the region on the first main surface 103 side. The low-concentration region 122b is formed in the region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the high-concentration region 122a. The n-type impurity concentration of the high-concentration region 122a is 1×10 16 cm -3 1×10 or more above 18 cm -3 It may be below this value. The n-type impurity concentration of the low-concentration region 122b is 1×10 15 cm -3 1×10 or more above 16 cm -3 It may be below this value. The thickness of the high-concentration region 122a is less than or equal to the thickness of the low-concentration region 122b. Specifically, the thickness of the high-concentration region 122a is less than the thickness of the low-concentration region 122b.

[0027] The semiconductor device 101 includes a drain electrode 123 that covers the second main surface 104 of the SiC semiconductor layer 102. The drain electrode 123 is formed as an example of a second main surface electrode and may be referred to as a drain pad. The maximum voltage that can be applied between the source electrode 110 and the drain electrode 123 during the off state may be 1000V or more and 10000V or less.

[0028] The drain electrode 123 may include at least one of a Ti (titanium) layer, a Ni (nickel) layer, an Au (gold) layer, or an Ag (silver) layer. The drain electrode 123 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer laminated in this order from the second main surface 104 of the SiC semiconductor layer 102.

[0029] The drain electrode 123 may have a four-layer structure including a Ti layer, an Al (aluminum) Cu (alloy of Al and Cu) layer, a Ni layer, and an Au layer laminated in this order from the second main surface 104 of the SiC semiconductor layer 102. The drain electrode 123 may have a four-layer structure including a Ti layer, an AlSi (silicon) Cu (alloy of Al, Si, and Cu) layer, a Ni layer, and an Au layer laminated in this order from the second main surface 104 of the SiC semiconductor layer 102. Instead of the Ti layer, the drain electrode 123 may have a TiN (titanium nitride) layer, or a laminated structure including a Ti layer and a TiN layer.

[0030] The semiconductor device 101 includes a p-type body region 126 formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 in the active region 106. The body region 126 defines the active region 106. That is, in this form, the body region 126 is formed over the entire region of the first main surface 103 of the SiC semiconductor layer 102 that forms the active region 106. The p-type impurity concentration of the body region 126 may be 1×10 17 cm -3 or more and 1×10 20 cm -3 or less.

[0031] The semiconductor device 101 includes a plurality of gate trenches 131 formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 in the active region 106. The plurality of gate trenches 131 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 131 are formed in a strip shape extending along a second direction Y intersecting the first direction X. The plurality of gate trenches 131 are formed in a stripe shape in plan view. The length of each gate trench 131 may be 0.5 mm or more. In this form, the length of each gate trench 131 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0032] Each gate trench 131 penetrates the body region 126 and reaches the SiC epitaxial layer 122. The bottom wall of each gate trench 131 is located within the SiC epitaxial layer 122. Specifically, the bottom wall of each gate trench 131 is located in the high-concentration region 122a of the SiC epitaxial layer 122. With respect to the normal direction Z of the first main surface 103 of the SiC semiconductor layer 102, the depth of the gate trench 131 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm). The depth of the gate trench 131 is preferably 0.5 μm or more and 1.0 μm or less. The width of the gate trench 131 in the first direction X may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm). The width of the gate trench 131 in the first direction X is preferably 0.1 μm or more and 0.5 μm or less.

[0033] A gate insulating layer 134 and a gate electrode layer 135 are formed in each gate trench 131. The gate insulating layer 134 contains silicon oxide. The gate insulating layer 134 may contain other insulating films such as silicon nitride. The gate insulating layer 134 is formed in a film shape along the inner wall surface of the gate trench 131 so that a concave space is defined in the gate trench 131.

[0034] The gate insulating layer 134 includes a first region 134a, a second region 134b, and a third region 134c. The first region 134a is formed along the sidewall of the gate trench 131. The second region 134b is formed along the bottom wall of the gate trench 131. The third region 134c is formed along the first main surface 103 of the SiC semiconductor layer 102. The thickness of the first region 134a is smaller than the thickness of the second region 134b and the thickness of the third region 134c. The thickness of the first region 134a may be not less than 0.01 μm and not more than 0.2 μm. The thickness of the second region 134b may be not less than 0.05 μm and not more than 0.5 μm. The thickness of the third region 134c may be not less than 0.05 μm and not more than 0.5 μm. Of course, a gate insulating layer 134 having a uniform thickness may be formed.

[0035] The gate electrode layer 135 is embedded in the gate trench 131 with the gate insulating layer 134 interposed therebetween. Specifically, the gate electrode layer 135 is embedded in the gate trench 131 so as to fill the concave space partitioned by the gate insulating layer 134. The gate electrode layer 135 is controlled by a gate voltage. The gate electrode layer 135 is electrically connected to the gate electrode 108 and the gate finger 109.

[0036] The gate electrode layer 135 is formed in a wall shape extending along the normal direction Z of the first main surface 103 of the SiC semiconductor layer 102 in a cross-sectional view perpendicular to the direction (second direction Y) in which the gate trench 131 extends. The gate electrode layer 135 may contain conductive polysilicon. The gate electrode layer 135 may contain n-type polysilicon or p-type polysilicon as an example of conductive polysilicon. Instead of conductive polysilicon, the gate electrode layer 135 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy.

[0037] The semiconductor device 101 includes a plurality of source trenches 141 formed on the first main surface 103 of the SiC semiconductor layer 102 in the active region 106. Each source trench 141 is formed in a region between two adjacent gate trenches 131. The plurality of source trenches 141 are each formed in a strip shape extending along the second direction Y. The plurality of source trenches 141 are formed in a stripe shape in a plan view. In the first direction X, the pitch between the centers of adjacent source trenches 141 may be 1.5 μm or more and 3 μm or less.

[0038] Each source trench 141 penetrates the body region 126 and reaches the SiC epitaxial layer 122. The bottom wall of each source trench 141 is located within the SiC epitaxial layer 122. Specifically, the bottom wall of each source trench 141 is located in the high-concentration region 122a. In this form, the depth of the source trench 141 is equal to or greater than the depth of the gate trench 131. Specifically, the depth of the source trench 141 is greater than the depth of the gate trench 131.

[0039] In the direction normal to the first main surface 103 of the SiC semiconductor layer 102, i.e., the Z direction, the depth of the source trench 141 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm). The width of the source trench 141 in the first direction may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm). A source insulating layer 142 and a source electrode layer 143 are formed in each source trench 141.

[0040] The source insulating layer 142 may contain silicon oxide. The source insulating layer 142 is formed in a film shape along the inner wall surface of the source trench 141 so that a concave space is defined within the source trench 141. The source insulating layer 142 includes a first region 142a and a second region 142b. The first region 142a is formed along the side wall of the source trench 141. The second region 142b is formed along the bottom wall of the source trench 141. The thickness of the first region 142a is smaller than the thickness of the second region 142b. The thickness of the first region 142a may be 0.01 μm or more and 0.2 μm or less. The thickness of the second region 142b may be 0.05 μm or more and 0.5 μm or less. Of course, a source insulating layer 142 having a uniform thickness may be formed.

[0041] The source electrode layer 143 is embedded in the source trench 141 with the source insulating layer 142 interposed therebetween. Specifically, the source electrode layer 143 is embedded in the source trench 141 so as to fill the concave space defined by the source insulating layer 142. The source electrode layer 143 is controlled by a source voltage. The thickness of the source electrode layer 143 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0042] The source electrode layer 143 preferably contains polysilicon having properties similar to SiC in terms of material. Thereby, the stress generated in the SiC semiconductor layer 102 can be reduced. The source electrode layer 143 may contain the same conductive material type as the gate electrode layer 135. The source electrode layer 143 may contain conductive polysilicon. The source electrode layer 143 may contain n-type polysilicon or p-type polysilicon as an example of conductive polysilicon. Instead of conductive polysilicon, the source electrode layer 143 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy.

[0043] Thus, the semiconductor device 101 has a trench gate structure and a trench source structure. The trench gate structure includes a gate trench 131, a gate insulating layer 134, and a gate electrode layer 135. The trench source structure includes a source trench 141, a source insulating layer 142, and a source electrode layer 143.

[0044] The semiconductor device 101 includes an n-type source region 153 formed in a region along the sidewall of the gate trench 131 in the surface layer portion of the body region 126. + In this form, a plurality of source regions 153 are formed along the sidewalls on one side and the other side of the gate trench 131 with respect to the first direction X. The n-type impurity concentration of the source region 153 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0045] The plurality of source regions 153 are each formed in a strip shape extending along the second direction Y. The plurality of source regions 153 are formed in a stripe shape in plan view. Each source region 153 is exposed from the sidewalls of the gate trench 131 and the source trench 141.

[0046] The semiconductor device 101 includes a plurality of p-type contact regions 154 formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The p-type impurity concentration of the contact region 154 is higher than the p-type impurity concentration of the body region 126. The p-type impurity concentration of the contact region 154 may be 1.0×10 + cm 18 or more and 1.0×10 -3 cm 21 or less. -3

[0047] ​The plurality of contact regions 154 are formed along the sidewalls of each source trench 141. The plurality of contact regions 154 are formed at intervals along the second direction Y. The plurality of contact regions 154 are formed at intervals along the first direction X from the gate trench 131. Each contact region 154 covers the sidewall and the bottom wall of the source trench 141.

[0048] The semiconductor device 101 includes a plurality of p-type deep well regions 155 formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The deep well region 155 is also referred to as a breakdown voltage adjustment region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the active region 106. Each deep well region 155 is formed along the inner wall of each source trench 141 so as to cover the contact region 154.

[0049] The p-type impurity concentration of the deep well region 155 may be approximately equal to the p-type impurity concentration of the body region 126. The p-type impurity concentration of the deep well region 155 may exceed the p-type impurity concentration of the body region 126. The p-type impurity concentration of the deep well region 155 may be less than the p-type impurity concentration of the body region 126. The p-type impurity concentration of the deep well region 155 may be less than or equal to the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the deep well region 155 may be less than the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the deep well region 155 may be 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less.

[0050] The deep well region 155 forms a pn junction with the SiC semiconductor layer 102 (the high-concentration region 122a of the SiC epitaxial layer 122). From this pn junction, a depletion layer extends toward the region between a plurality of adjacent gate trenches 131. This depletion layer extends toward the region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the gate trench 131.

[0051] The semiconductor device 101 includes an interlayer insulating layer 191 formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 191 selectively covers the active region 106 and the outer region 107. The interlayer insulating layer 191 may contain silicon oxide or silicon nitride. The interlayer insulating layer 191 may contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide.

[0052] The semiconductor device 101 includes the aforementioned source electrode 110 formed on the interlayer insulating layer 191. The source electrode 110 has a stacked structure including a first electrode layer 201, a second electrode layer 202, and a third electrode layer 203 stacked in this order from the first main surface 103 side (interlayer insulating layer 191 side) of the SiC semiconductor layer 102. The first electrode layer 201 may have a single-layer structure including a titanium layer or a titanium nitride layer. The first electrode layer 201 may have a stacked structure including a titanium layer and a titanium nitride layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0053] The thickness of the second electrode layer 202 is larger than the thickness of the first electrode layer 201. The second electrode layer 202 contains a conductive material having a lower resistance value than the resistance value of the first electrode layer 201. The second electrode layer 202 may contain at least one of aluminum, copper, an aluminum alloy, or a copper alloy. The second electrode layer 202 may contain at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-copper alloy. In this form, the second electrode layer 202 contains an aluminum-silicon-copper alloy. The first main surface 103 (the surface of the wafer) of the SiC semiconductor layer 102 has an uneven structure due to the presence or absence of the interlayer insulating layer 191 and the like, and the surface of the second electrode layer 202 has an uneven structure (uneven portion) formed following the above uneven structure.

[0054] The third electrode layer 203 contains at least one of nickel (Ni) and copper (Cu). The third electrode layer 203 may have a single-layer structure including a nickel layer or a copper layer. The third electrode layer 203 may have a laminated structure including a nickel layer and a copper layer. Preferably, the third electrode layer 203 contains a nickel layer. The third electrode layer 203 is harder than the second electrode layer 202. By providing the relatively hard third electrode layer 203 on the second electrode layer 202, for example, it is possible to suppress the source electrode 110 from peeling off or the structure from being damaged during wire bonding. That is, the mechanical strength can be improved.

[0055] For example, with respect to the normal direction Z of the first main surface 103 of the SiC semiconductor layer 102, the thickness of the third electrode layer 203 may be 1 μm or more and 10 μm or less. The surface of the third electrode layer 203 has higher flatness than the second electrode layer 202. Specifically, the difference between the highest position and the lowest position in the thickness direction of the third electrode layer 203 is smaller than the difference between the highest position and the lowest position in the thickness direction of the second electrode layer 202.

[0056] Specifically, the difference between the highest position and the lowest position in the thickness direction of the third electrode layer 203 in one active cell (see FIG. 2) is smaller than the difference between the highest position and the lowest position in the thickness direction of the second electrode layer 202. The highest position is typically the surface position of each layer at the center A of the interlayer insulating layer 191, and the lowest position is typically the surface position of each layer at the intermediate position B between two adjacent interlayer insulating layers 191. However, since the structures formed on the first main surface 103 (the surface of the wafer) of the SiC semiconductor layer 102 are various, the definitions of the highest position and the lowest position are not limited to this.

[0057] The semiconductor device 101 includes an oxide layer 204 formed on the third electrode layer 203. The oxide layer 204 is composed of a metal oxide layer containing a metal oxide. Specifically, the oxide layer 204 is formed by oxidizing the outer surface of the source electrode 110 (the first main surface electrode). That is, the oxide layer 204 contains the oxide of the source electrode 110. More specifically, the oxide layer 204 is formed by oxidizing the third electrode layer 203 and contains at least one oxide of nickel and copper. That is, the oxide layer 204 contains nickel oxide or copper oxide. Preferably, the oxide layer 204 has a thickness less than that of the source electrode 110. Particularly preferably, the oxide layer 204 has a thickness less than that of the third electrode layer 203.

[0058] During wire bonding, when the bonding wire is connected, the oxide layer 204 is removed, and the bonding wire and the third electrode layer 203 are directly connected. In regions other than the connection portion between the bonding wire and the third electrode layer 203, the oxide layer 204 remains even after wire bonding. Therefore, in the state where the bonding wire is connected, the third electrode layer 203 has a coated portion covered by the oxide layer 204 and a connection portion connected to the bonding wire. The connection portion of the third electrode layer 203 is composed of a removed portion where at least a part of the oxide layer 204 is removed, and the bonding wire is electrically and mechanically directly connected.

[0059] Although specific illustrations are omitted, the semiconductor device 101 includes the aforementioned gate electrode 108 and the aforementioned gate finger 109 formed on the interlayer insulating layer 191. Similar to the source electrode 110, the gate electrode 108 has a laminated structure including a first electrode layer 201, a second electrode layer 202, and a third electrode layer 203 laminated in this order from the first main surface 103 side (the interlayer insulating layer 191 side) of the SiC semiconductor layer 102. The aforementioned oxide layer 204 is also formed on the outer surface (the third electrode layer 203) of the gate electrode 108.

[0060] Next, the manufacturing process of the semiconductor device 101 will be described. FIGS. 3A to 3F are diagrams showing an example of the manufacturing method of the semiconductor device 101 shown in FIG. 2.

[0061] First, referring to FIG. 3A, n + -type SiC semiconductor substrate 121 as a base, an n + -type SiC semiconductor wafer 301 is prepared. The SiC semiconductor wafer 301 has a first wafer main surface 302 on one side and a second wafer main surface 303 on the other side. Next, an SiC epitaxial layer 122 is formed on the first wafer main surface 302 of the SiC semiconductor wafer 301. The SiC epitaxial layer 122 is formed by growing SiC from above the first wafer main surface 302 of the SiC semiconductor wafer 301 by an epitaxial growth method.

[0062] In this step, by adjusting the doping amount of the n-type impurity, an SiC epitaxial layer 122 having a high-concentration region 122a and a low-concentration region 122b is formed. Thereby, an SiC semiconductor layer 102 including the SiC semiconductor wafer 301 and the SiC epitaxial layer 122 is formed. The SiC semiconductor layer 102 includes a first main surface 103 and a second main surface 104. Hereinafter, the SiC semiconductor layer 102, the first main surface 103, and the second main surface 104 will be used for description.

[0063] Next, a p-type body region 126 is formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. In this step, the body region 126 is formed over the entire surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The body region 126 is formed by introducing a p-type impurity into the first main surface 103 of the SiC semiconductor layer 102.

[0064] Next, an n +A source region 153 of the type is formed. The source region 153 is formed by introducing n-type impurities into the surface layer portion of the body region 126. In this process, the source region 153 is formed over the entire surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. Next, a hard mask 304 is formed over the first main surface 103 of the SiC semiconductor layer 102. The hard mask 304 may contain silicon oxide. The hard mask 304 may be formed by a CVD (Chemical Vapor Deposition) method or a thermal oxidation treatment method. In this process, the hard mask 304 is formed by the thermal oxidation treatment method.

[0065] Next, referring to FIG. 3B, unnecessary portions of the SiC semiconductor layer 102 are removed by an etching method (e.g., a dry etching method) through a resist mask. In this process, unnecessary portions of the SiC epitaxial layer 122 are removed. Thereby, a gate trench 131 and a source trench 141 are formed. Next, a mask 307 is formed. The mask 307 fills the gate trench 131, the source trench 141, and the outer region 107 to cover the first main surface 103 of the SiC semiconductor layer 102. The mask 307 has a stacked structure including a polysilicon layer 308 and an insulating layer 309. The insulating layer 309 contains silicon oxide.

[0066] The polysilicon layer 308 may be formed by a CVD method. The insulating layer 309 may be formed by a CVD method or a thermal oxidation treatment method. In this process, the insulating layer 309 is formed by a thermal oxidation treatment method for the polysilicon layer 308.

[0067] Next, unnecessary portions of the mask 307 are removed by an etching method (e.g., a dry etching method) through a resist mask. Thereby, the source trench 141 and the outer region 107 are exposed from the mask 307. Next, unnecessary portions of the SiC semiconductor layer 102 are removed by an etching method (e.g., a dry etching method) through the mask 307. Thereby, the source trench 141 and the outer region 107 are further dug down.

[0068] Next, a deep well region 155 is formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The deep well region 155 is formed by introducing p-type impurities into the first main surface 103 of the SiC semiconductor layer 102. The p-type impurities are introduced into the first main surface 103 of the SiC semiconductor layer 102 through the mask 307.

[0069] Next, referring to FIG. 3D, the mask 307 is removed. Next, a contact region 154 is formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The contact region 154 is formed by introducing p-type impurities into the first main surface 103 of the SiC semiconductor layer 102. The p-type impurities are introduced into the first main surface 103 of the SiC semiconductor layer 102 through the resist mask.

[0070] Next, a base insulating layer serving as the base of the gate insulating layer 134 and the source insulating layer 142 is formed on the first main surface 103 of the SiC semiconductor layer 102. The base insulating layer may contain silicon oxide. The base insulating layer may be formed by a CVD method or a thermal oxidation treatment method. Next, a base conductor layer serving as the base of the gate electrode layer 135 and the source electrode layer 143 is formed on the first main surface 103 of the SiC semiconductor layer 102. The base conductor layer fills the gate trench 131, the source trench 141, and the outer region 107 and covers the first main surface 103 of the SiC semiconductor layer 102.

[0071] The base conductor layer may contain polysilicon. The base conductor layer may be formed by a CVD method. The CVD method may be a LP-CVD (Low Pressure-CVD) method. Next, unnecessary portions of the base conductor layer are removed. The unnecessary portions of the base conductor layer are removed until the base insulating layer is exposed. The unnecessary portions of the base conductor layer may be removed by an etch-back method using the base insulating layer as an etch stop layer.

[0072] Unnecessary portions of the base conductor layer may be removed by an etching method (e.g., a wet etching method) through a mask having a predetermined pattern. Thereby, the gate electrode layer 135 and the source electrode layer 143 are formed.

[0073] Next, referring to FIG. 3E, an interlayer insulating layer 191 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 191 collectively covers the active region 106 and the outer region 107. The interlayer insulating layer 191 may contain silicon oxide or silicon nitride. The interlayer insulating layer 191 may be formed by a CVD method. Next, unnecessary portions of the interlayer insulating layer 191 are removed. The unnecessary portions of the interlayer insulating layer 191 may be removed by an etching method (e.g., a dry etching method) through a resist mask.

[0074] Next, unnecessary portions of the base insulating layer exposed from the interlayer insulating layer 191 are removed. The unnecessary portions of the base insulating layer may be removed by an etching method (e.g., a dry etching method). Thereby, the base insulating layer is divided into the gate insulating layer 134 and the source insulating layer 142.

[0075] Next, a base electrode layer serving as a base for the gate electrode 108 and the source electrode 110 is formed on the interlayer insulating layer 191. In this step, a first electrode layer 201 and a second electrode layer 202 are formed. In this step, first, the first electrode layer 201 is formed on the interlayer insulating layer 191. The first electrode layer 201 includes a step of forming a titanium layer and a titanium nitride layer on the interlayer insulating layer 191 in this order from above. The titanium layer and the titanium nitride layer may be formed by a sputtering method. A first electrode layer 201 having a single-layer structure composed of a titanium layer or a titanium nitride layer may be formed.

[0076] Next, the second electrode layer 202 is formed on the first electrode layer 201. The second electrode layer 202 may contain an aluminum-silicon-copper alloy. The second electrode layer 202 may be formed by a sputtering method.

[0077] Next, a drain electrode 123 is formed on the second main surface 104 of the SiC semiconductor layer 102. This step may include a step of forming at least one of a Ti layer, a Ni layer, an Au layer, or an Ag layer as the drain electrode 123. The Ti layer, Ni layer, Au layer, or Ag layer may be formed by a sputtering method. The step of forming the drain electrode 123 may include a step of forming the Ti layer, Ni layer, Au layer, and Ag layer in this order from the second main surface 104 of the SiC semiconductor layer 102. The Ti layer, Ni layer, Au layer, and Ag layer may be formed by a sputtering method.

[0078] Next, referring to FIG. 3F, a third electrode layer 203 is formed on the second electrode layer 202. The third electrode layer 203 may include at least one of nickel and copper. The third electrode layer 203 may have a single-layer structure including a nickel layer or a copper layer. The third electrode layer 203 may have a laminated structure including a nickel layer and a copper layer.

[0079] In this step, first, a back tape 205 is attached to the surface of the drain electrode 123 on the second main surface 104 of the SiC semiconductor layer 102. Next, the third electrode layer 203 is formed on the second electrode layer 202 by a plating method. For example, the plating method may be an electroless plating method. After the formation of the third electrode layer 203, the back tape 205 is peeled off. After the formation of the third electrode layer 203, an oxide layer 204 is formed on the surface of the third electrode layer 203 by oxidation. The step of forming the oxide layer 204 may be included in the step of forming the third electrode layer 203.

[0080] Thereafter, the SiC semiconductor layer 102 (SiC semiconductor wafer 301) is selectively cut along a dicing line (dicing street). As a result, a plurality of semiconductor devices 101 are cut out from one SiC semiconductor wafer 301. For the semiconductor device 101 after dicing, a step of connecting a conductive wire (conductive connection member) such as a bonding wire to the third electrode layer 203 is performed. Through the steps including the above, the semiconductor device 101 is formed.

[0081] Here, the third electrode layer 203 is formed only on the first main surface 103 side by attaching the back tape 205. However, the electroless plating method may be performed without attaching the back tape 205, and electrode layers (third electrode layer 203) may be formed on both the first main surface 103 side and the second main surface 104 side. That is, the electrode layer corresponding to the third electrode layer 203 may cover the drain electrode 123.

[0082] FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device 101 in this case. As shown in the figure, the drain electrode 123 includes a fourth electrode layer 123a and a fifth electrode layer 123b formed in this order from the second main surface 104 of the SiC semiconductor layer 102. The fourth electrode layer 123a corresponds to the drain electrode 123 shown in FIG. 2.

[0083] The fourth electrode layer 123a is made of, for example, the same material as the second electrode layer 202. For example, the fourth electrode layer 123a and the second electrode layer 202 are made of aluminum. The fifth electrode layer 123b is made of the same material as the third electrode layer 203. The fifth electrode layer 123b is formed by the electroless plating method in the same process as the third electrode layer 203.

[0084] The fifth electrode layer 123b may contain at least one of nickel and copper. The fifth electrode layer 123b may have a single-layer structure including a nickel layer or a copper layer. The fifth electrode layer 123b may have a laminated structure including a nickel layer and a copper layer. The surface of the fifth electrode layer 123b may be covered by an oxide layer 204 in the same manner as the surface of the third electrode layer 203. That is, the semiconductor device 101 may include an oxide layer (oxide layer 204 on the second main surface 104 side) that covers the surface of the drain electrode 123 (the surface of the fifth electrode layer 123b) on the second main surface 104 side.

[0085] Next, the configuration of the semiconductor package 401 including the semiconductor device 101 will be described. FIG. 5 is a perspective view showing the semiconductor package 401 in which the aforementioned semiconductor device 101 is incorporated, through the sealing body 407.

[0086] The semiconductor package 401 includes a semiconductor chip 402, a pad portion 403, a heat spreader 404, a plurality (three in this embodiment) of terminals 405, a plurality (three in this embodiment) of conductive wires 406, and a sealing body 407. The aforementioned semiconductor device 101 is applied as the semiconductor chip 402.

[0087] The pad portion 403 includes a metal plate. The pad portion 403 may contain aluminum, copper, or the like. The pad portion 403 is formed in a square shape in plan view. The pad portion 403 has a planar area equal to or larger than the planar area of the semiconductor chip 402. The drain electrode 123 of the semiconductor chip 402 is electrically connected to the pad portion 403 by die bonding.

[0088] The heat spreader 404 is connected to one side of the pad portion 403. In this embodiment, the pad portion 403 and the heat spreader 404 are formed of a single metal plate. A through hole 404a is formed in the heat spreader 404. The through hole 404a is formed in a circular shape. The plurality of terminals 405 are arranged along the side of the pad portion 403 opposite to the heat spreader 404. The plurality of terminals 405 each include a metal plate extending in a strip shape. The terminal 405 may contain aluminum, copper, or the like. The plurality of terminals 405 include a first terminal 405A, a second terminal 405B, and a third terminal 405C.

[0089] The first terminal 405A, the second terminal 405B, and the third terminal 405C are arranged at intervals along the side of the pad portion 403 opposite to the heat spreader 404. The first terminal 405A, the second terminal 405B, and the third terminal 405C extend in a strip shape along a direction orthogonal to their arrangement direction. The second terminal 405B and the third terminal 405C sandwich the first terminal 405A from both sides.

[0090] The plurality of conductive wires 406 may be bonding wires or the like. In this form, the plurality of conductive wires 406 includes a conductive wire 406A, a conductive wire 406B, and a conductive wire 406C. The conductive wire 406A is electrically connected to the gate electrode 108 and the first terminal 405A of the semiconductor chip 402. The conductive wire 406B is electrically connected to the source electrode 110 and the second terminal 405B of the semiconductor chip 402. The conductive wire 406C is electrically connected to the pad portion 403 and the third terminal 405C. When the bonding wire is made of aluminum, it is preferable that at least the surface of the third electrode layer (third electrode layer 203) is made of nickel.

[0091] The encapsulant 407 encapsulates the semiconductor chip 402, the pad portion 403, and the plurality of conductive wires 406 so as to expose a part of the heat spreader 404 and the plurality of terminals 405. The encapsulant 407 includes an encapsulating resin. The encapsulant 407 is formed in a rectangular parallelepiped shape. The form of the semiconductor package 401 is not limited to the form shown in FIG. 5.

[0092] As the semiconductor package 401, an SOP (Small Outline Package), a QFN (Quad Flat Non Lead Package), a DFP (Dual Flat Package), a DIP (Dual Inline Package), a QFP (Quad Flat Package), a SIP (Single Inline Package), or an SOJ (Small Outline J - leaded Package), or various semiconductor packages similar thereto may be applied.

[0093] In the above description, an example in which the functional device (semiconductor element) included in the semiconductor device 101 is a vertical transistor is shown, but the semiconductor device 101 may include a vertical diode. The semiconductor device 101 may include either a transistor or a diode, or may include both a transistor and a diode.

[0094] FIG. 6 is a cross-sectional view of a semiconductor device 101 including a diode. As shown in FIG. 6, this semiconductor device 101 includes a SiC semiconductor layer 501. The SiC semiconductor layer 501 includes an n + -type SiC semiconductor substrate 502 and an n - -type SiC epitaxial layer 503. The impurity density of the SiC semiconductor substrate 502 is, for example, about 1×10 18 cm -3 ~about 1×10 21 cm -3 . The impurity density of the SiC epitaxial layer 503 is, for example, about 5×10 14 cm -3 ~about 5×10 16 cm -3 . The SiC epitaxial layer 503 may have a buffer layer formed on the SiC semiconductor substrate 502 and a drift layer formed on the buffer layer.

[0095] The semiconductor device 101 includes a cathode electrode 504 that covers the back surface ((000-1)C plane) of the SiC semiconductor substrate 502. The cathode electrode 504 is formed as an example of a second main surface electrode. The cathode electrode 504 covers the entire back surface of the SiC semiconductor substrate 502. The cathode electrode 504 is connected to a cathode terminal.

[0096] The semiconductor device 101 includes a field insulating film 505 formed on the surface ((0001)Si plane) of the SiC epitaxial layer 503. The field insulating film 505 is made of SiO2 (silicon oxide), but may be made of other insulators such as silicon nitride (SiN).

[0097] The semiconductor device 101 includes an anode electrode 506 formed on the field insulating film 505. The anode electrode 506 is formed as an example of a first main surface electrode. The anode electrode 506 is connected to an anode terminal. The anode electrode 506 includes a first electrode layer 507 and a second electrode layer 508. The first electrode layer 507 is formed on the SiC epitaxial layer 503 and the field insulating film 505. The second electrode layer 508 is formed on the first electrode layer 507.

[0098] For example, the first electrode layer 507 may contain at least one of aluminum, copper, an aluminum alloy, or a copper alloy. The first electrode layer 507 may contain at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-copper alloy.

[0099] The second electrode layer 508 may contain at least one of nickel and copper. The second electrode layer 508 may have a single-layer structure including a nickel layer or a copper layer. The second electrode layer 508 may have a laminated structure including a nickel layer and a copper layer. The second electrode layer 508 preferably contains a nickel layer. The second electrode layer 508 is harder than the first electrode layer 507. By providing the relatively hard second electrode layer 508 on the first electrode layer 507, for example, it is possible to suppress the anode electrode 506 from peeling off or the structure from being damaged during wire bonding. That is, the mechanical strength can be improved.

[0100] The semiconductor device 101 includes an oxide layer 509 formed on the second electrode layer 508. The oxide layer 509 is composed of a metal oxide layer containing a metal oxide. Specifically, the oxide layer 509 is formed by oxidizing the outer surface of the anode electrode 506 (the first main surface electrode). That is, the oxide layer 509 contains the oxide of the anode electrode 506. More specifically, the oxide layer 509 is formed by oxidizing the second electrode layer 508 and contains at least one oxide of the nickel layer and the copper layer. That is, the oxide layer 509 contains nickel oxide or copper oxide. The oxide layer 509 preferably has a thickness less than the thickness of the anode electrode 506. The oxide layer 509 particularly preferably has a thickness less than the thickness of the second electrode layer 508.

[0101] During wire bonding, when the bonding wire is connected, the oxide layer 509 is removed, and the bonding wire is directly connected to the second electrode layer 508. In regions other than the connection portion between the bonding wire and the second electrode layer 508, the oxide layer 204 remains even after wire bonding. Therefore, in a state where the bonding wire is connected, the second electrode layer 508 has a coated portion covered by the oxide layer 509 and a connection portion connected to the bonding wire. The connection portion of the second electrode layer 508 is composed of a removed portion where at least a part of the oxide layer 509 is removed, and the bonding wire is electrically and mechanically directly connected.

[0102] The semiconductor device 101 includes a p-type JTE (Junction Termination Extension) structure 510 (impurity region) formed near the surface (surface layer portion) of the SiC epitaxial layer 503. The JTE (Junction Termination Extension) structure 510 is formed so as to be in contact with the first electrode layer 507 of the anode electrode 506.

[0103] As described above, the semiconductor device according to the present embodiment has the following characteristics. The semiconductor device 101 according to one aspect of the present invention is a semiconductor device including a vertical power semiconductor element, as shown in FIG. 2. The semiconductor device 101 includes a SiC semiconductor layer 102, a first electrode layer (second electrode layer 202), a second electrode layer (third electrode layer 203), a third electrode layer (drain electrode 123), and an oxide layer 204.

[0104] The SiC semiconductor layer 102 has a first main surface 103 and a second main surface 104 opposite to the first main surface 103, and contains SiC as a main component. The first electrode layer (second electrode layer 202) is formed on the first main surface 103 side of the SiC semiconductor layer 102. The second electrode layer (third electrode layer 203) is formed on the first electrode layer (second electrode layer 202) and is electrically connected to the first terminal of the vertical power semiconductor element. The second electrode layer (third electrode layer 203) is harder than the first electrode layer (second electrode layer 202).

[0105] The third electrode layer (drain electrode 123) is formed on the second main surface 104 side of the SiC semiconductor layer 102 and is electrically connected to the second terminal of the vertical power semiconductor device. The oxide layer 204 is formed on the surface of the second electrode layer (third electrode layer 203). According to this structure, the second electrode layer (third electrode layer 203) can suppress, for example, the destruction of the structure during wire bonding. Therefore, the mechanical strength can be improved.

[0106] For example, the second electrode layer (third electrode layer 203) is made of nickel (Ni) or copper (Cu), and the oxide layer 204 is made of an oxide of nickel or copper. For example, the vertical power semiconductor device may be a vertical transistor, the first terminal may be a source terminal, and the second terminal may be a drain terminal. The vertical power semiconductor device may be a vertical transistor, the first terminal may be a gate terminal, and the second terminal may be a drain terminal. As shown in FIG. 6, the vertical power semiconductor device may be a vertical diode, and one of the first terminal and the second terminal may be an anode terminal and the other may be a cathode terminal.

[0107] For example, the second electrode layer (third electrode layer 203) is formed by a plating layer. For example, as shown in FIG. 4, the semiconductor device 101 further includes a fourth electrode layer (fifth electrode layer 123b). The fourth electrode layer (fifth electrode layer 123b) is formed on the surface of the third electrode layer (fourth electrode layer 123a) on the side opposite to the SiC semiconductor layer 102 side. The fourth electrode layer (fifth electrode layer 123b) is harder than the third electrode layer (fourth electrode layer 123a). For example, as shown in FIG. 5, the semiconductor package according to one aspect of the present invention includes the semiconductor device 101 (semiconductor chip 402) and a bonding wire (conductive wire 406) connected to the second electrode layer (third electrode layer 203).

[0108] A method for manufacturing a semiconductor device according to an aspect of the present invention is a method for manufacturing a semiconductor device 101 including a vertical power semiconductor element. This method for manufacturing a semiconductor device includes a first step, a second step, and a third step. In the first step, a first electrode layer (second electrode layer 202) is formed on the first main surface 103 side of the SiC semiconductor layer 102. In the second step, a second electrode layer (third electrode layer 203) that is electrically connected to the first terminal of the vertical power semiconductor element and is harder than the first electrode layer (second electrode layer 202) is formed on the first electrode layer (second electrode layer 202). In the third step, a bonding wire (conductive wire 406) is connected to the second electrode layer (third electrode layer 203). According to this manufacturing method, the second electrode layer (third electrode layer 203) can suppress the destruction of the structure during wire bonding. Therefore, the mechanical strength can be improved.

[0109] For example, in the step (second step) of forming the second electrode layer (third electrode layer 203), the second electrode layer (third electrode layer 203) is formed by a plating method. In the manufacturing method, the step of connecting the bonding wire (conductive wire 406) (third step) may be included in the method for manufacturing a semiconductor package.

[0110] As described above, the semiconductor device according to one or more aspects has been described based on the embodiments, but the present disclosure is not limited to these embodiments. As long as the gist of the present disclosure is not deviated from, various modifications conceivable by those skilled in the art, the forms implemented in the embodiments, and the forms constructed by combinations of components in different embodiments are also included in the scope of the present disclosure.

[0111] In addition, various changes, replacements, additions, omissions, etc. can be made to the above embodiments within the scope of the claims or their equivalents. The present invention can be applied to semiconductor devices, semiconductor packages, etc. as industrial applications.

[0112] Examples of features extracted from this specification and the drawings are shown below. Hereinafter, a semiconductor device, a semiconductor package, and a method for manufacturing them that can improve mechanical strength are provided. Hereinafter, the alphanumeric characters in parentheses represent corresponding components and the like in the foregoing embodiments, but are not intended to limit the scope of each item to the embodiments.

[0113] [A1] A semiconductor device (101) including a vertical power semiconductor element, having a first main surface (103) and a second main surface (104) opposite to the first main surface (103), a semiconductor layer (102, 501) containing SiC as a main component, a first electrode layer (202, 507) formed on the first main surface (103) side of the semiconductor layer (102, 501), a second electrode layer (203, 508) formed on the first electrode layer (202, 507) and electrically connected to a first terminal of the vertical power semiconductor element, and being harder than the first electrode layer (202, 507), and a third electrode layer (123, 123a, 123b, 504) formed on the second main surface (104) side of the SiC semiconductor layer (102, 501) and electrically connected to a second terminal of the vertical power semiconductor element, and an oxide layer (204, 509) formed on the surface of the second electrode layer (203, 508).

[0114] [A2] The semiconductor device (101) according to A1, wherein the second electrode layer (203, 508) is made of nickel or Cu, and the oxide layer (204, 509) is made of an oxide of nickel or Cu.

[0115] [A3] The semiconductor device (101) according to A1 or A2, wherein the vertical power semiconductor element is a vertical transistor, the first terminal is a source terminal, and the second terminal is a drain terminal.

[0116] [A4] The semiconductor device (101) according to any one of A1 to A3, wherein the second electrode layer (203, 508) is formed by plating.

[0117] [A5] The semiconductor device (101) further includes a fourth electrode layer (123b) that is formed on a surface of the third electrode layer (123, 123a, 123b, 504) opposite to the SiC semiconductor layer (102, 501) side and is harder than the third electrode layer (123, 123a, 123b, 504). The semiconductor device (101) according to any one of A1 to A4.

[0118] [A6] A semiconductor package (401) including the semiconductor device (101) according to any one of A1 to A5 and a bonding wire (406) connected to the second electrode layer (203, 508).

[0119] [A7] A method of manufacturing a semiconductor device (101) including a vertical power semiconductor element, the method including: forming a first electrode layer (202, 507) on a first main surface (103) side of a semiconductor layer (102, 501) containing SiC as a main component; and forming, on the first electrode layer (202, 507), a second electrode layer (203, 508) that is electrically connected to a first terminal of the vertical power semiconductor element and is harder than the first electrode layer (202, 507); and connecting a bonding wire (406) to the second electrode layer (203, 508).

[0120] [A8] In the step of forming the second electrode layer (203, 508), the second electrode layer (203, 508) is formed by plating. The method of manufacturing a semiconductor device (101) according to A7.

[0121] [B1] A semiconductor device (101) including a semiconductor layer (102, 501) having a first main surface (103) on one side and a second main surface (104) on the other side, a first electrode (202, 507) covering the first main surface (103), and a second electrode (108, 110, 506) including a second electrode (203, 508) having a hardness higher than that of the first electrode (202, 507) and covering the first electrode (202, 507), and an oxide layer (204, 509) covering the second electrode (108, 110, 506).

[0122] [B2] The semiconductor device (101) according to B1, wherein the oxide layer (204, 509) is composed of a metal oxide layer containing a metal oxide.

[0123] [B3] The semiconductor device (101) according to B1 or B2, wherein the oxide layer (204, 509) contains an oxide of the second electrode (108, 110, 506).

[0124] [B4] The semiconductor device (101) according to any one of B1 to B3, wherein the oxide layer (204, 509) is thinner than the second electrode (108, 110, 506).

[0125] [B5] The semiconductor device (101) according to any one of B1 to B4, wherein the oxide layer (204, 509) is thinner than the second electrode (203, 508).

[0126] [B6] The semiconductor device (101) according to any one of B1 to B5, wherein the oxide layer (204, 509) contains an oxide of the second electrode (203, 508).

[0127] [B7] The semiconductor device (101) according to B6, wherein the second electrode (203, 508) contains at least one of nickel and copper, and the oxide layer (204, 509) contains an oxide of at least one of nickel and copper.

[0128] [B8] The semiconductor device (101) according to any one of B1 to B7, wherein the second electrode (203, 508) is composed of a plating layer.

[0129] [B9] The semiconductor device (101) according to any one of B1 to B8, wherein the semiconductor layer (102, 501) mainly contains a wide bandgap semiconductor.

[0130] [B10] The semiconductor device (101) according to any one of B1 to B9, wherein the semiconductor layer (102, 501) mainly contains SiC.

[0131] The semiconductor device (101) according to any one of B1 to B10, further including a functional device formed in the semiconductor layer (102, 501), wherein the second electrode (108, 110, 506) is electrically connected to the functional device.

[0132] The semiconductor device (101) according to B11, wherein the functional device includes a transistor having a source, and the second electrode (108, 110, 506) includes a source electrode (110) electrically connected to the source of the transistor.

[0133] The semiconductor device (101) according to B11, wherein the functional device includes a transistor having a gate, and the second electrode (108, 110, 506) includes a gate electrode (108) electrically connected to the gate of the transistor.

[0134] The semiconductor device (101) according to B11, wherein the functional device includes a diode having an anode, and the second electrode (108, 110, 506) includes an anode electrode (506) electrically connected to the anode of the diode.

[0135] The semiconductor device (101) according to any one of B1 to B14, further including a second main surface electrode (123, 123a, 123b, 504) covering the second main surface (104).

[0136] The semiconductor device (101) according to B15, wherein the second main surface electrode (123, 123a, 123b, 504) includes a third electrode (123a) covering the second main surface (104), and a fourth electrode (123b) having a hardness higher than that of the third electrode (123a) and covering the third electrode (123a).

[0137] A semiconductor package (401) including the semiconductor device (101) according to any one of B1 to B16, and a bonding wire (406) electrically connected to the second electrode (108, 110, 506).

[0138] [B18] The bonding wire (406) penetrates through the oxide layers (204, 509) and is electrically and mechanically connected to the second electrodes (203, 508). The second electrodes (108, 110, 506) have a coated portion covered by the oxide layers (204, 509) and a connection portion directly connected to the bonding wire (406). The semiconductor package (401) according to B17.

[0139] [B19] A step of preparing a semiconductor layer (102, 501) having a main surface (103), forming a first electrode (202, 507) on the main surface (103), and forming a second electrode (203, 508) having a higher hardness than the first electrode (202, 507) on the first electrode (202, 507), thereby forming a second electrode (108, 110, 506) including the first electrode (202, 507) and the second electrode (203, 508) on the main surface (103); and a step of forming an oxide layer (204, 509) covering the outer surface of the second electrode (108, 110, 506). A method for manufacturing a semiconductor device (101).

[0140] [B20] A method for manufacturing a semiconductor package (401), including the method for manufacturing a semiconductor device (101) according to B19 and a step of connecting a bonding wire (406) to the second electrode (108, 110, 506).

Explanation of reference numerals

[0141] 101 Semiconductor device 102 SiC semiconductor layer 103 First main surface 104 Second main surface 108 Gate electrode (first main surface electrode) 110 Source electrode (first main surface electrode) 123 Drain electrode (second main surface electrode) 123a Fourth electrode layer 123b Fifth electrode layer 201 First electrode layer 202 Second electrode layer 203 Third electrode layer 204 Oxide layer 401 Semiconductor package 402 Semiconductor chip (semiconductor device) 406 Conductive wire (bonding wire) 501 SiC semiconductor layer 504 Cathode electrode (second main surface electrode) 506 Anode electrode (first main surface electrode) 507 First electrode layer 508 Second electrode layer 509 Oxide layer

Claims

1. A semiconductor layer having a first main surface on one side and a second main surface on the other side, An interlayer insulating layer that selectively covers the semiconductor layer on the first main surface, A first electrode that covers the first main surface and the interlayer insulating layer, and a first main surface electrode including a second electrode that has a higher hardness than the first electrode and covers the first electrode, An oxide layer that covers the first main surface electrode, The first main surface has an uneven structure caused by the presence or absence of the interlayer insulating layer, The surface of the first electrode includes uneven portions formed following the uneven structure, A semiconductor device in which the surface of the second electrode has higher flatness than the surface of the first electrode.

2. The semiconductor device according to claim 1, wherein the oxide layer is composed of a metal oxide layer containing a metal oxide.

3. The semiconductor device according to claim 1 or 2, wherein the oxide layer contains an oxide of the first main surface electrode.

4. The semiconductor device according to any one of claims 1 to 3, wherein the oxide layer is thinner than the first main surface electrode.

5. The semiconductor device according to any one of claims 1 to 4, wherein the oxide layer is thinner than the second electrode.

6. The semiconductor device according to any one of claims 1 to 5, wherein the oxide layer contains an oxide of the second electrode.

7. The second electrode contains at least one of nickel and copper, The semiconductor device according to claim 6, wherein the oxide layer contains an oxide of at least one of nickel and copper.

8. The semiconductor device according to any one of claims 1 to 7, wherein the second electrode is composed of a plating layer.

9. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor layer mainly contains a wide-bandgap semiconductor.

10. The semiconductor device according to any one of claims 1 to 9, wherein the semiconductor layer mainly contains SiC.

11. Further including a functional device formed in the semiconductor layer, The semiconductor device according to any one of claims 1 to 10, wherein the first main surface electrode is electrically connected to the functional device.

12. The functional device includes a transistor having a source, The semiconductor device according to claim 11, wherein the first main surface electrode includes a source electrode electrically connected to the source of the transistor.

13. The functional device includes a transistor having a gate, The semiconductor device according to claim 11, wherein the first main surface electrode includes a gate electrode electrically connected to the gate of the transistor.

14. The functional device includes a diode having an anode, The semiconductor device according to claim 11, wherein the first main surface electrode includes an anode electrode electrically connected to the anode of the diode.

15. The semiconductor device according to any one of claims 1 to 14, further including a second main surface electrode covering the second main surface.

16. The semiconductor device according to claim 15, wherein the second main surface electrode includes a third electrode covering the second main surface and a fourth electrode having a hardness higher than that of the third electrode and covering the third electrode.

17. A semiconductor package including the semiconductor device according to any one of claims 1 to 16, and a bonding wire electrically connected to the first main surface electrode.

18. The bonding wire penetrates the oxide layer and is electrically and mechanically connected to the second electrode, The semiconductor package according to claim 17, wherein the first main surface electrode has a covered portion covered by the oxide layer and a connection portion directly connected to the bonding wire.

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