Optoelectronic semiconductor chip and method for manufacturing the same

Abstract

The invention relates to an optoelectronic semiconductor chip (1) comprising a semiconductor body (3) having an n-doped region (3.1), a p-doped region (3.2) optionally including a p-type current distribution layer (4), and an active region (3.3) arranged between the n-doped region (3.1) and the p-doped region (3.2). The optoelectronic semiconductor chip further comprises a first dielectric layer (6) arranged on the p-doped region (3.2) and a mirror layer (7) comprising a metal arranged on the first dielectric layer (6), the first dielectric layer (6) electrically insulating the mirror layer (7) from at least the p-doped region (3.2). A second dielectric layer (8) is disposed on the mirror layer (7) and a metallization layer (9) is disposed on the second dielectric layer (8), said metallization layer (9) being electrically insulated from the mirror layer (7) and in electrical contact with the p-doped region (3.2). An n-type contact layer (15) is deposited on the n-doped region (3.1) on the side opposite the p-doped region (3.2).

Description

Technical Field

[0001] This application relates to optoelectronic devices and methods for manufacturing the same.

[0002] Optoelectronic semiconductor chips are provided, in particular optoelectronic semiconductor chips having an edge length of less than 40 μm. Such optoelectronic semiconductor chips can be referred to as optoelectronic semiconductor μ-chips, for example.

Background Art

[0003] In some embodiments, such μ-chips may not be encapsulated and thus may include many exposed sides. Due to the exposed sides, the chip has more stringent requirements in the encapsulation of components that are prone to corrosion. In particular, a reflective metal layer (which may also act as an electrode) plays a special role. When the reflective metal layer is used as an electrode, it may corrode at different rates depending on the applied potential. High-reflection mirror electrodes formed of silver, aluminum, or gold are widely used in semiconductor chips. However, highly reflective silver has the property of moving particularly easily when connected to the p-potential of the μ-chip under humidity and electric field conditions. The term "moving" can be understood as an electrochemical process in which metal ions move from a first metal layer to a second layer. In particular, in the case of a μ-chip, silver in the silver layer becomes ionic when connected to the p-potential, and the ions in the silver layer begin to move to the layer connected to the n-potential and solidify there. Therefore, the risk of short circuit in the μ-chip increases.

[0004] In a suitable semiconductor structure, the advantages of a specific metal having a very high reflectivity can be combined with electrochemical stabilization, but such electrochemical stabilization is complex and very costly.

[0005] Some optoelectronic semiconductor components are known from, for example, two unpublished German applications DE102020124258.1 and DE102021202026.7.

[0006] One of the objects to be solved is to provide an optoelectronic semiconductor chip that exhibits improved aging behavior and / or is simple and inexpensive to manufacture. SUMMARY OF THE INVENTION

[0007] This requirement and other requirements are satisfied by an optoelectronic semiconductor chip having the features of claim 1 and a method for manufacturing an optoelectronic semiconductor chip having the features of claim 11. Embodiments and further developments of the invention are described in the dependent claims.

[0008] The optoelectronic semiconductor chip is, for example, a radiation-emitting optoelectronic semiconductor chip. For example, the semiconductor chip may be a light-emitting diode (LED) chip or a laser chip. The optoelectronic semiconductor chip may generate light during operation. In particular, the optoelectronic semiconductor chip is capable of generating light in the spectral region from UV radiation to light in the infrared region, particularly visible light. Alternatively, the optoelectronic semiconductor chip may be a semiconductor chip for radiation detection, such as a photodiode.

[0009] The optoelectronic semiconductor chip may include, for example, an edge length of less than 100 μm, or less than 40 μm, particularly less than 10 μm. Thus, the optoelectronic semiconductor chip can be, for example, a μLED (LED for light-emitting devices, μLED for micro LEDs) or a μLED chip.

[0010] According to some embodiments, an optoelectronic semiconductor chip includes a semiconductor body having an n-doped region, a p-doped region optionally including a p-type current spreading layer, and an active region disposed between the n-doped region and the p-doped region. The optoelectronic semiconductor chip further includes a first dielectric layer disposed on the p-doped region and a mirror layer including metal disposed on the first dielectric layer. Thereby, the first dielectric layer electrically insulates the mirror layer from at least the p-doped region and thus from the optional p-type current spreading layer.

[0011] A second dielectric layer is further disposed on the mirror layer and a metallization layer is disposed on the mirror layer. The metallization layer is electrically insulated from the mirror layer and makes electrical contact with the p-doped region and thus with the optional p-type current spreading layer. Thus, the mirror layer is electrically insulated from the optional p-type current spreading layer, from the metallization layer, in particular from the p-doped region, by the first and second dielectric layers. In other words, the mirror layer is electrically insulated in particular from the p-potential to which the semiconductor chip can be connected during operation of the semiconductor chip.

[0012] In addition thereto, the optoelectronic semiconductor chip includes an n-type contact layer deposited on the n-doped region on the side opposite to the p-doped region, so that the optoelectronic semiconductor chip is in the form of a vertically contactable semiconductor chip that can be contacted in particular on two opposite sides of the semiconductor chip.

[0013] Thus, in some embodiments, the optoelectronic semiconductor chip can be electrically connected on two opposite sides of the semiconductor chip by the metallization layer and the n-type contact layer, thus forming a vertically contactable semiconductor chip.

[0014] In some embodiments, the mirror layer is electrically connected to the n-doped region and / or the n-type contact layer, and thus, the mirror layer is electrically connected to an n-potential that can be connected to the semiconductor chip during operation of the semiconductor chip. Thus, the mirror layer can be at the n-potential, but the mirror layer can also not be electrically connected to the n-potential and can thus be at a floating potential.

[0015] The core of the invention is, in particular, to reduce the migration of the mirror layer by avoiding the connection of the mirror layer to a p-electrode or a p-potential that can be connected to the semiconductor chip during operation of the semiconductor chip.

[0016] In some embodiments, at least the p-doped region, the active region, and optionally a part of the n-doped region form a first mesa structure, and optionally at least a part of the n-doped region forms a second mesa structure, and the second mesa structure protrudes laterally from the first mesa structure. In the case of the first and second mesa structures, the first mesa structure is arranged on the second mesa structure, in particular at the center of the virtual upper surface of the second mesa structure. The cross-sectional areas of the first and second mesa structures can, for example, each include a trapezoidal shape.

[0017] In some embodiments, the first dielectric layer is arranged on the p-doped region, in particular on an optional p-type current distribution layer, and on the side surface of the semiconductor body. In some embodiments, the first dielectric layer is arranged on the p-doped region, in particular on the p-type current distribution layer, and on all side surfaces of the semiconductor body. Thereby, the dielectric layer can cover only a part or the whole of the side surface(s). In particular, the first dielectric layer is arranged on the p-doped region, in particular on the p-type current distribution layer, and follows the outer shape of at least one side surface of the first mesa structure. By the term "follows", it can be understood that the dielectric layer is shaped to the outer shape of the side surface(s) of the semiconductor body, in particular to the side surface(s) of the first mesa structure.

[0018] In some embodiments, the mirror layer is disposed on a first dielectric layer on the side surface(s) of the semiconductor body. Thereby, the mirror layer can cover only a part of the first dielectric layer on the side surface(s) of the semiconductor body or the entire first dielectric layer on the side surface(s) of the semiconductor body. In particular, the mirror layer is disposed on the first dielectric layer on the side surface(s) of the first mesa structure and follows the outer shape of the first dielectric layer on the side surface(s) of the first mesa structure.

[0019] In some embodiments, the second dielectric layer follows the outer shape of at least one side surface of the semiconductor body, in particular the outer shape of at least one side surface of the first mesa structure. Thereby, the second dielectric layer can be disposed directly on the side surface(s) of the semiconductor body / first mesa structure, on the first dielectric layer on the side surface(s) of the semiconductor body / first mesa structure, or on the mirror layer disposed on the first dielectric layer on the side surface(s) of the semiconductor body / first mesa structure.

[0020] The mirror layer can comprise or consist of a metal such as, for example, silver, gold, and / or aluminum. In particular, the mirror layer can be characterized by the fact that it has a high reflectivity for light generated within the active region of the semiconductor body or for light to which the active region of the semiconductor body is sensitive. The mirror layer can in particular be configured to reflect light generated within the active region of the semiconductor body and exiting the active region against the main emission direction of the semiconductor chip in the direction of the main emission direction.

[0021] The p-type current distribution layer is optional so that the first dielectric layer can be disposed directly on the p-doped region. The p-type current distribution layer can comprise or consist of a conductive material that is at least partially optically transparent, for example, for light generated within the active region of the semiconductor body or for light to which the active region of the semiconductor body is sensitive. In particular, the p-type current distribution layer can comprise or consist of indium tin oxide (ITO).

[0022] In some embodiments, the first dielectric layer can be formed as a composite Bragg mirror.

[0023] In some embodiments, the metallization layer includes at least contact vias that pass through the first and second dielectric layers. The contact vias enable the metallization layer on the second dielectric layer to be in electrical contact with the p-doped region and thus optionally the p-type current spreading layer.

[0024] In some embodiments, the contact vias are disposed centrally with respect to the semiconductor body or on the edge of the semiconductor body. In other words, access of the metallization layer to the p-doped region of the semiconductor body can be disposed centrally with respect to the semiconductor body through the dielectric layer and the mirror layer, or can be laterally offset from the center of the mirror layer through the dielectric layer. In particular, when the contact vias are disposed on the edge of the semiconductor body, an area advantage can be obtained, while when the contact vias are disposed centrally with respect to the semiconductor body, an advantage regarding uniform emission of light generated within the active region of the semiconductor body can be obtained.

[0025] The metallization layer can comprise or consist of a conductive material such as, for example, platinum, rhodium, titanium, tungsten, gold, and / or aluminum. In particular, the metallization layer can be formed as a layer of comparable thinness on the second dielectric layer. The choice of material used for the metallization layer, in particular the choice of the contact vias of the metallization layer, can affect the need for a p-type current spreading layer. If the metallization layer does not include aluminum but includes, for example, rhodium, the p-type current spreading layer may be redundant and the metallization layer, in particular the contact vias of the metallization layer, can be in direct electrical contact with the p-doped region.

[0026] In some embodiments, the metallization layer can comprise or consist of a transparent and conductive material, such as a transparent conductive film (TCF). A TCF is a thin film of an optically transparent and conductive material. Indium tin oxide (ITO) is the most widely used, but alternatives include a wider spectrum of transparent conductive oxides (TCOs), conductive polymers, metal grids and random metal networks, carbon nanotubes (CNTs), graphene, nanowire meshes, and ultrathin metal films. A transparent conductive oxide (TCO) is, for example, a doped metal oxide fabricated using a polycrystalline or amorphous microstructure. Typical properties of a TCO are that the transmittance of incident light is greater than 80%, and the electrical conductivity is higher than 10 3 S / cm.

[0027] In some embodiments, the metallization layer is configured to be reflective or includes a reflective coating. The metallization layer can be formed particularly within the active region of the semiconductor body and configured to reflect light that exits the active region against the main emission direction of the semiconductor chip and is not reflected by the mirror layer in the direction of the main emission direction.

[0028] In some embodiments, the mirror layer includes one of a rectangular, polygonal, or circular shape having an opening disposed at the center of the semiconductor body when viewed from above the mirror layer, and a rectangular, polygonal, or circular shape having a recess on an edge of the mirror layer.

[0029] Thus, the mirror layer can include a ring shape having an opening at its center, a rectangle or polygon, or a rectangle or polygon having a recess on one of its edges (a corner is missing).

[0030] In some embodiments, the n-doped region includes an n-type current distribution layer. In some embodiments, the n-type contact layer comprises or consists of at least a partially transparent conductive material.

[0031] A method for manufacturing an optoelectronic semiconductor chip includes the step of providing a semiconductor body on a growth substrate, the semiconductor body including an n-doped region, a p-doped region optionally including a p-type current spreading layer, and an active region disposed between the n-doped region and the p-doped region; the step of depositing a first dielectric layer on the p-doped region and a mirror layer including metal on the first dielectric layer, the first dielectric layer electrically insulating the mirror layer from at least the p-doped region and from the optional p-type current spreading layer; the step of depositing a second dielectric layer on the mirror layer; the step of depositing a metallization layer on the second dielectric layer, the metallization layer being electrically insulated from the mirror layer and electrically contacting the p-doped region and thus the optional p-type current spreading layer; and the step of depositing an n-type contact layer on the n-doped region on the side opposite the p-doped region.

[0032] In some embodiments, the step of providing the semiconductor body includes forming a first mesa structure, for example, by an etching process. Thereby, the first mesa structure can include at least the p-doped region and the active region and optionally a part of the n-doped region.

[0033] In some embodiments, the method further includes the step of forming a second mesa structure, for example, by an etching process. Thereby, the second mesa structure can include at least a part of the n-doped region and can protrude laterally from the first mesa structure. The first mesa structure can be referred to as, for example, a "shallow mesa", and the second mesa structure can be referred to as a "deep mesa".

[0034] In some embodiments, depositing the first dielectric layer includes structuring the first dielectric layer such that at least one via through the first dielectric layer is provided in a region where the first dielectric layer is in direct contact with the n-doped region and / or in a region where the first dielectric layer is in direct contact with the p-doped region and / or the p-type current distribution layer. Structuring the first dielectric layer in a region where the first dielectric layer is in direct contact with the n-doped region can serve to provide a via through the first dielectric layer, for example, so that the mirror layer can be electrically connected to the n-doped region. However, structuring the first dielectric layer in a region where the first dielectric layer is in direct contact with the p-doped region and / or the p-type current distribution layer serves to provide a via through the first dielectric layer so that the metallization layer can be electrically connected to the p-doped region and / or the p-type current distribution layer. The structuring step can include, for example, a photolithography process and / or an etching process, particularly a dielectric wet etching process.

[0035] In some embodiments, depositing the mirror layer includes electrically connecting the mirror layer and the n-doped region. Thus, the mirror layer can be deposited on the structured dielectric layer such that the via through the first dielectric layer in the region where the first dielectric layer is in direct contact with the n-doped region is filled with the material of the mirror layer and thus is in electrical contact with the n-doped region.

[0036] In some embodiments, depositing the metallization layer includes etching vias through the second dielectric layer and / or the first dielectric layer and / or the p-type current distribution layer. By etching vias through the second dielectric layer and / or the first dielectric layer and / or the p-type current distribution layer, contact vias of the metallization layer can be formed through the second dielectric layer and / or the first dielectric layer and / or the p-type current distribution layer to be in electrical contact with the p-doped region and / or the p-type current distribution layer.

[0037] The step of depositing the metallization layer can include the target deposition of the metallization layer or the area deposition of the metallization layer, and the subsequent structuring of the area-deposited metallization layer.

[0038] In some embodiments, the method further includes the step of depositing a release layer on the metallization layer. The release layer can in particular be a temporary layer and can for example be easily removed by dissolution.

[0039] In some embodiments, the step of depositing the release layer includes forming a through-hole passing through the release layer in the area of the release layer, and the release layer is in direct contact with the first and / or second dielectric layer. The through-hole passing through the release layer can in particular serve to provide a subsequent support structure for the semiconductor chip.

[0040] In some embodiments, the method further includes the step of adhering or soldering the release layer onto a carrier so that the through-hole is filled with an adhesive or soldering material. In particular, an existing intermediate product is encapsulated in the adhesive or soldering material and can thus be re-bonded. The adhesive or soldering material in the trough hole can in particular form a subsequent support structure for the semiconductor chip.

[0041] In some embodiments, the method further includes the step of removing the growth substrate and / or the step of removing a part of the n-doped region until at least the release layer is partially exposed. Thereby, the release layer is at least partially exposed and the release layer can be removed, for example, by dissolution. The step of removing a part of the n-doped region can include, for example, the steps of thinning, grinding, polishing, chemical mechanical polishing (CMP), and / or etching the n-doped region.

[0042] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. It is schematically shown below.

Brief Description of the Drawings

[0043]

Figure 1

Figure 2

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Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 5E

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Figure 7

Figure 8A

Figure 8B

Figure 8C

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Figure 10

Figure 11

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Figure 17

DETAILED DESCRIPTION OF THE INVENTION

[0044] Next, the present disclosure will be described in more detail below with reference to the accompanying drawings. The drawings show typical embodiments of the present disclosure. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided for thoroughness and completeness. Like reference numerals refer to like components throughout the description. The drawings are not necessarily to scale, and certain features may be exaggerated to better illustrate and describe typical embodiments of the present disclosure.

[0045] FIG. 1 shows a first step of a method for manufacturing an optoelectronic semiconductor chip 1. Accordingly, a semiconductor body 3 is provided on a growth substrate 2. The semiconductor body 3 includes an n-doped region 3.1, a p-doped region 3.2, and an active region 3.3 disposed between the n-doped region 3.1 and the p-doped region 3.2. The n-doped region 3.1 further includes an n-type current distribution layer 3.4 disposed within the n-doped region 3.1. Accordingly, the semiconductor body 3 can be formed as a semiconductor layer stack of a semiconductor material such as GaN, for example, in the form of a support and a growth wafer. In this and the following figures, only a part of the subsequent semiconductor chip is typically shown of the growth substrate 2 and the semiconductor layer stack. However, the growth substrate 2 and the semiconductor layer stack and subsequent layers and components may continue to the left and right of the illustrated part.

[0046] In a further step, a p-type current distribution layer 4 is deposited on the p-doped region 3.2. The p-type current distribution layer 4 in particular comprises or consists of a conductive material. The conductive material is furthermore at least partially transmissive to light. As shown in the figure, the p-type current distribution layer 4 may be structured, for example, to include an opening that is centered or offset from the center with respect to the semiconductor body 3.

[0047] Figure 2 shows a further step of the method. Here, a first mesa structure 5 is formed from the semiconductor body 3. For example, by using an etching process, in particular a dry etching process, the first mesa structure 5 is formed to include at least the p-doped region 3.2, the active region 3.3, and a part of the n-doped region 3.1.

[0048] On the formed outer shape, a first dielectric layer 6 is deposited as shown in Figure 3. The first dielectric layer 6 is disposed on the p-type current distribution layer 4, on the p-doped region 3.2, on a part of the n-doped region 3.1, and on the side surface 5.1 of the first mesa structure 5.

[0049] In a further step, as shown in Figure 4, a mirror layer 7 is deposited on the first dielectric layer 6. The mirror layer 7 can for example comprise or consist of a metal such as silver, aluminum, and / or gold, and can in particular be highly reflective. As shown in the figure, the mirror layer 7 can be disposed only in the region on the first dielectric layer 6 that is opposite to the p-doped region 3.2, but as shown in Figures 5A to 5E below, it can also be disposed in other regions on the first dielectric layer 6.

[0050] However, in any case, the first dielectric layer 6 is disposed between the mirror layer 7 and the p-type current distribution layer 4 and / or the p-doped region 3.2, and electrically insulates the mirror layer 7 from the p-type current distribution layer 4 and the p-doped region 3.2.

[0051] Figure 5A shows a first modification of the mirror layer 7 disposed on the first dielectric layer 6 in a cross-sectional view and a plan view. The mirror layer 7 has a rectangular shape with an opening in its center when viewed from above the mirror layer 7. Below the opening of the mirror layer 7, the first dielectric layer 6 is structured / includes a through hole, and a later metallization layer can be electrically connected to the p-doped region 3.2 and / or the p-type current distribution layer 4. By such an arrangement of the opening in the center of the mirror layer, advantages can be obtained with respect to the uniform emission of light generated in the active region 3.3 of the semiconductor body 3.

[0052] Figure 5B shows a second modification of the mirror layer 7 in a cross-sectional view and a plan view. The mirror layer 7 has a rectangular shape with a recess in one of its corners. In other words, one corner of the mirror layer 7 is missing. Below the recess of the mirror layer 7, the first dielectric layer 6 is structured / includes a through hole, and a later metallization layer can be electrically connected to the p-doped region 3.2 and / or the p-type current distribution layer 4. By such an arrangement of the recess, in particular, an area advantage for the semiconductor chip can be obtained. This is because the contact to the p-doped region 3.2 can be made from the edge of the semiconductor chip, thereby reducing space consumption.

[0053] A further development of the mirror layer 7 shown in Figure 5A is shown in Figure 5C. Thereby, the mirror layer 7 not only covers the region of the first dielectric layer 6 on the side opposite to the p-doped region 3.2, but also covers along the side surface 5.1 of the first mesa structure 5. Therefore, the mirror layer 7 surrounds the back and side surfaces of the first mesa structure 5, ensuring that the light (which exits from the active region 3.3 in any direction but not in the main emission direction E of the semiconductor chip) generated in the active region 3.3 of the semiconductor body 3 is reflected by the mirror layer 7 in the direction of the main emission direction E. Therefore, more light generated in the active region 3.3 of the semiconductor body 3 can be guided, and thereby emitted from the semiconductor chip in the direction of the main emission direction E, so that the efficiency of the semiconductor chip can be improved.

[0054] As shown in FIG. 5D, in addition to the mirror layer 7 of FIG. 5C, the mirror layer 7 is electrically connected to the n-doped region 3.1. Therefore, the first dielectric layer 6 includes at least two through holes shown in the figure in a region where the first dielectric layer 6 is in direct contact with the n-doped region 3.1. Thereby, the mirror layer 7 can be electrically connected to an n-potential that can be connected to the semiconductor chip during the operation of the semiconductor chip. Therefore, the mirror layer 7 can be connected to the n-potential and is not floating.

[0055] FIG. 5E shows a mirror layer 7 that, in contrast to the mirror layer 7 of FIG. 5D, includes a recess at one of its corners and does not include an opening at its center. Thereby, the area advantage can be combined with the advantage of improving the efficiency of the semiconductor chip and the advantage that the mirror layer is connected to the n-potential.

[0056] FIG. 6 shows a further step of a method for manufacturing the optoelectronic semiconductor chip. Thereby, a second dielectric layer 8 is deposited on the mirror layer 7. The second dielectric layer 8 is disposed on the mirror layer 7 and the first dielectric layer 6 and follows the outer shapes of the two layers. Therefore, the second dielectric layer 8 also follows the outer shape of the side surface 5.1 of the first mesa structure 5. The second dielectric layer 8 is, in particular, a material different from the first dielectric layer 6, but in some embodiments, it can also be the same material as the first dielectric layer 6.

[0057] The second dielectric layer 8, and if not already done in previous steps, the first dielectric layer 6 and the p-type current distribution layer 4 are structured as shown in FIG. 7 to provide through holes through the second dielectric layer 8 and / or the first dielectric layer 6 and / or the p-type current distribution layer 4, and a later metallization layer can be connected to the p-doped region 3.2 and / or the p-type current distribution layer 4 by contact vias.

[0058] The metallization layer 9 can be deposited on the second dielectric layer 8 according to any one of the variations shown in FIGS. 8A to 8C. According to FIG. 8A, the metallization layer 9 is deposited only on the region of the second dielectric layer 8 where subsequent p - contacts / p - pads are to be provided within the semiconductor chip. The metallization layer 9 includes contact vias 9.1 that pass through the second dielectric layer 8 and the first dielectric layer 6 and is not in contact with the p - type current distribution layer 4. However, the metallization layer 9 can also be deposited over the entire area of the second dielectric layer 8 and can be structured in a subsequent step to achieve the desired shape. The current introduced through the metallization layer 9 diffuses directly into the p - region 3.2 thereby. This can be particularly advantageous because there may be a material interaction between the metallization layer 9 and the p - type current distribution layer 4. The material interaction is prevented by the metal layer not being in direct contact with the p - region and not introducing current through the p - type current distribution layer 4. For example, if the p - type current distribution layer 4 includes a material such as ITO and the metallization layer 9, and thus the contact vias 9.1, include a material such as titanium (Ti), an undesirable effect may occur due to the material interaction between these two materials.

[0059] FIG. 8B shows a variation of the metallization layer 9 that includes contact vias 9.1 passing through the second dielectric layer 8, the first dielectric layer 6, and the p - type current distribution layer 4. The contact vias 9.1 are in contact with the p - type current distribution layer 4 along the inner surface 4.1 of the p - type current distribution layer 4. The advantage of such an arrangement is that the current introduced through the metallization layer 9 diffuses into the p - type current distribution layer 4 in an improved manner and there is no or only a minimal amount of current that diffuses directly into the p - region 3.2.

[0060] In this specific example shown in FIG. 8B, the contact via 9.1 includes an indentation along its propagation direction. This may be caused by the process of depositing the metallization layer 9 on the second dielectric layer 8. This is because the deposition process may involve the growth of the metallization layer 9 on the existing profile. Therefore, the through holes passing through the second dielectric layer 8, the first dielectric layer 6, and the p-type current distribution layer 4 may not be completely filled with the material of the metallization layer 9.

[0061] FIG. 8C shows a further deformation of the metallization layer 9. In contrast to the metallization layer shown in FIG. 8A, the contact via 9.1 of the metallization layer 9 contacts the p-type current distribution layer 4 but does not contact the p-doped region 3.2. This is because the p-type current distribution layer 4 is formed as a continuous layer and is neither structured nor includes through holes. Therefore, the current introduced through the metallization layer 9 diffuses directly into the p-type current distribution layer 4.

[0062] The metallization layer 9 may include a reflective material or, further, may include a reflective coating on its surface facing at least the semiconductor body 3. Thereby, when the light generated in the active region 3.3 of the semiconductor body 3 exits the active region 3.3 against the main emission direction E of the semiconductor chip and is not reflected by the mirror layer 7, it can be reflected from the metallization layer 9 in the direction of the main emission direction E.

[0063] As shown in FIG. 9, the method further includes the step of forming a second mesa structure 10. By using, for example, an etching process, particularly a dry etching process, the second mesa structure 10 is formed to include a part of the n-doped region 3.1 and parts of the first and second dielectric layers 6, 8, and the second mesa structure 10 projects laterally from the first mesa structure 5.

[0064] The order of the step of forming the second mesa structure 10 and the step of depositing the metallization layer 9 can also be interchanged as shown in FIG. 10. The second mesa structure 10 was formed before depositing the metallization layer 9 on the second dielectric layer 8 and on the side surface 10.1 of the second mesa structure 10. However, in subsequent steps, the metallization layer 9 is structured to achieve the desired shape of the metallization layer 9 while avoiding electrical contact between the metallization layer 9 and the n-doped region 3.1.

[0065] FIG. 11 shows a further step of the method of depositing the release layer 11 on the metallization layer 9, the second dielectric layer 8, and the side surface 10.1 of the second mesa structure 10. The release layer 11 can in particular be a temporary layer and can for example be easily removed by dissolution. As shown in the figure, the release layer covers the entire surface on the side opposite to the growth substrate 2 in preparation for a subsequent adhesion / soldering step.

[0066] After depositing the release layer 11 on the metallization layer 9, as shown in FIG. 12, through-holes 12 are formed through the release layer 11 in the region of the release layer 11 where the release layer 11 is in direct contact with the second dielectric layer 8. The through-holes 12 through the release layer 11 serve to provide a subsequent support structure for the semiconductor chip.

[0067] By means of the adhesion / soldering step, the existing intermediate product / web is encapsulated in the adhesion / solder material 13 on the carrier 14. As a result, as shown in FIG. 13, the through-holes 12 are also filled with the adhesion / solder material 13, forming a subsequent support structure for the semiconductor chip. Then, the resulting intermediate product can be inverted and the growth substrate 2 can be removed as shown in FIG. 14.

[0068] In a further step, as shown in FIG. 15, a part of the n-doped region 3.1 is removed until the release layer 11 is at least partially exposed. The step of removing the n-doped region 3.1 can include, for example, steps of thinning, grinding, polishing, and / or etching the n-doped region 3.1.

[0069] FIG. 16 shows the step of depositing an n-type contact layer 15 on the n-doped region 3.1, on the side opposite to the p-doped region 3.2. The n-type contact layer 15 can, in particular, function as an n-contact / n-pad of the semiconductor chip.

[0070] Then, the release layer 11 is dissolved, for example, as shown in FIG. 17, so that the resulting semiconductor chip 1 is connected only to the support structure 16. And the semiconductor chip 1 can be removed from the wafer, for example, by a stamping process or any other process known in the art.

[0071] The resulting semiconductor chip 1 is characterized in particular by the fact that the mirror layer 7 is not at least electrically connected to the p-doped region 3.2, the p-type current distribution layer 4, and the metallization layer 9. Therefore, the aging behavior of the semiconductor chip 1 is improved.

Description of reference numerals

[0072] 1 Optoelectronic semiconductor chip 2 Growth substrate 3 Semiconductor body 3.1 n-doped region 3.2 p-doped region 3.3 Active region 3.4 n-type current distribution layer 4 p-type current distribution layer 5 First mesa structure 5.1 Side surface 6 First dielectric layer 7 Mirror layer 8 Second dielectric layer 9 Metallization layer 9.1 Contact via 10 Second mesa structure 10.1 Side surface 11 Release layer 12 Through hole 13 Adhesive / solder material 14 Carrier 15 n-type contact layer E Main emission direction

Claims

1. An optoelectronic semiconductor chip (1), comprising: A semiconductor body (3), comprising: An n-doped region (3.1); A p-doped region (3.2); An active region (3.3) disposed between the n-doped region (3.1) and the p-doped region (3.2); The semiconductor body (3) having the foregoing; A first dielectric layer (6) disposed on the p-doped region (3.2), and a mirror layer (7) containing metal disposed on the first dielectric layer (6), wherein the first dielectric layer (6) electrically insulates the mirror layer (7) from the p-doped region (3.2) and the n-doped region (3.1), the first dielectric layer (6) and the mirror layer (7); A second dielectric layer (8) disposed on the mirror layer (7), and a metallization layer (9) disposed on the second dielectric layer (8), wherein the metallization layer (9) is electrically insulated from the mirror layer (7) and electrically contacts the p-doped region (3.2), the second dielectric layer (8) and the metallization layer (9); An n-type contact layer (15) deposited on the n-doped region (3.1) on a side opposite to the p-doped region (3.2); The first dielectric layer (6) is disposed on a side surface (5.1) of the semiconductor body (3); The mirror layer (7) is disposed on the first dielectric layer (6) on the side surface (5.1) of the semiconductor body (3), the optoelectronic semiconductor chip (1).

2. The optoelectronic semiconductor chip according to claim 1, wherein at least the p-doped region (3.2) and the active region (3.3) form a first mesa structure (5).

3. The optoelectronic semiconductor chip according to claim 2, wherein at least a part of the n-doped region (3.1) forms a second mesa structure (10), and the second mesa structure (10) protrudes laterally from the first mesa structure (5).

4. The optoelectronic semiconductor chip according to claim 2, wherein the first dielectric layer (6) follows the side surface (5.1) of the first mesa structure (5).

5. The optoelectronic semiconductor chip according to any one of claims 1 to 4, wherein the second dielectric layer (8) follows the side surface (5.1) of the semiconductor body (3).

6. The optoelectronic semiconductor chip (1) according to any one of claims 1 to 5 is electrically connectable on two opposite sides of the semiconductor chip by the metallization layer (9) and the n-type contact layer (15).

7. The optoelectronic semiconductor chip according to any one of claims 1 to 6, wherein the metallization layer (9) includes contact vias (9.1) passing through at least the first and second dielectric layers (6, 8).

8. The optoelectronic semiconductor chip according to claim 7, wherein the contact via (9.1) is arranged centrally with respect to the semiconductor body (3) or on an edge of the semiconductor body (3).

9. The optoelectronic semiconductor chip according to any one of claims 1 to 8, wherein the metallization layer (9) is configured to be reflective or includes a reflective coating.

10. When viewed from above the mirror layer (7), the mirror layer has a rectangular, polygonal, or circular shape with an opening arranged in the center of the semiconductor body, The optoelectronic semiconductor chip according to any one of claims 1 to 9, including one of a rectangular, polygonal, or circular shape having a recess on an edge of the mirror layer.

11. The optoelectronic semiconductor chip according to any one of claims 1 to 10, wherein the n-type contact layer (15) includes or consists of at least a partially transparent material.

12. A method for manufacturing an optoelectronic semiconductor chip (1), comprising: providing a semiconductor body (3) on a growth substrate (2), wherein the semiconductor body has an n-doped region (3.1), a p-doped region (3.2), an active region (3.3) arranged between the n-doped region (3.1) and the p-doped region (3.2), and the step including the above; depositing a first dielectric layer (6) on the p-doped region (3.2) and a mirror layer (7) containing metal on the first dielectric layer (6), wherein the first dielectric layer (6) electrically insulates the mirror layer (7) from at least the p-doped region (3.2) and the n-doped region (3.1); depositing a second dielectric layer (8) on the mirror layer (7); Depositing a metallization layer (9) on the second dielectric layer (8), wherein the metallization layer (9) is electrically insulated from the mirror layer (7) and is in electrical contact with the p-doped region (3.2), said step; Depositing a release layer (11) on the metallization layer, Said step of depositing the release layer (11) includes forming a through-hole (12) passing through the release layer (11) in the region of the release layer (11), and the release layer (11) is in direct contact with the first and / or second dielectric layer (6, 8), said step of depositing the release layer (11); Adhering or soldering the release layer (11) onto a carrier (14) such that the through-hole (12) is filled with an adhesive or soldering material (13); Depositing an n-type contact layer (15) on the opposite side of the p-doped region (3.2) with respect to the n-doped region (3.1); Removing the release layer (11), said method comprising.

13. Said step of providing the semiconductor body (3) includes forming a first mesa structure (5), and the first mesa structure (5) includes at least the p-doped region (3.2) and the active region (3.3), the method according to claim 12.

14. Further including the step of forming a second mesa structure (10), the second mesa structure (10) includes at least a part of the n-doped region (3.1) and protrudes laterally from the first mesa structure (5), the method according to claim 13.

15. Said step of depositing the first dielectric layer (6) includes structuring the first dielectric layer (6) such that at least one through-hole passing through the first dielectric layer (6) is provided in a region where the first dielectric layer (6) is in direct contact with the n-doped region (3.1) and / or in a region where the first dielectric layer (6) is in direct contact with the p-doped region (3.2), the method according to any one of claims 12 to 14.

16. Said step of depositing the mirror layer (7) includes electrically connecting the mirror layer (7) and the n-doped region (3.1), the method according to any one of claims 12 to 15.

17. The method according to any one of claims 12 to 16, wherein the step of depositing the metallization layer (9) includes a step of etching a through hole passing through the second dielectric layer (8) and / or the first dielectric layer (6).

18. The method according to any one of claims 12 to 17, wherein the step of depositing the metallization layer (9) includes structuring the metallization layer (9).

19. The method according to claim 12, further comprising a step of removing the growth substrate (2) and / or a step of removing a part of the n-doped region (3.1) until at least the release layer (11) is partially exposed.

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