Semiconductor device

Abstract

To provide a semiconductor device in which the stagnation of decrease in resistance value of a drift layer due to carrier diffusion from a third semiconductor layer to a first semiconductor layer is suppressed.SOLUTION: A drift layer 10 of a first conductivity type, an anode layer 20 of a second conductivity type and a cathode layer 30 of the first conductivity type are provided. Inside the drift layer, a plurality of FS layers 41 and 42 of the first conductivity type whose impurity concentration is higher than the drift layer and lower than the anode layer and the cathode layer are provided. In the drift layer, the FS layers are arranged apart from each other from the cathode layer to the anode layer. The separation distance between the cathode layer and the first FS layer 41 at a position closest to the cathode layer among the FS layers is longer than the separation distance between the FS layers.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The disclosure described in this specification relates to a semiconductor device.

Background Art

[0002] As shown in Patent Document 1, a semiconductor device including a p-anode layer, an n-cathode layer, and a drift layer sandwiched between the p-anode layer and the n-cathode layer is known. In this semiconductor device, a plurality of broad buffer regions are formed in the drift layer.

[0003] The plurality of broad buffer regions are spaced apart from each other and arranged in a direction from the n-cathode layer toward the p-anode layer. The broad buffer region has a higher impurity concentration than the drift layer. Also, the broad buffer region has a lower impurity concentration than each of the n-cathode layer and the p-anode layer.

[0004] When a forward bias is applied between the p-anode layer and the n-cathode layer, carriers diffuse from a region with a high impurity concentration to a region with a low impurity concentration. Excluding the diffusion of carriers from the p-anode layer, in terms of specifying the location of carrier diffusion, carriers are diffused from the n-cathode layer between the n-cathode layer and the broad buffer region in the drift layer. Between two broad buffer regions in the drift layer, carriers are diffused from the broad buffer region.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] By the way, in the semiconductor device described in Patent Document 1, the separation distance between the broad buffer region and the n-cathode layer is shorter than the separation distance between the plurality of broad buffer regions.

[0007] In this case, before the carriers diffused from the broad buffer region on the n-cathode layer side reach the broad buffer region on the p-anode layer side, the carriers diffused from the n-cathode layer reach the broad buffer region on the n-cathode layer side. A large number of carriers already exist in this broad buffer region. Therefore, the ratio of the amount of carriers diffused from the n-cathode layer to the total carrier amount in the broad buffer region decreases. Also, after carriers reach the broad buffer region from the n-cathode layer, the increase rate of the total amount of carriers diffused from the n-cathode layer (third semiconductor layer) to the drift layer (first semiconductor layer) becomes small. As a result, the decrease in the resistance value of the drift layer due to carrier diffusion under forward bias is delayed.

[0008] Therefore, an object of the disclosure described in this specification is to provide a semiconductor device in which the delay in the decrease in the resistance value of the drift layer due to carrier diffusion from the third semiconductor layer to the first semiconductor layer is suppressed.

Means for Solving the Problem

[0009] One of the disclosures is a first semiconductor layer (10) of a first conductivity type, A second semiconductor layer (20) of a second conductivity type provided on the front surface of the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer, A third semiconductor layer (30) of a first conductivity type provided on the back surface of the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer, A plurality of fourth semiconductor layers (41, 42) of a first conductivity type provided inside the first semiconductor layer between the second semiconductor layer and the third semiconductor layer, having a higher impurity concentration than the first semiconductor layer and a lower impurity concentration than each of the second semiconductor layer and the third semiconductor layer, Inside the first semiconductor layer, the plurality of fourth semiconductor layers are arranged separately and side by side from the third semiconductor layer toward the second semiconductor layer, The first separation distance between the impurity peak concentration position of the fourth semiconductor layer (41) located closest to the third semiconductor layer among the plurality of fourth semiconductor layers and the impurity peak concentration position of the third semiconductor layer is longer than the second separation distance between the impurity peak concentration positions of adjacent fourth semiconductor layers. The impurity peak concentration of the fourth semiconductor layer (42) located closest to the second semiconductor layer among the plurality of fourth semiconductor layers is Peak higher than the impurity concentrations of the other fourth semiconductor layers.

[0010] Thus, in the present disclosure, Adjacent the first separation distance between the impurity peak concentration positions of the fourth semiconductor layers is Of the placement longer than the second separation distance between the impurity peak concentration positions of the fourth semiconductor layers. Located closest to the third semiconductor layer among the plurality of fourth semiconductor layers That is, the first separation distance between the impurity peak concentration position of the fourth semiconductor layer and the impurity peak concentration position of the third semiconductor layer is longer.

[0011] Therefore , the the arrival of carriers diffused from the third semiconductor layer (30) at the fourth semiconductor layer (41) is suppressed. The increase rate of the total carriers diffused from the third semiconductor layer (30) to the first semiconductor layer (10) due to the majority carriers contained in the fourth semiconductor layer (41) is suppressed from decreasing, and consequently, the decrease in the resistance value of the first semiconductor layer (10) is suppressed from being delayed.

[0012] Note that the reference numerals in the parentheses above merely indicate the correspondence with the configurations described in the embodiments below, and do not limit the technical scope in any way.

Brief Description of the Drawings

[0013]

Figure 1

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Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments will be described with reference to the drawings.

[0015] (First Embodiment) Based on FIGS. 1 to 5, the semiconductor device 100 according to this embodiment will be described. The semiconductor device 100 is formed on an n-type impurity-doped semiconductor substrate. An anode layer 20 containing p-type impurities such as boron is formed on one surface side of this semiconductor substrate. A cathode layer 30 containing n-type impurities such as phosphorus is formed on the back surface side of the semiconductor substrate. This cathode layer 30 is formed at a high concentration to reduce the contact resistance with an electrode formed of AL, Ti, or the like. The portion between the anode layer 20 and the cathode layer 30 in the semiconductor substrate is the drift layer 10. Thus, the semiconductor device 100 is a diode having a pn junction.

[0016] The n-type conductivity corresponds to the first conductivity type. The p-type conductivity corresponds to the second conductivity type. The drift layer 10 corresponds to the first semiconductor layer. The anode layer 20 corresponds to the second semiconductor layer. The cathode layer 30 corresponds to the third semiconductor layer.

[0017] Each of the anode layer 20 and the cathode layer 30 has a higher impurity concentration than the drift layer 10. An anode electrode (not shown) is formed in the anode layer 20. A cathode electrode (not shown) is formed in the cathode layer 30. These anode and cathode electrodes are connected to an electric circuit shown in, for example, FIG. 4. This electric circuit will be described later.

[0018] As shown in FIG. 1, an n-type conductivity FS layer 40 is formed in the drift layer 10 by irradiating H+ (protons) having a longer flight distance than phosphorus or the like at the same acceleration voltage. FS is an abbreviation for field stop. The FS layer 40 is located on the cathode layer 30 side in the drift layer 10. The FS layer 40 has a higher impurity concentration than the drift layer 10. The FS layer 40 has a lower impurity concentration than each of the anode layer 20 and the cathode layer 30.

[0019] In the present embodiment, there are a first FS layer 41 and a second FS layer 42 as the FS layer 40. The first FS layer 41 and the second FS layer 42 are arranged in sequence and spaced apart from the cathode layer 30 side toward the anode layer 20 side. . The The 1FS layer 41 and the second FS layer 42 correspond to a plurality of fourth semiconductor layers.

[0020] FIG. 1 shows the time change of the carrier concentration distribution when a forward bias is applied to the semiconductor device 100. This shows the time change of the carrier concentration distribution at the forward recovery time of the semiconductor device 100. As indicated by the arrow, the carrier concentration of the semiconductor device 100 gradually increases as time elapses from the application of the forward bias. In FIG. 1, the carrier concentration distributions when 15 ns, 55 ns, 75 ns, 125 ns, 165 ns, and 6 μs have elapsed from the application of the forward bias are shown. The horizontal axis shown in FIG. 1 indicates the distance from one side or the back side of the semiconductor substrate.

[0021] The carrier concentration distribution of the semiconductor device 100 with the shortest elapsed time since the application of the forward bias is equivalent to the net doping concentration distribution of the semiconductor device 100. As shown in this carrier concentration distribution, the impurity concentrations of the first FS layer 41 and the second FS layer 42 each have a maximum value (peak concentration). The impurity concentrations of the first FS layer 41 and the second FS layer 42 each decrease from the maximum value toward the anode layer 20 side and the cathode layer 30 side. Also, the impurity concentration of the cathode layer 30 has a maximum value. And the separation distance L1 between the maximum value of the cathode layer 30 and the maximum value of the first FS layer 41 is longer than the separation distance L2 between the maximum value of the first FS layer 41 and the maximum value of the second FS layer 42.

[0022] When a forward bias is applied to the semiconductor device 100, carriers are diffused from the anode layer 20, the cathode layer 30, the first FS layer 41, and the second FS layer 42 into the drift layer 10 respectively. Carriers are accumulated in the entire semiconductor device 100 due to the carrier diffusion from these layers into the drift layer 10. Thus, in the semiconductor device 100, carriers are diffused from not only the anode layer 20 and the cathode layer 30 but also the first FS layer 41 and the second FS layer 42 into the drift layer 10.

[0023] As a comparative configuration, FIG. 2 shows the time change of the carrier concentration distribution of the first diode including the drift layer 10, the anode layer 20, and the cathode layer 30. An FS layer 40 is not formed in this first diode. Therefore, the increase in the carrier concentration is slower compared to the semiconductor device 100. In FIG. 2, the carrier concentration distributions when 15 ns, 55 ns, 75 ns, 125 ns, 165 ns, and 6 μs have elapsed since the application of the forward bias are shown.

[0024] Fig. 3 shows the time variation of the carrier concentration distribution of a second diode including a drift layer 10, an anode layer 20, a cathode layer 30, and a first FS layer 41. The second FS layer 42 is not formed in this second diode. Therefore, the increase in the carrier concentration is slower compared to the semiconductor device 100. Fig. 3 shows the carrier concentration distribution when 15 ns, 55 ns, 75 ns, 95 ns, 115 ns, 135 ns, 165 ns, and 6 μs have elapsed since the forward bias is applied.

[0025] <Carrier diffusion> Specifically explaining the carrier diffusion in the semiconductor device 100, carriers are diffused from the cathode layer 30 into the region between the cathode layer 30 and the first FS layer 41 in the drift layer 10. Carriers are diffused from the first FS layer 41 into the region between the first FS layer 41 and the second FS layer 42 in the drift layer 10. Carriers are diffused from the second FS layer 42 and the anode layer 20 into the region between the second FS layer 42 and the anode layer 20 in the drift layer 10.

[0026] In the following, for the sake of simplicity of notation, the region between the cathode layer 30 and the first FS layer 41 in the drift layer 10 is denoted as the first drift layer. The region between the first FS layer 41 and the second FS layer 42 in the drift layer 10 is denoted as the second drift layer.

[0027] The diffusion of carriers from each of the above-described layers into the drift layer 10 becomes deeper as the difference in impurity concentration between each layer and the drift layer 10 is larger. As described above, the impurity concentration of the cathode layer 30 is higher than that of the first FS layer 41 and the second FS layer 42, respectively. Therefore, carriers are more likely to be diffused deeper into the drift layer 10 on the anode layer 20 side from the cathode layer 30 than from the first FS layer 41 and the second FS layer 42, respectively.

[0028] Due to this difference in the ease of carrier diffusion, for example, when the separation distance L1 is shorter than the separation distance L2, before the carriers diffused from the first FS layer 41 to the second drift layer side reach the second FS layer 42, the carriers diffused from the cathode layer 30 to the first drift layer side reach the first FS layer 41 faster. There are already many majority carriers in the first FS layer 41. Therefore, the amount of carriers diffused from the cathode layer 30 in the total carrier amount of the first FS layer 41 becomes smaller. Also, after carriers reach the first FS layer 41 from the cathode layer 30, the increase in the total amount of carriers diffused from the cathode layer 30 to the drift layer 10 becomes smaller.

[0029] On the other hand, in the semiconductor device 100 as described above, the separation distance L1 is longer than the separation distance L2. In this case, the difference between the time for the carriers diffused from the first FS layer 41 to the second drift layer side to reach the second FS layer 42 and the time for the carriers diffused from the cathode layer 30 to the first drift layer side to reach the first FS layer 41 becomes shorter compared to the configuration where the separation distance L1 is shorter than the separation distance L2. The time for the carriers diffused from the cathode layer 30 to the first drift layer side to reach the first FS layer 41 becomes slower. Due to this time difference, the carrier diffusion from the cathode layer 30 to the first drift layer becomes less dependent on the majority carriers in the first FS layer 41. Therefore, the decrease in the increase in the total amount of carriers diffused from the cathode layer 30 to the drift layer 10 is suppressed.

[0030] As a result, it is suppressed that the decrease in the resistance value of the drift layer 10 is delayed due to the diffusion of carriers by the forward bias.

[0031] <Forward recovery voltage> Incidentally, during the transient period (forward recovery time) when the resistance value of the drift layer 10 decreases due to forward biasing, the forward voltage of the semiconductor device 100 exhibits a behavior of instantaneously increasing above the forward voltage in the steady state and reaching a peak value. Hereinafter, the forward voltage higher than the forward voltage in the steady state during this forward recovery time is referred to as the forward recovery voltage. This forward recovery voltage tends to increase when the above-mentioned carrier diffusion is delayed. When the forward recovery voltage increases, for example, problems occur in the electric circuit shown in FIG. 4.

[0032] In the electric circuit shown in FIG. 4, a power supply 110, a load inductance 120, and an IGBT 130 are connected in series in a counterclockwise loop. At the same time, the load inductance 120, the semiconductor device 100, and a parasitic inductance 140 are connected in series in a clockwise loop. The anode electrode of the semiconductor device 100 is connected to each of the load inductance 120 and the IGBT 130. The cathode electrode of the semiconductor device 100 is connected to the parasitic inductance 140.

[0033] In such an electrical connection configuration, when the IGBT 130 switches from the open state to the closed state, a current flows from the power supply 110 through the load inductance 120 to the IGBT 130. As a result, electrical energy is stored in the load inductance 120. At this time, a reverse bias is applied to the semiconductor device 100. Therefore, no current flows through the semiconductor device 100 and the parasitic inductance 140.

[0034] When the IGBT 130 switches from the closed state to the open state, a forward bias is applied to the semiconductor device 100 by the electrical energy stored in the load inductance 120. As a result, a current tries to flow from the load inductance 120 through the semiconductor device 100 to the parasitic inductance 140.

[0035] Fig. 5 shows the forward voltage Vak of the semiconductor device 100 when the forward bias starts to be applied. When a forward bias is applied to the semiconductor device 100, a current starts to flow through the drift layer 10. Accordingly, the forward voltage Vak increases. After a while since the current If starts to flow through the semiconductor device 100, carriers are accumulated in the drift layer 10. The forward voltage Vak shows a behavior of taking a peak value (forward recovery voltage).

[0036] When the current If starts to flow through the semiconductor device 100, a current also starts to flow through the parasitic inductance 140. Thereby, a voltage is generated due to the time change of the current flowing through the parasitic inductance 140 and the inductance component of the parasitic inductance 140. The sum of these forward recovery voltage, the voltage due to the inductance component, and the voltage of the power supply 110 is applied to the IGBT 130. If this applied voltage exceeds the rating of the IGBT 130, there is a risk of damage to the IGBT 130.

[0037] However, as described above, in the semiconductor device 100, the delay in the decrease of the resistance value when the forward bias is applied is suppressed. Therefore, the increase in the forward recovery voltage is suppressed. Thereby, the occurrence of damage to the IGBT 130 is suppressed. Naturally, when active elements and passive elements (not shown) are provided in this electric circuit, the occurrence of damage to these active elements and passive elements due to the forward recovery voltage of the semiconductor device 100 is suppressed.

[0038] As described above, the preferred embodiments of the present disclosure have been described. However, the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present disclosure.

[0039] (First Modified Example) In this embodiment, a method for determining the separation distance L1 has not been particularly described. For example, as shown in FIGS. 6 and 7, the separation distance L1 may be determined based on the time change of the carrier concentration distribution of the first diode shown as a comparative configuration. The increase in the carrier concentration of the drift layer 10 on the cathode layer 30 side in this first diode is caused by carrier diffusion from the cathode layer 30.

[0040] For example, as shown by the rhombus in FIG. 6, the position where the reference carrier concentration indicated by the broken line in the drift layer 10 reaches changes with the passage of time. When 55 ns has elapsed since the application of the bias, the position where the reference carrier concentration is reached is displaced to a position approximately 11 μm away from the back surface of the semiconductor substrate. When 75 ns has elapsed, the position where the reference carrier concentration is reached is displaced to a position approximately 19 μm away from the back surface. When 95 ns has elapsed, the position where the reference carrier concentration is reached is displaced to a position approximately 23 μm away from the back surface. When 115 ns has elapsed, the position where the reference carrier concentration is reached is displaced to a position approximately 26 μm away from the back surface.

[0041] In FIG. 7, the time change of the position where the reference carrier concentration is reached is shown by a solid line. And a line that is constant at a distance of 3 μm is shown by a broken line. The region indicated by the hatching defined by these two lines is preferable as the formation position of the first FS layer 41 in consideration of the short-circuit withstand of the semiconductor device 100. The constant line indicated by a distance of 3 μm shows the boundary at which the first FS layer 41 can be provided closest to the cathode layer 30 when considering the formation region of the cathode layer 30 and the short-circuit withstand of the semiconductor device 100.

[0042] Note that, for example, the separation distance L1 may be determined so as to become longer as the impurity concentration of the cathode layer 30 increases. The separation distance L2 may be determined so as to become longer as the impurity concentration of the first FS layer 41 increases.

[0043] (Second Modification Example) In this embodiment, an example in which the impurity concentrations of the first FS layer 41 and the second FS layer 42 are equal has been shown. However, the impurity concentrations of the first FS layer 41 and the second FS layer 42 may be different from each other.

[0044] (Third Modification Example) In this embodiment, an example in which only the semiconductor device 100 (diode) is formed on the semiconductor substrate doped with n-type impurities has been shown. However, for example, as shown in FIGS. 8 and 9, a configuration (RC-IGBT) in which the IGBT 200 is formed together with the semiconductor device 100 on the semiconductor substrate can also be adopted.

[0045] In FIGS. 8 and 9, a broken line is provided at the boundary between the semiconductor device 100 and the IGBT 200. The trench gate 210 is formed in the anode layer 20. An n-type emitter layer 220 is formed in the anode layer 20 of the IGBT 200. A p-type collector layer 230 is formed in the formation region of the IGBT 200 on the back side of the semiconductor substrate.

[0046] In the drift layer 10 of the IGBT 200 shown in FIG. 8, the first FS layer 41 and the second FS layer 42 are formed. In the drift layer 10 of the IGBT 200 shown in FIG. 9, a third FS layer 50 different from the first FS layer 41 and the second FS layer 42 is formed. The third FS layer 50 is separated from the anode layer 20 more than the first FS layer 41. The separation distance between the third FS layer 50 and the collector layer 230 is shorter than the separation distance between the first FS layer 41 and the cathode layer 30.

[0047] (Fourth Modification Example) In this embodiment, an example in which the first FS layer 41 and the second FS layer 42 are formed in the drift layer 10 has been shown. However, the number of FS layers formed in the drift layer 10 is not limited to two. A configuration in which three or more FS layers are formed in the drift layer 10 can also be adopted.

[0048] However, in consideration of the short-circuit withstand of the semiconductor device 100, it is preferable that the total amount of the net doping concentration of the plurality of FS layers is equal regardless of the change in the number of FS layers.

Explanation of Reference Numerals

[0049] 10… Drift layer, 20… Anode layer, 30… Cathode layer, 40… FS layer, 41… First FS layer, 42… Second FS layer, 100… Semiconductor device

Claims

1. a first semiconductor layer (10) of a first conductivity type; a second semiconductor layer (20) of a second conductivity type, which is provided on the front surface of the first semiconductor layer and has a higher impurity concentration than the first semiconductor layer; a third semiconductor layer (30) of the first conductivity type, which is provided on the back surface of the first semiconductor layer and has a higher impurity concentration than the first semiconductor layer; a plurality of fourth semiconductor layers (41, 42) of the first conductivity type, which are provided inside the first semiconductor layer between the second semiconductor layer and the third semiconductor layer, have a higher impurity concentration than the first semiconductor layer, and have a lower impurity concentration than each of the second semiconductor layer and the third semiconductor layer; inside the first semiconductor layer, the plurality of fourth semiconductor layers are arranged side by side at intervals from the third semiconductor layer toward the second semiconductor layer; a first separation distance between an impurity peak concentration position of the fourth semiconductor layer (41) located closest to the third semiconductor layer among the plurality of fourth semiconductor layers and an impurity peak concentration position of the third semiconductor layer is longer than a second separation distance between impurity peak concentration positions of adjacent fourth semiconductor layers; a semiconductor device in which an impurity peak concentration of the fourth semiconductor layer (42) located closest to the second semiconductor layer among the plurality of fourth semiconductor layers is higher than an impurity peak concentration of the other fourth semiconductor layers.

2. The semiconductor device according to claim 1, wherein an impurity contained in the fourth semiconductor layer is different from an impurity contained in the third semiconductor layer.

3. The semiconductor device according to claim 1 or claim 2, wherein the first separation distance is determined based on a time change of a distance of carrier diffusion from the third semiconductor layer to the first semiconductor layer when a forward bias is applied.

4. Three or more of the fourth semiconductor layers are provided, The semiconductor device according to any one of claims 1 to 3, wherein the second separation distance becomes longer as an impurity peak concentration of the fourth semiconductor layer located on the third semiconductor layer side among two adjacent fourth semiconductor layers arranged side by side becomes higher.

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