Charge Separation High-Speed CMOS Time Delay and Integrated Imaging

Abstract

Apparatus, methods, and techniques are provided for performing readout of multiple (N) time delay and integration (TDI) pixel registers to receive respective signal charges at multiple (N) sense nodes (SNs). The readout uses multiple (N) charge steering (CST) gates to steer and separate respective charges from each pixel register to a corresponding SN. Outputs are provided from the SNs (e.g., through parallel conversion using an ADC) to generate respective digital values. In one embodiment, charges are transferred vertically to the CST for horizontal demultiplexing to the SNs. The CST can be configured in a multi-stage configuration to support good charge steering. The CST may be associated with a barrier implant to support proper charge steering.

Description

Technical Field

[0001] The present disclosure relates to a complementary metal-oxide-semiconductor (CMOS) time delay and integration (TDI) high-fidelity imaging method and apparatus for parallel readout operation, and more particularly, to charge demultiplex for high-speed charge-coupled CMOS time delay and integration (TDI) imaging.

Background Art

[0002] In a conventional CMOS TDI imager, a row-by-row readout operation as follows is performed. This continuous operation limits the sensor speed. 1. A sense node (SN) is reset to a reset drain voltage (VDD) via a reset gate (RST). 2. The signal charge of the final TDI stage is transferred to the SN. 3. The signal charge is converted to a signal voltage at the SN and output via a source follower (SF). 4. Then, the analog signal voltage is converted to a digital value by an analog-to-digital converter (ADC).

[0003] In the current state-of-the-art CMOS TDI imager, it takes at least about 3 μs to complete the processing of one TDI row (i.e., a maximum line rate of about 300 kHz).

Summary of the Invention

[0004] Embodiments of the present invention relate to a high-speed charge-coupled CMOS TDI image sensor in which a plurality of CCD pixels are arranged in a matrix form. In one embodiment, a column slice of such a pixel array includes M TDI imaging pixels, N Charge Steering gates (CSTs), N SNs, a global reset structure (e.g., RST and VDD), N SFs, N sample-and-hold (S / H) capacitor circuits for correlated double sampling (CDS) operation, and N column-parallel ADCs, and N parallel readout structures, where N is less than or equal to M.

[0005] In a plurality (N) of SNs, an apparatus, method, and technique are provided for performing a readout of a plurality (N) of TDI pixel registers to receive respective signal charges. The readout uses a plurality (N) of CSTs to steer and demultiplex respective charges from respective pixel registers to corresponding SNs. Outputs are provided from the SNs to generate respective digital values (e.g., through parallel conversion using an ADC). In one embodiment, charges are transferred vertically to the CSTs for horizontal separation to the SNs. The CSTs may be configured in a multi-stage configuration to assist in good charge steering. The CSTs may be associated with a barrier implant to assist in proper charge steering. The apparatus may be a high-speed charge-coupled CMOS TDI image sensor in which a plurality of CCD pixels are arranged in a matrix form. Such an image sensor may be configured for bidirectional operation.

[0006] In one embodiment, a method is provided that performs readout of a plurality (N) of time delay and integration (TDI) pixel registers to receive respective signal charges at a plurality (N) of sense nodes, the readout using a plurality (N) of charge manipulation gates to manipulate and separate respective charges from each pixel register to a plurality of sense nodes, and providing outputs from the plurality of sense nodes to generate respective digital values.

[0007] In one embodiment, the method is implemented in a high-speed CMOS TDI image sensor that includes a plurality of charge-coupled device (CCD) pixels arranged in the form of a CCD pixel matrix, the column slice of which includes a plurality (N) of TDI pixel registers, a plurality (N) of isolation (ISO) registers includes a plurality (N) of CSTs, a plurality (N) of output structures includes a plurality (N) of sense nodes, a global reset structure, and a plurality of SFs, and a plurality (N) of parallel conversion components each includes an S / H capacitor array and a column-parallel ADC.

[0008] In one embodiment, an apparatus is provided that includes a circuit configured to perform a method according to any one of the method embodiments herein.

[0009] In one embodiment, an apparatus is provided that includes a plurality (N) of time delay and integration (TDI) pixel registers, a plurality (N) of isolation (ISO) registers including a plurality (N) of charge manipulation gates coupled to the plurality (N) of TDI pixel registers, and a plurality (N) of output structures including a plurality (N) of sense nodes coupled to receive respective signal charges read out from the plurality (N) of TDI pixel registers to be manipulated and separated by the plurality (N) of charge manipulation gates, the plurality (N) of sense nodes being coupled to provide an output for generating a digital value.

[0010] In one embodiment, each of a plurality (N) of sense nodes is configured using a circuit that provides a parallel reset function. In one embodiment, each of a plurality (N) of sense nodes is coupled via a plurality (N) of source followers (SFs) to a plurality (N) of sample-and-hold (S / H) capacitor circuits and a plurality (N) of column-parallel analog-to-digital converters (ADCs), and generates in parallel a respective digital value for each respective signal charge.

[0011] In one embodiment, the apparatus includes a CMOS TDI image sensor in which a plurality of CCD pixels are arranged in the form of a CCD pixel matrix, the column slice of which includes a plurality (N) of TDI pixel registers, the plurality (N) of ISO registers include a plurality (N) of CSTs, the plurality (N) of output structures include a plurality (N) of sense nodes, the global reset structure provides a parallel reset function, and includes a plurality (N) of SFs, a plurality (N) of S / H capacitor arrays, and a plurality (N) of column-parallel ADCs.

[0012] The present invention addresses the above-described conventional slow sequential readout operation by separating the charges accumulated in a plurality of TDI rows into corresponding readout structures, and enables a high-speed parallel readout operation.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0025] FIG. 1 is a diagram showing a column slice of a high-speed charge-coupled CMOS TDI imager pixel array 100 in one embodiment. The pixel array 100 is a partial one in which its column slice 102 is shown, and the pixel array 100 may include additional columns. The column slice 102 includes a plurality (M) of TDI (pixel) registers (e.g., 1041, 1042, …, 104 N-1 , 104 N , …, 104 M-1 , and 104 M ), a plurality (N) of TDI registers 106 (N is less than or equal to M) including a subset of the TDI registers 1041, 1042, …, and 104 N , and a plurality (N) of sense nodes (SN) 108 (e.g., 1081, 1082, … 108 N-1 , and 108 N ). The N SNs 108 are components of N output structures.

[0026] The plurality (M) of TDI registers 104 are coupled to a plurality (N) of sense nodes 108 that receive signal charges from the plurality (N) of TDI registers 106. The plurality (N) of sense nodes 108 are coupled to receive signal charges from the plurality (N) of TDI registers 106 via a plurality (N) of charge steering (CST) gates (e.g., 1101, 1102, … 110 N-1 , and 110 N ). The N CSTs 110 are components of N isolation (ISO) registers.

[0027] Each of the N sense nodes 108 has a global signal reset functionality 112 and outputs to a parallel conversion function 114 via the N source followers (SFs) 116 to each of the N correlated double sampling (CDS) and ADC circuits (further described in FIGS. 3 and 4).

[0028] In contrast to conventional readouts, according to an embodiment, a high-speed multiple rows-based parallel operation is achieved as follows.

[0029] The N SNs 108 within the TDI column 102 are reset in parallel via the function 112 and are ready to extract the (signal) charge transferred from the N TDI row pixel registers 106 from the M TDI row pixel registers 104.

[0030] Each charge is transferred vertically from each of the N TDI pixel registers, steered by each of the corresponding N CSTs, and demultiplexed horizontally to each of the corresponding N SNs.

[0031] Each of the N signal charges accumulated in each of the N SNs is converted in parallel to a signal voltage.

[0032] Each of the analog signal voltages is output via each of the corresponding N SFs and then converted in parallel to a digital value by each of the corresponding N parallel conversion functions 114. The AD processing overlaps with the subsequent charge transfer. That is, the AD conversion of the current set of analog signal voltages is also performed in parallel while the next set of signal charges accumulated in the N TDI registers is transferred.

[0033] FIG. 2 is a diagram of a column slice of imager array 200 configured for three TDI row operations. The imager array shows TDI rows 1, 2, and 3 (e.g., 202, 204, and 206), where each row (202, 204, and 206) is clocked by four phase image register clocks, where the gate electrodes are each shown as Clx, where x = 1, 2, 3, and 4. The Clx within ISO row 214 (e.g., of the ISO register) between N CST110s and N SN108s are similarly clocked. Since the N CSTs are in phase with CI1 (see FIG. 4), there is no Cl1 in ISO row 214. FIG. 2 shows reset function 112 with reset gate (RST) 112A and reset drain (VDD) 112B. In one embodiment, function 112 is used to reset multiple sense nodes in parallel, and resetting includes emptying the multiple sense nodes to 0 in parallel to the reset drain voltage via the reset gate.

[0034] Each of the Clx is horizontally continuous in ISO row 214 as well as in active imaging TDI rows 202, 204, and 206, while each of the CSTs is discontinuous (e.g., each is separate and not a continuous horizontal structure). FIG. 2 shows a plurality (N - 1) of channel stops 216 in ISO row 214 that limit the spread of charge between adjacent respective channels (not shown themselves), and each channel extends between the corresponding CST110 and SN108 in ISO row 214. Although not shown, additional channel stops are present in active imaging TDI rows 202, 204, and 206, such as between adjacent TDI columns. In one embodiment, the continuous Clx gates eliminate the need for x - y matrix addressing (e.g., targeted individual addressing) for both the Clx of individual pixels and the ISO row.

[0035] Figure 3 is a schematic diagram of a single TDI row (e.g., the second row 204) readout circuit 300, which includes a corresponding source follower SF2, a sample and hold (S / H) capacitor array 302, and a comparator 304 of a column-parallel ADC for the second TDI row 204. In summary, the SF2, S / H capacitor (array) circuit 302, and column-parallel ADC 304 provide a parallel conversion function 1142 for the second TDI row 204. It should be understood that the readout circuits corresponding to the first row 202 and the third row 206 are not shown. Figure 4 shows the operation timing 400 of the readout circuits such as the image array 200 and the circuit 300.

[0036] The operation timing 400 shows the charge transfer periods 402 of three TDI rows where the respective charges at the current time are transferred, the charge transfer periods 404 of three TDI rows where the respective charges at the next time are transferred, the AD conversion windows 406 of three TDI rows where the time charges from the previous period are converted, and the AD conversion windows 408 of three TDI rows where the time charges from the current period are converted. Therefore, Figure 4 shows the overlap between charge transfer and AD conversion, and the AD conversion is delayed by only one cycle.

[0037] As shown in Figure 4, when the charge accumulated in the first TDI row 202 is separated into SN1 (the first of SN108), only CST1 (the first of CST110) is clocked high in synchronization with Cl1, and CST2 and CST3 (the second and third CSTs of CST110 respectively) are held low.

[0038] Similarly, when the charges stored in the second and third TDI lines (204 and 206) are vertically transferred, the corresponding CST2 and CST3 (the second and third CSTs of CST110) are clocked high in synchronization with Cl1, while the other two of each CST (e.g., CST1 + CST3 and CST1 + CST2 respectively) are held low for horizontal charge demultiplexing. These charge manipulation operations are shown by structures 208, 210, and 212 indicated by the dashed lines in FIG. 2.

[0039] In FIG. 4, OSx (x = 1, 2, and 3) are analog signal voltages at the outputs of the respective SF116 (e.g., SF1, SF2, and SF3). OS2 is also shown in FIG. 3. After the charge demultiplexing of the three TDI lines 202, 204, and 206 is completed, the analog signal voltages are sampled and AD-converted in parallel via the N parallel conversion functions 114 as follows with reference to FIGS. 3 and 4.

[0040] When both the SHS (sample hold signal) and SHR (sample hold reset) switches are closed, the pixel reference level is sampled at C1 when the first switch (SH1) is closed and the second switch (SH2) is open. Thereafter, both the SHR switch and the SH1 switch open, holding the reference level at C1. At the same time, the SH2 switch is closed for the CDS operation of the signal voltage of the pixel sampled by Csig transferred from the second TDI line from the previous point in time, and the pixel reference level is held at C2 sampled from the previous point in time. Thereafter, the SHS switch is opened for the next cycle. The AD conversion of the signal voltage of the previous TDI line is performed while the signal charges stored in the current TDI line are separated. Thereby, one cycle of the operation timing diagram shown in FIG. 4 is completed.

[0041] For the next cycle, when both the SHS and SHR switches are closed again, the pixel reference level is sampled to C2 when the SH2 switch is closed and the SH1 switch is open. Thereafter, both the SHR switch and the SH2 switch are opened to hold the reference level at C2. At the same time, the SH1 switch is closed for the CDS operation of the signal voltage of the pixel sampled by Csig transferred from the current second TDI row, and the current pixel reference level is held at C1. Thereafter, the SHS switch is opened again for the next cycle. The AD conversion of the signal voltage of the current TDI row is performed while the signal charge accumulated in the next TDI row is separated.

[0042] Accordingly, referring to FIG. 3, each circuit operates in a ping-pong fashion to convert its respective signal voltage by the following operation of the S / H capacitor array circuit: sampling each respective reference voltage at the current time in parallel to each respective first reference capacitor of each S / H capacitor array; sampling each respective earlier-in-time signal voltage in parallel to each respective signal capacitor; and providing in parallel to each column-parallel ADC the CDS voltage from each respective earlier-in-time reference voltage sampled by each respective second reference capacitor and each respective earlier-in-time signal voltage sampled by the signal capacitor to generate each respective earlier-in-time digital value.

[0043] In one embodiment, the operation further includes receiving, in parallel, each respective reference voltage to each respective second reference capacitor and the current signal voltage to each respective signal capacitor, and receiving, in parallel, each respective reference voltage by each respective column-parallel ADC to generate each respective current digital value from each respective current reference voltage sampled by each respective first reference capacitor and each respective current signal voltage sampled by the signal capacitor for each respective column-parallel ADC.

[0044] In one embodiment, converting each signal voltage into each digital value in parallel is, at the current time, further executed in parallel with the execution of the readout of each of the plurality of signal charges to the plurality of sense nodes at the next time. In one embodiment, executing the readout of the plurality of TDI registers to receive each signal charge is executed at the current time and is further executed in parallel with the conversion of each earlier signal voltage into each earlier digital value in terms of time. Multi-Stage Charge Steering

[0045] Figures 5A and 5B are respective embodiments of a portion (500 and 520 respectively) of a column slice of an imager pixel array configured for N = 4 TDI operation. Portion 500 shows corresponding N = 4 sense nodes 108 including SN1, SN2, SN3, and SN4 for four TDI rows (not shown). Portion 500 shows an N = 4 CST110 comprising CST1, CST2, CST3, and CST4 in a single stage or layer, which has a similar configuration to the N = 3 CST110 in the embodiment for the N = 3 TDI row of FIG. 2. In contrast, portion 520 shows a corresponding N = 4 sense node 108 and a multi-stage configuration 522 of CSTs. Here, the N = 4 CST110 defines a second layer or stage including CST2-1, CST2-2, CST2-3, and CST2-4 adjacent to SN502. The N CSTs having channels to the SNs are the final layer of the cascade. Note that there are channel stops 216 between each adjacent pair of channels. Further, portion 520 comprises a first layer 524 (an example of a prior layer) of CSTs having CST1-1 and CST1-2 that feed the second layer of CST110. Thus, in FIG. 5B, one pixel column is gradually separated into half of the column through the first stage of CST524 and then into another half (i.e., a quarter) of the column through the second stage 110. This enables better charge manipulation compared to directly separating into a quarter of the column only through CST1 to CST4 110 as shown in FIG. 5A.

[0046] In portion 500, the charge at the left end of the pixel is steered to the right end via CST4 as indicated by the dashed arrow 506. On the other hand, in portion 520, the same charge is transferred in two steps, with each transfer configured to be smaller than the total transfer indicated by the dashed arrow 506. In portion 520, the same charge first moves a shorter distance to CST1-2 as indicated by the dash-dotted arrow 526, and then moves to CST2-4 as indicated by the dotted arrow 528 in the cascade (or multi-stage) configuration of portion 520.

[0047] In one embodiment, for better charge manipulation in this cascade configuration, the number of the final CST gates is made \(2^k\), enabling expansion to any \(k\) stages. Between the CST stages, there is no channel stop for the manipulation operation in the embodiment, but the channel stop 216 exists between the last layer of CST110 and SN108 as described above.

[0048] FIG. 6 is a diagram showing the operation timing 600 of a two-stage configuration of an N = 4 TDI line operation as in FIG. 5B. The operation timing 600 shows periods 602, 604, 606, 608, and 610 regarding the current TDI lines 1 to 4 and the next TDI line 1, respectively. The following is observed in FIG. 6: CST1-1 is clocked high during the periods (dashed arrows 612 and 614) when CST2-1 and CST2-2 are clocked high, and CST1-2 is clocked high during the periods (dashed arrows 616 and 618) when CST2-3 and CST2-4 are clocked high; CST2-x lags behind CST1-x by \(n\) line periods, where \(n\) is the number of ISO lines between CST1-x and CST2-x. Barrier Implant (BIM)

[0049] FIG. 7 shows a column slice of a high-speed charge-coupled CMOS TDI imager pixel array 700 in one embodiment that is configured for N = 2 TDI operation and uses a charge manipulation gate 110 associated with a barrier implant (BIM) 702. The ISO row 214 includes additional gates Cl-last 704 and SET 706. FIG. 8 is a cross-sectional view of FIG. 7 along line A-A' or B-B' showing a portion 800 of the imager pixel array 700 that includes a charge manipulation gate CSTx (x = 1 or 2) corresponding to one of the CSTs 110 associated with the barrier implant 702. FIG. 9 is a graph 900 showing simulated channel potentials 902 and 904 along cut lines A-A' and B-B' when CST1 and CST2 are clocked high and low, respectively. FIG. 10 shows an operation timing 1000 in one embodiment. The operation timing 1000 relates to the high-speed charge-coupled CMOS TDI imager pixel array 700. The operation timing 1000 is similar to the embodiment of FIG. 4 but with N = 2 and has different specific timings for the structure in the embodiment of FIG. 7, showing timing periods 402, 404, 406, and 408. The operation timing 1000 further includes the timing of the last AC gate electrode Cl-last 704 before the DC gate SET 706.

[0050] In one embodiment, as shown in FIG. 8, the portion 800 includes a silicon substrate 802 carrying a buried channel 804 having a gate oxide 806 on its top. On the gate oxide 806, various gate electrodes (collectively 808) are provided, including four phase clocks (Cl1, Cl2, Cl3, and CI4) and electrodes for the charge steering gate CSTx. The BIM 702 is disposed within the buried channel 804 under the CSTx and under the gate oxide 806. The BIM 702 includes p-type dopants (e.g., boron) and generates a potential barrier when the gate CSTx is clocked low. The graph 900 shows a simulation of the resulting channel potential values. The use of the BIM 702 helps to ensure that charge separation is appropriate and that charge does not leak on the CST when it is clocked low.

[0051] In embodiments of the BIM, the timing shown in FIG. 10 is different compared to the timing of FIG. 4 for a non-BIM embodiment of a single layer. Unlike a CST without BIM, charge cannot be accumulated under a CST with BIM. An embodiment including a single layer of CST110 is shown, but the BIM is useful for multi-stage CSTs. Bidirectional

[0052] FIGS. 11A and 11B are block diagrams showing high-speed charge-coupled CMOS TDI imagers 1100A and 1100B configured for bidirectional operation according to respective embodiments. The bidirectional operation responds to the scanning direction (e.g., forward and reverse) performed by the CMOS TDI imager. In a first bidirectional embodiment, a CCD pixel array 1101 marked by a dashed box is shown, comprising a plurality of TDI pixel registers 1102 having a plurality of ISO registers 1004 at the bottom (forward direction) and a plurality of ISO registers 1006 at the top (reverse direction) coupled to their respective ends.

[0053] In one embodiment, each of the ISO registers 1104 and 1106 includes a CST110. Each of the ISO registers 1104 and 1106 is connected to respective plural output structures 1108 and 1110 that include an SN108, a reset function 112, and an SF116 (not shown in FIG. 11A), and the output structures 1108 and 1110 are coupled to respective plural S / H capacitor array circuits and column-parallel ADCs 1112 and 1114, respectively.

[0054] FIG. 11A shows a representative column slice 1116 of the CMOS TDI imager 1100A, marked with a dashed line. The column slice 1116 includes a column subset of the TDI pixel registers 1102, a column subset of the ISO registers 1104 and 1106, respective column subsets of the output structures 1108 and 1110, and respective column subsets of the S / H capacitor array circuits and the column-parallel ADCs 1112 and 1114. The column subset of the TDI pixel registers 1102 is equivalent to a plurality of M TDI pixel registers 104.

[0055] In a second bidirectional embodiment 1100B, the respective output structures 1108 and 1110 at each end of the CCD pixel array 1101 are multiplexed to an S / H capacitor array and a column-parallel ADC 1112 located at one end of the CMOS TDI imager 1100A.

[0056] It will be appreciated that FIGS. 11A and 11B are simplified and can be implemented with appropriate adaptations using, for example, the CST110 and the above-described readout circuit 300.

[0057] FIG. 12 is a flowchart showing operation 1200 in one embodiment. In one example, the operation is performed by an apparatus including a circuit. In one embodiment, the apparatus includes a circuit as shown in any of the respective embodiments of FIGS. 1, 2, 7, 11A, and 11B. In operation 1202, to receive respective signal charges at a plurality (N) of sense nodes, a readout of a plurality (N) of TDI pixel registers is performed, and the readout uses a plurality (N) of charge manipulation gates to manipulate and separate respective charges from each pixel register to the plurality of sense nodes. In operation 1204, an output from the plurality of sense nodes is provided to generate respective digital values. In one embodiment, the output is used to perform a parallel conversion of the plurality of sense nodes. In one embodiment, the operation of performing the parallel conversion includes converting respective signal charges in parallel to respective signal voltages and converting respective signal voltages in parallel to respective digital values.

[0058] In one embodiment, the operation includes resetting a plurality of sense nodes in parallel to receive respective signal charges. Resetting the plurality of sense nodes in parallel includes setting the plurality of sense nodes to 0 at a reset drain voltage in parallel via a reset gate.

[0059] In one embodiment, charges are transferred in a vertical direction and manipulated by a plurality (N) of charge manipulation gates and separated in a horizontal direction to the plurality of sense nodes.

[0060] In one embodiment, the plurality (N) of charge manipulation gates define a final stage of the manipulation gates, and the operation includes transferring charges (e.g., from a TDI row) to a stage before the manipulation gates in a cascade for manipulation at the final stage of the manipulation gates.

[0061] In one embodiment, each charge manipulation gate of the plurality (N) of charge manipulation gates is associated with (e.g., receives) a respective barrier implant (BIM) that defines a potential barrier when the respective charge manipulation gate is clocked low.

[0062] In one embodiment, multi-phase image register clocks are used to clock a pixel register, each charge manipulation gate, and a plurality (N) of respective ISO registers for transferring charge. In one embodiment, each gate electrode (Clx) is associated with a respective phase of a horizontally continuous clock in order to remove x-y matrix addressing to each Clx within the ISO register. In one embodiment, a channel stop is used between channels extending from each of a plurality (N) of charge manipulation gates to each of a plurality (N) of sense nodes in order to avoid mixing of charge between channels within the ISO register.

[0063] In one embodiment, each of the sense nodes is coupled to a respective source follower (SF) to provide a respective signal voltage for conversion to a respective digital value.

[0064] In one embodiment, the operation is performed in a high-speed CMOS TDI image sensor that includes a plurality of CCD pixels arranged in a matrix form, the column slice of which includes a plurality (N) of TDI pixel registers, the plurality of ISO registers includes CST, and the plurality of output structures includes a plurality of sense nodes, a global reset structure, and a plurality of SFs, a plurality of S / H capacitor arrays, and a plurality of column parallel ADCs.

[0065] In a bidirectional embodiment, a forward sense node is coupled to one end of the CCD pixel array, a reverse sense node is coupled to the other end of the CCD pixel array, and the operation is performed using one of the forward sense node and the reverse sense node as the plurality of sense nodes in response to a scan direction.

[0066] Practical implementations can include any or all of the features described herein. These and other aspects, features and various combinations can be represented as a method for performing functions, an apparatus, a system, a means and other ways of combining the features described herein. Some embodiments have been described. Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of the processes and techniques described herein. In addition, other steps can be provided, or steps can be excluded from the described processes, and other components can be added to or removed from the described systems. Accordingly, other aspects are within the scope of the claims.

[0067] Throughout the description and claims of this specification, the words "comprise", "contain" and their variants mean "including but not limited to" and are not intended to exclude other components, integers or steps. Throughout this specification, the singular form encompasses the plural form unless the context requires otherwise. In particular, when an indefinite article is used, it should be understood that both the singular and the plural are intended unless the context requires otherwise.

[0068] Features, integers, characteristics or groups described in connection with a particular aspect, embodiment or example of the invention are to be understood as applicable to any other aspect, embodiment or example, unless incompatible therewith. All features (including any appended claims, abstract and drawings) disclosed in this specification and / or all steps of any method or process so disclosed may be combined in any combination, except combinations where at least some of such features and / or steps are mutually exclusive. The invention is not limited to the details of any foregoing example or embodiment. The invention extends to any novel one or any novel combination of features disclosed in this specification (including any appended claims, abstract and drawings) or any novel one or any novel combination of steps of any method or process so disclosed. <Others> <Means> The method of Technical Idea 1 performs the readout of a plurality (N) of time delay and integration (TDI) pixel registers to receive respective signal charges at a plurality (N) of sense nodes, and the readout uses a plurality (N) of charge manipulation gates to manipulate and separate respective charges from respective pixel registers to a plurality of sense nodes and provides outputs from the plurality of sense nodes to generate respective digital values. The method of Technical Idea 2, in the method described in Technical Idea 1, includes resetting the plurality of sense nodes in parallel to receive the respective signal charges. The method of Technical Idea 3, in the method described in Technical Idea 2, resetting the plurality of sense nodes in parallel includes setting the reset drain voltage to 0 for the plurality of sense nodes via a parallel reset gate. The method of Technical Idea 4, in the method described in any one of Technical Ideas 1 to 3, the charges are manipulated by the plurality (N) of charge manipulation gates for separating in the horizontal direction to the plurality of sense nodes and transferred in the vertical direction. The method of Technical Idea 5, in the method described in any one of Technical Ideas 1 to 4, the plurality (N) of charge manipulation gates define a final stage of the charge manipulation gate, and the method includes transferring the charges to a previous stage of the charge manipulation gate in a cascade to manipulate at the final stage of the charge manipulation gate. The method of Technical Idea 6, in the method described in any one of Technical Ideas 1 to 5, each charge manipulation gate of the plurality (N) of charge manipulation gates receives a respective barrier implant (BIM) that defines a potential barrier when each charge manipulation gate is clocked low. The method of Technical Idea 7 is, in the method described in any of Technical Ideas 1 to 6, in order to transfer charges using a multiphase image register clock, each of the pixel registers, each of the charge manipulation gates, and each of the plurality (N) of isolation (ISO) registers is clocked, and each of the respective gate electrodes (Clx) associated with each phase of the multiphase image register clock where each Clx is horizontally continuous is used to remove the x-y matrix addressing to each Clx in the ISO register, and in order to avoid the mixing of charges between channels in the ISO register, a channel stop between channels extending from each of the plurality (N) of charge manipulation gates to each of the plurality (N) of sense nodes is used. The method of Technical Idea 8 is, in the method described in any of Technical Ideas 4 to 6, in order to transfer charges from one of the pixel registers to the corresponding one of the charge manipulation gates, only the corresponding one of the charge manipulation gates is a high clock while the remaining ones of the plurality (N) of charge manipulation gates are low clocks. The method of Technical Idea 9 is, in the method described in any of Technical Ideas 1 to 8, each of the sense nodes is coupled to a respective source follower (SF) to provide the respective signal voltage for the conversion to the respective digital value. The method of Technical Idea 10 is, in the method described in any of Technical Ideas 1 to 9, the output is provided to perform a parallel conversion of the plurality of sense nodes to generate the respective digital values. The method of Technical Idea 11 is, in the method described in Technical Idea 10, performing the parallel conversion includes converting each signal charge to a respective signal voltage in parallel and converting each signal voltage to a respective digital value in parallel. The method of Technical Idea 12 is, in the method described in Technical Idea 11, that converting each of the signal voltages includes sampling the reference voltage at each of the first reference capacitors of each S / H capacitor array in parallel at the current time point, sampling the earlier signal voltage in terms of time at each of the signal capacitors in parallel, and providing, in parallel to each column-parallel analog-to-digital converter (ADC), the correlated double sampling (CDS) voltage from each of the earlier reference voltages sampled at each of the second reference capacitors and the earlier signal voltage sampled at the signal capacitor, so as to generate each earlier digital value, and operating a sample-and-hold (S / H) capacitor array circuit in a ping-pong manner. The method of Technical Idea 13 is, in the method described in Technical Idea 12, further including, in parallel, receiving each reference voltage to each of the second reference capacitors and the current signal voltage to each of the signal capacitors, and providing, in parallel to each column-parallel ADC, each CDS voltage to generate each current digital value from each of the current reference voltages sampled at each of the first reference capacitors and each of the current signal voltages sampled at the signal capacitor. The method of Technical Idea 14 is, in the method described in any one of Technical Ideas 11 to 13, that converting each of the signal voltages into each digital value in parallel is further executed in parallel with the execution of the readout at the next time point of each of the plurality of signal charges to the plurality of sense nodes at the current time point. The method of Technical Idea 15 is, in the method described in any one of Technical Ideas 1 to 14, that executing the readout of the plurality of TDI registers to receive each of the signal charges is executed at the current time point and is further executed in parallel with the conversion of each of the earlier signal voltages into each of the earlier digital values. The method of Technical Idea 16 is the method described in any of Technical Ideas 1 to 15, wherein the method is executed by a high-speed CMOS TDI image sensor including a plurality of charge-coupled device (CCD) pixels arranged in the form of a CCD pixel matrix, the column slices of which include the plurality (N) of TDI pixel registers, the plurality (N) of separate (ISO) registers include the plurality (N) of CSTs, the plurality (N) of output structures include the plurality (N) of sense nodes, a global reset structure, and a plurality of SFs, and the plurality (N) of parallel conversion components include an S / H capacitor array and a plurality of column-parallel ADCs. The method of Technical Idea 17 is the method described in Technical Idea 16, wherein the forward sense node is coupled to one end of the CCD pixel matrix, the reverse sense node is coupled to the other end of the CCD pixel matrix, and in response to the scanning direction, it is executed using one of i) the forward sense node and ii) the reverse sense node as the plurality (N) of sense nodes. The apparatus of Technical Idea 18 includes a plurality (N) of time delay and integration (TDI) pixel registers, a plurality (N) of separate (ISO) registers including a plurality (N) of charge manipulation gates coupled to the plurality (N) of TDI pixel registers, and a plurality (N) of output structures including a plurality (N) of sense nodes coupled to receive respective signal charges read out from the plurality (N) of TDI pixel registers to be manipulated and separated by the plurality (N) of charge manipulation gates. The plurality (N) of sense nodes are coupled to provide outputs for generating digital values, each of the plurality (N) of sense nodes is configured to include a circuit providing a parallel reset function, and each of the plurality (N) of sense nodes is coupled via a plurality (N) of source followers (SFs) to a plurality (N) of sample and hold (S / H) capacitor circuits and a plurality (N) of column-parallel analog-to-digital converters (ADCs) to generate respective digital values for respective signal charges in parallel. The device of Technical Idea 19, in the device described in Technical Idea 18, the charges are manipulated by the plurality (N) of charge manipulation gates to be separated horizontally in the plurality of sense nodes and transferred vertically. The device of Technical Idea 20, in the device described in Technical Idea 18 or 19, the plurality (N) of charge manipulation gates define the final stage of the charge manipulation gates, and in cascade, to manipulate the charges at the final stage of the charge manipulation gates, it includes the stage before the manipulation gate coupled to the TDI pixel register and the final stage of the charge manipulation gates. The device of Technical Idea 21, in the device described in Technical Idea 18 or 19, each charge manipulation gate of the plurality (N) of charge manipulation gates receives a respective barrier implant (BIM) that defines a potential barrier when each charge manipulation gate is clocked low. The device of Technical Idea 22, in the device described in any one of Technical Ideas 18 to 21, a polyphase image register clock for clocking the pixel register, each of the charge manipulation gates, and each of the ISO registers for transferring the charges, and each gate electrode (Clx), each Clx is associated with a respective phase of the polyphase image register clock that is continuous horizontally to remove the x - y matrix addressing for each Clx in the ISO register, and a channel stop between channels extending from each channel of the plurality (N) of charge manipulation gates to each channel of the plurality (N) of sense nodes to avoid mixing of charges between channels in the ISO register. The device of Technical Idea 23, in the device described in any one of Technical Ideas 19 to 21, is configured to transfer the charges from one of the pixel registers to the corresponding one of the charge manipulation gates, and while clocking the remaining charge manipulation gates of the plurality (N) of charge manipulation gates low, only the corresponding one of the charge manipulation gates is clocked high. The device of technical idea 24 is the device described in any one of technical ideas 16 to 23, wherein each of the sense nodes is coupled to each of the S / H capacitors via an SF for CDS operation. The device of technical idea 25 is the device described in technical idea 23 or 24, wherein while the column-parallel ADC converts the respective signal charges from the current point in time, the respective signal charges are configured to be read out to the sense nodes at the next point in time. The device of technical idea 26 is the device described in technical idea 25, wherein each of the sense nodes is coupled to the column-parallel ADC via each S / H capacitor array, and each of the arrays includes two reference capacitors and a signal capacitor for ping-pong type S / H operation. The device of technical idea 27 is the device described in technical idea 26, wherein each first reference capacitor of each of the S / H capacitor arrays samples each reference voltage in parallel at the current point in time, samples each earlier signal voltage in parallel at each signal capacitor, and provides in parallel to each column-parallel ADC the CDS voltage from each earlier reference voltage sampled at each second reference capacitor and each earlier signal voltage sampled at the signal capacitor to generate each earlier digital value, and the respective S / H capacitor arrays operate collectively. The device of technical idea 28 is the device described in technical idea 27, and further in parallel, receives each reference voltage to each of the second reference capacitors and the current signal voltage to each of the signal capacitors, and provides in parallel to each column-parallel ADC the CDS voltage from each current reference voltage sampled at each first reference capacitor and each current signal voltage sampled at the signal capacitor to generate each current digital value, and the respective S / H capacitor arrays operate collectively. The apparatus of technical idea 29 is an apparatus described in any one of technical ideas 18 to 28, and includes a complementary metal-oxide semiconductor (CMOS) TDI image sensor. A plurality of charge-coupled device (CCD) pixels are arranged in the form of a CCD pixel matrix, and its column slice includes a plurality (N) of TDI pixel registers. The plurality (N) of ISO registers include the plurality (N) of CSTs. The plurality (N) of output structures include the plurality (N) of sense nodes, a global reset structure that provides the parallel reset function, and the plurality (N) of SFs, the plurality (N) of S / H capacitor arrays, and the plurality (N) of column-parallel ADCs. The apparatus of technical idea 30 is an apparatus described in technical idea 29, and includes a forward sense node coupled to a first end of the CCD pixel matrix and a reverse sense node coupled to a second end of the CCD pixel matrix for bidirectional operation. One of i) the forward sense node and ii) the reverse sense node selectively defines the plurality (N) of sense nodes in response to a scanning direction. The apparatus of technical idea 31 includes a circuit configured to execute the method described in any one of technical ideas 1 to 17.

Claims

1. The reading of a plurality (N) of time delay and integration (TDI) pixel registers is performed in parallel to receive the respective charges in parallel at a plurality (N) of sense nodes provided corresponding to each of the plurality of TDI pixel registers, and the reading uses a plurality (N) of charge manipulation gates provided corresponding to each of the plurality of TDI pixel registers to manipulate and separate the respective charges from the plurality of TDI pixel registers to the plurality of sense nodes in parallel, A method characterized by providing the outputs from the plurality of sense nodes in parallel to generate the respective digital values in parallel.

2. The reading of a plurality (N) of time delay and integration (TDI) pixel registers is performed in parallel to receive the respective charges in parallel at a plurality (N) of sense nodes provided corresponding to each of the plurality of TDI pixel registers, and the reading uses a plurality (N) of charge manipulation gates provided corresponding to each of the plurality of TDI pixel registers to manipulate and separate the respective charges from the plurality of TDI pixel registers to the plurality of sense nodes in parallel, The plurality of charge manipulation gates separate the vertical charges transferred from the plurality of TDI pixel registers in the horizontal direction and manipulate the charges in parallel to the plurality of sense nodes. A method characterized by providing the outputs from the plurality of sense nodes in parallel to generate the respective digital values in parallel.

3. The method according to claim 1 or 2, characterized in that a plurality of the sense nodes are reset to receive the respective charges.

4. The method according to claim 3, characterized in that resetting the plurality of sense nodes is to set the reset drain voltage to 0 for the plurality of sense nodes via a reset gate.

5. The method according to any one of claims 1 to 4, characterized in that the charges are manipulated by the plurality of charge manipulation gates for separating in the horizontal direction to the plurality of sense nodes and transferred in the vertical direction.

6. The method according to any one of claims 1 to 5, characterized in that, in a cascade, the charges are transferred to a stage preceding the charge steering gate in order for the plurality of charge steering gates to define a final stage of the charge steering gate and for the method to steer to the final stage of the charge steering gate.

7. The method according to any one of claims 1 to 6, characterized in that each of the plurality of charge steering gates receives a respective barrier implant (BIM) that defines a potential barrier when each of the charge steering gates is clocked low.

8. Each of the TDI pixel registers, each of the charge steering gates, and each of the plurality (N) of isolation (ISO) registers is clocked to transfer the charges using a polyphase image register clock, Using each of the Clx associated with each phase of the polyphase image register clock, where each gate electrode (Clx) is horizontally continuous, to remove x-y matrix addressing to each of the Clx in the ISO register, The method according to any one of claims 1 to 7, characterized in that channel stops between the channels are used that extend from each of the plurality of charge steering gates to each of the plurality of sense nodes to avoid mixing of the charges between the channels in the ISO register.

9. The method according to any one of claims 5 to 7, characterized in that only a corresponding one of the charge steering gates is clocked high while the remaining charge steering gates are clocked low to transfer the charges from one of the TDI pixel registers to the corresponding one of the charge steering gates.

10. The method according to any one of claims 1 to 9, characterized in that each of the sense nodes is coupled to a respective source follower (SF) to provide a respective signal voltage for conversion to a respective digital value.

11. The output is provided to perform a parallel conversion of the plurality of sense nodes to generate respective digital values, Performing the parallel conversion is To convert each of the charges in parallel to a respective signal voltage and to convert each of the signal voltages in parallel to a respective digital value. Converting each of the signal voltages into each of the digital values in parallel is further characterized in that, at the current time point, it is executed in parallel with the execution of the readout at the next time point of each of the plurality of charges to the plurality of sense nodes, according to any one of claims 1 to 10.

12. Executing the readout of the plurality of TDI pixel registers to receive each of the charges is executed at the current time point and is further executed in parallel with the conversion of each of the earlier signal voltages into each of the earlier digital values, according to any one of claims 1 to 11.

13. The method is executed in a high-speed CMOS TDI image sensor including a plurality of charge-coupled device (CCD) pixels arranged in the form of a CCD pixel matrix, the column slice of which includes a plurality (N) of the TDI pixel registers, the plurality (N) of isolation (ISO) registers include a plurality (N) of the charge manipulation gates, the plurality (N) of output structures include a plurality (N) of the sense nodes, a global reset structure and a plurality of source followers (SF), and the plurality (N) of parallel conversion components include an S / H capacitor array and a plurality of column-parallel ADCs, according to any one of claims 1 to 12.

14. The forward sense node is coupled to one end of the CCD pixel matrix. The reverse sense node is coupled to the other end of the CCD pixel matrix. Responsive to the scanning direction, it is characterized in that it is executed using one of i) the forward sense node and ii) the reverse sense node as a plurality (N) of the sense nodes, according to claim 13.

15. A plurality (N) of time delay and integration (TDI) pixel registers, A plurality (N) of isolation (ISO) registers each having a plurality (N) of charge manipulation gates coupled to each of the plurality of TDI pixel registers, A plurality (N) of output structures each having a plurality (N) of sense nodes coupled to receive in parallel each of the charges read out from the plurality of TDI pixel registers so as to be manipulated and separated in parallel by the plurality of charge manipulation gates, and the plurality (N) of the sense nodes are coupled to provide an output for generating digital values in parallel. Each of the plurality of the sense nodes is configured to include a circuit that provides a parallel reset function. Each of the plurality of the sense nodes is coupled to a plurality (N) of sample and hold (S / H) capacitor circuits and a plurality (N) of column parallel analog-to-digital converters (ADCs) via a plurality (N) of source followers (SF), and is characterized in that it generates, in parallel, respective digital values for respective ones of the respective charges. **Claim 16**: A plurality (N) of time delay and integration (TDI) pixel registers, a plurality (N) of isolation (ISO) registers each having a plurality (N) of charge manipulation gates coupled to a respective one of the plurality of the TDI pixel registers, a plurality (N) of output structures each having a plurality (N) of sense nodes coupled to receive, in parallel, respective charges read out from the plurality of the TDI pixel registers so as to be manipulated and separated in parallel by the plurality of the charge manipulation gates, wherein the plurality (N) of the sense nodes are coupled to provide outputs for generating digital values in parallel, the plurality of the charge manipulation gates separate the vertical-direction charges transferred from the plurality of the TDI pixel registers in the horizontal direction and manipulate the charges to the plurality of the sense nodes in parallel. Each of the plurality of the sense nodes is configured to include a circuit that provides a parallel reset function. Each of the plurality of the sense nodes is coupled to a plurality (N) of sample and hold (S / H) capacitor circuits and a plurality (N) of column parallel analog-to-digital converters (ADCs) via a plurality (N) of source followers (SF), and is characterized in that it generates, in parallel, respective digital values for respective ones of the respective charges. **Claim 17**: The apparatus according to claim 15 or 16, wherein the charges are manipulated by the plurality of the charge manipulation gates to be transferred in the vertical direction for separation in the horizontal direction to the plurality of the sense nodes. **Claim 18** The plurality of charge manipulation gates define a final stage of the charge manipulation gates, and in a cascade, to manipulate the charge at the final stage of the charge manipulation gates, comprise a stage before the manipulation gate coupled to the TDI pixel register and the final stage of the charge manipulation gates, for the apparatus according to any one of claims 15 to 17.

19. Each of the plurality of charge manipulation gates receives a respective barrier implant (BIM) that defines a potential barrier when each of the charge manipulation gates is clocked low, for the apparatus according to any one of claims 15 to 17.

20. A polyphase image register clock for clocking the TDI pixel register, each of the charge manipulation gates, and each of the ISO registers for transferring the charge; Each gate electrode (Clx), each Clx associated with a respective phase of the polyphase image register clock in which each Clx is horizontally continuous, to remove x - y matrix addressing for each Clx in the ISO register; A channel stop between channels extending from each channel of the plurality of charge manipulation gates to each channel of the plurality of sense nodes to avoid mixing of the charge between channels in the ISO register, for the apparatus according to any one of claims 15 to 19.

21. Configured to transfer the charge from one of the TDI pixel registers to a corresponding one of the charge manipulation gates, and clock only the corresponding one of the charge manipulation gates high while clocking the remaining charge manipulation gates low, for the apparatus according to any one of claims 17 to 19.

22. Each of the sense nodes is coupled to a respective S / H capacitor via the SF for CDS operation, for the apparatus according to any one of claims 15 to 21.

23. Configured to read each of the charges to the sense node at a next time point while the column - parallel ADC converts each of the charges from a current time point, for the apparatus according to claim 21 or 22.

24. An apparatus according to any of claims 15 to 23, comprising a complementary metal oxide semiconductor (CMOS) TDI image sensor, wherein a plurality of charge coupled device (CCD) pixels are arranged in the form of a CCD pixel matrix, a column slice of which includes a plurality of the TDI pixel registers, a plurality of the ISO registers includes a plurality of the charge manipulation gates, and a plurality of the output structures include a plurality of the sense nodes, a global reset structure providing the parallel reset function, and a plurality of the SF, a plurality of the S / H capacitor arrays, and a plurality of the column parallel ADCs.

25. Including the forward sense node coupled to the first end of the CCD pixel matrix and the reverse sense node coupled to the second end of the CCD pixel matrix for bidirectional operation, One of i) the forward sense node and ii) the reverse sense node is characterized by selectively defining a plurality of the sense nodes in response to a scanning direction, for the apparatus according to claim 24.

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