3D Bit Cost Scalable Memory

Abstract

To provide a 3D bit cost scalable memory device.SOLUTION: A 3D bit cost scalable memory device includes a stack of layers and a via electrode 150 extending vertically through the stack of layers. The layers include a separator layer 110, a controllable conductivity layer 120 and an electrode layer. The electrode layer has an electrode conductor portion 130 and a separator portion 140 that separates the via electrode from the electrode conductor portion of the electrode layer. At least one storage portion of the controllable conductivity layer is in electrical series between the via electrode and the electrode conductor portion of the electrode layer. The via electrode comprises, for example, tungsten (W). The controllable conductivity layer comprises, for example, an ovonic threshold switch material. The electrode conductor portion of the electrode layer comprises, for example, carbon (C).SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present disclosure relates to memory cells, including memory cells used in integrated circuits.

Background Art

[0002] Memory cells (such as those used in integrated circuits) benefit from performance improvements such as reduced latency, increased bandwidth, and / or decreased power consumption. Memory cells further benefit from cost improvements such as increased density. For example, the scaling of DRAM has slowed down, resulting in a stall in performance and / or cost improvement.

Summary of the Invention

[0003] One or more computer systems can be configured to perform a particular operation or action, which is due to software, firmware, hardware, or a combination thereof that installs in the system to perform and / or control such actions in the operation. One or more computer programs can be configured to perform a particular operation or action, which is due to instructions included therein that cause such actions to be performed by the data processing device when executed.

[0004] A first aspect includes a memory device. The memory device includes a stack of layers, where the layers optionally have a controllable conductive layer and an electrode layer adjacent to the controllable conductive layer; and a via electrode extending longitudinally through the stack, where the electrode layer optionally includes a conductor portion and a separator portion separating the via electrode from the conductor portion, and at least one storage portion of the controllable conductive layer is electrically continuous between the via electrode and the conductor portion.

[0005] The deformable form optionally includes one or more of the following features, either alone or in any combination. The stack of the layers has an inner sidewall defining a hole for accommodating the via electrode. The controllable conductive layer includes an ovonic threshold switch (OTS) material. The conductor portion optionally includes carbon (C) combined with a metallic material. The conductor portion optionally includes a material selected from the group consisting of tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), cobalt (Co), and ruthenium (Ru). The via electrode optionally includes tungsten (W). The via electrode optionally has titanium nitride (TiN). The separator portion optionally includes a dielectric material. The via electrode is one of a plurality of via electrodes each extending longitudinally in the stack, and the stack has a plurality of inner sidewalls defining holes for accommodating each of the plurality of via electrodes. The controllable conductive layer is one of a plurality of controllable conductive layers, the electrode layer is one of a plurality of electrode layers, and each controllable conductive layer of the plurality of controllable conductive layers is adjacent to each of the plurality of electrode layers. The layer optionally has a separation layer, and at least one of the separation layers separates each controllable conductive layer of the plurality of controllable conductive layers from other controllable conductive layers of the plurality of controllable conductive layers, and at least one of the separation layers separates each electrode layer of the plurality of electrode layers from other electrode layers of the plurality of electrode layers. The conductor portion is one of a plurality of conductor portions, the separator portion is one of a plurality of separator portions, each electrode layer of the plurality of electrode layers optionally includes each of the plurality of conductor portions, and corresponding to each via electrode of the plurality of via electrodes, each separator portion of the plurality of separator portions is optionally included, and the plurality of separator portions separate the via electrode from the plurality of conductor portions.The memory portion is a specific memory portion, and corresponding to each via electrode among the plurality of via electrodes and each electrode layer among the plurality of electrode layers, at least one memory portion of the controllable conductive layer adjacent to each electrode layer is electrically continuous between the each via electrode and the conductor portion of the each electrode layer, and the specific memory portion is one of the each memory portion. Each conductor portion among the plurality of conductor portions is operable as a respective word line of a memory array, each via electrode among the plurality of via electrodes is operable as a respective bit line of the memory array, each memory portion can be used as a non-volatile storage for storing a portion of information of the memory array, and the information can be decomposed into binary information of one or more bits accessible using the word line and the bit line between which the memory portion is electrically continuous. The memory device is suitable for implementing non-volatile storage in a solid state disk (SSD), implementing a storage class memory (SCM), and / or implementing a memory compliant with Compute Express Link (CXL).

[0006] A second aspect includes a method of forming a memory device. The method includes forming a stack of layers, where the layers include a controllable conductive layer and an electrode layer adjacent to the controllable conductive layer; and forming via electrodes extending vertically through the stack, where the electrode layer optionally includes a conductor portion and a separator portion, the separator portion separating the conductor portion from the via electrode, and at least one memory portion of the controllable conductive layer is electrically continuous between the via electrode and the conductor portion.

[0007] The deformed form optionally includes one or more of the following features, either alone or in any combination. In the method, the step of forming the via electrode optionally includes the step of forming a hole so as to penetrate the stack, and the hole defines the dimensions of the via electrode throughout the layer. An undercut is formed in the electrode layer such that the undercut surrounds the hole and the undercut defines the volume for the separator portion, whereby the electrode layer is formed. The electrode layer is formed by forming the separator portion within the undercut. The controllable conductive layer optionally includes an ovonic threshold switch (OTS) material, and the conductor portion optionally includes carbon (C).

[0008] A third aspect includes a processor and a memory capable of storing instructions executable by the processor, and when executed by the processor, the instructions cause the processor to perform an operation. The operation includes a method of forming a memory device.

[0009] The deformed form of the above aspect optionally includes hardware, a method or process, or computer software on a computer-accessible medium.

[0010] Other aspects and advantages of the present disclosure will become apparent from the drawings, the detailed description, and the claims.

Brief Description of the Drawings

[0011]

Fig. 1A

Fig. 1B

Fig. 1C

[0012]

Fig. 2

[0013]

Fig. 3

[0014]

Fig. 4

Fig. 5

Fig. 6

Fig. 7

Fig. 8

[0015]

Fig. 9

DETAILED DESCRIPTION OF THE INVENTION

[0016] With reference to FIGS. 1A to 1C and FIGS. 2 to 9, a detailed description of the technology related to 3D bit-cost scalable memory is provided.

[0017] One or more flow diagrams are described herein. The processes described by these flow diagrams can be implemented and / or directed using a processor, which is programmed using a computer program executable by the processor and stored in a memory accessible by a computer system, using dedicated logic hardware (including field programmable integrated circuits), and using various combinations thereof. It is possible to combine various actions, execute them in parallel, and / or execute various actions in different sequences without affecting the processes being implemented. In some cases, the same result is achieved only when the actions are rearranged and, in addition, certain other changes are made. In other cases, the same result is achieved only when the actions are rearranged and certain conditions are met. Further, for clarity, some of the flow diagrams in this specification omit some specific actions that are not necessary to understand the disclosed technology. It is possible to perform various additional actions before, after, and / or between the illustrated actions.

[0018] The following are examples of selected acronyms, abbreviations, and short forms used within the description. [Table 1] Concept of 3D bit cost scalable memory

[0019] The 3D bit cost scalable memory described herein comprises a structure for forming non-volatile memory cells. These memory cells are enabled to store information such as one or more bits of information per memory cell. The memory cells are formed at the intersections of vertical bit lines and horizontal word planes, and information storage is provided at these intersections. Each memory cell is formed by an active layer pair. A separation layer separates the memory cells from each other in the vertical dimension.

[0020] The word line plane is formed from a thin film layer deposited on the wafer plane. The vertical bit lines are orthogonal to the wafer plane.

[0021] To fabricate an electronic device comprising one or more 3D bit cost scalable memories described herein, integrated circuit fabrication techniques such as those based on planar processing of a silicon wafer can be used.

[0022] Some 3D bit cost scalable memories described herein enable access latency equivalent to DRAM (e.g., faster than 3D NAND-based memory) and also enable density equivalent to 3D NAND-based memory (e.g., higher density than DRAM). Some 3D bit cost scalable memories described herein enable cost reduction in memory fabrication as compared to other memory fabrication techniques.

[0023] Throughout the description herein and the associated drawings, elements with like numbers are the same element, substantially the same element, and / or corresponding to an example thereof. For example, via electrode 150 in FIG. 1A is the same as via electrode 150 in FIG. 1B. For other examples, the completed separator layer 510 in FIG. 5 is the same as the completed separator layer 510 in FIG. 6.

[0024] Throughout the drawings, unless otherwise indicated, similarly hatched elements correspond to elements that include the same or substantially the same type of material (such as the same or substantially similar chemical composition and / or structure). For example, the hatching of controllable conductive layer 420 in FIG. 4 is the same as that of the completed controllable conductive layer 520 in FIG. 5, indicating that controllable conductive layer 420 and the completed controllable conductive layer 520 are made of substantially the same material such as an OTS material.

[0025] Figures 1A through 1C show various aspects of a memory cell of a 3D bit-cost scalable memory. Figure 1A shows a 3D view of a portion of the 3D bit-cost scalable memory. There are six examples of via electrodes 150. There are five examples of separator layers 110, four examples of controllable conductive layers 120, and four examples of electrode layers including electrode conductor portions 130 and separator portions 140. At each intersection of examples of via electrodes 150 and electrode conductor portions 130, there is an example of a separator portion 140.

[0026] Figure 1B shows a side view of a portion of the 3D bit-cost scalable memory. This figure corresponds to cross-section B-B of Figure 1C. The upper and lower layers of the stack are examples of separator layers 110. Each example of a controllable conductive layer 120 is adjacent to a corresponding layer comprising an example of an electrode conductor portion 130 and an example of a separator portion 140. Each example of a separator portion 140 surrounds a portion of one of the examples of via electrodes 150. The example of the separator layer 110 forms the top and bottom layers, and a further example of the separator layer 110 forms a separator between the layer formed from the electrode conductor portion 130 combined with the separator portion 140 and the controllable conductive layer 120. The parentheses 199 indicate that any number of repetitions of a three-layer stack of (1) the controllable conductive layer 120, (2) the electrode layer formed from the electrode conductor portion 130 combined with the separator portion 140, and (3) the separator layer 110 are possible. For example, within an example of the controllable conductive layer 120, information storage is provided respectively by an (active) portion that is electrically continuous between an example of a via electrode 150 and an example of an electrode conductor portion 130.

[0027] Figure 1C shows a top view of a portion of the 3D bit-cost scalable memory. This figure corresponds to cross-section A-A of Figure 1B. An example of a via electrode 150 surrounded by an example of a separator portion 140 is disposed within an example of an electrode conductor portion 130.

[0028] Figure 2 shows a schematic diagram of various aspects of a memory cell of a 3D bit-cost scalable memory. For clarity, the structures associated with two bit lines (bit lines 250 and 251) are shown. Bit line 250 is coupled in parallel to a plurality of memory cells. An exemplary memory cell is shown as memory cell 280. Bit line 250 is coupled to a source line selector (not shown) via a To source line selector (SLS) 290. Bit line 251 is coupled to a source line selector (not shown) via a To source line selector (SLS) 291. As indicated by bracket 299, the number of memory cells implemented is arbitrary. Bracket 299 conceptually corresponds to bracket 199 of FIG. 1B.

[0029] Memory cell 280 is implemented by elements of FIG. 1B, such as, for example, a two-layer stack of electrode layers formed from (1) a controllable conductive layer 120 and (2) an electrode conductor portion 130 combined with a separator portion 140. As a specific example, memory cell 280 is implemented by a portion that is electrically continuous between an example of a via electrode 150 and an example of an electrode conductor portion 130 among examples of the controllable conductive layer 120.

[0030] The word plane is associated with each memory cell. The word planes are shown as word planes 260, 261, 268, and 269. Each word plane corresponds to an example of the electrode conductor portion 130 of FIG. 1B. For example, as shown by word plane 260 being coupled to the memory cells of bit lines 250 and 251, each word plane is associated with a plurality of bit lines. Each of bit lines 250 and 251 corresponds to an example of the via electrode 150 of FIG. 1B.

[0031] Bracket 299 indicates that any number of repetitions of a three-layer stack of (1) a controllable conductive layer 120, (2) an electrode layer formed from an electrode conductor portion 130 combined with a separator portion 140, and (3) a separator layer 110 is possible.

[0032] FIG. 3 shows a 3D view of various aspects of a memory array of a 3D bit cost scalable memory. Bit line (BL) 350 is an exemplary implementation of via electrode 150 of FIG. 1B and is also, for example, an example of bit line 250 of FIG. 2. Bit line selector (BLS) connection 370 is one implementation of a plurality of connections for bit line (BL) 350. OTS layer 320 is an exemplary implementation of a plurality of controllable conductive layers 120 of FIG. 1B. Source line selector (SLS) 392 is an example of a source line selector coupled to, for example, To source line selector (SLS) 290 of FIG. 2. Source line (SL) 391 is coupled to source line selector (SLS) 392. OTS and SL connection 321 is an example of a plurality of connections to other elements (e.g., a driver not shown). Contact 398 is an example of a contact between source line (SL) 391 and other elements (e.g., a source ground not shown). Exemplary Fabrication of 3D Bit Cost Scalable Memory

[0033] FIGS. 4 through 8 show a time - series snapshot of an example of the fabrication of a 3D bit cost scalable memory. This time - series progresses monotonically in time, starting at FIG. 4 and ending at FIG. 8. Each of the snapshots is a cross - sectional view.

[0034] FIG. 4 shows the first of the time - series snapshots. A fabrication processing apparatus performs thin - film deposition of three alternating planar material layers. Two of these layers are an active layer pair. One of these layers is a separator layer. The first layer of the active layer pair is represented by controllable conductive layer 420. The second layer of the active layer pair is represented by electrode conductor layer 430. The separator layer is represented by separator layer 410. The separator layer separates each active layer pair from the other pairs of active layer pairs.

[0035] Thin film deposition begins with the fabrication processing equipment depositing a first layer (e.g., a base layer) as the separator layer 410 on the top portion of the substrate (e.g., the top portion of a silicon-based wafer). Subsequently, in thin film deposition, the fabrication processing equipment deposits a second layer as the controllable conductive layer 420. Thus, the controllable conductive layer 420 is adjacent to and coplanar with the separator layer 410. Subsequently, in thin film deposition, the fabrication processing equipment deposits a third layer as the electrode conductor layer 430. Thus, the electrode conductor layer 430 is adjacent to and coplanar with the controllable conductive layer 420.

[0036] Subsequently, in thin film deposition, the fabrication processing equipment deposits additional examples of the separator layer 410, the controllable conductive layer 420, and the electrode conductor layer 430 until a predetermined number of layers are deposited. In various exemplary 3D bit cost scalable memories, there are examples of various numbers of layers, such as 300 layers (e.g., 100 active layer pairs and 100 separator layers) or 3000 layers.

[0037] After thin film deposition, the fabrication processing equipment performs further processing on the material layer to form a plurality of 3D bit cost scalable memory cells (as shown in FIGS. 4 to 8).

[0038] In some exemplary fabrications of 3D bit cost scalable memories, the first example of the separator layer 410 is omitted and the first example of the controllable conductive layer 420 is deposited directly on the substrate. As shown, the last layer deposited is an example of the separator layer 410. Alternatively, the last layer deposited can be an example of the controllable conductive layer 420 or an example of the electrode conductor layer 430, and there are various possibilities.

[0039] In various fabrication examples, the materials used and / or their thicknesses can vary, such as being the same for (a) all examples of the separator layer 410, (b) all except the first example of the separator layer 410, (c) all except the last example of the separator layer 410, or (d) all except the first and last examples of the separator layer 410.

[0040] See the thin film deposition 904 of FIG. 9 and the related explanatory paragraphs for additional explanation regarding FIG. 4.

[0041] FIG. 5 shows the second of the time series snapshots. The fabrication processing equipment executes etching to form a plurality of parallel holes orthogonal to the planar material layer. These holes extend through the layer. Each hole establishes respective inner sidewalls extending through the layer. These holes are represented by respective examples of holes 550 (for via electrodes 850). By etching an example of the hole 550, the examples of the separator layer 410, the controllable conductive layer 420, and the electrode conductor layer 430 shown in FIG. 4 are respectively transformed into the examples of the completed separator layer 510, the completed controllable conductive layer 520, and the electrode conductor layer 530 shown in FIG. 5. In some variations, the holes extend through all layers except the first example of the separator layer 410. In some variations, the holes extend through all layers including the first example of the separator layer 410.

[0042] See the hole opening etching 905 of FIG. 9 and the related explanatory paragraphs for additional explanation regarding FIG. 5.

[0043] FIG. 6 shows the third of the time series snapshots. The fabrication processing equipment executes etching to form an undercut within the example of the electrode conductor layer 530 to form an example of the completed electrode conductor portion 630 and an example of the corresponding electrode separator undercut 640. Within each example of the electrode conductor layer 530, there is an example of the electrode separator undercut 640 for each example of the hole 550. At this fabrication stage, the examples of the hole 550 and the electrode separator undercut 640 are conceptual. They are conceptual in that for each example of the hole 550, the example of the electrode separator undercut 640 adjacent thereto forms a single 3D void jointly with each example of the hole 550. In the drawing, the adjacency of the examples of the hole 550 and the electrode separator undercut 640 is indicated by a dashed line.

[0044] As one specific example, in the context of the circular hole 550, each example of the electrode separator undercut 640 is a ring-shaped volume of material that is further removed from the electrode conductor layer 530 so as to form the completed electrode conductor portion 630.

[0045] Examples of the hole 550, the completed separator layer 510, and the completed controllable conductive layer 520 are not affected by the undercut etching.

[0046] See the undercut etching 906 of FIG. 9 and the related explanatory paragraphs for additional explanation regarding FIG. 6.

[0047] FIG. 7 shows the fourth of the time-series snapshots. The fabrication processing equipment performs the deposition of separator material into the examples of the electrode separator undercut 640 and the hole 550, and then etches back the separator material to form an example of the completed separator portion 740. Thus, after the deposition of the separator material, each internal sidewall (e.g., those illustrated and described with respect to FIG. 5) established by the hole opening etching is effectively restored.

[0048] Examples of the completed electrode conductor portion 630, the hole 550, the completed separator layer 510, and the completed controllable conductive layer 520 are not affected by the deposition of the separator material.

[0049] See the deposition and etch-back 907 of FIG. 9 and the related explanatory paragraphs for additional explanation regarding FIG. 7.

[0050] FIG. 8 shows the fifth of the time-series snapshots. The fabrication processing equipment performs the deposition of via electrode material (e.g., via metal deposition) to (entirely) fill the example of the hole 550, and then performs CMP to form an example of the via electrode 850.

[0051] Examples of the completed separator layer 510, the completed controllable conductive layer 520, the completed electrode conductor portion 630, and the completed separator portion 740 are not affected by the deposition of the via electrode material.

[0052] Thus, FIG. 8 shows the completed portions of the 3D bit cost scalable memory. FIGS. 4 through 8 represent an example of the fabrication of the 3D bit cost scalable memory shown in FIGS. 1A through 1C. The examples of the completed separator layer 510, the completed controllable conductive layer 520, the completed electrode conductor portion 630, the completed separator portion 740, and the via electrode 850 in FIG. 8 respectively correspond to the examples of the separator layer 110, the controllable conductive layer 120, the electrode conductor portion 130, the separator portion 140, and the via electrode 150 in FIGS. 1A through 1C.

[0053] See the via deposition and CMP execution 908 in FIG. 9 and the related explanatory paragraphs for additional explanation regarding FIG. 8. Exemplary Fabrication Flow of 3D Bit Cost Scalable Memory

[0054] Devices comprising 3D bit cost scalable memory are fabricated from a wafer, such as a semiconductor (e.g., silicon) wafer. The wafer has a top surface that is suitable for fabrication by processing across the entire top surface of the wafer. This fabrication is executable within semiconductor manufacturing equipment. By this process, one or more regions of 3D bit cost scalable memory elements are formed, and optionally other regions are formed. These other regions optionally comprise circuitry for using the 3D bit cost scalable memory element as a memory device, which includes one or more processors, interfaces, and / or circuitry enabled for interoperability with the memory, etc. These other regions optionally comprise circuitry for using the 3D bit cost scalable memory device within a system and / or elements of the system itself.

[0055] FIG. 9 shows a flow diagram for a technique for fabricating one or more regions of a 3D bit cost scalable memory element such as those shown in any of the previous drawings.

[0056] The operations include depositing and etching materials for forming a 3D bit cost scalable memory. The etching is guided using one or more masks such as a photomask. The etching optionally has an intermediate action of depositing a layer of photosensitive material, which is selectively removed (or maintained) based on selectively exposing the photosensitive material to electromagnetic irradiation (e.g., ultraviolet light) through a photomask. Various photomasks are used for the various actions shown in the drawings. For clarity, in the following description of the drawings, specific references to photomasks are omitted.

[0057] The fabrication processing equipment first deposits three plural planar thin film layers that alternate, such as the example of the separator layer 410, the controllable conductive layer 420, and the electrode conductor layer 430 of FIG. 4 (thin film deposition 904). An active layer pair is formed, followed by a separation layer that separates the next active layer pair to be formed, and this continues in the same way until the desired number of layers are formed, with the thin film layers alternating.

[0058] The first deposit (e.g., the first example of the separator layer 410) covers at least substantially the entire area of the top surface of the wafer that will be the vertically 3D bit cost scalable memory element. The second deposit (e.g., the controllable conductive layer 420 adjacent to the separator layer 410) covers at least substantially the entire top surface of the first deposit. The third deposit (e.g., the electrode conductor layer 430 adjacent to the controllable conductive layer 420) covers at least substantially the entire top surface of the second deposit, and this is repeated as follows. The separation layer (corresponding to the first deposit, the fourth deposit, etc.) serves to separate (e.g., electrically and / or thermally) the active layer pairs from other pairs among the active layer pairs. The separation layer (e.g., the separator layer 410) optionally contains the same material (such as silicon nitride or silicon oxide, e.g., a specific dielectric) for example. The active layer pairs (corresponding to the second and third deposits, the fifth and sixth deposits, etc.) serve to form a part of the active circuit of the 3D bit cost scalable memory element. The first of the active layer pairs (e.g., the controllable conductive layer 420) comprises a controllable conductive material such as a specific OTS material. The second of the active layer pairs (e.g., the electrode conductor layer 430) comprises a conductive material such as a material having carbon (C). The deposition continues until the target number of layers are deposited, for example, a total of 3*8, 3*32, 3*64, 3*1024 layers (corresponding to 8, 32, 64, and 1024 active layer pairs) are formed.

[0059] Thin film deposition can be performed using CVD.

[0060] The fabrication processing equipment then forms holes for the next material deposition to form (deep) via electrodes such as the example of the hole 550 in FIG. 5 (hole opening etching 905). These holes are for the deposition of the material for the central electrode next. The hole formation can be performed by etching, for example, using RIE technology. In some variations, an etching stop layer is used to determine the depth of the hole etching, for example, to prevent the etching from becoming too deep.

[0061] Next, the fabrication processing apparatus forms a conductor portion (such as that shown by the completed electrode conductor portion 630 in FIG. 6) (which is of the electrode conductor layer). This formation is by etching an undercut (such as that shown by the electrode separator undercut 640 in FIG. 6) in each of the electrode conductor layers (undercut etching 906).

[0062] Undercut etching can be performed using wet or dry etching techniques. One exemplary etching technique is O2 plasma etching. Another exemplary etching technique is N2 plasma etching. The extension of the undercut can be controlled by controlling the etching time.

[0063] Next, the fabrication processing apparatus forms a separator portion (such as that shown by the completed separator portion 740 in FIG. 7) (which is of the electrode conductor layer). This formation is by material deposition and subsequent etching (deposition and etch-back 907). In material deposition, the undercuts as well as the holes are filled with separator material. Then, by etching, the separator material is removed (e.g., reduced), and the holes at the time of initial formation (such as those in the hole opening etching 905) are reformed (e.g., as shown by the completed separator portion 740 in FIG. 7).

[0064] Material deposition can be performed by ALD technology. In some variations, the etching can be performed by RIE technology.

[0065] Next, the fabrication processing apparatus forms a (deep) via electrode. This formation is by material deposition and subsequent polishing (via deposition and CMP execution 908). In material deposition, the holes initially formed in the hole opening etching 905 and then reformed in the deposition and etch-back 907 are filled with via electrode material. The material is removed by polishing, for example, such that the uppermost separator layer is exposed.

[0066] Material deposition can be performed by CVD technology. Polishing can be performed by CMP technology.

[0067] Thus, the process for fabricating a 3D bit-cost scalable memory element is completed.

[0068] In some fabrication flows, additional processing is performed before, after, and / or completely or partially simultaneously with any one or more of the actions shown in FIG. 9. For example, the additional processing is for circuitry related to using the 3D bit-cost scalable memory element as a memory device, using that memory device within a system, and / or forming one or more components of that system. Materials for 3D bit-cost scalable memory

[0069] Suitable materials for (deep) via electrodes include one or more conductive materials such as tungsten (W) and titanium nitride (TiN), either alone, optionally in combination with each other, or in a form that serves as a basis for materials made in combination with one or more other materials.

[0070] Suitable materials for the conductor portion of the electrode layer include one or more conductive materials such as carbon (C), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), cobalt (Co), and ruthenium (Ru), either alone, optionally in combination with each other, or in a form that serves as a basis for materials made in combination with one or more other materials. Some conductor portions include carbon (C) combined with a metallic material such as tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), and ruthenium (Ru).

[0071] Suitable materials for the controllable conductive material include arsenic (As), selenium (Se), silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), and indium (In), either alone, in any combination with each other, or in a form that serves as the basis for a material made in combination with one or more other materials. For various examples, one or more of the OTS elements are made from chalcogenides including (i) As, Se, and Ge (e.g., AsSeGe), (ii) AsSeGe and Si (e.g., AsSeGeSi), (iii) AsSeGeSi and In (e.g., AsSeGeSiIn), and (iv) AsSeGeIn.

[0072] Suitable materials for the separator portion of the separation layer and / or the electrode layer include one or more dielectric materials such as silicon nitride or silicon oxide. 3D Bit-Cost Scalable Memory Devices and Systems

[0073] Some devices (e.g., integrated circuits, one or more system-on-chip dies, and / or packaged dies) include one or more arrays of 3D bit-cost scalable memory cells (as described elsewhere herein) having additional circuitry for implementing memory devices that can be used as stand-alone devices and / or as components within a system. This additional circuitry provides interface and control functions to enable the 3D bit-cost scalable memory cell array to be implemented in variously organized forms as one or more planes, each plane comprising one or more blocks, and each block having one or more pages.

[0074] The additional circuitry variously includes hardware circuits such as bit line circuits, sense amplifiers, page caches / buffers, interface circuits, word line decoders / drivers, controllers, and / or bias circuits (such as voltage and / or current sources).

[0075] In some variations, additional circuitry enables the use of an array of 3D bit-cost scalable memory cells as DRAM and / or SCM for alternative and / or additional elements within the system, such as those packaged within a DIMM or SODIMM. In some variations, additional circuitry enables coupling an array of 3D bit-cost scalable memory cells to a CPU and / or GPU via a high-performance communication technology such as CXL. In some variations, additional circuitry enables the use of an array of 3D bit-cost scalable memory cells within one or more portions of the memory and / or storage hierarchy, such as within a component corresponding to an SSD and / or DRAM.

[0076] In some variations, additional circuitry enables the use of an array of 3D bit-cost scalable memory cells as various non-volatile memory elements for alternative and / or additional elements within the system, such as those packaged within and / or operating as an NVDIMM. Additional Information on 3D Bit-Cost Scalable Memory

[0077] Figures 1A through 1C and 2 through 9 disclose various aspects of exemplary 3D bit-cost scalable memory technologies that provide non-volatile information storage using a controlled conductive layer, such as one that includes an OTS material.

[0078] The present invention is disclosed with respect to preferred embodiments and the above examples, which are intended in an illustrative rather than a limiting sense. Modifications and combinations will readily occur to those skilled in the art and are within the spirit of the invention and the scope of the following claims.

Claims

1. A stack of layers, wherein the layers are a first separation layer, a first electrode layer, a first controllable conductive layer between the first separation layer and the first electrode layer and in contact with the first separation layer and the first electrode layer, a second controllable conductive layer, wherein the first controllable conductive layer and the second controllable conductive layer comprise the same material, a second separation layer between the first electrode layer and the second controllable conductive layer and in contact with the first electrode layer and the second controllable conductive layer, and a via electrode extending longitudinally through the stack and comprising the first electrode layer includes a first conductor portion and a first separator portion separating the via electrode from the first conductor portion, the first conductor portion being in contact with the first controllable conductive layer, at least one storage portion of the first controllable conductive layer is electrically continuous between the via electrode and the first conductor portion, a memory device.

2. The memory device according to claim 1, wherein the stack of layers has an inner sidewall defining a hole for accommodating the via electrode.

3. The memory device according to claim 1, wherein the first controllable conductive layer comprises an ovonic threshold switch (OTS) material.

4. The memory device according to claim 1, wherein the first conductor portion comprises carbon (C) combined with a metallic material.

5. The memory device according to claim 1, wherein the first conductor portion comprises a material selected from the group consisting of tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), cobalt (Co), and ruthenium (Ru).

6. The memory device according to claim 1, wherein the via electrode comprises tungsten (W).

7. The memory device according to claim 1, wherein the via electrode comprises titanium nitride (TiN).

8. The memory device according to claim 1, wherein the first separator portion comprises a dielectric material.

9. The via electrode is one of a plurality of via electrodes each extending longitudinally through the stack, and the stack has a plurality of inner sidewalls defining holes for accommodating each of the plurality of via electrodes, The memory device according to any one of claims 1 to 8. [

10. ] Above the second controllable conductive layer, further comprising a second electrode layer in contact with the second controllable conductive layer, the second electrode layer including a second conductor portion and a second separator portion separating the via electrode from the second conductor portion. The memory device according to claim 9. [

11. ] The second separator portion contacts the second controllable conductive layer. The memory device according to claim 10. [

12. ] The first separator portion contacts the first controllable conductive layer. The memory device according to claim 10. [

13. ] The first separator portion and the second separator portion include the same material. The memory device according to claim 12. [

14. ] Each of the first conductor portion and the second conductor portion is operable as a respective word line of a memory array, and each via electrode of the plurality of via electrodes is operable as a respective bit line of the memory array. The memory device according to claim 13. [

15. ] The memory device is suitable for implementing non-volatile storage in a solid state disk (SSD), implementing storage class memory (SCM), and / or implementing memory compliant with Compute Express Link (CXL). The memory device according to claim 14. [

16. ] A method of forming a memory device, comprising: forming a stack of layers, the layers including a first separation layer, an electrode layer, a first controllable conductive layer between the first separation layer and the electrode layer and in contact with the first separation layer and the electrode layer, and a second controllable conductive layer, the first controllable conductive layer and the second controllable conductive layer including the same material, the second controllable conductive layer, and a second separation layer between the electrode layer and the second controllable conductive layer and in contact with the electrode layer and the second controllable conductive layer, and forming a via electrode extending vertically through the stack, wherein the electrode layer includes a conductor portion and a separator portion, the separator portion separates the via electrode from the conductor portion, and at least one storage portion of the first controllable conductive layer is electrically continuous between the via electrode and the conductor portion, and the conductor portion contacts the first controllable conductive layer. Method.

17. The method according to claim 16, wherein the step of forming the via electrode comprises forming a hole that penetrates the stack, and the hole defines the dimensions of the via electrode through the entire layer.

18. The method according to claim 17, wherein an undercut is formed in the electrode layer, the undercut surrounds the hole, and the undercut defines the volume for the separator portion, whereby the electrode layer is formed.

19. The method according to claim 18, wherein the electrode layer is formed by forming the separator portion within the undercut.

20. The first controllable conductive layer comprises an ovonic threshold switch (OTS) material, the conductor portion comprises carbon (C), The method according to any one of claims 16 to 19.

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