Semiconductor device

Abstract

Provided is a semiconductor device comprising: a semiconductor chip having a major surface; a high-potential region formed in a surface layer portion of the major surface; a low-potential region formed in the surface layer portion of the major surface spaced apart from the high-potential region; a drift region of a first conductivity type formed in a region between the high-potential region and the low-potential region in the surface layer portion of the major surface; and a resurf region of the first conductivity type which is partly formed in a surface layer portion of the drift region in such a way that a part of a region forming a current path in the drift region is exposed from the major surface, and which has an impurity concentration exceeding that in the drift region.

Description

Technical Field

[0001] This application corresponds to Japanese Patent Application No. 2020-023747 filed with the Japan Patent Office on February 14, 2020, and the entire disclosure of this application is incorporated herein by reference.

[0002] The present invention relates to a semiconductor device.

Background Art

[0003] Patent Document 1 discloses a semiconductor device including a semiconductor layer, a first electrode, a second electrode, and a lateral element. The first electrode is formed on the surface of the semiconductor layer. The second electrode is formed on the surface of the semiconductor layer with a space from the first electrode. The lateral element is formed in a region between the first electrode and the second electrode in the surface layer portion of the surface of the semiconductor layer and is electrically connected to the first electrode and the second electrode.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment of the present invention provides a semiconductor device capable of reducing on-resistance while suppressing a decrease in breakdown voltage.

Means for Solving the Problems

[0006] One embodiment of the present invention provides a semiconductor device including a semiconductor chip having a main surface, a high-potential region formed in a surface layer portion of the main surface, a low-potential region formed in the surface layer portion of the main surface with a space from the high-potential region, a drift region of a first conductivity type formed in a region between the high-potential region and the low-potential region in the surface layer portion of the main surface, and a RESURF region of the first conductivity type partially formed in a surface layer portion of the drift region so as to expose a part of a region serving as a current path in the drift region from the main surface and having an impurity concentration exceeding that of the drift region. According to this semiconductor device, the on-resistance can be reduced while suppressing a decrease in breakdown voltage.

[0007] One embodiment of the present invention provides a semiconductor device including a semiconductor chip having a main surface, a high-potential region and a low-potential region formed in the surface layer portion of the main surface with a space therebetween, a drift region of a first conductivity type formed in a region between the high-potential region and the low-potential region in the surface layer portion of the main surface, a RESURF region of the first conductivity type formed in a line shape extending in a direction facing the high-potential region and the low-potential region in the surface layer portion of the drift region so as to expose a part of a region serving as a current path in the drift region from the main surface and having an impurity concentration exceeding that of the drift region, a field insulating film covering the drift region and the RESURF region, and a field electrode formed on the field insulating film and routed in a line shape so as to intersect the RESURF region in a plan view. According to this semiconductor device, the on-resistance can be reduced while suppressing a decrease in breakdown voltage.

[0008] The above-described or further other objects, features, and effects of the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] FIG. 1 is a plan view showing a semiconductor chip 2 of a semiconductor device 1 according to a first embodiment of the present invention. FIG. 2 is an enlarged view of a region II shown in FIG. 1. FIG. 3 is an enlarged view of a region III shown in FIG. 2. FIG. 4 is a partially cutaway perspective cross-sectional view of a region III shown in FIG. 2. FIG. 5 is a cross-sectional view taken along line V-V shown in FIG. 3. FIG. 6 is an enlarged view of a main part showing a RESURF region 20.

[0011] Referring to FIGS. 1 to 6, the semiconductor device 1 includes a silicon semiconductor chip 2 formed in a rectangular parallelepiped shape. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a square shape in a plan view (hereinafter simply referred to as "plan view") as viewed from their normal direction Z.

[0012] The first to fourth side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The first side surface 5A and the second side surface 5B extend in a first direction X and face each other in a second direction Y orthogonal to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face each other in the first direction X. In this embodiment, the semiconductor chip 2 has a stacked structure including a p-type semiconductor substrate 6 and an n-type epitaxial layer 7 formed on the semiconductor substrate 6.

[0013] The semiconductor substrate 6 forms a part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. The semiconductor substrate 6 may have a p-type impurity concentration of 1.0×10 13 cm -3 or more and 1.0×10 15 cm -3 or less. The thickness of the semiconductor substrate 6 may be 100 μm or more and 500 μm or less. The epitaxial layer 7 forms a part of the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0014] The epitaxial layer 7 may have an n-type impurity concentration exceeding the p-type impurity concentration of the semiconductor substrate 6. The n-type impurity concentration of the epitaxial layer 7 may be 1.0×10 14 cm -3 or more and 1.0×10 16 cm -3 or less. The n-type impurity concentration of the epitaxial layer 7 is preferably 1.0×10 15 cm -3 or more and 5.0×10 15 cm -3 or less. The thickness of the epitaxial layer 7 may be 5 μm or more and 20 μm or less.

[0015] The semiconductor device 1 includes a plurality of device regions 8 partitioned on the first main surface 3. The number and arrangement of the plurality of device regions 8 are arbitrary. Each of the plurality of device regions 8 includes a functional device formed using the first main surface 3 and / or the surface layer portion of the first main surface 3. The functional device may include at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may include a circuit network in which at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device are combined.

[0016] The semiconductor switching device may include at least one of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor). The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, and an inductor.

[0017] The plurality of device regions 8 includes an LDMIS region 9 in which an LDMISFET (Lateral Double diffused MISFET), which is an example of a MISFET, is formed (see region II in FIG. 1). Hereinafter, the structure of the LDMIS region 9 will be specifically described.

[0018] Referring to FIGS. 2 to 5, the semiconductor device 1 includes an n-type impurity region 10 formed in the surface layer portion of the first main surface 3 in the LDMIS region 9. In this form, the impurity region 10 is formed using a part of the epitaxial layer 7. Therefore, the impurity region 10 has an n-type impurity concentration equal to the n-type impurity concentration of the epitaxial layer 7. In this form, the impurity region 10 is formed in an oval shape in plan view. The impurity region 10 may be formed in a circular shape, an elliptical shape, or a polygonal shape (for example, a square shape).

[0019] The semiconductor device 1 includes a high potential region 11, a low potential region 12, and a drift region 13 formed in the surface layer portion of the first main surface 3 in the LDMIS region 9. The high potential region 11 is formed at the center of the impurity region 10. The low potential region 12 is formed in the surface layer portion of the first main surface 3 at an interval from the high potential region 11 and is connected to the impurity region 10. The drift region 13 is formed in the impurity region 10 in the region between the high potential region 11 and the low potential region 12.

[0020] Specifically, the high potential region 11 includes an n-type well region 14 formed in the surface layer portion of the impurity region 10. The well region 14 has an n-type impurity concentration exceeding the n-type impurity concentration of the impurity region 10. The n-type impurity concentration of the well region 14 may be 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less. In this form, the well region 14 is formed in an oval shape extending along the impurity region 10 in plan view. The well region 14 may be formed in a circular shape, an elliptical shape, or a polygonal shape (for example, a square shape).

[0021] The high potential region 11 includes an n-type drain region 15 formed in the surface layer portion of the well region 14. The drain region 15 has an n-type impurity concentration exceeding the n-type impurity concentration of the well region 14. The n-type impurity concentration of the drain region 15 is 1.0×10 18 cm -3 or more and may be 1.0×10 21 cm -3 or less. The drain region 15 is formed in the inner portion of the well region 14 at a distance from the periphery of the well region 14. In this form, the drain region 15 is formed in an oval shape extending along the well region 14 in plan view. The drain region 15 may be formed in a circular shape, an elliptical shape, or a polygonal shape (for example, a square shape).

[0022] Specifically, the low potential region 12 includes a p-type body region 16 formed in the surface layer portion of the first main surface 3 adjacent to the impurity region 10. The body region 16 may have a p-type impurity concentration of 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less. The body region 16 has a bottom connected to the semiconductor substrate 6 and fixes the semiconductor substrate 6 to the same potential. The body region 16 is formed in a strip shape extending along the impurity region 10. Specifically, the body region 16 is formed in an annular shape (an oval annular shape in this form) surrounding the impurity region 10 and partitions the impurity region 10 into a predetermined shape (an oval shape in this form).

[0023] The body region 16 includes a first straight portion 16A, a second straight portion 16B, a first curved portion 16C, and a second curved portion 16D in plan view. The first straight portion 16A is formed in a region on one side of the impurity region 10 with respect to the second direction Y and extends in the first direction X. The second straight portion 16B is formed in a region on the other side of the impurity region 10 so as to face the first straight portion 16A across the impurity region 10 with respect to the second direction Y and extends parallel to the first straight portion 16A. With respect to the first direction X, the lengths of the first straight portion 16A and the second straight portion 16B are preferably equal to or less than the length of the drain region 15.

[0024] The first curved portion 16C is formed in a strip shape that extends in an arc between one end of the first straight portion 16A and one end of the second straight portion 16B. The second curved portion 16D faces the first curved portion 16C with the impurity region 10 interposed therebetween, and is formed in a strip shape that extends in an arc between the other end of the first straight portion 16A and the other end of the second straight portion 16B.

[0025] The low potential region 12 includes an n-type source region 17 formed in the surface layer portion of the body region 16 at a distance from the impurity region 10. The source region 17 is formed on the inner edge side (the impurity region 10 side) of the body region 16, and defines a channel region 18 of the LDMISFET with the impurity region 10 (drift region 13). The source region 17 has an n-type impurity concentration exceeding the n-type impurity concentration of the well region 14. The n-type impurity concentration of the source region 17 is 1.0×10 18 cm -3 or more and may be 1.0×10 21 cm -3 or less. The n-type impurity concentration of the source region 17 is preferably equal to the n-type impurity concentration of the drain region 15.

[0026] In this form, the source region 17 is formed in an end-bounded strip shape in a partial region of the body region 16 in plan view. Specifically, the source region 17 is formed on the first straight portion 16A and the second straight portion 16B at intervals from the first curved portion 16C and the second curved portion 16D. That is, the source region 17 is not formed on the first curved portion 16C and the second curved portion 16D of the body region 16. The source region 17 is formed in an end-bounded strip shape that extends along the first straight portion 16A and the second straight portion 16B in plan view.

[0027] The source region 17 faces the drain region 15 in the second direction Y and forms a current path extending in the second direction Y between the source region 17 and the drain region 15 in the drift region 13. In the first direction X, the length of the source region 17 is preferably equal to or less than the length of the drain region 15. Of course, the source region 17 may be formed in an annular shape (specifically, an oval annular shape) surrounding the impurity region 10. That is, the source region 17 may also be formed in the first curved portion 16C and the second curved portion 16D of the body region 16.

[0028] The low potential region 12 includes a p-type contact region 19 formed in a region different from the source region 17 in the surface layer portion of the body region 16. The contact region 19 is formed on the outer edge side of the body region 16 (the side opposite to the impurity region 10) and faces the channel region 18 with the source region 17 interposed therebetween. The contact region 19 has a p-type impurity concentration exceeding the p-type impurity concentration of the body region 16. The p-type impurity concentration of the contact region 19 is 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0029] In this form, the contact region 19 is formed in an end-banded shape in a partial region of the body region 16 in plan view. Specifically, the contact region 19 is formed in the first straight portion 16A and the second straight portion 16B at intervals from the first curved portion 16C and the second curved portion 16D of the body region 16, respectively. That is, the contact region 19 is not formed in the first curved portion 16C and the second curved portion 16D of the body region 16. The contact region 19 is formed in an end-banded shape extending along the first straight portion 16A and the second straight portion 16B in plan view.

[0030] The contact region 19 faces the drain region 15 in the second direction Y. In the first direction X, the length of the contact region 19 is preferably equal to or less than the length of the drain region 15. Of course, the contact region 19 may be formed in an annular shape (specifically, an oval annular shape) surrounding the impurity region 10. That is, the contact region 19 may also be formed on the first curved portion 16C and the second curved portion 16D of the body region 16.

[0031] The drift region 13 is part of the impurity region 10. The drift region 13 forms a current path connecting the high potential region 11 and the low potential region 12. Specifically, the drift region 13 is defined in the impurity region 10 in the region between the drain region 15 (well region 14) and the source region 17 (body region 16). Thereby, the drift region 13 forms a current path connecting the drain region 15 and the source region 17.

[0032] The drift region 13 is formed in an annular shape (in this form, an oval annular shape) surrounding the drain region 15. In this form, the drift region 13 has a straight portion partitioned by the first straight portion 16A (second straight portion 16B) of the body region 16, and a curved portion partitioned by the first curved portion 16C (second curved portion 16D) of the body region 16. The distance of the drift region 13 may be 50 μm or more and 200 μm or less. The distance of the drift region 13 is preferably formed at a constant distance along the annular shape (in this form, an oval annular shape).

[0033] Referring to FIGS. 4 to 6, the semiconductor device 1 includes an n-type RESURF region 20 formed partially in the surface layer portion of the drift region 13 so as to expose a part of the drift region 13 from the first main surface 3. The RESURF region 20 has an n-type impurity concentration higher than that of the drift region 13. The n-type impurity concentration of the RESURF region 20 is 1.0×10 15 cm -3 or more and 5.0×10 16 cm -3 or less.

[0034] The RESURF region 20 preferably has an upper limit value of 20 times the n-type impurity concentration of the drift region 13. The n-type impurity concentration of the RESURF region 20 is greater than 2.25×10 15 cm -3 and preferably not exceeding 3.25×10 16 cm -3 . The n-type impurity concentration of the RESURF region 20 is preferably 1.25×10 15 cm -3 or more and particularly preferably 2.5×10 16 cm -3 or less. The n-type impurity concentration of the RESURF region 20 is preferably less than the n-type impurity concentration of the well region 14.

[0035] In this form, a plurality of RESURF regions 20 are formed at intervals in the surface layer portion of the drift region 13. The plurality of RESURF regions 20 are formed at intervals from the bottom of the drift region 13 toward the first main surface 3 side. Specifically, the plurality of RESURF regions 20 are formed shallower than the well region 14 and deeper than the drain region 15. The plurality of RESURF regions 20 face the semiconductor substrate 6 with a part of the drift region 13 interposed therebetween.

[0036] The plurality of RESURF regions 20 extend linearly in the facing direction of the high potential region 11 and the low potential region 12 in plan view, and are formed in a stripe shape with intervals in the direction orthogonal to the facing direction. As a result, in plan view, a part of the drift region 13 is exposed from the first main surface 3 in a stripe shape by the plurality of RESURF regions 20.

[0037] The plurality of RESURF regions 20 are formed in a region between the drain region 15 and the body region 16 in the surface layer portion of the drift region 13. Specifically, the RESURF region 20 is formed in a region between the well region 14 and the body region 16. In this form, the RESURF region 20 has one end connected to the well region 14 and the other end connected to the body region 16. Thereby, the RESURF region 20 forms a current path that continuously extends in the region between the well region 14 and the body region 16.

[0038] The plurality of RESURF regions 20 are formed in the straight portion of the drift region 13 at an interval from the curved portion of the drift region 13. That is, the plurality of RESURF regions 20 are not formed in the region between the first curved portion 16C (second curved portion 16D) of the drain region 15 and the body region 16. The plurality of RESURF regions 20 are formed in the region between the first straight portion 16A (second straight portion 16B) of the drain region 15 and the body region 16.

[0039] The RESURF region 20 is preferably partially formed in the surface layer portion of the drift region 13 so as to expose a part of the region that becomes the current path in the drift region 13 from the first main surface 3. That is, the plurality of RESURF regions 20 are preferably formed only in the region sandwiched between the drain region 15 and the source region 17 in the surface layer portion of the drift region 13. Thereby, the RESURF region 20 forms a current path that continuously extends through the region between the drain region 15 and the source region 17. When the source region 17 (contact region 19) is formed in an annular shape surrounding the impurity region 10, the plurality of RESURF regions 20 may be formed in the curved portion of the drift region 13.

[0040] The semiconductor device 1 includes a plurality of drift line regions 13A (drift exposed regions) partitioned in the regions between the plurality of RESURF regions 20 adjacent to each other in the surface layer portion of the drift region 13. The plurality of drift line regions 13A are part of the drift region 13. The plurality of drift line regions 13A extend linearly in the facing direction of the high potential region 11 and the low potential region 12 in a plan view, and are alternately formed with the plurality of RESURF regions 20 in the direction orthogonal to the facing direction.

[0041] The n-type impurity concentration in the drift line region 13A is less than the n-type impurity concentration in the RESURF region 20. Therefore, the current density flowing through the drift line region 13A is less than the current density flowing through the RESURF region 20. On the other hand, the depletion layer expanding from the drift line region 13A is larger than the depletion layer expanding from the RESURF region 20. Therefore, in the LDMIS region 9, the reduction of the breakdown voltage is suppressed by the drift line region 13A, and the on-resistance Ron is reduced by the RESURF region 20.

[0042] Referring to FIG. 6, the plurality of RESURF regions 20 each have a first width W1. The first width W1 is the width in a direction orthogonal to the direction in which the RESURF region 20 extends. The plurality of drift line regions 13A each have a second width W2. The second width W2 is the width in a direction orthogonal to the direction in which the drift line region 13A extends.

[0043] The ratio W1 / W2 of the first width W1 of the RESURF region 20 to the second width W2 of the drift line region 13A may be 0.5 or more and 2.0 or less (0.5 ≤ W1 / W2 ≤ 2.0). The ratio W1 / W2 is preferably 1.0 or less (0.5 ≤ W1 / W2 ≤ 1.0). The ratio W1 / W2 is more preferably less than 1.0 (0.5 ≤ W1 / W2 < 1.0). That is, it is preferable that the RESURF region 20 having a width narrower than the drift line region 13A is formed.

[0044] The first width W1 may be 1 μm or more and 5 μm or less. The second width W2 may be 1 μm or more and 5 μm or less. The first width W1 and the second width W2 are each preferably 3 μm or less. The total value W1 + W2 of the first width W1 and the second width W2 is preferably 3 μm or more and 6 μm or less.

[0045] A plurality of resurf regions 20 are formed in the facing region between the drain region 15 and the source region 17 at a first exclusive ratio R1. The first exclusive ratio R1 is the ratio of the plurality of resurf regions 20 occupying the facing region when the facing region is regarded as "1". A plurality of drift line regions 13A are formed in the facing region at a second exclusive ratio R2. The second exclusive ratio R2 is the ratio of the plurality of drift line regions 13A occupying the facing region when the facing region is regarded as "1".

[0046] The second exclusive ratio R2 may be 0.5 times or more and 2.0 times or less of the first exclusive ratio R1 (0.5×R1≦R2≦2×R1). It is preferable that the second exclusive ratio R2 is R1 or more (R1≦R2≦2×R1). It is more preferable that the second exclusive ratio R2 exceeds the first exclusive ratio R1 (R1<R2≦2×R1).

[0047] The semiconductor device 1 includes a field insulating film 21 formed on the first main surface 3 so as to cover the drift region 13 and the plurality of resurf regions 20 in the LDMIS region 9. The field insulating film 21 contains silicon oxide. In this form, the field insulating film 21 is composed of a LOCOS film formed by selective oxidation of the first main surface 3. The field insulating film 21 may have a thickness of 0.1 μm or more and 2 μm or less.

[0048] Specifically, the field insulating film 21 is formed in an annular shape (an oval ring shape in this form) covering the region between the drain region 15 and the body region 16 in plan view. The field insulating film 21 includes an inner edge portion 22 and an outer edge portion 23. In FIGS. 2 and 3, the outer edge portion 23 of the field insulating film 21 is indicated by a broken line. The inner edge portion 22 of the field insulating film 21 covers the well region 14 and exposes the drain region 15.

[0049] The outer edge 23 of the field insulating film 21 is formed at a distance from the inner edge of the body region 16 toward the high potential region 11, exposing the body region 16, the source region 17, and the contact region 19. The outer edge 23 of the field insulating film 21 exposes a part of the drift region 13 and a part of the RESURF region 20 from between it and the inner edge of the body region 16.

[0050] The semiconductor device 1 includes an outer field insulating film 24 formed on the first main surface 3 so as to cover the region outside the LDMIS region 9. The outer field insulating film 24 has the same thickness as the field insulating film 21 and contains the same material as the field insulating film 21. That is, in this form, the outer field insulating film 24 is made of a LOCOS film. The outer field insulating film 24 covers the outer edge of the body region 16, exposing the body region 16, the source region 17, and the contact region 19.

[0051] Referring to FIGS. 4 and 5, the semiconductor device 1 includes a field electrode 31 routed linearly on the field insulating film 21. The field electrode 31 includes conductive polysilicon in this form. The field electrode 31 consists of a field resistance film electrically connected to the high potential region 11 and the low potential region 12 in this form. Specifically, the field electrode 31 is electrically connected to the drain region 15 and the body region 16 (source region 17 and contact region 19). The field electrode 31 forms a voltage drop from the high potential region 11 toward the low potential region 12, suppressing the bias in the electric field distribution in the drift region 13.

[0052] The field electrode 31 extends in a line shape intersecting a plurality of RESURF regions 20 in a plan view, and crosses the plurality of RESURF regions 20 multiple times. Specifically, the field electrode 31 includes a linearly extending portion and a curvedly extending portion. The field electrode 31 crosses the plurality of RESURF regions 20 multiple times in the linearly extending portion. That is, when one straight line connecting the high potential region 11 and the low potential region 12 is set in a plan view, the field electrode 31 crosses the straight line multiple times. The field electrode 31 faces the drift region 13 with the field insulating film 21 interposed therebetween in the curvedly extending portion.

[0053] Specifically, the field electrode 31 surrounds the high potential region 11 multiple times in a plan view. More specifically, the field electrode 31 is formed in a spiral shape having an inner end portion 32 on the drain region 15 side, an outer end portion 33 on the body region 16 side, and a spiral portion 34 extending between the inner end portion 32 and the outer end portion 33 in a plan view. The arrangement of the inner end portion 32 and the outer end portion 33 is arbitrary.

[0054] In this form, the inner end portion 32 is formed at a position facing the drain region 15 in the second direction Y. The inner end portion 32 may face the well region 14 with the field insulating film 21 interposed therebetween. In this form, the outer end portion 33 is formed at a position facing the source region 17 in the second direction Y. The outer end portion 33 may face the drift line region 13A and the RESURF region 20 with the field insulating film 21 interposed therebetween.

[0055] The spiral portion 34 is wound outward from the inner end portion 32 toward the outer end portion 33 so as to surround the drain region 15 in a plan view, and is formed in an oval spiral shape. The spiral portion 34 faces the drift line region 13A and the RESURF region 20 with the field insulating film 21 interposed therebetween.

[0056] The field electrode 31 has a structure that causes a voltage drop in a spiral direction from the inner end portion 32 toward the outer end portion 33. That is, the field electrode 31 forms a potential gradient that gradually decreases from the high potential region 11 toward the low potential region 12 according to the potential corresponding to the voltage drop in the direction orthogonal to the spiral direction. The deviation of the electric field distribution in the drift region 13 is suppressed by utilizing such electrical properties of the field electrode 31.

[0057] Referring to FIG. 6, the field electrode 31 has a line width W3. The line width W3 is defined by the width in the direction orthogonal to the extending direction (that is, the spiral direction) of the field electrode 31. The line width W3 may be 1 μm or more and 5 μm or less. The line width W3 is preferably 3 μm or less. The line width W3 may be equal to or greater than the first width W1 of the RESURF region 20 (W1 ≦ W3). The line width W3 may be equal to or greater than the second width W2 of the drift line region 13A (W2 ≦ W3).

[0058] The resistance value of the field electrode 31 may be 10 MΩ or more and 100 MΩ or less. The pitch of the field electrode 31 may be 1 μm or more and 10 μm or less. The pitch of the field electrode 31 is preferably 2 μm or more. The pitch of the field electrode 31 is defined by the distance between adjacent portions (that is, the winding pitch of the spiral portion 34). The number of windings of the field electrode 31 may be 5 or more and 20 or less. The line width W3, resistance value, pitch, and number of windings of the field electrode 31 are arbitrary and are adjusted according to the electric field to be relaxed.

[0059] The semiconductor device 1 includes an inner field electrode 36 formed in the region between the field electrode 31 and the high potential region 11 (drain region 15) on the field insulating film 21. In this form, the inner field electrode 36 is formed in the region surrounded by the field electrode 31 and is fixed to the same potential as the high potential region 11 (drain region 15). The inner field electrode 36 has the same thickness as the field electrode 31 and includes the same material as the field electrode 31 (that is, conductive polysilicon).

[0060] The inner field electrode 36 is formed in an annular shape (specifically, an oval annular shape) that surrounds the drain region 15 with a space from the drain region 15 and the field electrode 31. The inner field electrode 36 may face the well region 14 with the field insulating film 21 interposed therebetween. The inner field electrode 36 is preferably formed at a distance from a plurality of resurf regions 20 toward the drain region 15 in a plan view.

[0061] The inner field electrode 36 includes an inner edge portion 37 and an outer edge portion 38. The inner edge portion 37 of the inner field electrode 36 surrounds the drain region 15 with a space from the drain region 15. The inner edge portion 37 of the inner field electrode 36 is preferably formed at a substantially constant distance from the drain region 15.

[0062] The outer edge portion 38 of the inner field electrode 36 is formed with a space from the field electrode 31. The outer edge portion 38 of the inner field electrode 36 is preferably formed at a substantially constant distance from the field electrode 31. The distance between the inner field electrode 36 and the field electrode 31 is preferably equal to the pitch of the field electrode 31.

[0063] In this form, the inner field electrode 36 is formed with a non-uniform width along the circumferential direction. Specifically, the inner field electrode 36 has a field protruding portion 39 at the outer edge portion 38. The field protruding portion 39 is drawn toward the field electrode 31 so as to face the tip of the inner end portion 32 in the spiral direction of the field electrode 31. The field protruding portion 39 maintains the distance between the inner field electrode 36 and the field electrode 31 substantially constant and suppresses the bias of the electric field caused by the inner end portion 32 of the field electrode 31.

[0064] In this embodiment, the inner field electrode 36 is connected to the inner end portion 32 of the field electrode 31 and fixed to the same potential as that of the inner end portion 32. Specifically, the field overhang portion 39 is connected to the inner end portion 32. As long as the inner field electrode 36 and the inner end portion 32 can be fixed to the same potential, the inner field electrode 36 does not necessarily have to be connected to the inner end portion 32. Also, the presence or absence of the inner field electrode 36 is arbitrary and may be removed as needed.

[0065] The line width of the inner field electrode 36 may be 1 μm or more and 15 μm or less. The inner field electrode 36 is preferably formed wider than the field electrode 31. The line width of the inner field electrode 36 is preferably 1.5 times or more and 5 times or less the line width W3 of the field electrode 31. Of course, an inner field electrode 36 having a line width less than or equal to the line width W3 may be formed.

[0066] Referring to FIGS. 4 and 5, the semiconductor device 1 includes a gate insulating film 40 that covers the channel region 18 on the first main surface 3. In this embodiment, the gate insulating film 40 is made of silicon oxide. The gate insulating film 40 is formed in a strip shape extending along the field insulating film 21 in plan view, exposing the body region 16, the source region 17, and the contact region 19.

[0067] In this embodiment, the gate insulating film 40 is formed in an annular shape (specifically, an oval annular shape) surrounding the field insulating film 21 in plan view. The gate insulating film 40 has a thickness less than that of the field insulating film 21 and is connected to the field insulating film 21 (outer edge portion 23). Thereby, the gate insulating film 40 covers the portion exposed between the inner edge of the body region 16 and the outer edge portion 23 of the field insulating film 21 in the drift region 13 (drift line region 13A) and the RESURF region 20. The thickness of the gate insulating film 40 may be 10 nm or more and 200 nm or less.

[0068] The semiconductor device 1 includes a gate electrode 41 formed on the gate insulating film 40. The gate electrode 41 has the same thickness as the field electrode 31 and includes the same material as the field electrode 31 (i.e., conductive polysilicon). The gate electrode 41 faces the channel region 18 with the gate insulating film 40 interposed therebetween. In this form, the gate electrode 41 also faces the drift region 13 (drift line region 13A) and the RESURF region 20 with the gate insulating film 40 interposed therebetween. The gate electrode 41 is formed in a strip shape extending along the field insulating film 21 in plan view. In this form, the gate electrode 41 is formed in an annular shape (specifically, an oval annular shape) surrounding the field insulating film 21 in plan view.

[0069] The gate electrode 41 has a covering portion 42 drawn from above the gate insulating film 40 onto the field insulating film 21. The covering portion 42 is formed in an annular shape (specifically, an oval annular shape) surrounding the field electrode 31 with a space from the field electrode 31. The covering portion 42 faces the drift region 13 and the RESURF region 20 with the field insulating film 21 interposed therebetween.

[0070] The gate electrode 41 includes an inner edge portion 43 and an outer edge portion 44. The inner edge portion 43 of the gate electrode 41 is formed by the covering portion 42 and crosses the drift line region 13A and the RESURF region 20 in plan view. It is preferable that the inner edge portion 43 of the gate electrode 41 is formed at a substantially constant interval from the field electrode 31. The distance between the gate electrode 41 and the field electrode 31 is preferably equal to the pitch of the field electrode 31. The outer edge portion 44 of the gate electrode 41 is formed in a region overlapping the body region 16 in plan view. It is preferable that the outer edge portion 44 of the gate electrode 41 is formed at a substantially constant interval from the outer edge portion 23 of the field insulating film 21.

[0071] In this form, the gate electrode 41 is formed with a non-uniform width along the circumferential direction. In this form, the gate electrode 41 has a gate overhang portion 45 at the inner edge portion 43. The gate overhang portion 45 is drawn toward the field electrode 31 so as to face the tip of the outer end portion 33 in the spiral direction of the field electrode 31. The gate overhang portion 45 keeps the distance between the gate electrode 41 and the field electrode 31 substantially constant and suppresses the electric field bias caused by the outer end portion 33 of the field electrode 31.

[0072] Referring to FIG. 4, the semiconductor device 1 includes an insulating layer 71 laminated on the first main surface 3 and covering the LDMIS region 9. The insulating layer 71 is composed of a multilayer wiring structure 74 having a laminated structure in which a plurality of interlayer insulating layers 72 and a plurality of wiring layers 73 are alternately laminated. The interlayer insulating layer 72 means an insulating layer interposed between two adjacent wiring layers 73 in the vertical direction. However, the lowermost interlayer insulating layer 72 among the plurality of interlayer insulating layers 72 means an insulating layer interposed between the semiconductor chip 2 and the first wiring layer 73.

[0073] FIG. 4 shows a portion where the first to second interlayer insulating layers 72A to 72B and the first to second wiring layers 73A to 73B of the multilayer wiring structure 74 are alternately laminated. The number of laminations of the interlayer insulating layer 72 and the wiring layer 73 is arbitrary and is not limited to a specific value. The multilayer wiring structure 74 may have a laminated structure in which three or more interlayer insulating layers 72 and three or more wiring layers 73 are alternately laminated.

[0074] Each interlayer insulating layer 72 includes at least one of a SiO2 film and a SiN film. Each interlayer insulating layer 72 may have a single-layer structure composed of a SiO2 film or a SiN film. Each interlayer insulating layer 72 may have a laminated structure in which one or more SiO2 films and / or one or more SiN films are laminated in an arbitrary order. Each wiring layer 73 may include at least one of an Al film, a Cu film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film.

[0075] On the first interlayer insulating layer 72A, a plurality of first wiring layers 73A are formed. The plurality of first wiring layers 73A are electrically connected to corresponding connection targets through one or more first via electrodes 75 penetrating the first interlayer insulating layer 72A, respectively. The first via electrode 75 may be a tungsten plug electrode. Specifically, the plurality of first wiring layers 73A include a first drain wiring 76, a first source wiring 77, a first gate wiring 78, an inner field wiring 79, and an outer field wiring 80.

[0076] The first drain wiring 76 is electrically connected to the drain region 15 through one or more first via electrodes 75. The first source wiring 77 is electrically connected to the source region 17 (body region 16 and contact region 19) through one or more first via electrodes 75. The first gate wiring 78 is electrically connected to the gate electrode 41 through one or more first via electrodes 75.

[0077] The inner field wiring 79 is electrically connected to the inner end portion 32 of the field electrode 31 through one or more first via electrodes 75. The inner field wiring 79 may be electrically connected to the inner field electrode 36 through one or more first via electrodes 75. The inner field wiring 79 may be integrally formed with the first drain wiring 76. The outer field wiring 80 is electrically connected to the outer end portion 33 of the field electrode 31 through one or more first via electrodes 75. The outer field wiring 80 may be integrally formed with the first source wiring 77.

[0078] On the second interlayer insulating layer 72B, a plurality of second wiring layers 73B are formed. The plurality of second wiring layers 73B are electrically connected to corresponding connection targets through one or more second via electrodes 81 penetrating the second interlayer insulating layer 72B, respectively. The second via electrode 81 may be a tungsten plug electrode. Specifically, the plurality of second wiring layers 73B include a second drain wiring 82, a second source wiring 83, and a second gate wiring (not shown).

[0079] The second drain wiring 82 is electrically connected to the first drain wiring 76 and the inner field wiring 79 via a plurality of second via electrodes 81. The second drain wiring 82 covers the drain region 15 and the inner field wiring 79 in a plan view. Preferably, the second drain wiring 82 covers the entire area of the drain region 15 and the entire area of the inner field wiring 79 in a plan view. Preferably, the second drain wiring 82 is drawn out to a position facing the inner field electrode 36 in a plan view. Preferably, the second drain wiring 82 is further drawn out to a position facing a portion forming the innermost peripheral portion of the field electrode 31 in a plan view.

[0080] The second source wiring 83 is electrically connected to the first source wiring 77 and the outer field wiring 80 via a plurality of second via electrodes 81. The second source wiring 83 is formed in an annular shape extending along the body region 16 in a plan view. Preferably, the second source wiring 83 covers the gate electrode 41 and the outer field wiring 80 in a plan view.

[0081] Preferably, the second drain wiring 82 covers the entire area of the body region 16, the entire area of the gate electrode 41, and the entire area of the outer field wiring 80 in a plan view. Preferably, the second source wiring 83 is further drawn out to a position facing a portion forming the outermost peripheral portion of the field electrode 31 in a plan view.

[0082] Hereinafter, with reference to FIGS. 7 to 9, the electrical characteristics of the semiconductor device 1 will be described. Here, as the electrical characteristics of the semiconductor device 1, the on-resistance Ron, the breakdown voltage VB, and the gate threshold voltage Vth were examined. The breakdown voltage VB is the withstand voltage of the semiconductor device 1. When examining the electrical characteristics of the semiconductor device 1, a first device, a second device, a third device, and a fourth device were prepared.

[0083] The first device is a semiconductor device 1 having a structure in which the ratio W1 / W2 of the first width W1 of the resurf region 20 to the second width W2 of the drift line region 13A is set to "0.5". The second device is a semiconductor device 1 having a structure in which the ratio W1 / W2 is set to "1.0". The third device is a semiconductor device 1 having a structure in which the ratio W1 / W2 is set to "2.0". Here, the first width W1 and the second width W2 are each adjusted in the range of 1 μm or more and 3 μm or less. Also, the sum W1+W2 of the first width W1 and the second width W2 is each adjusted in the range of 3 μm or more and 6 μm or less.

[0084] The fourth device is a semiconductor device according to a comparative example. In the semiconductor device according to the comparative example, the resurf region 20 is formed in the entire region that serves as a current path in the drift region 13, and the drift line region 13A is not formed. That is, in the semiconductor device according to the comparative example, the resurf region 20 is formed in the entire opposing region between the drain region 15 and the source region 17 in the surface layer portion of the drift region 13.

[0085] In addition, the n-type impurity concentration of the RESURF region 20 in each of the first to fourth devices is 1.25×10 16 cm -3 , 2.5×10 16 cm -3 , and 3.25×10 16 cm -3 The n-type impurity concentration of the drift region 13 (drift line region 13A) was adjusted to 2.25×10 15 cm -3 It was.

[0086] FIG. 7 is a graph showing actual measurements to explain the on-resistance Ron. The vertical axis shows the on-resistance Ron [Ω]. The horizontal axis shows the n-type impurity concentration (=2.25×10 15 cm -3 ) as the reference n-type impurity concentration [cm -3 ] is shown.

[0087] In FIG. 7, first to fourth broken lines LA1 to LA4 are shown. The first broken line LA1 is composed of four square plot points and shows the characteristics of the on-resistance Ron of the first device (W1 / W2 = 0.5). The second broken line LA2 is composed of four triangular plot points and shows the characteristics of the on-resistance Ron of the second device (W1 / W2 = 1.0). The third broken line LA3 is composed of four circular plot points and shows the characteristics of the on-resistance Ron of the second device (W1 / W2 = 2.0). The fourth broken line LA4 is composed of four black circular plot points and shows the characteristics of the on-resistance Ron of the fourth device (comparative example).

[0088] Referring to the first to fourth broken lines LA1 to LA4, the on-resistance Ron decreased with the formation of the RESURF region 20 and further decreased in response to an increase in the n-type impurity concentration of the RESURF region 20. Also, the rate of decrease of the on-resistance Ron when increasing the n-type impurity concentration increased in the order of the first to fourth devices. That is, the rate of decrease of the on-resistance Ron increased in response to an increase in the ratio W1 / W2, and was greatest when the RESURF region 20 was formed over the entire opposing region between the drain region 15 and the source region 17.

[0089] Therefore, the n-type impurity concentration of the RESURF region 20 is preferably set to a relatively high value. Also, the ratio W1 / W2 is preferably set to a relatively large value. That is, in order to reduce the on-resistance Ron, it is preferable that a relatively high-concentration and relatively wide RESURF region 20 is formed under the condition of exceeding the n-type impurity concentration of the drift region 13.

[0090] FIG. 8 is a measured graph for explaining the breakdown voltage VB. The vertical axis represents the breakdown voltage VB [V]. The horizontal axis represents the n-type impurity concentration of the RESURF region 20 [cm 15 cm -3 with respect to the n-type impurity concentration (= 2.25×10 -3 ) of the drift region 13 (drift line region 13A).

[0091] Figure 8 shows the first to fourth broken lines LB1 to LB4. The first broken line LB1 is composed of four square plot points and shows the characteristics of the breakdown voltage VB of the first device (W1 / W2 = 0.5). The second broken line LB2 is composed of four triangular plot points and shows the characteristics of the breakdown voltage VB of the second device (W1 / W2 = 1.0). The third broken line LB3 is composed of four circular plot points and shows the characteristics of the breakdown voltage VB of the second device (W1 / W2 = 2.0). The fourth broken line LB4 is composed of four black circular plot points and shows the characteristics of the breakdown voltage VB of the fourth device (comparative example).

[0092] Referring to the first to fourth broken lines LB1 to LB4, it was found that the breakdown voltage VB tends to decrease with the formation of the RESURF region 20. Also, the breakdown voltage VB decreased in response to an increase in the n-type impurity concentration of the RESURF region 20. The rate of decrease of the breakdown voltage VB when the n-type impurity concentration was increased increased in the order of the first to fourth devices. That is, the rate of decrease of the breakdown voltage VB increased in response to an increase in the ratio W1 / W2, and was the largest when the RESURF region 20 was formed in the entire opposing region between the drain region 15 and the source region 17.

[0093] In particular, in the fourth device, the breakdown voltage VB decreased significantly. In this regard, the breakdown voltages VB related to the first to third devices exceeded the breakdown voltage VB related to the fourth device at any n-type impurity concentration. Therefore, it is preferable that the RESURF region 20 is partially formed in the surface layer portion of the drift region 13 so as to expose a part of the region that becomes the current path in the drift region 13 from the first main surface 3. Also, it is preferable that the RESURF region 20 is not formed in the entire region that becomes the current path in the drift region 13.

[0094] Further, the n-type impurity concentration in the RESURF region 20 is preferably set to a relatively low value. Also, the ratio W1 / W2 is preferably set to a relatively small value. That is, in order to improve the breakdown voltage VB, it is preferable to form a RESURF region 20 with a relatively low concentration and a relatively narrow width under the condition that it exceeds the n-type impurity concentration in the drift region 13.

[0095] Referring to FIGS. 7 and 8, the on-resistance Ron and the breakdown voltage VB have an inverse relationship with respect to the n-type impurity concentration in the RESURF region 20. Specifically, when the n-type impurity concentration in the RESURF region 20 is increased, the on-resistance Ron can be reduced, but the breakdown voltage VB decreases. On the other hand, when the n-type impurity concentration in the RESURF region 20 is decreased, the on-resistance Ron increases, but the breakdown voltage VB can be improved. The n-type impurity concentration in the RESURF region 20 can be set to any value within a range exceeding the n-type impurity concentration in the drift region 13 (drift line region 13A), but it needs to be adjusted in view of the on-resistance Ron and the breakdown voltage VB.

[0096] Similarly, the on-resistance Ron and the breakdown voltage VB have an inverse relationship with respect to the ratio W1 / W2. Specifically, when the ratio W1 / W2 is increased, the on-resistance Ron can be reduced, but the breakdown voltage VB decreases. On the other hand, when the ratio W1 / W2 is decreased, the on-resistance Ron increases, but the breakdown voltage VB can be improved. The ratio W1 / W2 can be set to any value, but it needs to be adjusted in view of the on-resistance Ron and the breakdown voltage VB.

[0097] The drift line region 13A has the property of improving the breakdown voltage VB and increasing the on-resistance Ron, while the RESURF region 20 has the property of reducing the on-resistance Ron and decreasing the breakdown voltage VB. Therefore, by bringing the n-type impurity concentration in the RESURF region 20 closer to the n-type impurity concentration in the drift region 13 (drift line region 13A), the on-resistance Ron can be reduced while suppressing the decrease in the breakdown voltage VB.

[0098] From the results of the first to third devices, the n-type impurity concentration in the RESURF region 20 is preferably adjusted to be more than 2.25×10 15 cm -3 and below 3.25×10 16 cm -3 Furthermore, the ratio W1 / W2 is preferably adjusted to be 0.5 or more and 2.0 or less. Thereby, while suppressing a decrease in the breakdown voltage VB, the on-resistance Ron can be reduced.

[0099] As can also be understood from the graph of FIG. 8, the breakdown voltage VB for the first to third devices rapidly decreases when the n-type impurity concentration in the RESURF region 20 exceeds 2.5×10 16 cm -3 Therefore, the n-type impurity concentration in the RESURF region 20 is particularly preferably adjusted to be 1.25×10 15 cm -3 or more and 2.5×10 16 cm -3 or less. Thereby, a decrease in the breakdown voltage VB can be appropriately suppressed.

[0100] Also, the rate of decrease in the breakdown voltage VB increases as the ratio W1 / W2 increases. Therefore, the ratio W1 / W2 is preferably 0.5 or more and less than 2.0. The ratio W1 / W2 is particularly preferably 0.5 or more and 1.0 or less. Thereby, while appropriately suppressing a decrease in the breakdown voltage VB, the on-resistance Ron can be appropriately reduced.

[0101] FIG. 9 is an actual measurement graph for explaining the gate threshold voltage Vth. The vertical axis indicates the gate threshold voltage Vth [V]. The horizontal axis indicates the n-type impurity concentration [cm 15 cm -3 in the RESURF region 20 with respect to the n-type impurity concentration (2.25×10 -3 ) in the drift region 13 (drift line region 13A) as a reference.

[0102] Figure 9 shows first to fourth broken lines LC1 to LC4. The first broken line LC1 is composed of four square plot points and shows the characteristics of the gate threshold voltage Vth of the first device (W1 / W2 = 0.5). The second broken line LC2 is composed of four triangular plot points and shows the characteristics of the gate threshold voltage Vth of the second device (W1 / W2 = 1.0). The third broken line LC3 is composed of four circular plot points and shows the characteristics of the gate threshold voltage Vth of the second device (W1 / W2 = 2.0). The fourth broken line LC4 is composed of four black circular plot points and shows the characteristics of the gate threshold voltage Vth of the fourth device (comparative example).

[0103] Referring to the first to fourth broken lines LC1 to LC4, the gate threshold voltages Vth of the first to fourth devices were substantially constant regardless of the n-type impurity concentration in the RESURF region 20 and the ratio W1 / W2. Therefore, according to the first to third devices, the on-resistance Ron can be reduced while suppressing fluctuations in the gate threshold voltage Vth and a decrease in the breakdown voltage VB.

[0104] As described above, the semiconductor device 1 includes a semiconductor chip 2, a high potential region 11, a low potential region 12, an n-type drift region 13, and an n-type RESURF region 20. The high potential region 11 is formed in the surface layer portion of the first main surface 3 of the semiconductor chip 2. The low potential region 12 is formed in the surface layer portion of the first main surface 3 at a distance from the high potential region 11. The drift region 13 is formed in the region between the high potential region 11 and the low potential region 12 in the surface layer portion of the first main surface 3.

[0105] The RESURF region 20 is partially formed in the surface layer portion of the drift region 13 so as to expose a part of the drift region 13 from the first main surface 3. Specifically, the RESURF region 20 is formed so as to expose a part of the region that becomes the current path in the drift region 13 from the first main surface 3. The RESURF region 20 has an n-type impurity concentration higher than that of the drift region 13.

[0106] The current density flowing through the RESURF region 20 exceeds the current density flowing through the drift region 13. On the other hand, the depletion layer expanding from the drift region 13 is larger than the depletion layer expanding from the RESURF region 20. Thereby, the breakdown voltage VB (breakdown voltage) can be suppressed from decreasing by the drift region 13, and the on-resistance Ron can be reduced by the RESURF region 20.

[0107] It is preferable that a plurality of RESURF regions 20 are formed at intervals in the surface layer portion of the drift region 13. According to this structure, the on-resistance Ron can be reduced by the plurality of RESURF regions 20. The RESURF region 20 preferably extends linearly in the facing direction of the high potential region 11 and the low potential region 12. According to this structure, the on-resistance Ron can be reduced in the current path that linearly connects the high potential region 11 and the low potential region 12.

[0108] The plurality of RESURF regions 20 are preferably formed in a stripe shape extending in the facing direction, and a part of the drift region 13 is exposed in a stripe shape from the first main surface 3. In this case, a plurality of drift line regions 13A extending in a stripe shape in the facing direction are partitioned between the plurality of RESURF regions 20 adjacent to each other. The plurality of drift line regions 13A are formed alternately with the plurality of RESURF regions 20. According to this structure, the region for suppressing the decrease in breakdown voltage and the region for reducing the on-resistance Ron are alternately formed in the surface layer portion of the drift region 13. Therefore, the decrease in breakdown voltage can be appropriately suppressed, and the on-resistance Ron can be appropriately reduced.

[0109] The semiconductor device 1 further includes an n-type impurity region 10 formed in the surface layer portion of the first main surface 3. The high potential region 11 includes an n-type drain region 15 formed in the surface layer portion of the impurity region 10. The low potential region 12 includes a p-type body region 16 formed in the surface layer portion of the first main surface 3 adjacent to the impurity region 10, and an n-type source region 17 formed in the surface layer portion of the body region 16 at a distance from the impurity region 10.

[0110] The drift region 13 is formed in the impurity region 10 in the region between the drain region 15 and the source region 17. The RESURF region 20 is formed in the surface layer portion of the drift region 13 in the region between the drain region 15 and the source region 17. According to this structure, the on-resistance Ron can be reduced in the current path connecting the drain region 15 and the source region 17.

[0111] The RESURF region 20 is preferably formed only in the region of the drift region 13 sandwiched between the drain region 15 and the source region 17. According to this structure, a relatively low-resistance RESURF region 20 is not formed outside the region sandwiched between the drain region 15 and the source region 17. Therefore, an undesired current flowing outside the region sandwiched between the drain region 15 and the source region 17 can be appropriately suppressed.

[0112] The high potential region 11 may include an n-type well region 14 formed in the surface layer portion of the impurity region 10 and a drain region 15 formed in the surface layer portion of the well region 14 at a distance from the periphery of the well region 14. In this case, the RESURF region 20 may be formed in the region between the well region 14 and the source region 17 in the surface layer portion of the drift region 13. According to this structure, an undesired current flowing outside the region sandwiched between the well region 14 and the source region 17 can be appropriately suppressed. In this case, the RESURF region 20 is preferably connected to one or both (preferably both) of the well region 14 and the body region 16.

[0113] The semiconductor device 1 further includes a field insulating film 21 and a field electrode 31. The field insulating film 21 covers the drift region 13 and the RESURF region 20 on the first main surface 3. The field electrode 31 is routed linearly on the field insulating film 21 and crosses the RESURF region 20 in plan view. According to this structure, the field concentration in the drift region 13 and the RESURF region 20 can be suppressed by the field electrode 31. Therefore, the breakdown voltage can be improved.

[0114] In this case, it is preferable that the field electrode 31 crosses the RESURF region 20 a plurality of times in a plan view. More preferably, the field electrode 31 surrounds the high potential region 11 a plurality of times. According to these structures, the electric field concentration in the drift region 13 and the RESURF region 20 can be appropriately suppressed.

[0115] The field electrode 31 preferably comprises a field resistance film electrically connected to the high potential region 11 and the low potential region 12. According to this structure, the electric field can be appropriately distributed in the drift region 13 by utilizing the voltage drop in the field electrode 31. Therefore, the electric field concentration in the drift region 13 and the RESURF region 20 can be appropriately suppressed.

[0116] FIG. 10 is a diagram corresponding to FIG. 5 and is a cross-sectional view for explaining a semiconductor device 91 according to a second embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0117] The high potential region 11 of the semiconductor device 91 includes a p-type collector region 92 instead of the drain region 15. As described above, according to the semiconductor device 91, an IGBT can be provided instead of the LDMISFET. In this case, the "source" of the LDMISFET is read as the "emitter" of the IGBT. Also, the "drain" of the LDMISFET is read as the "collector" of the IGBT. Even when an IGBT is adopted instead of the LDMISFET, the same effects as those described for the semiconductor device 1 can be achieved.

[0118] FIG. 11 is a diagram corresponding to FIG. 5 and is a cross-sectional view for explaining a semiconductor device 101 according to a third embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0119] The high-potential region 11 related to the semiconductor device 101 includes an n-type cathode well region 102 instead of the well region 14, and includes an n-type cathode region 103 instead of the drain region 15. Also, the low-potential region 12 related to the semiconductor device 101 includes a p-type anode well region 104 instead of the body region 16, and includes a p-type anode region 105 instead of the source region 17 and the contact region 19. The drift region 13 related to the semiconductor device 101 is formed in the region between the cathode well region 102 (cathode region 103) and the anode well region 104 (anode region 105).

[0120] The semiconductor device 101 does not have a gate insulating film 40 and a gate electrode 41. The cathode well region 102 and the cathode region 103 are each formed in a manner similar to the well region 14 and the drain region 15 according to the first embodiment. The anode well region 104 is formed in a manner similar to the body region 16 according to the first embodiment.

[0121] The anode region 105 is formed in the surface layer portion of the anode well region 104. The anode region 105 has a p-type impurity concentration exceeding the p-type impurity concentration of the anode well region 104. The p-type impurity concentration of the anode region 105 is 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less may be sufficient.

[0122] In this form, the anode region 105 is formed in the first straight portion 16A and the second straight portion 16B at intervals from the first curved portion 16C and the second curved portion 16D of the anode well region 104 (see also FIG. 2). That is, the anode region 105 is not formed in the first curved portion 16C and the second curved portion 16D of the anode well region 104. The anode region 105 is formed in an end-belt shape extending along the first straight portion 16A and the second straight portion 16B in plan view.

[0123] As a result, the anode region 105 faces the cathode region 103 in the second direction Y, and forms a current path along the second direction Y between the anode region 105 and the cathode region 103 in the drift region 13. Preferably, with respect to the first direction X, the length of the anode region 105 is less than the length of the cathode region 103. Of course, the anode region 105 may be formed in an annular shape (specifically, an oval annular shape) surrounding the impurity region 10. That is, the anode region 105 may also be formed in the first curved portion 16C and the second curved portion 16D of the anode well region 104.

[0124] The semiconductor device 101 includes a RESURF region 20 formed in the surface layer portion of the drift region 13. The RESURF region 20 related to the semiconductor device 101 is formed in the same manner as the RESURF region 20 according to the first embodiment. That is, in this form, a plurality of RESURF regions 20 are formed at intervals in the surface layer portion of the drift region 13.

[0125] The plurality of RESURF regions 20 are formed at intervals from the bottom of the drift region 13 toward the first main surface 3 side. Specifically, the plurality of RESURF regions 20 are formed shallower than the cathode well region 102 and deeper than the cathode region 103. The plurality of RESURF regions 20 face the semiconductor substrate 6 with a part of the drift region 13 interposed therebetween.

[0126] The plurality of RESURF regions 20 extend linearly in the facing direction of the high potential region 11 and the low potential region 12 in plan view, and are formed in a stripe shape with intervals in the direction orthogonal to the facing direction. As a result, the plurality of RESURF regions 20 expose a part of the drift region 13 from the first main surface 3 in a stripe shape in plan view.

[0127] The plurality of RESURF regions 20 are formed in a region between the cathode region 103 and the anode well region 104 in the surface layer portion of the drift region 13. Specifically, the plurality of RESURF regions 20 are formed in a region between the cathode well region 102 and the anode well region 104. In this form, the RESURF region 20 has one end connected to the cathode well region 102 and the other end connected to the anode well region 104. Thereby, the RESURF region 20 forms a current path continuously extending through the region between the cathode well region 102 and the anode well region 104.

[0128] The plurality of RESURF regions 20 are formed in the straight portion of the drift region 13 at an interval from the curved portion of the drift region 13. That is, the plurality of RESURF regions 20 are not formed in the region between the first curved portion 16C (second curved portion 16D) of the cathode region 103 and the anode well region 104. The plurality of RESURF regions 20 are formed in the region between the first straight portion 16A (second straight portion 16B) of the cathode region 103 and the anode well region 104.

[0129] The plurality of RESURF regions 20 are formed only in a region sandwiched between the cathode region 103 and the anode region 105 in the surface layer portion of the drift region 13. Thereby, the RESURF region 20 forms a current path continuously extending through the region between the cathode region 103 and the anode region 105. When the anode region 105 is formed in an annular shape surrounding the impurity region 10, the plurality of RESURF regions 20 may be formed in the curved portion of the drift region 13. Since the other configuration of the plurality of RESURF regions 20 is the same as that in the first embodiment, a specific description thereof is omitted.

[0130] The semiconductor device 101 includes a plurality of drift line regions 13A (drift exposed regions) partitioned in regions between the plurality of RESURF regions 20 adjacent to each other in the surface layer portion of the drift region 13. Since the configuration of the plurality of drift line regions 13A is the same as that in the first embodiment, a specific description thereof is omitted.

[0131] The first wiring layer 73A related to the semiconductor device 101 includes a first cathode wiring 106 and a first anode wiring 107 instead of the first drain wiring 76, the first source wiring 77, and the first gate wiring 78. The first cathode wiring 106 and the first anode wiring 107 are each formed in the same manner as the first drain wiring 76 and the first source wiring 77 according to the first embodiment.

[0132] The second wiring layer 73B related to the semiconductor device 101 includes a second cathode wiring 108 and a second anode wiring 109 instead of the second drain wiring 82, the second source wiring 83, and the second gate wiring (not shown). The second cathode wiring 108 and the second anode wiring 109 are each formed in the same manner as the second drain wiring 82 and the second source wiring 83 according to the first embodiment.

[0133] As described above, according to the semiconductor device 101, a diode can be provided instead of the LDMISFET. Even when a diode is adopted instead of the LDMISFET, the same effects as those described for the semiconductor device 1 can be achieved. The diode related to the semiconductor device 101 can be used as a freewheeling diode that is reversely connected in parallel to a semiconductor switching device such as a MISFET (for example, the LDMISFET according to the first embodiment) or an IGBT (for example, the IGBT according to the second embodiment).

[0134] Embodiments of the present invention can be implemented in other forms.

[0135] In each of the above-described embodiments, an example in which the field electrode 31 made of a field resistance film is formed has been described. However, a field electrode 31 in an electrically floating state may be formed. In this case, a plurality of field electrodes 31 that concentrically surround the high potential region 11 a plurality of times may be formed. In this case, the inner field electrode 36 may be removed.

[0136] The diode in the foregoing third embodiment may be formed on the same semiconductor chip 2 (first main surface 3) as the LDMISFET according to the first embodiment. In this case, the LDMISFET according to the first embodiment is formed in one device region 8 (LDMIS region 9), and the diode according to the third embodiment is formed in another device region 8. Further, in this case, the diode may be connected in anti-parallel to the LDMISFET as a reflux diode.

[0137] The diode in the foregoing third embodiment may be formed on the same semiconductor chip 2 (first main surface 3) as the IGBT according to the second embodiment. In this case, the IGBT according to the second embodiment is formed in one device region 8, and the diode according to the third embodiment is formed in another device region 8. Further, in this case, the diode may be connected in anti-parallel to the IGBT as a reflux diode.

[0138] In each of the foregoing embodiments, the resistive field electrode 31 may be used as a current monitor for detecting a current flowing between the high potential region 11 and the low potential region 12. The current flowing between the high potential region 11 and the low potential region 12 is detected, for example, from the voltage drop of the field electrode 31 or the current flowing through the field electrode 31. According to this structure, the electric field can be appropriately distributed by the field electrode 31, and at the same time, the convenience of the semiconductor devices 1, 91, and 101 can be enhanced by the current monitor function.

[0139] In each of the foregoing embodiments, a configuration in which the conductivity types of various semiconductor regions are inverted may be adopted. That is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

[0140] In each of the foregoing embodiments, an example in which a plurality of RESURF regions 20 extending in a stripe shape are formed has been described. However, the RESURF regions 20 shown in FIGS. 12 to 15 may be formed.

[0141] FIG. 12 is a perspective cross-sectional view corresponding to FIG. 4 and for explaining the RESURF region 20 according to the first modification example. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 1, the same reference numerals are given and the description thereof is omitted.

[0142] The RESURF region 20 according to the first exemplary form is formed in a lattice shape having a plurality of crossroads in plan view. Specifically, the RESURF region 20 includes a plurality of first regions 111 and a plurality of second regions 112. The plurality of first regions 111 extend in a stripe shape in the facing direction (second direction Y) of the high potential region 11 and the low potential region 12. The plurality of second regions 112 extend in a stripe shape in the direction orthogonal to the facing direction (first direction X) and intersect the plurality of first regions 111 in a cross shape, respectively.

[0143] On the surface layer portion of the drift region 13, a plurality of divided regions 113 each formed of a part of the drift region 13 by the RESURF region 20 are defined. The plurality of divided regions 113 correspond to a structure in which the drift line region 13A according to the first embodiment is divided into a plurality of parts by the plurality of second regions 112.

[0144] The plurality of divided regions 113 are arranged in a matrix at intervals in the first direction X and the second direction Y in plan view. In this example, the plurality of divided regions 113 are each formed in a strip shape extending in the second direction Y in plan view. The planar shape of the plurality of divided regions 113 is arbitrary and may be formed in a square shape, a circular shape, an elliptical shape, or an oval shape.

[0145] As described above, even when the RESURF region 20 according to the first modification example is formed, the same effects as those described for the semiconductor device 1 can be achieved. The RESURF region 20 according to the first modification example can also be applied to the aforementioned second to third embodiments.

[0146] FIG. 13 is a perspective sectional view corresponding to FIG. 4 and for explaining the RESURF region 20 according to the second modification. Hereinafter, for structures corresponding to the structures described for the semiconductor device 1, the same reference numerals are given and the description thereof is omitted.

[0147] The RESURF region 20 according to the second exemplary form is formed in a lattice shape having a plurality of T-shaped paths in plan view. Specifically, the RESURF region 20 includes a plurality of first regions 111 and a plurality of second regions 112. The plurality of first regions 111 extend in a stripe shape in the facing direction (second direction Y) of the high potential region 11 and the low potential region 12. The plurality of second regions 112 are formed at intervals in the facing direction in the regions between the adjacent plurality of first regions 111, and connect the adjacent plurality of first regions 111 in a T shape, respectively.

[0148] On the surface layer portion of the drift region 13, a plurality of divided regions 113 each formed of a part of the drift region 13 by the RESURF region 20 are partitioned. The plurality of divided regions 113 correspond to a structure in which the drift line region 13A according to the first embodiment is divided into a plurality of parts by the plurality of second regions 112.

[0149] The plurality of divided regions 113 are arranged in a staggered manner with intervals in the first direction X and the second direction Y in plan view. In this example, the plurality of divided regions 113 are each formed in a strip shape extending in the second direction Y in plan view. The planar shape of the plurality of divided regions 113 is arbitrary and may be formed in a square shape, a circular shape, an elliptical shape, or an oval shape.

[0150] As described above, even when the RESURF region 20 according to the second modification is formed, the same effects as those described for the semiconductor device 1 can be achieved. The RESURF region 20 according to the second modification can also be applied to the aforementioned second to third embodiments.

[0151] FIG. 14 is a perspective cross-sectional view corresponding to FIG. 4 and for explaining the RESURF region 20 according to the third modification. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 1, the same reference numerals are given and the description thereof is omitted.

[0152] In the third modification, a plurality of RESURF regions 20 are formed in a matrix at intervals in the facing direction (second direction Y) of the high potential region 11 and the low potential region 12 and in the direction orthogonal to the facing direction (first direction X) in plan view. In this example, the plurality of RESURF regions 20 are each formed in a strip shape extending in the second direction Y in plan view. The planar shape of the plurality of RESURF regions 20 is arbitrary, and may be formed in a square shape, a circular shape, an elliptical shape, or an oval shape.

[0153] On the surface layer portion of the drift region 13, a drift line region 13A which is a part of the drift region 13 is partitioned by a plurality of RESURF regions 20. The drift line region 13A is partitioned in a lattice shape having a plurality of crossroads. That is, the drift line region 13A includes a plurality of first line regions 114 and a plurality of second line regions 115 that form crossroads. The plurality of first line regions 114 extend in a stripe shape in the facing direction (second direction Y). The plurality of second line regions 115 extend in a stripe shape in the orthogonal direction (first direction X) and cross the plurality of first line regions 114 in a cross shape, respectively.

[0154] As described above, even when the RESURF region 20 according to the third modification is formed, the same effects as those described for the semiconductor device 1 can be achieved. However, in the third modification, since the plurality of RESURF regions 20 are formed with a space therebetween across a part of the drift region 13, the structure of the semiconductor device 1 is preferable for reducing the on-resistance Ron. The RESURF region 20 according to the third modification can also be applied to the second to third embodiments described above.

[0155] FIG. 15 is a perspective sectional view corresponding to FIG. 4 and for explaining a RESURF region 20 according to a fourth modification. In the following, for structures corresponding to the structures described for the semiconductor device 1, the same reference numerals are given and the description thereof is omitted.

[0156] In the fourth modification, a plurality of RESURF regions 20 are formed in a staggered pattern with spaces therebetween in the facing direction (second direction Y) of the high potential region 11 and the low potential region 12 and in the direction orthogonal to the facing direction (first direction X) in a plan view. In this example, the plurality of RESURF regions 20 are each formed in a strip shape extending in the second direction Y in a plan view. The planar shape of the plurality of RESURF regions 20 is arbitrary, and may be formed in a square shape, a circular shape, an elliptical shape, or an oval shape.

[0157] On the surface layer portion of the drift region 13, a drift line region 13A, which is a part of the drift region 13, is partitioned by a plurality of RESURF regions 20. The drift line region 13A is partitioned in a lattice shape having a plurality of T-shaped intersections. That is, the drift line region 13A includes a plurality of first line regions 114 and a plurality of second line regions 115 that form the T-shaped intersections. The plurality of first line regions 114 extend in a stripe shape in the facing direction (second direction Y). The plurality of second line regions 115 are formed with spaces therebetween in the facing direction in the regions between adjacent first line regions 114, and connect the adjacent first line regions 114 in a T shape, respectively.

[0158] As described above, even when the RESURF region 20 according to the fourth modification is formed, the same effects as those described for the semiconductor device 1 can be achieved. However, in the fourth modification, since the plurality of RESURF regions 20 are formed with spaces therebetween across a part of the drift region 13, the structure of the semiconductor device 1 is preferable for reducing the on-resistance Ron. The RESURF region 20 according to the fourth modification can also be applied to the second to third embodiments described above.

[0159] The semiconductor devices 1, 91, and 101 described above can be incorporated into a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, automobiles (including electric vehicles), trains, industrial robots, air conditioners, air compressors, fans, vacuum cleaners, dryers, refrigerators, and the like. Further, the semiconductor devices 1, 91, and 101 described above can also be incorporated into a power module used in an inverter circuit of a solar cell, a wind power generator, or other power generation devices. Further, the semiconductor devices 1, 91, and 101 described above can also be incorporated into a circuit module used for an analog control power supply, a digital control power supply, or the like.

[0160] Examples of features extracted from this specification and the drawings are shown below. The following [A1] to [A19] and [B1] to [B20] provide a semiconductor device capable of reducing the on-resistance while suppressing a decrease in breakdown voltage. Hereinafter, the alphanumeric characters in parentheses represent the corresponding components in the above-described embodiments, but the scope of each item is not intended to be limited to the embodiments.

[0161] [A1] A semiconductor device (1, 91, 101) including a semiconductor chip (2) having a main surface (3), a high-potential region (11) formed in a surface layer portion of the main surface (3), a low-potential region (12) formed in the surface layer portion of the main surface (3) at a distance from the high-potential region (11), a first-conductivity-type drift region (13)(13) formed in a region between the high-potential region (11) and the low-potential region (12) in the surface layer portion of the main surface (3), and a first-conductivity-type resurf region (20) partially formed in a surface layer portion of the drift region (13) so as to expose a part of a region that becomes a current path in the drift region (13) from the main surface (3), the resurf region (20) having an impurity concentration exceeding that of the drift region (13). According to this semiconductor device (1, 91, 101), the on-resistance (Ron) can be reduced while suppressing a decrease in breakdown voltage (VB).

[0162] [A2] The semiconductor device (1, 91, 101) according to A1, wherein the resurf region (20) is formed in a line shape extending in a direction facing the high-potential region (11) and the low-potential region (12).

[0163] [A3] The semiconductor device (1, 91, 101) according to A1 or A2, wherein a plurality of the RESURF regions (20) are formed at intervals in the surface layer portion of the drift region (13).

[0164] [A4] The semiconductor device (1, 91, 101) according to A3, wherein the plurality of the RESURF regions (20) are formed in a stripe shape extending in the facing direction of the high potential region (11) and the low potential region (12), and a part of the drift region (13) is exposed in a stripe shape from the main surface (3).

[0165] [A5] The semiconductor device (1, 91, 101) according to any one of A1 to A4, further comprising a field insulating film (21) covering the drift region (13) and the RESURF region (20) on the main surface (3), and a field electrode (31) routed linearly on the field insulating film (21) and crossing the RESURF region (20) in a plan view.

[0166] [A6] The semiconductor device (1, 91, 101) according to A5, wherein the field electrode (31) crosses the RESURF region (20) a plurality of times in a plan view.

[0167] [A7] The semiconductor device (1, 91, 101) according to A5 or A6, wherein the field electrode (31) surrounds the high potential region (11) a plurality of times.

[0168] [A8] The semiconductor device (1, 91, 101) according to any one of A5 to A7, wherein the field electrode (31) is formed of a field resistance film electrically connected to the high potential region (11) and the low potential region (12).

[0169] [A9] The high potential region (11) includes a drain region (15) of a first conductivity type formed in the surface layer portion of the main surface (3), the low potential region (12) includes a body region (16) of a second conductivity type formed in the surface layer portion of the main surface (3), and a source region (17) of the first conductivity type formed in the surface layer portion of the body region (16), the drift region (13) is formed in a region between the drain region (15) and the body region (16) in the surface layer portion of the main surface (3), and the RESURF region (20) is formed in a region between the drain region (15) and the source region (17) in the surface layer portion of the drift region (13). The semiconductor device (1) according to any one of A1 to A8.

[0170] [A10] The RESURF region (20) is connected to the body region (16). The semiconductor device (1) according to A9.

[0171] [A11] The high potential region (11) includes a well region (14) of a first conductivity type formed in the surface layer portion of the main surface (3), and the drain region (15) formed in the surface layer portion of the well region (14), and the RESURF region (20) is formed in a region between the well region (14) and the source region (17) in the surface layer portion of the drift region (13). The semiconductor device (1) according to A9 or A10.

[0172] [A12] The RESURF region (20) is connected to the well region (14). The semiconductor device (1) according to A11.

[0173] [A13] The RESURF region (20) is formed only in a region sandwiched by the source region (17) and the drift region (13) in the drift region (13). The semiconductor device (1) according to any one of A9 to A12.

[0174] [A14] The semiconductor device (1) according to any one of A9 to A13, wherein the body region (16) surrounds the drain region (15), and the source region (17) is formed in an end shape on the surface layer portion of the body region (16).

[0175] [A15] The semiconductor device (1) according to any one of A9 to A14, further comprising a channel region (18) formed between the drift region (13) and the source region (17) in the surface layer portion of the body region (16), a gate insulating film (40) covering the channel region (18) on the main surface (3), and a gate electrode (41) formed on the gate insulating film (40).

[0176] [A16] The semiconductor device (1, 91, 101) according to A15, wherein the gate insulating film (40) covers the drift region (13) and the RESURF region (20).

[0177] [A17] A semiconductor chip (2) having a main surface (3), a high-potential region (11) and a low-potential region (12) formed at intervals from each other in the surface layer portion of the main surface (3), a drift region (13) of a first conductivity type formed in a region between the high-potential region (11) and the low-potential region (12) in the surface layer portion of the main surface (3), a RESURF region (20) of a first conductivity type formed in a line shape extending in the facing direction of the high-potential region (11) and the low-potential region (12) in the surface layer portion of the drift region (13) so as to expose a part of the region serving as a current path in the drift region (13) from the main surface (3) and having an impurity concentration exceeding that of the drift region (13), a field insulating film (21) covering the drift region (13) and the RESURF region (20), and a field electrode (31) formed on the field insulating film (21) and routed in a line shape so as to intersect the RESURF region (20) in plan view.

[0178] [A18] The field electrode (31) is the semiconductor device (1, 91, 101) according to A17, which is composed of a field resistance film electrically connected to the high potential region (11) and the low potential region (12).

[0179] [A19] The field electrode (31) is the semiconductor device (1, 91, 101) according to A17 or A18, which is orthogonal to the RESURF region (20) in a plan view.

[0180] [B1] A semiconductor device (101) including a semiconductor chip (2) having a main surface (3), a cathode region (103) of a first conductivity type formed in a surface layer portion of the main surface (3), an anode region (105) of a second conductivity type formed in the surface layer portion of the main surface (3) at an interval from the cathode region (103), a drift region (13) of the first conductivity type formed in a region between the cathode region (103) and the anode region (105) in the surface layer portion of the main surface (3), and a RESURF region (20) of the first conductivity type which is partially formed in a surface layer portion of the drift region (13) so as to expose a part of a region serving as a current path in the drift region (13) from the main surface (3) and has an impurity concentration exceeding that of the drift region (13). According to this semiconductor device (101), the on-resistance (Ron) can be reduced while suppressing a decrease in breakdown voltage (VB).

[0181] [B2] The semiconductor device (101) according to B1, in which a high potential is applied to the cathode region (103) and a low potential is applied to the anode region (105).

[0182] [B3] The drift region (13) has an impurity concentration lower than that of the cathode region (103) in the semiconductor device (101) according to B1 or B2.

[0183] [B4] The RESURF region (20) is formed in a line shape extending in a direction facing the cathode region (103) and the anode region (105) in the semiconductor device (101) according to any one of B1 to B3.

[0184] The semiconductor device (101) according to any one of B1 to B4, wherein a plurality of the RESURF regions (20) are formed in the surface layer portion of the drift region (13) at intervals.

[0185] [B6] The semiconductor device (101) according to B5, wherein the plurality of the RESURF regions (20) are formed in a stripe shape extending in the facing direction of the cathode region (103) and the anode region (105), and a part of the drift region (13) is exposed in a stripe shape from the main surface (3).

[0186] [B7] The semiconductor device (101) according to B6, wherein the plurality of the RESURF regions (20) partition a plurality of drift exposed regions (13A) extending in a stripe shape in the facing direction on the main surface (3).

[0187] [B8] The semiconductor device (101) according to any one of B1 to B7, further comprising: a field insulating film (21) covering the drift region (13) and the RESURF region (20) on the main surface (3); and a field electrode (31) routed linearly on the field insulating film (21) and crossing the RESURF region (20) in a plan view.

[0188] [B9] The semiconductor device (101) according to B8, wherein the field electrode (31) crosses the RESURF region (20) a plurality of times in a plan view.

[0189] [B10] The semiconductor device (101) according to B8 or B9, wherein the field electrode (31) surrounds the cathode region (103) a plurality of times.

[0190] [B11] The semiconductor device (101) according to any one of B8 to B10, wherein the field electrode (31) is composed of a field resistance film electrically connected to the cathode region (103) and the anode region (105).

[0191] [B12] The semiconductor device (101) according to any one of B1 to B11, wherein the RESURF region (20) is formed only in a region sandwiched by the cathode region (103) and the anode region (105) in the drift region (13).

[0192] [B13] The semiconductor device (101) according to any one of B1 to B12, further comprising: an impurity region (11) of a first conductivity type formed in a surface layer portion of the main surface (3); a cathode well region (102) of a first conductivity type formed in a surface layer portion of the impurity region (11); and an anode well region (104) of a second conductivity type formed in a surface layer portion of the main surface (3) adjacent to the impurity region (11). The cathode region (103) is formed in a surface layer portion of the cathode well region (102), the anode region (105) is formed in a surface layer portion of the anode well region (104), the drift region (13) is formed in a region between the cathode well region (102) and the anode well region (104), and the RESURF region (20) is formed in a region between the cathode well region (102) and the anode well region (104) in a surface layer portion of the drift region (13).

[0193] [B14] The semiconductor device (101) according to B13, wherein the cathode region (103) has an impurity concentration exceeding that of the cathode well region (102), and the anode region (105) has an impurity concentration exceeding that of the anode well region (104).

[0194] [B15] The semiconductor device (101) according to B13 or B14, wherein the RESURF region (20) is connected to the cathode well region (102).

[0195] [B16] The semiconductor device (101) according to any one of B13 to B15, wherein the RESURF region (20) is connected to the anode well region (104).

[0196] [B17]The anode well region (104) surrounds the impurity region (11), and the anode region (105) is formed in an open-ended strip shape extending along the impurity region (11). The semiconductor device (101) according to any one of B13 to B16.

[0197] [B18]A semiconductor chip (2) having a main surface (3), a cathode region (103) of a first conductivity type and an anode region (105) of a second conductivity type formed at intervals from each other in the surface layer portion of the main surface (3), and the cathode region (103) and the anode region (105) in the surface layer portion of the main surface (3). A drift region (13) of a first conductivity type formed in the region therebetween, and a line shape extending in the direction facing the cathode region (103) and the anode region (105) in the surface layer portion of the drift region (13) so as to expose a part of the drift region (13) from the main surface (3). A RESURF region (20) of a first conductivity type having an impurity concentration exceeding that of the drift region (13), a field insulating film (21) covering the drift region (13) and the RESURF region (20), and formed on the field insulating film (21). A semiconductor device (101) including a field electrode (31) routed in a line shape so as to intersect the RESURF region (20) in plan view.

[0198] [B19]The field electrode (31) is composed of a field resistance film electrically connected to the cathode region (103) and the anode region (105). The semiconductor device (101) according to B18.

[0199] [B20]The field electrode (31) is orthogonal to the RESURF region (20) in plan view. The semiconductor device (101) according to B18 or B19.

[0200] Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples. The scope of the present invention is limited by the appended claims.

Description of Symbols

[0201] 1 Semiconductor device 2 Semiconductor chip 3 First main surface 11 High potential region 12 Low potential region 13 Drift region 14 Well region 15 Drain region 16 Body region 17 Source region 18 Channel region 20 Resurf region 21 Field insulating film 31 Field electrode 40 Gate insulating film 41 Gate electrode 91 Semiconductor device 101 Semiconductor device

Claims

1. A semiconductor chip having a main surface, A high-potential region formed in a surface layer portion of the main surface, A low-potential region formed in a surface layer portion of the main surface at a distance from the high-potential region, A drift region of a first conductivity type formed in a region between the high-potential region and the low-potential region in the surface layer portion of the main surface, A RESURF region of a first conductivity type, which is partially formed in a surface layer portion of the drift region so as to expose a part of a region serving as a current path in the drift region from the main surface and has an impurity concentration exceeding that of the drift region, The semiconductor device, wherein the RESURF region is formed in a line shape extending in a direction facing the high-potential region and the low-potential region.

2. The semiconductor device according to claim 1, wherein a plurality of the RESURF regions are formed in the surface layer portion of the drift region at intervals.

3. The semiconductor device according to claim 2, wherein the plurality of the RESURF regions are formed in a stripe shape extending in a direction facing the high-potential region and the low-potential region, and a part of the drift region is exposed from the main surface in a stripe shape.

4. A field insulating film covering the drift region and the RESURF region on the main surface, The semiconductor device according to any one of claims 1 to 3, further comprising a field electrode routed in a line shape on the field insulating film and crossing the RESURF region in a plan view.

5. The semiconductor device according to claim 4, wherein the field electrode crosses the RESURF region a plurality of times in a plan view.

6. The semiconductor device according to claim 4 or 5, wherein the field electrode surrounds the high-potential region a plurality of times.

7. The semiconductor device according to any one of claims 4 to 6, wherein the field electrode is composed of a field resistance film electrically connected to the high-potential region and the low-potential region.

8. The high-potential region includes a drain region of a first conductivity type formed in a surface layer portion of the main surface, The low-potential region includes a body region of a second conductivity type formed in a surface layer portion of the main surface and a source region of a first conductivity type formed in a surface layer portion of the body region, The drift region is formed in a region between the drain region and the body region in the surface layer portion of the main surface, The semiconductor device according to any one of claims 1 to 7, wherein the RESURF region is formed in a region between the drain region and the source region in a surface layer portion of the drift region.

9. The semiconductor device according to claim 8, wherein the RESURF region is connected to the body region.

10. The high potential region includes a well region of a first conductivity type formed in a surface layer portion of the main surface, and the drain region formed in a surface layer portion of the well region. The semiconductor device according to claim 8 or 9, wherein the RESURF region is formed in a region between the well region and the source region in a surface layer portion of the drift region.

11. The semiconductor device according to claim 10, wherein the RESURF region is connected to the well region.

12. The semiconductor device according to any one of claims 8 to 11, wherein the RESURF region is formed only in a region sandwiched between the source region and the drift region in the drift region.

13. The body region surrounds the drain region. The semiconductor device according to any one of claims 8 to 12, wherein the source region is formed in an end shape in a surface layer portion of the body region.

14. A channel region formed between the drift region and the source region in a surface layer portion of the body region; A gate insulating film covering the channel region on the main surface; The semiconductor device according to any one of claims 8 to 13, further comprising a gate electrode formed on the gate insulating film.

15. The semiconductor device according to claim 14, wherein the gate insulating film covers the drift region and the RESURF region.

16. A semiconductor chip having a main surface; A high potential region and a low potential region formed at intervals from each other in a surface layer portion of the main surface; A drift region of a first conductivity type formed in a region between the high potential region and the low potential region in a surface layer portion of the main surface; A RESURF region of a first conductivity type, which is formed in a line shape extending in a direction facing the high potential region and the low potential region in a surface layer portion of the drift region so as to expose a part of a region serving as a current path in the drift region from the main surface, and has an impurity concentration exceeding that of the drift region; A field insulating film covering the drift region and the RESURF region; A semiconductor device including a field electrode formed on the field insulating film and routed in a line shape so as to intersect the RESURF region in a plan view.

17. The semiconductor device according to claim 16, wherein the field electrode is composed of a field resistance film electrically connected to the high potential region and the low potential region.

18. The semiconductor device according to claim 16 or 17, wherein the field electrode is orthogonal to the RESURF region in a plan view.

Images