Inverse wide-base double magnetic tunnel junction device

Abstract

A method for fabricating a double magnetic tunnel junction device is provided, the method including forming a first magnetic tunnel junction stack, forming a spin conducting layer on the first magnetic tunnel junction stack, and forming a second magnetic tunnel junction stack on the spin conducting layer, the second magnetic tunnel junction stack having a width greater than a width of the first magnetic tunnel junction stack.

Description

Technical Field

[0001] The present invention relates to a magnetic random access memory (MRAM) device cell including a dual magnetic tunnel junction (DMTJ) stack and a method of manufacturing an MRAM device. Tunnel magnetoresistance (TMR) and write efficiency are factors that affect the performance of an MRAM device, and certain DMTJ devices can suffer from low magnetoresistivity.

Summary of the Invention

[0002] Embodiments of the present invention relate to a method of manufacturing a dual magnetic tunnel junction device. The method includes forming a first magnetic tunnel junction stack, forming a spin conduction layer on the first magnetic tunnel junction stack, and forming a second magnetic tunnel junction stack on the spin conduction layer. The second magnetic tunnel junction stack has a width greater than the width of the first magnetic tunnel junction stack.

[0003] Other embodiments relate to a dual magnetic tunnel junction device. The dual magnetic tunnel junction device includes a first magnetic tunnel junction stack, a spin conduction layer on the first magnetic tunnel junction stack, and a second magnetic tunnel junction stack on the spin conduction layer. The second magnetic tunnel junction stack has a width greater than the width of the first magnetic tunnel junction stack.

[0004] The above summary is not intended to describe each exemplary embodiment or every implementation of the present invention.

[0005] The drawings included in this application are incorporated into and form a part of the specification. They illustrate embodiments of the invention and, together with the description, explain the principles of the invention. The drawings merely illustrate particular embodiments and do not limit the invention.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0007] The present disclosure describes an MRAM device including a dual magnetic tunnel junction (DMTJ) stack and a method of manufacturing the MRAM device. In particular, the present disclosure describes a single-bit MRAM device having two MJT stacks stacked perpendicular to an inverted wide base (i.e., the upper MTJ stack has a larger critical dimension (CD) than the bottom MTJ stack).

[0008] Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments may be devised without departing from the scope of the present invention. Note that in the following description and drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) are described between elements. These connections or positional relationships or both may be direct or indirect, and the present invention is not intended to be limited in this regard. Thus, the coupling of entities can refer to either direct or indirect coupling, and the positional relationship between entities can be direct or indirect. As an example of an indirect positional relationship, a reference herein to forming layer “A” on layer “B” includes a situation where one or more intermediate layers are between layer “A” and layer “B” as long as the relevant characteristics and functions of layer “A” and layer “B” are not substantially changed by the intermediate layer (e.g., layer “C”).

[0009] The following definitions and abbreviations are used for the interpretation of the claims and the specification. In this specification, the terms "comprises", "comprising", "includes", "including", "has", "having", "contains", "containing", or any other variation thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements, but may include other elements not expressly listed, or other elements inherent to such composition, mixture, process, method, article, or apparatus.

[0010] For the purposes of the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof are related to the structures and methods described as oriented in the drawings. The terms "overlying", "atop", "on top", "positioned on", or "positioned atop" mean that a first element, such as a first structure, is present on a second element, such as a second structure, and that intervening elements, such as an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intervening conductive, insulating, or semiconductor layer at the interface of the two elements. It should be noted that terms such as "selective to", e.g., "a first element selective to a second element", mean that the first element can be etched and the second element can act as an etch stop.

[0011] For the sake of brevity, the prior art related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Further, the various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, since the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, many conventional steps are either briefly mentioned here or completely omitted without providing details of well-known processes for the sake of brevity.

[0012] Generally, the various processes used to form microchips packaged within an IC are classified into four general categories, namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0013] Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). Another deposition technique is plasma-enhanced chemical vapor deposition (PECVD), which is a process that uses the energy within a plasma to cause reactions on the wafer surface that require higher temperatures than conventional CVD. The energy ion collisions during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0014] Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), etc. An example of a removal process is ion beam etching (IBE). Generally, IBE (or milling) refers to a dry plasma etching method that utilizes a separated, broad beam of ion / plasma source to remove substrate material by means of a physically inert gas or a chemically reactive gas or both. Similar to other dry plasma etching techniques, IBE has advantages such as etching rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). Generally, RIE uses a chemically reactive plasma to remove the material deposited on a wafer. In RIE, a plasma is generated under low pressure (vacuum) by an electromagnetic field. High energy ions from the RIE plasma collide with and react with the substrate surface to remove the material.

[0015] Semiconductor doping is generally a change in electrical properties, for example by doping the source and drain of a transistor, by diffusion or ion implantation or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing provides activation of the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used for connection and insulation of transistors and their components. By selectively doping various regions of a semiconductor substrate, it becomes possible to change the conductivity of the substrate by applying a voltage. By fabricating the structures of these various components, millions of transistors can be constructed and integratedly wired to form the complex circuits of modern microelectronic devices.

[0016] Semiconductor lithography forms a three-dimensional relief image or pattern on a semiconductor substrate and then transfers the pattern to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called photoresist. To construct the complex structures that make up transistors and the numerous interconnects that connect millions of transistors in a circuit, the lithography and etching / pattern transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned to previously formed patterns, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0017] Turning now to an overview of the technology particularly relevant to aspects of the present invention, embedded DRAM (eDRAM) is a dynamic random access memory (DRAM) integrated on the same die or multi-chip module (MCM) as an application specific integrated circuit (ASIC) or microprocessor. eDRAM is implemented using silicon-on-insulator (SOI) technology, which refers to the use of a layered silicon-insulator-silicon substrate instead of a conventional silicon substrate in semiconductor manufacturing. eDRAM technology has had varying degrees of success, and the demand for SOI technology as a server memory option has been decreasing in recent years.

[0018] Magnetoresistive random access memory (MRAM) devices using magnetic tunnel junctions (MTJs) are one option to replace existing eDRAM technology. MRAM is a non-volatile memory, and this advantage has been the driving force behind the development of this memory technology. Current MRAM MTJ structures are relatively slow, and the only way to reach the write target speed of a MJT comparable to eDRAM (~5 ns) is to use a double magnetic tunnel junction (DMTJ).

[0019] In certain DMTJ devices, the switching characteristics of the MTJ are improved by using a wide non-magnetic base modified DMTJ device to eliminate both the resistance area (RA) penalty and the magnetic resistance (MR) penalty associated with both the top MTJ and the bottom MTJ having similar critical dimensions (CD). These types of wide-base devices offer the advantages of double spin current supply (DSTT). Also, in these types of devices, the bottom barrier layer can have a relatively high RA. Some of these devices utilize spin diffusion transport within a non-magnetic (NM) metal layer provided between two MTJ stacks to achieve a reduction in the charge current density through the bottom MgO layer. However, in some of these wide-base DMTJ devices, each of the MTJ stacks includes a reference layer. The combination of two separate reference layers and an intermediate NM layer results in a taller DMTJ stack, increasing the complexity of the manufacturing process and allowing for electrical short circuits across the barrier.

[0020] This embodiment includes a DMTJ structure in which one of the MTJ stacks has a wider base than the other, and a method of manufacturing the DMTJ structure. In some of these embodiments, the MRAM device includes a DMTJ structure having an inverted structure (i.e., the top MTJ stack has a larger critical dimension (CD) than the bottom MTJ stack).

[0021] Here, referring to the drawings in which like reference numerals indicate like or similar elements, and first referring to the drawing shown in FIG. 1, an exemplary method of manufacturing a DMTJ stack to which the present embodiment can be applied is shown. Several back - end - of - line (BEOL) layers are formed. Generally, BEOL is the second part of IC manufacturing where individual devices (transistors, capacitors, resistors, etc.) are interconnected by wiring on a wafer. As shown in FIG. 1, the first BEOL layer includes a BEOL metal layer 102 and a BEOL dielectric layer 100. The BEOL metal layer 102 can include, for example, Cu, TaN, Ta, Ti, TiN, or a combination thereof. The BEOL dielectric layer 100 is formed laterally to the BEOL metal layer 102. The BEOL dielectric layer 100 can include, for example, SiO x , SiN x , SiBCN, low - k, NBLOK, or any other suitable dielectric material.

[0022] The other BEOL layers are formed on top of the BEOL metal layer 102 and the BEOL dielectric layer 100. In particular, a via fill layer 104 is formed on the BEOL metal layer 102, and a via dielectric layer 106 is formed laterally to the via fill layer 104. First, the via dielectric layer 106 can be formed by patterning through lithography. Next, vias are formed in the via dielectric layer 106, for example, by RIE, and the space for filling the via fill layer 104 is removed later. In an embodiment, the via fill layer 104 includes materials such as W, Cu, TaN, Ta, Ti, TiN, TiOCN, TaOCN, or a combination of these materials. The via fill layer 104 can be formed by CVD, PVD, ALD, or a combination thereof. After the via fill layer 104 is formed, the structure is planarized, for example, by CMP, for further processing. The structure including the BEOL layers shown in FIG. 1 is the first structure in which the MTJ stack is formed.

[0023] Referring now to FIG. 2, a seed layer 202 is formed over the via dielectric layer 106. The seed layer 202 has a crystal lattice and a granular structure suitable as a growth surface for the free layer of the first MTJ stack 204. The seed layer 202 can be, for example, a metal seed layer including Ru, Ta, NiCr, or a combination of these materials.

[0024] Referring again to FIG. 2, a first MTJ stack 204 is formed over the seed layer. Generally, an MTJ stack can include a magnetic free layer, a tunnel barrier layer, and a reference layer (not shown). Generally, the magnetic free layer has a magnetic moment or magnetization that can be reversed. In certain embodiments, the tunnel barrier layer is a barrier between two electrically conductive layers, such as a thin insulating layer or an electrical potential. Electrons (or quasiparticles) pass through the tunnel barrier by a process of quantum tunneling. In certain embodiments, the tunnel barrier layer includes at least one sublayer composed of MgO. In certain embodiments, each layer of the MTJ stack can have a thickness of less than 1 angstrom to several angstroms or several nanometers. Examples of typical materials within the MTJ stack can include MgO for the tunnel barrier layer, CoFeB for the free layer, and multiple layers including different materials for the reference layer. It should be understood that the MRAM material stack (MTJ stack) is not limited to these materials or the layers described above. That is, the MRAM material stack can be composed of a stack of any known materials used in an MRAM device. Further, it should be understood that either the first MTJ stack 204 or the second MTJ stack 704 (see FIG. 7) can include additional layers, certain layers can be omitted, and each layer can include any number of sublayers. Further, the composition of a layer or sublayer or a combination thereof can be different between the first MTJ stack 204 and the second MTJ stack 704 (see FIG. 7).

[0025] As shown in FIG. 2, a non-magnetic spin conduction layer 206 is formed on the first MTJ stack 204. The spin conduction layer 206 is formed between the first MTJ stack 204 and the second MTJ stack 704 (see FIG. 7), and in one example, may include Cu, CuN, Ag, AgSn, or combinations thereof. Generally, the function of the spin conduction layer 206 is to collect spin current from the tunnel barrier layer of the first MTJ stack 204.

[0026] Here, referring to FIG. 3, a sacrificial dielectric / organic hard mask stack 302 is deposited on the spin conduction layer 206, and subsequently the hard mask stack 302 is patterned by lithography and RIE. In certain embodiments, the hard mask stack 302 comprises an organic planarization layer (OPL) material, SiN x , SiO x , photoresist, or combinations thereof.

[0027] Here, referring to FIG. 4, the first MTJ stack 204 is patterned by IBE or RIE while utilizing the sacrificial dielectric / organic hard mask stack 302 for the pattern. As shown in FIG. 4, the etching stops inside (or near the top) of the via dielectric layer 106. Thus, after the etching procedure, the widths of the spin conduction layer 206, the first MTJ stack 204, and the seed layer 202 are reduced. In certain embodiments, an air break may be used at this stage of the manufacturing process (i.e., after the formation of the spin conduction layer 206). In certain embodiments, controlled in-situ oxidation can be utilized to remove partial electrical short circuits due to metal redeposition.

[0028] Referring now to FIG. 5, a first dielectric layer 502 is deposited. This first dielectric layer 502 can be composed of SiN, SiBCN, combinations thereof, or any other suitable dielectric material. As shown in FIG. 5, the first dielectric layer 502 is deposited to a height sufficient to at least cover the sidewalls of the spin conduction layer 206, the first MTJ stack 204, and the seed layer 202. In certain embodiments, the first dielectric layer 502 is first formed up to the level of the top surface of the sacrificial dielectric / organic hard mask stack 302.

[0029] Referring now to FIG. 6, CMP is performed on the device to remove a portion of the thickness of the most recently deposited first dielectric layer 502. The CMP is performed until the point where the sacrificial dielectric / organic hard mask stack 302 is removed, generally corresponding to the top surface of the spin conduction layer 206. That is, sufficient material is removed to expose the top surface of the spin conduction layer 206.

[0030] Referring now to FIG. 7, the growth of the spin conduction layer 206 is continued until it first covers the entire surface of the device. Although the spin conduction layer 206 is shown as a single layer, it should be understood that it is grown in two separate steps. Thus, the material of the upper portion of the spin conduction layer 206 may be the same as or different from the material of the lower portion of the spin conduction layer 206. In certain embodiments, prior to the formation of the upper portion of the spin conduction layer 206, after the CMP described above with respect to FIG. 6, pre-sputter cleaning may be performed to remove any native oxide. Next, a second MTJ stack 704 is formed on top of the spin conduction layer 206. The number and type of the second MTJ stack 704 may be the same as or different from the layers within the first MTJ stack 204. Next, a metal etch stop layer 706 is formed on the second MTJ stack 704. The metal etch stop layer 706 is composed of Ru or any other suitable metal or alloy. Next, a top electrode metal hard mask layer 708 is formed on the metal etch stop layer 706. The top electrode metal hard mask layer 708 is composed of W, TaN, TiN, combinations thereof, or any other suitable material. Next, a second sacrificial dielectric / organic hard mask stack 710 is formed on the top electrode metal hard mask layer 708. The second sacrificial dielectric / organic hard mask stack 710 may be formed of the same or different materials (e.g., OPL, SiN x , SiO x , photoresist, etc.) as the first sacrificial dielectric / organic hard mask stack 302 described above with respect to FIG. 3. Finally, as shown in FIG. 7, the top electrode metal hard mask layer 708 and the second sacrificial dielectric / organic hard mask stack 710 are patterned by lithography and RIE such that the width of these layers is wider than the width of the previously formed first MTJ stack 204.

[0031] Referring now to FIG. 8, the second MTJ stack 704 is patterned by IBE, RIE, or a combination thereof using the second sacrificial dielectric / organic hard mask stack 710 as a mask. Accordingly, the width of the second MTJ stack 704 and the width of the upper portion of the spin conduction layer 206 are reduced to be approximately the same as the width of the second sacrificial dielectric / organic hard mask stack 710. As shown in FIG. 8, the device is etched to a level inside (e.g., near the top) of the first dielectric layer 502. Even after this removal step, the width of the second MTJ stack 704 is still larger than the width of the first MTJ stack 204. In some embodiments, an air break can be used at this stage of the manufacturing process. In some embodiments, controlled in-situ oxidation can be utilized to remove partial electrical shorting due to re-deposition of metal near the MgO tunnel barrier layer (not shown) of the second MTJ stack 704.

[0032] Referring now to FIG. 9, a dielectric capping layer 902 is formed to cover the exposed surfaces of the spin conduction layer 206, the second MTJ stack 704, the metal etch stop layer 706, and the top electrode metal hard mask layer 807. For example, the dielectric capping layer 902 can include at least one of AlO x , TiO x , BN, SiN, and SiBCN. In some embodiments, following the formation of the dielectric capping layer 902, the device can undergo any pre-treatment using, for example, plasma O2, H2, N2, NH3, or a combination thereof. Thereafter, an interlayer dielectric layer 904 is deposited and formed to fill the space between adjacent DMTJ devices.

[0033] Referring now to FIG. 10, a CMP planarization process is performed on the device, exposing the upper surfaces of the top electrode metal hard mask layer 708 and the dielectric encapsulation layer 902. Referring now to FIG. 11, following the CMP planarization process, a second ILD layer 1100 is formed by lithography. Referring to FIG. 12, the second ILD layer 1100 is subjected to a removal process (e.g., RIE) to remove a portion of the second ILD layer 1100 in order to once again expose a portion of the top electrode metal hard mask layer 708 and the dielectric encapsulation layer 902. Referring now to FIG. 13, following the RIE process of FIG. 12, a fill liner 1202 is formed, followed by the formation of the bit line 1402 shown in FIG. 14. In certain embodiments, the bit line is composed of Ta, TaN, Cu, or any suitable combination thereof.

[0034] In this embodiment, the DMTJ device can achieve an improvement in switching efficiency (which is proportional to the holding force and inversely proportional to the switching current) compared to the associated single MTJ device. Further, this embodiment can achieve an increased magnetoresistivity that potentially reduces the switching current.

[0035] The descriptions of the various embodiments have been presented for purposes of illustration, and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or a technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method of manufacturing a dual magnetic tunnel junction device, the method comprising: forming a first magnetic tunnel junction stack; forming a spin conduction layer on the first magnetic tunnel junction stack; and forming a second magnetic tunnel junction stack on the spin conduction layer, the second magnetic tunnel junction stack having a width greater than the width of the first magnetic tunnel junction stack. Method.

2. The method according to claim 1, wherein the first magnetic tunnel junction stack is formed on a back end of line layer.

3. The first magnetic tunnel junction stack includes a first reference layer, a first tunnel barrier layer, and a first magnetic free layer. The second magnetic tunnel junction stack includes a second reference layer, a second tunnel barrier layer, and a second magnetic free layer. The method according to claim 1.

4. After forming the spin conduction layer, the method further includes: forming a first dielectric layer on sides of the first magnetic tunnel junction stack and on sides of the spin conduction layer; and forming a second spin conduction layer on the spin conduction layer, the second spin conduction layer having a width greater than the width of the spin conduction layer and greater than the width of the first magnetic tunnel junction stack. The method according to claim 1.

5. The method according to claim 4, wherein the second spin conduction layer is formed in direct contact with the spin conduction layer and has the same material composition as the spin conduction layer.

6. After forming the spin conduction layer, the method further includes: forming the first dielectric layer on the sides of the first magnetic tunnel junction stack and on the sides of the spin conduction layer; forming a second spin conduction layer on the spin conduction layer and on the first dielectric layer; forming the second magnetic tunnel junction stack on the second spin conduction layer; forming a metal etch stop layer on the second magnetic tunnel junction stack; forming a metal hard mask layer on the metal etch stop layer; and further etching a part of the film thicknesses of the metal etch stop layer, the second magnetic tunnel junction stack, the second spin conduction layer, and the first dielectric layer. The second spin conduction layer has the same width as the second magnetic tunnel junction stack. The method according to claim 4.

7. The method according to claim 4, further comprising performing a cleaning process on the exposed surface before forming the second spin conduction layer.

8. The method according to claim 1, wherein the spin conduction layer comprises at least one non-magnetic material selected from the group consisting of Cu, CuN, Ag, and AgSn.

9. The method according to claim 1, further comprising forming a dielectric encapsulation layer on the second magnetic tunnel junction stack.

10. The dielectric encapsulation layer is AlO ｘ , TiO ｘ , BN, SiN, and at least one selected from the group consisting of SiBCN, the method according to claim 9.

11. A first magnetic tunnel junction stack, a first dielectric layer on the side of the first magnetic tunnel junction stack, a spin conduction layer on at least a part of the top of the first magnetic tunnel junction stack and on the top surface of the first dielectric layer, and a second magnetic tunnel junction stack on the spin conduction layer, wherein the second magnetic tunnel junction stack has a width larger than the width of the first magnetic tunnel junction stack, A dual magnetic tunnel junction device.

12. The dual magnetic tunnel junction device according to claim 11, wherein the first magnetic tunnel junction stack is on a backend-of-line layer.

13. The first magnetic tunnel junction stack includes a first reference layer, a first tunnel barrier layer, and a first magnetic free layer, The second magnetic tunnel junction stack includes a second reference layer, a second tunnel barrier layer, and a second magnetic free layer, The dual magnetic tunnel junction device according to claim 11.

14. The dual magnetic tunnel junction device according to claim 11, wherein the spin conduction layer comprises at least one non-magnetic material selected from the group consisting of Cu, CuN, Ag, and AgSn.

15. A first magnetic tunnel junction stack on a backend-of-line layer, a spin conduction layer on the first magnetic tunnel junction stack, and a second magnetic tunnel junction stack on the spin conduction layer, wherein the second magnetic tunnel junction stack has a width larger than the width of the first magnetic tunnel junction stack, and a seed layer is between the backend-of-line layer and the first magnetic tunnel junction stack, and a first dielectric layer on the side of the first magnetic tunnel junction stack, on the side of the spin conduction layer, and on the side of the seed layer, the dual magnetic tunnel junction device further comprising.

16. A first magnetic tunnel junction stack, The spin conduction layer on the first magnetic tunnel junction stack, The second magnetic tunnel junction stack on the spin conduction layer, The first dielectric layer on the side of the first magnetic tunnel junction stack and on the side of the spin conduction layer, and The second spin conduction layer on the spin conduction layer A dual magnetic tunnel junction device, including, wherein the second magnetic tunnel junction stack has a width greater than the width of the first magnetic tunnel junction stack, and the second spin conduction layer has a width greater than the width of the spin conduction layer and greater than the width of the first magnetic tunnel junction stack.

17. The dual magnetic tunnel junction device according to claim 16, wherein the second spin conduction layer is in direct contact with the spin conduction layer and the second spin conduction layer has the same material composition as the spin conduction layer.

18. The first dielectric layer on the side of the first magnetic tunnel junction stack and on the side of the spin conduction layer, The second spin conduction layer on the spin conduction layer, The second magnetic tunnel junction stack formed on the second spin conduction layer, The metal etching stop layer on the second magnetic tunnel junction stack, and Further including a metal hard mask layer on the metal etching stop layer, The second spin conduction layer has the same width as the second magnetic tunnel junction stack, The dual magnetic tunnel junction device according to claim 16.

19. The first magnetic tunnel junction stack, The spin conduction layer on the first magnetic tunnel junction stack, The first dielectric layer on the side of the first magnetic tunnel junction stack and on the side of the spin conduction layer, The second magnetic tunnel junction stack on the spin conduction layer, and The dielectric encapsulation layer on the second magnetic tunnel junction stack A dual magnetic tunnel junction device, including, wherein the second magnetic tunnel junction stack has a width greater than the width of the first magnetic tunnel junction stack.

20. The dielectric encapsulation layer is AlO ｘ , TiO ｘ , the double magnetic tunnel junction device according to claim 19, comprising at least one selected from the group consisting of BN, SiN, and SiBCN.

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