Transistor and Semiconductor Device

Abstract

a first insulating film located between the first electrode and the third electrode and / or the second electrode and the third electrode; and a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, wherein the crystalline oxide semiconductor includes a first region adjacent to but not in contact with the third electrode, and a second region adjacent to but in contact with the first insulating film, wherein the second region has a relatively higher average carrier concentration than the first region.

Description

Technical Field

[0001] The present invention relates to a transistor and a semiconductor device. Specifically, the present invention relates to a transistor and a semiconductor device capable of improving contact resistance.

Background Art

[0002] Transistors having an amorphous oxide semiconductor layer such as indium gallium zinc oxide (IGZO) as a channel are known (Patent Documents 1 and 2). When such an oxide semiconductor layer is used as a channel, a high-resistance metal oxide layer may be formed between the oxide semiconductor layer and the metal electrode, increasing the contact resistance between the oxide semiconductor layer and the metal electrode. In order to suppress the increase in contact resistance, Patent Documents 1 and 2 propose interposing a specific oxide layer between the oxide semiconductor layer and the metal electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

[0004] However, in conventional technologies including Patent Documents 1 and 2, there is still room for further improvement from the viewpoint of improving contact resistance in transistors.

[0005] One object of the present invention is to provide a transistor and a semiconductor device capable of improving contact resistance.

Means for Solving the Problems

[0006] As a result of intensive studies, the inventors of the present invention have found that by using a crystalline oxide semiconductor as the oxide semiconductor and selectively increasing the average carrier concentration in a region that is likely to cause contact resistance in the oxide semiconductor, the above problems can be solved, and the present invention has been completed. According to the present invention, the following transistors and the like can be provided. 1. A first electrode, A second electrode, A third electrode located between the first electrode and the second electrode, A first insulating film located between the first electrode and the third electrode and / or between the second electrode and the third electrode, A crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, Comprising: The crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact and a second region adjacent to the first insulating film with or without contact, The average carrier concentration in the second region is relatively higher than that in the first region, Transistor. 2. The crystalline oxide semiconductor is provided in a columnar shape penetrating the first insulating film and the third electrode, The first region is a region that penetrates the third electrode in the crystalline oxide semiconductor, The second region is a region that penetrates the first insulating film in the crystalline oxide semiconductor, The transistor according to 1. 3. The first electrode, the first insulating film, the third electrode, the first insulating film, and the second electrode are laminated in this order, The crystalline oxide semiconductor is provided in a columnar shape penetrating the first insulating film and the third electrode, The first region is a region that penetrates the third electrode in the crystalline oxide semiconductor, The second region is a region that penetrates the first insulating film in the crystalline oxide semiconductor, The transistor according to 1. 4. 4. The transistor according to 2 or 3, wherein the columnar crystalline oxide semiconductor has a length in the height direction of 2 to 1000 nm. 5. In the columnar crystalline oxide semiconductor, The ratio of the height of the first region to the height of the second region is 10:1 to 1:1. 5. The transistor according to any one of 2 to 4. 6. the composition ratio of metal elements constituting the crystalline oxide semiconductor is substantially the same in the first region and the second region; 6. The transistor according to any one of 1 to 5. 7. the first region includes a highly crystallized region having a relatively high degree of crystallinity compared to the crystalline oxide semiconductor of the second region; 7. The transistor according to claim 6. 8. In each FFT pattern obtained by fast Fourier transforming an image obtained by irradiating an electron beam onto the same area of each of the first region and the second region, a variation X of the FFT pattern calculated by the following formula is larger in the second region than in the first region, 8. The transistor according to claim 7. X = [Σ(luminance - average luminance in FFT domain)] 2 ] / number of samples (In the above formula, the FFT region is the region of the FFT pattern obtained by fast Fourier transforming the image, the brightness is the brightness of each spot in the FFT region, and the number of samples is the number of times the electron beam was irradiated to obtain the image.) 9. the crystal orientation in an electron diffraction pattern obtained by irradiating the crystalline oxide semiconductor with an electron beam includes a cubic crystal structure of indium oxide and is composed of at least one or more planes of (211), (222), (400), (440), and (622); 9. The transistor according to claim 8. 10. The average hydrogen concentration in the second region is relatively high compared to the first region. The transistor according to any one of 1 to 9. 11. The transistor according to any one of 1 to 10, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N). 12. The transistor according to any one of 1 to 10, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), titanium (Ti), and titanium nitride (TiN). 13. The transistor according to any one of 1 to 12, further comprising a second insulating film provided between the third electrode and the crystalline oxide semiconductor. 14. The ratio of the average carrier concentration of the second region to the average carrier concentration of the first region (average carrier concentration of the second region / average carrier concentration of the first region) is 2 to 10 4 The transistor according to any one of 1 to 13. 15. The ratio of the average carrier concentration of the second region to the average carrier concentration of the first region (average carrier concentration of the second region / average carrier concentration of the first region) is 10 to 10 4 The transistor according to 14. 16. The average carrier concentration in the first region is 10 14 ~10 18 cm-3 and the average carrier concentration in the second region is 10 17 ~10 22 cm -3 is the transistor according to any one of 1 to 15. 17. The ratio of the average hydrogen concentration in the second region to the average hydrogen concentration in the first region (average hydrogen concentration in the second region / average hydrogen concentration in the first region) is 5 to 5×10 3 is the transistor according to any one of 1 to 16. 18. the transistor according to any one of 1 to 17, wherein the crystalline oxide semiconductor includes a Bixbyite crystal structure. 19. the transistor according to any one of 1 to 18, wherein the crystalline oxide semiconductor contains indium oxide as a main component. 20. the transistor according to any one of 1 to 19, wherein the crystalline oxide semiconductor contains Ga or Al. 21. the transistor according to any one of 1 to 19, wherein the crystalline oxide semiconductor contains Ga. 22. the transistor according to any one of 1 to 19, wherein the crystalline oxide semiconductor contains Ga and Al. 23. the transistor according to any one of 1 to 22, wherein the crystalline oxide semiconductor is a polycrystalline oxide semiconductor. 24. the transistor according to any one of 1 to 22, wherein the crystalline oxide semiconductor is a single crystal oxide semiconductor. 25. the transistor according to any one of 1 to 24, wherein the crystalline oxide semiconductor is a crystalline oxide semiconductor formed by an atomic layer deposition method. 26. A semiconductor device including the transistor according to any one of 1 to 25. 27. The semiconductor device according to 26, which is a semiconductor memory device. 28. a first electrode, a second electrode, a third electrode positioned between the first electrode and the second electrode, a first insulating film positioned between the first electrode and the third electrode and / or between the second electrode and the third electrode, a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, and comprising: the crystalline oxide semiconductor includes a bicrystal structure, the crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact and a second region adjacent to the first insulating film with or without contact, the average carrier concentration in the second region is relatively higher than that in the first region, in the first region and the second region, the composition ratio of the metal elements constituting the crystalline oxide semiconductor is substantially the same, the first region includes a highly crystallized region having a relatively high crystallinity compared to the crystalline oxide semiconductor of the second region, in each FFT pattern obtained by performing a fast Fourier transform on an image obtained by irradiating the same area of each of the first region and the second region with an electron beam, the variation X of the FFT pattern calculated by the following formula is greater in the second region than in the first region, X = 1 / number of samplings × Σ (luminance - average value of luminance in the FFT region) 2 (However, in the above formula, the FFT region is the region of the FFT pattern obtained by performing a fast Fourier transform on the image, the luminance is the luminance of each spot in the FFT region, and the number of samplings is the number of irradiations of the electron beam irradiated to obtain the image.) a transistor. 29. a first electrode, a second electrode, a third electrode positioned between the first electrode and the second electrode, A first insulating film positioned between the first electrode and the third electrode and / or between the second electrode and the third electrode, a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, is provided, the crystalline oxide semiconductor includes a perovskite crystal structure, the crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact and a second region adjacent to the first insulating film with or without contact, compared with the first region, the average carrier concentration in the second region is relatively high, compared with the first region, the average hydrogen concentration in the second region is relatively high, at least one of the first electrode and the second electrode is at least one selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), titanium (Ti), and titanium nitride (TiN), a transistor.

[0007] According to the present invention, a transistor and a semiconductor device capable of improving contact resistance can be provided.

Brief Description of Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Embodiments for Carrying Out the Invention

[0009] Hereinafter, the transistor and the semiconductor device of the present invention will be described in detail. In the present specification, "x to y" represents a numerical range of "x or more and y or less". The upper limit value and the lower limit value described for the numerical range can be arbitrarily combined. In addition, among the individual embodiments of the aspects according to the present invention described below, those that are not mutually contradictory can be combined in two or more, and an embodiment obtained by combining two or more embodiments is also an embodiment of the aspect according to the present invention.

[0010] 1. Transistor A transistor according to one aspect of the present invention is a first electrode, a second electrode, a third electrode positioned between the first electrode and the second electrode, a first insulating film positioned between the first electrode and the third electrode and / or between the second electrode and the third electrode, a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, and includes: the crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact and a second region adjacent to the first insulating film with or without contact, and the average carrier concentration in the second region is relatively higher than that in the first region. According to the transistor of this aspect, an effect of improving contact resistance can be obtained. In the crystalline oxide semiconductor, the second region is farther from the third electrode that functions as a gate electrode than the first region. Therefore, even when a gate voltage is applied to the third electrode, carriers are not easily induced in the second region inherently, and contact resistance is likely to occur. However, as described above, since the average carrier concentration in the second region is higher than that in the first region, an increase in contact resistance in the second region is prevented, and the contact resistance of the transistor can be improved. During the manufacture of the transistor, by utilizing the properties of the crystalline oxide semiconductor (the property of crystallization) to perform post-annealing under specific conditions or relatively increase the average hydrogen concentration in the second region, the average carrier concentration in the second region can be increased compared to the first region and this state can be maintained. As a comparison, when an amorphous oxide semiconductor such as IGZO is used as the semiconductor, since the semiconductor is not crystalline, it is presumed that the above-described conditions for the average carrier concentration cannot be satisfied and the improvement in contact resistance as described above does not occur.

[0011] Hereinafter, with reference to FIGS. 1 and 2, an example (first embodiment) of the transistor according to this aspect will be described. FIG. 1 is a schematic perspective view showing a cross-section of the transistor according to the first embodiment. FIG. 2 is a schematic cross-sectional view of the transistor. In this embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, first insulating films 14a and 14b, and a crystalline oxide semiconductor 15. The third electrode 13 is located between the first electrode 11 and the second electrode 12.

[0012] Of the first insulating films 14a and 14b, one of the first insulating films 14a is located between the first electrode 11 and the third electrode 13. Thereby, the first electrode 11 and the third electrode 13 are electrically insulated by the first insulating film 14a. Also, the other first insulating film 14b is located between the second electrode 12 and the third electrode 13. Thereby, the second electrode 12 and the third electrode 13 are electrically insulated by the first insulating film 14b.

[0013] Note that, in the region shown in FIG. 2, the third electrode 13 is disposed between the first insulating film 14a and the first insulating film 14b. However, outside the region shown in FIG. 2, the first insulating film 14a and the first insulating film 14b may be in contact with each other to form one layer. In this case, in the region, the third electrode 13 does not have to be disposed between the first insulating film 14a and the first insulating film 14b.

[0014] The crystalline oxide semiconductor 15 is provided so as to penetrate at least the first insulating films 14a and 14b and connect the first electrode 11 and the second electrode 12. The crystalline oxide semiconductor 15 may penetrate the third electrode 13 in addition to the first insulating film 14a and the first insulating film 14b. Here, the crystalline oxide semiconductor 15 is provided in a columnar shape penetrating the first insulating film 14a, the third electrode 13, and the first insulating film 14b in this order. In this case, the third electrode 13 preferably surrounds the side of the crystalline oxide semiconductor 15 (the periphery in the direction perpendicular to the length direction) over the entire circumference at a part in the length direction of the crystalline oxide semiconductor 15 (the central part in the example of FIG. 2) via the second insulating film 16 described later. Thereby, even if the channel length of the crystalline oxide semiconductor 15 described later becomes short, it becomes easy to prevent leakage current. At the same time, it is also advantageous in terms of miniaturization. Note that the length direction of the crystalline oxide semiconductor 15 here may be the vertical direction in FIG. 2 (the direction connecting the first electrode and the second electrode), may be the direction along the channel length described later, may be the thickness direction of the laminate in which the first insulating film 14a, the third electrode 13, and the first insulating film 14b are laminated in this order, and may be the height direction of the columnar structure when the crystalline oxide semiconductor 15 is columnar.

[0015] The transistor 10 further includes a second insulating film 16 provided between at least the third electrode 13 and the crystalline oxide semiconductor 15. By providing the second insulating film 16 between the third electrode 13 and the crystalline oxide semiconductor 15, the third electrode 13 and the crystalline oxide semiconductor 15 may be insulated. The second insulating film 16 may be provided, for example, also between the first insulating films 14a and 14b and the crystalline oxide semiconductor 15 in addition to between the third electrode 13 and the crystalline oxide semiconductor 15. Here, the second insulating film 16 is provided so as to surround the side surface of the columnar crystalline oxide semiconductor 15 over the entire circumference.

[0016] In one aspect, the transistor 10 has a through hole that penetrates a laminate in which a first insulating film 14a, a third electrode 13, and a first insulating film 14b are laminated in this order in the thickness direction of the laminate (the vertical direction in FIGS. 1 and 2), and the inner peripheral surface of the through hole is covered with a cylindrical second insulating film 16, and it can also be said that the inside of the cylindrical second insulating film 16 is filled with a crystalline oxide semiconductor 15.

[0017] The dimensions of the transistor 10 may be appropriately designed according to its use and the like. The channel length of the crystalline oxide semiconductor 15 is, for example, 1 nm to 10 μm, preferably 2 to 1000 nm, more preferably 3 to 100 nm, still more preferably 4 to 50 nm, still more preferably 5 to 30 nm, and still more preferably 6 to 20 nm. Incidentally, the channel length of the crystalline oxide semiconductor 15 is the length of the crystalline oxide semiconductor 15 along the thickness direction of the laminate (the vertical direction in FIGS. 1 and 2) in which the first insulating film 14a, the third electrode 13, and the first insulating film 14b are laminated in this order, and may coincide with the distance between the first electrode 11 and the second electrode 12. When the crystalline oxide semiconductor 15 is columnar, the channel length of the crystalline oxide semiconductor 15 corresponds to the length in the height direction of the columnar structure. The channel length of the crystalline oxide semiconductor 15 may be measured by processing the corresponding portion with a focused ion beam (FIB) to expose it and observing the cross section with a transmission electron microscope (TEM).

[0018] The channel width of the crystalline oxide semiconductor 15 is, for example, 1 nm or more and 1000 nm or less, preferably 2 nm or more and 500 nm or less. Note that the channel width of the crystalline oxide semiconductor 15 is the length of the crystalline oxide semiconductor 15 along a direction perpendicular to the thickness direction of the laminate in which the first insulating film 14a, the third electrode 13, and the first insulating film 14b are laminated in this order (for example, the left-right direction in FIG. 2). As shown in FIGS. 1 and 2, when the channel width of the crystalline oxide semiconductor 15 is not constant with respect to the channel length direction, the channel width of the crystalline oxide semiconductor 15 may be the average width along the channel length direction. The average width along the channel length direction is the average value when the channel width is measured at 10 or more positions along the channel length direction. When the crystalline oxide semiconductor 15 has a columnar shape, the channel width of the crystalline oxide semiconductor 15 corresponds to the lateral width of the columnar structure. Note that when the channel width of the crystalline oxide semiconductor 15 varies depending on the observation direction (for example, when the channel width is different between the case of observing from a direction perpendicular to the plane of FIG. 2 and the case of observing from the left-right direction in FIG. 2), the channel width when observed from at least one direction may be within the above range.

[0019] The thickness of the second insulating film 16 is, for example, 1 Å or more and 500 nm or less, preferably 1 nm or more and 100 nm or less. In order to suppress the capacitance of the second insulating film 16 from becoming a parasitic component, the thickness of the second insulating film 16 may be 50 nm or less, 10 nm or less, or 2 nm or less. The channel width of the crystalline oxide semiconductor 15 and the thickness of the second insulating film 16 may be measured in the same manner as the channel length.

[0020] In the transistor 10, the first electrode 11 can function as a source electrode, and the second electrode 12 can function as a drain electrode. In another example, the first electrode 11 can function as a drain electrode, and the second electrode 12 can function as a source electrode. The third electrode 13 can function as a gate electrode. The crystalline oxide semiconductor 15 can function as the channel (current path) of the transistor 10. For example, when a gate voltage is applied to the third electrode 13 which is the gate electrode, the first electrode 11 and the second electrode 12 are electrically connected by the crystalline oxide semiconductor 15, and the transistor 10 is in the ON state. Also, when no gate voltage is applied, the electrical connection between the first electrode 11 and the second electrode 12 by the crystalline oxide semiconductor 15 is released, and the transistor 10 is in the OFF state.

[0021] In addition, in this specification etc., "electrically connected" includes the case of being connected via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transmission and reception of electrical signals between the connection targets.

[0022] In the transistor 10, the crystalline oxide semiconductor 15 is provided so as to connect the first electrode 11 and the second electrode 12. "Provided so as to connect the first electrode 11 and the second electrode 12" means being provided in a state where the first electrode 11 and the second electrode 12 can be electrically connected. Therefore, the crystalline oxide semiconductor 15 does not necessarily physically contact the first electrode 11 and the second electrode 12. For example, a conductive material may be provided between the crystalline oxide semiconductor 15 and the first electrode 11 and / or the second electrode 12.

[0023] The crystalline oxide semiconductor 15 may be a crystalline oxide that can function as a semiconductor. Specifically, metal oxides can be mentioned. Examples of the metal contained in the metal oxide include In, Ga, Zn, Al, Sn, etc. Specific examples of the metal oxide include indium oxide (IO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium aluminum oxide (IGAO), indium gallium tin zinc oxide (IGTZO), indium tin zinc oxide (ITZO), etc.

[0024] In one embodiment, the crystalline oxide semiconductor 15 contains indium atoms (In). In one embodiment, the ratio of indium atoms to all metal atoms contained in the crystalline oxide semiconductor 15 is 80 atomic % or more, 90 atomic % or more, or 95 atomic % or more. Incidentally, the content (atomic ratio) of each metal element in the crystalline oxide semiconductor 15 can be analyzed by TEM-EDS (Energy Dispersive X-ray Spectroscopy) measurement using an electron microscope.

[0025] In one embodiment, the crystalline oxide semiconductor 15 contains indium oxide as a main component. "Containing indium oxide as a main component" means that more than 50 mass % of the material constituting the crystalline oxide semiconductor is indium oxide.

[0026] In one embodiment, the crystalline oxide semiconductor 15 contains indium oxide (IO), indium gallium oxide (IGO), or indium gallium aluminum oxide (IGAO). In one embodiment, the content of indium oxide in the crystalline oxide semiconductor 15 may be 55 mass % or more, 60 mass % or more, 70 mass % or more, 80 mass % or more, 90 mass % or more, 95 mass % or more, 97 mass % or more, 98 mass % or more, or 99 mass %, or may be 100 mass %.

[0027] In one embodiment, the crystalline oxide semiconductor 15 further contains a trivalent metal. As the trivalent metal, Ga and Al are preferable, and Ga is more preferable. In one embodiment, the crystalline oxide semiconductor 15 further contains Ga or Al, may contain Ga, may contain Al, or may contain Ga and Al. In one embodiment, the atomic ratio of the trivalent metal to all metal elements contained in the crystalline oxide semiconductor 15 ([trivalent metal] / ([trivalent metal] + [all metal elements other than trivalent metal]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%. Here, "trivalent metal" may be read as Ga and Al. In one embodiment, the atomic ratio of Ga to all the metal elements contained in the crystalline oxide semiconductor 15 ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%. In one embodiment, the atomic ratio of Al to all the metal elements contained in the crystalline oxide semiconductor 15 ([Al] / ([Al] + [all metal elements other than Al]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%.

[0028] In one embodiment, the crystalline oxide semiconductor 15 further contains one or more additive elements selected from B, Si, Sc, Zn, Ce, Y, Zr, Sn, Sm, Hf, Ta, and Yb. In one embodiment, the atomic ratio of the total amount of the additive elements to all the metal elements contained in the crystalline oxide semiconductor 15 ([total amount of additive elements] / ([total amount of additive elements] + [all metal elements other than additive elements]) × 100) is 0 to 10 at%, and may be 0.1 to 8 at%, 0.5 to 5 at%, or 1 to 3 at%.

[0029] In one embodiment, the crystalline oxide semiconductor 15 includes a body-centered cubic crystal structure. The presence or absence of the body-centered cubic structure can be determined based on the X-ray diffraction pattern in X-ray diffraction (XRD) or the electron beam diffraction spots in electron beam diffraction. In one embodiment, the crystalline oxide semiconductor 15 includes an In2O3 phase having a body-centered cubic crystal structure.

[0030] In one embodiment, the crystalline oxide semiconductor 15 is a polycrystalline oxide semiconductor or a single-crystalline oxide semiconductor. In one embodiment, the crystalline oxide semiconductor 15 is a polycrystalline oxide semiconductor. In one embodiment, the crystalline oxide semiconductor 15 is a single-crystalline oxide semiconductor.

[0031] Here, whether a crystalline oxide semiconductor is a polycrystalline oxide semiconductor or a single-crystalline oxide semiconductor may be confirmed by, for example, electron backscatter diffraction (EBSD). When the crystal orientation measured by EBSD is uniform and no grain boundaries are confirmed, it may be determined to be a single-crystalline oxide semiconductor. When grain boundaries are confirmed, it may be determined to be a polycrystalline oxide semiconductor. When the difference in crystal orientation between two adjacent measurement points exceeds 5°, it may be defined that a grain boundary exists between them.

[0032] By configuring the crystalline oxide semiconductor 15 as described above, a selective increase in the average carrier concentration in the second regions 18a and 18b described below is effectively promoted, which tends to further improve the contact resistance of the transistor 10.

[0033] There are no particular limitations on the materials for the first electrode 11, the second electrode 12, and the third electrode 13 as long as they are conductive. Examples of conductive materials include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (NiN).

[0034] In one embodiment, at least one of the first electrode 11 and the second electrode 12 is at least one selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), titanium (Ti), and titanium nitride (TiN). These materials have the property of absorbing hydrogen, so by forming at least one of the first electrode 11 and the second electrode 12 using these materials while absorbing hydrogen, the hydrogen concentration in the second region can be selectively increased.

[0035] Each of the first insulating films 14a and 14b and the second insulating film 16 is not particularly limited as long as it is a film containing an insulator or made of an insulator. Examples of the insulator include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and the like. Further, each of the first insulating films 14a and 14b and the second insulating film 16 may be a laminated film of the above materials. Note that the insulating film may contain La, N, Zr, or the like. The insulators included in the first insulating films 14a and 14b and the second insulating film 16 may be the same as or different from each other.

[0036] As described above, according to the transistor of this embodiment, an effect of improving the contact resistance can be obtained. This will be described below with particular reference to FIG. 2.

[0037] As shown by the dotted line in FIG. 2, the crystalline oxide semiconductor 15 includes a first region 17 that is adjacent (proximate) to the third electrode 13 without contact and second regions 18a and 18b that are adjacent (proximate) to the first insulating films 14a and 14b without contact. In this example, the first region 17 can also be said to be a region defined corresponding to the formation range in the thickness direction (vertical direction in FIG. 2) of the third electrode 13. Further, the second regions 18a and 18b can also be said to be regions defined corresponding to the formation ranges in the thickness directions (vertical directions in FIG. 2) of the first insulating films 14a and 14b, respectively. In this example, the first region 17 is adjacent to the third electrode 13 with the second insulating film 16 interposed therebetween. Further, the second regions 18a and 18b are adjacent to the first insulating films 14a and 14b, respectively, with the second insulating film 16 interposed therebetween. In one aspect, the first region 17 of the crystalline oxide semiconductor 15 is a region closer to the third electrode 13 than the second regions 18a and 18b. Also, the second region 18a of the crystalline oxide semiconductor 15 is a region closer to the first insulating film 14a than the first region 17. Similarly, the second region 18b of the crystalline oxide semiconductor 15 is a region closer to the first insulating film 14b than the first region 17. Note that the second regions 18a and 18b do not necessarily have to be adjacent to the first insulating films 14a and 14b without contact, and in other embodiments, they may be adjacent to and in contact with the first insulating films 14a and 14b.

[0038] In the present embodiment, the crystalline oxide semiconductor 15 is provided in a columnar shape penetrating the first insulating film 14a, the third electrode 13, and the first insulating film 14b. Here, the first region 17 is a region penetrating the third electrode 13 in the crystalline oxide semiconductor 15. Also, the second region 18a is a region penetrating the first insulating film 14a in the crystalline oxide semiconductor 15. Similarly, the second region 18b is a region penetrating the first insulating film 14b in the crystalline oxide semiconductor 15. In one aspect, the first region 17 is a region surrounded laterally by the third electrode 13 in the crystalline oxide semiconductor 15. Also, the second region 18a is a region surrounded laterally by the first insulating film 14a in the crystalline oxide semiconductor 15. Similarly, the second region 18b is a region surrounded laterally by the first insulating film 14b in the crystalline oxide semiconductor 15.

[0039] In one embodiment, in the crystalline oxide semiconductor 15, the ratio of the height of the first region to the height of the second region is, for example, 10:1 to 1:1, preferably 8:1 to 1:1. The ratio of the first region to the second region of the crystalline oxide semiconductor 15 may be measured by processing and exposing the corresponding portion with a focused ion beam (FIB) and observing the cross-section with a transmission electron microscope (TEM). In one embodiment, the ratio of the thickness of the third electrode 13 along the crystalline oxide semiconductor 15 to the thickness of the first insulating film 14a and / or the thickness of the first insulating film 14b is, for example, 10:1 to 1:1 (thickness of the third electrode 13:thickness of the first insulating film 14a, thickness of the third electrode 13:thickness of the first insulating film 14b), and preferably 8:1 to 1:1.

[0040] It is preferable that the composition ratio of the metal elements constituting the crystalline oxide semiconductor 15 is substantially the same in the first region and the second region. The phrase "the composition ratio of the metal elements is the same" means that the types of metal elements constituting the crystalline oxide semiconductor are the same and the content ratios are also the same. Furthermore, the phrase "substantially" the same composition of metal elements means that the composition ratio of the metal elements is the same, excluding unavoidable impurities. It is preferable that the crystalline oxide semiconductor 15 is formed in the first region and the second region by a continuous process, and it is preferable that a process that changes the carrier concentration, such as ion implantation, is not carried out in only one of the regions.

[0041] In this embodiment, the crystalline oxide semiconductor 15 has a relatively higher average carrier concentration in the second region 18a than in the first region 17, and / or the crystalline oxide semiconductor 15 has a relatively higher average carrier concentration in the second region 18b than in the first region 17. This can improve the contact resistance of the transistor 10. That is, the second regions 18a and 18b are farther away from the third electrode 13, which functions as a gate electrode, than the first region 17. Therefore, even when a gate voltage is applied to the third electrode 13, carriers are inherently less likely to be induced in the second regions 18a and 18b, which makes them more likely to have contact resistance. However, as described above, by selectively increasing the average carrier concentration in the second regions 18a and 18b, the contact resistance in the second regions 18a and 18b is prevented from increasing, and the contact resistance of the transistor 10 can be improved. As will be described in detail later, during transistor manufacturing, the properties (crystallization properties) of crystalline oxide semiconductors can be utilized to perform post-annealing under specific conditions or to relatively increase the average hydrogen concentration in the second region, thereby increasing the average carrier concentration in the second region compared to the first region, and maintaining that state. In comparison, when an amorphous oxide semiconductor such as IGZO is used as the semiconductor, the semiconductor is not crystalline, and therefore the above-mentioned average carrier concentration condition cannot be satisfied, and it is presumed that the above-mentioned improvement in contact resistance does not occur.

[0042] The average carrier concentration is the average value of the carrier concentration in each region. When the crystalline oxide semiconductor 15 is an n-type semiconductor, the carrier concentration is the electron density. When the crystalline oxide semiconductor 15 is a p-type semiconductor, the carrier concentration is the hole density. The average carrier concentration can be measured and calculated by the following method. First, a cross section of the crystalline oxide semiconductor 15 is processed to have a flat observation surface with a roughness of 1 nm or less, and then immediately transferred to a high vacuum and measured using a scanning tunneling microscope. At this time, the tunneling current is measured by sweeping along the channel length direction of the crystalline oxide semiconductor 15, for example, through the second region 18a, the first region 17, and the second region 18b. This tunneling current can be quantified as a carrier concentration distribution using current imaging tunneling spectroscopy (CITS). The average carrier concentration in each region is calculated as the arithmetic mean of the measurements at five measurement points. That is, during measurement, each region is divided into five equal parts in the vertical direction (channel length direction), and each of these is used as a CITS measurement point. Furthermore, in the crystalline oxide semiconductor 15, the fact that the second region 18a has a relatively higher average carrier concentration than the first region 17, and that the second region 18b has a relatively higher average carrier concentration than the first region 17, can be determined by using a scanning tunneling electron microscope (STEM) to measure the tunneling current that flows when the surface of each region is scanned. When using a STEM, two-dimensional carrier concentration distribution can be observed with a spatial resolution of 1 nm. Therefore, not only can the differences in average carrier concentration between the first region 17 and the second regions 18a and 18b be determined, but also the absolute value of the average carrier concentration of each region can be determined.

[0043] In one embodiment, the average carrier concentration in the first region 17 is 10 14 ~10 18 cm -3 It is. In one embodiment, the average carrier concentration in the second region 18a and / or the second region 18b is 10 17 cm -3 More than 10, preferably 17 ~10 22 cm -3 It is. In one embodiment, the ratio of the average carrier concentration of the second region 18a to the average carrier concentration of the first region 17 (average carrier concentration of the second region 18a / average carrier concentration of the first region 17) and / or the ratio of the average carrier concentration of the second region 18b to the average carrier concentration of the first region 17 (average carrier concentration of the second region 18b / average carrier concentration of the first region 17) is 2 to 10 4 and preferably 10 to 10 4 and more preferably 10 to 3 × 10 3 It is. In one embodiment, the average carrier concentration in the first region 17 is 10 14 ~10 18 cm -3 and the average carrier concentration in the second region 18a and / or the second region 18b is 10 17 cm -3 More than 10, preferably 17 ~10 22 cm -3and the ratio of the average carrier concentration in the second region 18a to the average carrier concentration in the first region 17 (average carrier concentration in the second region 18a / average carrier concentration in the first region 17), and / or the ratio of the average carrier concentration in the second region 18b to the average carrier concentration in the first region 17 (average carrier concentration in the second region 18b / average carrier concentration in the first region 17) is 2 to 10 4 and preferably 10 to 10 4 and more preferably 10 to 3×10 3 is.

[0044] In one embodiment, in the crystalline oxide semiconductor 15, the average hydrogen concentration in the second region 18a is relatively high compared to the first region 17, and / or in the crystalline oxide semiconductor 15, the average hydrogen concentration in the second region 18b is relatively high compared to the first region 17. Thus, by increasing the average hydrogen concentration in the second region 18a and / or the second region 18b as compared with the first region 17, the average carrier concentration in the second region 18a and / or the second region 18b tends to be further increased. Thereby, the contact resistance of the transistor 10 can be further improved. Further, since the crystalline oxide semiconductor 15 has a smaller hydrogen diffusion constant than the amorphous oxide semiconductor, the difference in the average hydrogen concentration as described above is stably maintained. As will be described later, by setting the film formation conditions (for example, hydrogen partial pressure, etc.) of the first insulating films 14a and 14b to specific conditions, the average hydrogen concentration in the second regions 18a and 18b can be increased. Further, in the crystalline oxide semiconductor 15, the fact that the average hydrogen concentration in the second region 18a is relatively high compared to the first region 17 and the fact that the average hydrogen concentration in the second region 18b is relatively high compared to the first region 17 can be determined by secondary ion mass spectrometry (SIMS). When using SIMS, not only the level of the average hydrogen concentration in the first region 17 and the second regions 18a and 18b but also the absolute value of the average hydrogen concentration in each region can be obtained. Note that the average hydrogen concentration is obtained as the arithmetic mean of the measured values (hydrogen concentration) at five measurement points in each region. That is, in the measurement, each region is divided into five equal parts in the longitudinal direction (channel length direction), and each is used as a SIMS measurement point.

[0045] In one embodiment, the average hydrogen concentration in the second region 18a and / or the second region 18b is 1×10 21 atoms / cm 3 or more, more preferably 2×10 21 atoms / cm 3 or more, still more preferably 5×10 21 atoms / cm 3 or more. In one embodiment, the average hydrogen concentration in the first region 17 is relatively lower than that in the second region 18a and / or the second region 18b. In one embodiment, the ratio of the average hydrogen concentration in the second region 18a to the average hydrogen concentration in the first region 17 (average hydrogen concentration in the second region 18a / average hydrogen concentration in the first region 17), and / or the ratio of the average hydrogen concentration in the second region 18b to the average hydrogen concentration in the first region 17 (average hydrogen concentration in the second region 18b / average hydrogen concentration in the first region 17) is 5 to 5×10 3 , preferably 10 to 3×10 3 , more preferably 20 to 2×10 3 . In one embodiment, the average hydrogen concentration in the second region 18a and / or the second region 18b is 1×10 21 atoms / cm 3 or more, more preferably 2×10 21 atoms / cm 3 or more, still more preferably 5×10 21 atoms / cm 3 or more, and the ratio of the average hydrogen concentration in the second region 18a to the average hydrogen concentration in the first region 17 (average hydrogen concentration in the second region 18a / average hydrogen concentration in the first region 17), and / or the ratio of the average hydrogen concentration in the second region 18b to the average hydrogen concentration in the first region 17 (average hydrogen concentration in the second region 18b / average hydrogen concentration in the first region 17) is 5 to 5×10 3 , preferably 10 to 3×10 3 , more preferably 20 to 2×10 3 .

[0046] The average hydrogen concentration can also be measured for the insulating films (the first insulating films 14a and 14b, the second insulating film 16). The measurement method is the same as the measurement method described for the crystalline oxide semiconductor 15. In one embodiment, the average hydrogen concentration in the first insulating film 14a and / or the first insulating film 14b is, for example, 5×10 22 atoms / cm 3 or less, 2×10 22 atoms / cm 3 or less, 1×10 22 atoms / cm 3 or less, 5×10 21 atoms / cm 3 or less, 1×10 21 atoms / cm 3 or less, 5×10 20 atoms / cm 3 or less, or 1×10 20 atoms / cm 3 or less, and may also be, for example, for example, 5×10 18 atoms / cm 3 or more, 1×10 19 atoms / cm 3 or more, 5×10 19 atoms / cm 3 or more, 1×10 20 atoms / cm 3 or more, 5×10 20 atoms / cm 3 or more, or 1×10 21 atoms / cm 3 or more, and may also be.

[0047] In one embodiment, the average hydrogen concentration in the second insulating film 16 is, for example, 1×10 18 atoms / cm 3 or more, 5×10 18 atoms / cm 3 or more, 1×10 19 atoms / cm 3 or more, 5×10 19 atoms / cm 3 or more, 1×10 20 atoms / cm3 or more than 5×10 20 atoms / cm 3 It may also be the above. The average hydrogen concentration in the second insulating film 16 is, for example, 5×10 22 atoms / cm 3 or less, 1×10 22 atoms / cm 3 or less, 5×10 21 atoms / cm 3 or less, 2×10 21 atoms / cm 3 or less, 1×10 21 atoms / cm 3 or less, 5×10 20 atoms / cm 3 or less, or 1×10 20 atoms / cm 3 It may also be the above.

[0048] In one embodiment, the crystallinity of the crystalline oxide semiconductor 15 in the first region 17 is relatively high compared to the second region 18a and / or the second region 18b. That is, the first region 17 includes a highly crystallized region having a relatively high crystallinity compared to the crystalline oxide semiconductors in the second region 18a and / or the second region 18b. The degree of crystallinity can be compared, for example, by obtaining the variation of the FFT pattern obtained by performing a fast Fourier transform (FFT) on the image obtained by irradiating an electron beam. The shape of the spot image obtained by electron beam diffraction indicates the crystallinity and quality of the crystal. This is because sharp and clear spots indicate high crystallinity, and blurred and spread spots indicate low crystallinity and non-uniform structure. For example, in one embodiment, in each FFT pattern obtained by performing a fast Fourier transform on the image obtained by irradiating an electron beam on the same area in each of the first region and the second region, the variation X of the FFT pattern calculated by the following formula is larger in the second region than in the first region. X = [Σ (luminance - average value of luminance in the FFT region) 2 / number of samplings (However, in the above formula, the FFT region is the region of the FFT pattern obtained by performing a fast Fourier transform on the above image, the luminance is the luminance of each spot in the FFT region, and the number of samplings is the number of irradiations of the electron beam irradiated to obtain the image. The number of samplings is set to 5. Therefore, the above formula is also represented by the following formula.)

[0049]

Number

[0050] When obtaining the FFT pattern, it is preferable to measure by aligning the orientation of the crystal plane of the observation surface in the first region and the second region. Also, it is preferable to select the measurement position so that there is no grain boundary in the spot of the electron beam. Further, the variation X of the FFT pattern is preferably calculated by measuring, for example, five points in each of the first region and the second region and obtaining the average value for each region. When it is difficult to align the orientation of the crystal plane of the observation surface between the first region and the second region, or when it is difficult to exclude the grain boundary from the spot of the electron beam, the luminance of the FFT pattern is corrected by a conventionally known method.

[0051] In one embodiment, the crystal orientation in the electron diffraction pattern obtained by irradiating the crystal oxide semiconductor 15 with an electron beam includes the cubic crystal structure of indium oxide and is composed of at least one or more planes of (211), (222), (400), (440), and (622).

[0052] Hereinafter, an example of the manufacturing method of the transistor 10 according to the present embodiment will be described, but the manufacturing method is not limited to this example.

[0053] FIG. 3 is a diagram for explaining an example of the manufacturing method of the transistor 10 according to the present embodiment. FIG. 3(a) shows a state in which the second electrode 12 and the insulating film 19 supporting the second electrode 12 in FIGS. 1 and 2 are formed by a known method. Although not shown in FIG. 3(a), the second electrode 12 and the insulating film 19 may be further formed on another substrate. Further, the second electrode 12 may be connected to an element outside the transistor according to the present embodiment.

[0054] Next, as shown in FIG. 3(b), the first insulating film 14b, the third electrode 13, and the first insulating film 14a are formed in this order. At this time, as will be described later, the third electrode 13 may be formed so as to be connected to the word line. Alternatively, the third electrode 13 itself may be used as the word line.

[0055] The first insulating film 14b is formed, for example, by forming a film containing an insulator as described above by various methods such as chemical vapor deposition (CVD) method, plasma CVD (PECVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, sol-gel method, and coating method.

[0056] The third electrode 13 is formed, for example, by forming a conductor as described above such as tungsten. The third electrode 13 may be patterned into an arbitrary shape. The third electrode 13 may form a pattern during film formation, or may form a pattern by etching after film formation.

[0057] The first insulating film 14a is formed, for example, by forming a film containing an insulator as described above by various methods such as chemical vapor deposition (CVD) method, plasma CVD (PECVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, sol-gel method, and coating method.

[0058] Next, as shown in FIG. 3(c), a through hole H is formed by etching so as to penetrate the first insulating film 14a, the third electrode 1, and the first insulating film 14b. Etching for forming the through hole H may use various methods such as dry etching and wet etching. Further, before etching, a resist for defining the region where the through hole H is to be formed may be formed on the first insulating film 14a.

[0059] Next, as shown in FIG. 3(d), a second insulating film 16 including an insulator as described above is formed by various methods such as a chemical vapor deposition (CVD) method, a plasma CVD (PECVD) method, a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, a sol-gel method, and a coating method.

[0060] Next, as shown in FIG. 3(e), a crystalline oxide semiconductor 15 is formed in the through hole H in which the second insulating film 16 is formed. Examples of the method for forming the crystalline oxide semiconductor 15 include a chemical vapor deposition (CVD) method, a plasma CVD (PECVD) method, a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, a sol-gel method, and a coating method. Note that the CVD method includes metalorganic CVD (MO-CVD), inductively coupled plasma CVD (ICP-CVD), mist CVD, and the like. The PVD method includes DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, ion plating, and the like.

[0061] However, the oxide semiconductor 15 formed in the process shown in FIG. 3(e) may be amorphous or crystalline. When an amorphous oxide semiconductor is formed in FIG. 3(e), the oxide semiconductor is crystallized in any subsequent process. The crystalline oxide semiconductor 15 may be formed by performing post-annealing, which will be described later, after forming an amorphous oxide semiconductor. The crystalline oxide semiconductor 15 may be formed by performing post-annealing after forming the amorphous oxide semiconductor, and post-annealing may be further performed after the oxide semiconductor is crystallized to form the crystalline oxide semiconductor 15. Alternatively, the crystalline oxide semiconductor 15 may be formed without post-annealing, and post-annealing may be performed after forming the crystalline oxide semiconductor 15 to adjust the crystallinity of the crystalline oxide semiconductor 15.

[0062] It is preferable to perform post-annealing on the oxide semiconductor formed in the process shown in FIG. 3(e). The post-annealing can be performed, for example, after forming the subsequent first electrode 11 or before forming the first electrode 11 after forming the oxide semiconductor. The state of the oxide semiconductor before post-annealing may be amorphous or crystalline. The post-annealing atmosphere may contain nitrogen or oxygen and may be under vacuum or in the air. The post-annealing temperature is preferably 250°C or higher and 600°C or lower, more preferably 300°C or higher and 500°C or lower, and still more preferably 350°C or higher and 450°C or lower. The post-annealing time is within 5 minutes to 2 hours, preferably within 30 minutes to 1 hour. By setting the post-annealing conditions as described above, the selective increase in the average carrier concentration in the second regions 18a and 18b described above can be effectively promoted. In order to relatively improve the average carrier concentration in the second regions 18a and 18b, it is preferable to adjust the heating rate during post-annealing, the holding time at the maximum temperature, the cooling rate, etc. For example, by setting specific conditions such as shortening the holding time at the maximum temperature during post-annealing or increasing the cooling rate, there is a tendency to effectively promote the selective increase in the average carrier concentration in the second regions 18a and 18b described above. This is because under the above specific conditions, crystallization starts later in the second regions 18a and 18b adjacent to the first insulating films 14a and 14b, where the temperature rise is slow, compared to the first region 17 adjacent to the third electrode 13, which is easy to conduct heat, and the influence (non-uniformity) due to such a delay in crystallization is preserved. As a result, the average carrier concentration in the second regions 18a and 18b selectively increases and this state is maintained.

[0063] Next, as shown in FIG. 3(f), the first electrode 11 is formed on the upper layer of the crystalline oxide semiconductor 15 by a known method. The first electrode 11 may be patterned into an arbitrary shape. The first electrode 11 may form a pattern during film formation, or may form a pattern by etching after film formation.

[0064] As described above, the transistor 10 as shown in FIGS. 1 and 2 can be obtained.

[0065] In the above manufacturing method, the crystalline oxide semiconductor 15 is formed in the through-hole H on which the second insulating film 16 is formed. Therefore, as a method for forming the crystalline oxide semiconductor 15, an atomic layer deposition method (ALD) is preferable. The atomic layer deposition (ALD) method defines one cycle as a process of alternately exposing a raw material (which may be referred to as a precursor or a precurser) containing a metal element that constitutes the film formation target (here, the crystalline oxide semiconductor 15) and an oxidizing agent to the substrate surface. In one cycle, one atomic layer is formed, and the film is formed by repeating this cycle until the desired film thickness is achieved. Therefore, by using ALD, a dense crystalline oxide semiconductor 15 can be formed even in the second region 18b near the second electrode 12 away from the opening in the through-hole H on which the second insulating film 16 is formed. Thereby, the contact resistance between the crystalline oxide semiconductor 15 and the second electrode 12 can be further reduced. Further, by sequentially changing the film formation conditions of ALD, selective increase in the average carrier concentration in the second regions 18a and 18b may be effectively promoted.

[0066] One atomic layer deposition cycle of ALD may include the following four steps. (1) Vaporize the precursor (precurser) in a container containing the precursor as the raw material, introduce it into the chamber, apply a predetermined system pressure, react it with the OH groups on the substrate surface or the film surface for a predetermined time, and adsorb single molecules. When the vapor pressure of the precursor is low, the container containing the precursor may be heated to promote vaporization, and when the vapor pressure of the precursor is high, the container containing the precursor may be cooled to suppress vaporization for adjustment. (2) Remove unreacted raw materials and by-produced gases from the chamber by purging with an inert gas, and deposit one atomic layer. (3) Introduce a reactive gas into the chamber, and oxidize the metal of the precursor using heat, plasma, or the like. (4) Remove unreacted oxidizing agent and by-produced gases by purging with an inert gas. After step (4), return to step (1), and repeat steps (1) to (4) until the desired film thickness is achieved.

[0067] When performing ALD, various ALD apparatuses can be used. Specifically, for example, apparatuses capable of supplying a precursor by bubbling and apparatuses having a vaporization chamber can be mentioned. Further, apparatuses capable of performing plasma treatment or the like on a reactive gas (oxidizing agent) can be mentioned. Note that not only a single-wafer apparatus equipped with a film formation chamber but also an apparatus capable of simultaneously processing multiple wafers using a batch furnace may be used.

[0068] Examples of the types of ALD precursors include organometals (e.g., AlMe3), metal hydrides (e.g., AsH3), metal alkoxides (e.g., Ti(OCHMe2)4), metal amides (e.g., Ti(NMe2)4), β-diketonates (e.g., Co(acac)2), metallocenes (e.g., MgCp2), metal amidines, and the like. Various metal compounds are commercially available as ALD precursors, and a precursor and an oxidizing agent capable of forming a target film to be formed may be selected.

[0069] Examples of the precursor include one or more selected from the group consisting of compounds used as organic ligands such as alkyl compounds, alcohol compounds, glycol compounds, β-diketone compounds, cyclopentadiene compounds, and organic amine compounds, and compounds of silicon or metal.

[0070] Examples of the metal species of the precursor include, for example, lithium, sodium, potassium, magnesium, calcium, strontium, barium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, iron, ruthenium, cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, zinc, boron, aluminum, silicon, indium, gallium, germanium, tin, lead, antimony, bismuth, scandium, ruthenium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

[0071] When the oxide semiconductor 15 contains indium atoms (In), a precursor containing In may be used. Further, when the oxide semiconductor 15 contains other metals, a precursor containing the metal may be used. When forming an oxide semiconductor using two or more metals, there are a method of vaporizing and supplying each component independently (sometimes referred to as the "single-source method") and a method of vaporizing and supplying a mixed raw material in which multi-component raw materials are previously mixed in a desired composition (sometimes referred to as the "cocktail-source method"). In the case of the single-source method, each precursor to be used is preferably a precursor having similar thermal and / or oxidative decomposition behavior. In the case of the cocktail-source method, as each precursor, in addition to having similar thermal and / or oxidative decomposition behavior, a compound that does not cause alteration due to chemical reaction or the like during mixing is preferred.

[0072] Examples of the compound used as the organic ligand of the precursor include the following. Also, depending on the valence of the central metal, a plurality of the following ligands can coordinate. In the precursor, when a plurality of ligands coordinate to the central metal, these plurality of ligands may be the same as each other, or two or more types of ligands may be combined.

[0073] Examples of the alkyl compound used as the organic ligand of the precursor include methyl, ethyl, propyl, isopropyl, butyl, sec-butyl, isobutyl, tert-butyl, pentyl, isopentyl, tert-pentyl, and the like.

[0074] Examples of the alcohol compounds used as the organic ligand of the precursor include alkyl alcohols such as methanol, ethanol, propanol, isopropyl alcohol, butanol, sec-butyl alcohol, isobutyl alcohol, tert-butyl alcohol, pentyl alcohol, isopentyl alcohol, and tert-pentyl alcohol; ether alcohols such as 2-methoxyethanol, 2-ethoxyethanol, 2-butoxyethanol, 2-(2-methoxyethoxy)ethanol, 2-methoxy-1-methylethanol, 2-methoxy-1,1-dimethylethanol, 2-ethoxy-1,1-dimethylethanol, 2-isopropoxy-1,1-dimethylethanol, 2-butoxy-1,1-dimethylethanol, 2-(2-methoxyethoxy)-1,1-dimethylethanol, 2-propoxy-1,1-diethylethanol, 2-s-butoxy-1,1-diethylethanol, and 3-methoxy-1,1-dimethylpropanol; dialkylamino alcohols such as dimethylaminoethanol, ethylmethylaminoethanol, diethylaminoethanol, dimethylamino-2-pentanol, ethylmethylamino-2-pentanol, dimethylamino-2-methyl-2-pentanol, ethylmethylamino-2-methyl-2-pentanol, and diethylamino-2-methyl-2-pentanol.

[0075] Examples of the glycol compounds used as the organic ligand of the precursor include 1,2-ethanediol, 1,2-propanediol, 1,3-propanediol, 2,4-hexanediol, 2,2-dimethyl-1,3-propanediol, 2,2-diethyl-1,3-propanediol, 1,3-butanediol, 2,4-butanediol, 2,2-diethyl-1,3-butanediol, 2-ethyl-2-butyl-1,3-propanediol, 2,4-pentanediol, 2-methyl-1,3-propanediol, 2-methyl-2,4-pentanediol, 2,4-hexanediol, and 2,4-dimethyl-2,4-pentanediol.

[0076] Examples of β-diketone compounds used as organic ligands of the precursor include alkyl-substituted β-diketones such as acetylacetone, hexane-2,4-dione, 5-methylhexane-2,4-dione, heptane-2,4-dione, 2-methylheptane-3,5-dione, 5-methylheptane-2,4-dione, 6-methylheptane-2,4-dione, 2,2-dimethylheptane-3,5-dione, 2,6-dimethylheptane-3,5-dione, 2,2,6-trimethylheptane-3,5-dione, 2,2,6,6-tetramethylheptane-3,5-dione, octane-2,4-dione, 2,2,6-trimethyloctane-3,5-dione, 2,6-dimethyloctane-3,5-dione, 2,9-dimethylnonane-4,6-dione, 2-methyl-6-ethyldecane-3,5-dione, 2,2-dimethyl-6-ethyldecane-3,5-dione; fluorine-substituted alkyl β-diketones such as 1,1,1-trifluoropentane-2,4-dione, 1,1,1-trifluoro-5,5-dimethylhexane-2,4-dione, 1,1,1,5,5,5-hexafluoropentane-2,4-dione, 1,3-diperfluorohexylpropane-1,3-dione; ether-substituted β-diketones such as 1,1,5,5-tetramethyl-1-methoxyhexane-2,4-dione, 2,2,6,6-tetramethyl-1-methoxyheptane-3,5-dione, 2,2,6,6-tetramethyl-1-(2-methoxyethoxy)heptane-3,5-dione, and the like.

[0077] Examples of cyclopentadiene compounds used as organic ligands of the precursor include cyclopentadiene, methylcyclopentadiene, ethylcyclopentadiene, propylcyclopentadiene, isopropylcyclopentadiene, butylcyclopentadiene, sec-butylcyclopentadiene, isobutylcyclopentadiene, tert-butylcyclopentadiene, dimethylcyclopentadiene, tetramethylcyclopentadiene, and the like.

[0078] Examples of the organic amine compound used as the organic ligand of the precursor include methylamine, ethylamine, propylamine, isopropylamine, butylamine, sec-butylamine, tert-butylamine, isobutylamine, dimethylamine, diethylamine, dipropylamine, diisopropylamine, ethylmethylamine, propylmethylamine, isopropylmethylamine, and the like.

[0079] In addition, a metal halogen compound (for example, InCl3, InBr3, InF3, etc.) may be used as a precursor. When a plurality of halogens are coordinated to the metal, these plurality of halogens may be the same as each other, or two or more kinds of halogens may be combined. Further, a part of the halogen may be replaced by hydrogen.

[0080] Examples of the indium-containing precursor include, for example, InCl3, TMIn (trimethyl indium), TEIn (triethyl indium), InCp (cyclopentadienyl indium(I)), InEtCp (ethylcyclopentadienyl indium(I)), In(acac)3 (indium acetylacetonate), In(tmhd)3 (indium 2,2,6,6-tetramethyl-3,5-heptanedionate), In[[( iPrN)2CNR2]3(R=Me)(indium-tris-guanidinates), Et2InN(TMS)2(diethyl[bis-(trimethylsilyl)amido]indium), INCA(diethyl[1,1,1-trimethyl-N-(trimethylsilyl)silanaminato]indium), DADI([3-(dimethylamino)propyl]dimethyl In(dmamp)3((1-dimethylamino-2-methyl-2-propoxy)indium), Me2In(EDPA)(dimethyl(N-ethoxy-2,2-dimethylpropanamido)indium), tris(N,N'-diisopropylacetamidinato)indium(III), and the like.

[0081] These ALD precursors may be used alone or in combination of two or more.

[0082] The precursors described above can be produced according to known production methods. For example, when an alcohol compound is used as the organic ligand, the precursor can be produced by reacting the inorganic salt of the metal or a hydrate thereof described above with an alkali metal alkoxide of the alcohol compound. Examples of inorganic salts of metals or hydrates thereof include metal halides and nitrates. Examples of alkali metal alkoxides include sodium alkoxides, lithium alkoxides, and potassium alkoxides.

[0083] Examples of oxidizing agents used in ALD include H2O, O2, O3, O2 plasma, H2O plasma, hydrogen peroxide (H2O2), etc. These oxidizing agents may be used alone or in combination of two or more.

[0084] When using two or more oxidizing agents, the two or more oxidizing agents may be used simultaneously, or they may be used individually while changing the two or more oxidizing agents. For example, by using two types of O2 plasma and H2O plasma as oxidizing agents, both advantages of high mobility obtained when using O2 plasma and the effects of reducing carbon concentration and improving the stability of mobility against heat treatment obtained when using H2O plasma can be utilized. By using two or more oxidizing agents, high mobility and low carbon concentration can be adjusted. Depending on the desired effect, the usage ratio, usage order, number of cycles, etc. of O2 plasma and H2O plasma may be appropriately selected.

[0085] The pressure of the system (inside the film formation chamber) in step (1) may be appropriately set according to the type of precursor, substrate temperature, etc. For example, 1 to 10,000 Pa is preferable, 10 to 1,000 Pa is more preferable, 50 to 500 Pa is further preferable, and 80 to 120 Pa is particularly preferable.

[0086] In one embodiment, in the film formation step, H2O plasma is used as the oxidizing agent. In one embodiment, in the film formation step, O2 plasma is used as the oxidizing agent. In one embodiment, in the film formation step, O3 is used as the oxidizing agent. By using these oxidizing agents, the effect of being able to control the electrical characteristics of the oxide semiconductor film in a good state can be obtained.

[0087] To vaporize the precursor, the container containing the precursor may be heated at a temperature at which the precursor is sufficiently vaporized as necessary. When using a precursor with a high vapor pressure, the container containing the precursor may be cooled as necessary. In one embodiment, the container containing the indium-containing precursor (for example, triethylindium) is heated in the range of 25 to 150 °C. The above temperature is preferably in the range of 50 to 150 °C, more preferably in the range of 75 to 125 °C.

[0088] In the above manufacturing method, the substrate temperature during film formation is usually in the range of 50 to 600°C, preferably 85 to 500°C, more preferably 80 to 350°C, and even more preferably 100 to 250°C.

[0089] Incidentally, the growth amount of the oxide semiconductor film per ALD process cycle varies depending on the precursor used during film formation, the types of reactive gases, and the substrate temperature during film formation.

[0090] The growth amount per ALD process cycle is called Growth per cycle (GPC), and can be calculated, for example, by measuring the film thickness of the oxide semiconductor when repeating 30 ALD cycles. Here, GPC varies depending on the combination of the precursor, the oxidizing agent, and the substrate temperature, and also varies depending on the type of substrate. Therefore, the above number of cycles varies depending on a number of factors such as the types of precursors and oxidizing agents used and their combinations, the type of substrate, the substrate temperature during film formation, and the desired film thickness, and can be appropriately set in consideration of these factors.

[0091] When using O3 as the oxidizing agent, the substrate temperature during film formation is preferably above 100°C, more preferably 110 to 250°C, 120 to 230°C, 130 to 220°C. When using H2O plasma and O2 plasma as the oxidizing agent, the substrate temperature during film formation is preferably 100 to 150°C.

[0092] Examples of the inert gas for purging unreacted raw materials and unreacted oxidizing agents include argon, nitrogen, etc., and in the method of this embodiment, argon or nitrogen is preferred.

[0093] In the above step (3), it is preferable to generate plasma of the reactive gas (oxidizing agent).

[0094] In the process shown in Fig. 3(b) of the above manufacturing method, when forming the first insulating film 14a, hydrogen gas may be added to the atmosphere during ALD or CVD film formation, or a precursor containing a large amount of hydrogen may be used, and further, the hydrogen concentration of the first insulating film 14a may be increased by activating it with plasma. Thereby, hydrogen can be supplied from the first insulating film 14a, through the second insulating film 16, to the second region 18a of the crystalline oxide semiconductor 15. As a result, the average hydrogen concentration in the second region 18a of the crystalline oxide semiconductor 15 selectively increases, and the effect of further increasing the average carrier concentration is obtained. Also, when forming the first insulating film 14b, the hydrogen concentration of the first insulating film 14b may be selectively increased by adding hydrogen gas to the atmosphere during film formation. Thereby, hydrogen can be supplied from the first insulating film 14b, through the second insulating film 16, to the second region 18b of the crystalline oxide semiconductor 15. As a result, the average hydrogen concentration in the second region 18b of the crystalline oxide semiconductor 15 selectively increases, and the effect of further increasing the average carrier concentration is obtained. The supply of hydrogen as described above proceeds efficiently during the post-annealing of the crystalline oxide semiconductor 15. In particular, by performing the post-annealing under the conditions as described above, the supply of hydrogen is promoted, and the above-described effects are more significantly exhibited.

[0095] The crystalline oxide semiconductor 15 is preferably a crystalline oxide semiconductor formed by an atomic layer deposition (ALD) method. Note that a crystalline oxide semiconductor formed by an atomic layer deposition (ALD) method has different uniformity from a crystalline oxide semiconductor formed by a method such as sputtering, but it is impossible or impractical to generally specify the structure or characteristics related to the difference in words.

[0096] In the above description, the case where the transistor includes the first insulating film between the first electrode and the third electrode and between the second electrode and the third electrode has been mainly shown, but the present invention is not limited thereto. For example, the transistor may include the first insulating film only between either the first electrode and the third electrode or between the second electrode and the third electrode. Further, the second insulating film 16 may be omitted. Further, as long as the effects of the present embodiment are achieved, the transistor may have a structure other than the structures shown in FIGS. 1 to 3.

[0097] 2. Semiconductor Device A semiconductor device according to an aspect of the present invention includes a transistor according to an aspect of the present invention. The semiconductor device may include one or more transistors according to an aspect of the present invention. Since the semiconductor device according to the present aspect can improve the contact resistance in the transistor, it has excellent electrical characteristics and high reliability. The type of the semiconductor device is not particularly limited, but from the viewpoint that the above effects are significantly exhibited, volatile memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM); mask ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory (NOR type flash memory, NAND type flash memory), MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), ReRAM (Resistive RAM), etc. are preferably semiconductor memory devices. Alternatively, the semiconductor device according to this aspect may be a logic device such as TTL (Transistor-Transistor Logic), CMOS (Complementary Metal-Oxide-Semiconductor), BiCMOS, PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), MPU (Microprocessor Unit), etc. Further, since the transistor according to one aspect of the present invention has a vertical structure, it is suitable for arranging a plurality of transistors at high density in a semiconductor memory device, and also contributes to the miniaturization of the semiconductor memory device. Furthermore, since the transistor according to one aspect of the present invention uses an oxide semiconductor as a channel, the leakage current tends to be small. Therefore, by using it in a semiconductor memory device, the capacitance of the capacitor can be reduced or the capacitor can be omitted. As a result, by using the transistor according to one aspect of the present invention, the semiconductor memory device can be miniaturized.

[0098] FIG. 4 is a diagram showing an example of the circuit configuration of a semiconductor memory device including the transistor according to one aspect of the present invention. As shown in FIG. 4, a semiconductor memory device 50 includes a transistor 10, a capacitor 51, a word line WL, and a bit line BL. The source electrode of the transistor 10 is connected to a bit line BL. The drain electrode of the transistor 10 is connected to one end of a capacitor 51. The gate electrode of the transistor 10 is connected to a word line WL. The other end of the capacitor 51 is grounded. The bit line BL may be connected to a first electrode 11 of the transistor 10 and may be connected to a second electrode 12. The word line WL may be connected to a third electrode 13 of the transistor 10. One end of the capacitor 51 may be connected to the first electrode 11 of the transistor 10 and may be connected to the second electrode 12.

[0099] 4, one memory cell 52 is formed by the transistor 10 and the capacitor 51. The memory cell 52 can store data based on the charge held by the capacitor 51. Note that the configuration of the memory cell 52 is not limited to this example, and in other examples, the capacitor 51 is omitted. When the capacitor 51 is omitted, data can be stored based on the charge held in the transistor 10 itself. Also, the memory cell 52 may be configured by combining two or more transistors. When the transistor 10 itself is to have the function of retaining charge, for example, one or more of the configurations described below can be applied. (1) For the second insulating film, a high dielectric constant insulator such as hafnium oxide (HfO2) or zirconium oxide (ZrO2) is used. (2) For the second insulating film, a ferroelectric material such as (Pb,La)(Zr,Ti)O3 (PLZT), SrTiO3 (STO), or yttria-stabilized zirconia (YSZ) is used. (3) An element that forms a level in the gap of a crystalline oxide semiconductor is added to the crystalline oxide semiconductor, and hysteresis is utilized. (4) A parasitic capacitance is utilized when a part of the source electrode and / or drain electrode and a part of the gate electrode are arranged so as to face each other with an insulating film interposed therebetween. Further, in the above (4), for example, a parasitic capacitance formed by arranging a part of one of the source electrode and the drain electrode and a part of the gate electrode to face each other with an insulating film interposed therebetween can be utilized. At this time, the other of the source electrode and the drain electrode can be arranged away from the gate electrode (for example, the distance between the other of the source electrode and the drain electrode and the gate electrode may be longer than the distance between one of the source electrode and the drain electrode and the gate electrode). Here, in the crystalline oxide semiconductor, the second region described above may be formed in a region close to the other of the source electrode and the drain electrode.

[0100] The semiconductor memory device 50 can read the data stored in the memory cell 52 to the bit line BL by controlling the word line WL, and can also write the data transferred to the bit line BL into the memory cell 52. The semiconductor memory device 50 includes a memory cell array (not shown) composed of a plurality of memory cells 52.

[0101] Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art can easily make many changes to these exemplary embodiments and / or examples without substantially departing from the novel teachings and effects of the present invention. Therefore, many of these changes are included in the scope of the present invention. The contents of the documents described in this specification are all incorporated by reference.

Explanation of reference numerals

[0102] 10: Transistor 11: First electrode 12: Second electrode 13: Third electrode 14a, 14b: First insulating film 15: Crystalline oxide semiconductor 16: Second insulating film 17: First region 18a, 18b: Second region 19: Insulating film 50: Semiconductor memory device 51: Capacitor 52: Memory cell WL: Word line BL: Bit line

Claims

1. a first electrode; a second electrode; a third electrode positioned between the first electrode and the second electrode; a first insulating film positioned between the first electrode and the third electrode and / or between the second electrode and the third electrode; a crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode; comprising; the crystalline oxide semiconductor includes a first region that does not contact the third electrode and is adjacent, and a second region that contacts or does not contact the first insulating film and is adjacent; the average carrier concentration in the second region is relatively higher than that in the first region; a transistor.

2. the crystalline oxide semiconductor is provided in a columnar shape penetrating the first insulating film and the third electrode; the first region is a region that penetrates the third electrode in the crystalline oxide semiconductor; the second region is a region that penetrates the first insulating film in the crystalline oxide semiconductor; the transistor according to claim 1.

3. the first electrode, the first insulating film, the third electrode, the first insulating film, and the second electrode are laminated in this order; the crystalline oxide semiconductor is provided in a columnar shape penetrating the first insulating film and the third electrode; the first region is a region that penetrates the third electrode in the crystalline oxide semiconductor; the second region is a region that penetrates the first insulating film in the crystalline oxide semiconductor; the transistor according to claim 1.

4. the length in the height direction of the columnar crystalline oxide semiconductor is 2 to 1000 nm, the transistor according to claim 2 or 3.

5. in the columnar crystalline oxide semiconductor, the ratio of the height of the first region: the height of the second region is 10:1 to 1:1; the transistor according to claim 2 or 3.

6. in the first region and the second region, the composition ratio of the metal elements constituting the crystalline oxide semiconductor is substantially the same; the transistor according to any one of claims 1 to 3.

7. the first region includes a highly crystallized region having a relatively higher crystallinity compared to the crystalline oxide semiconductor of the second region; the transistor according to claim 6.

8. In each FFT pattern obtained by performing a fast Fourier transform on an image obtained by irradiating the first region and the second region with an electron beam having the same area, the variation X of the FFT pattern calculated by the following formula is greater in the second region than in the first region. The transistor according to claim 7. X = [Σ (luminance - average value of luminance in FFT region) ２ / number of samplings (However, in the above formula, the FFT region is the region of the FFT pattern obtained by performing a fast Fourier transform on the image, the luminance is the luminance of each spot in the FFT region, and the number of samplings is the number of irradiations of the electron beam irradiated to obtain the image. The number of samplings is 5.)

9. The crystal orientation in the electron diffraction pattern obtained by irradiating the crystal oxide semiconductor with an electron beam includes a cubic crystal structure of indium oxide and is composed of at least one or more planes of (211), (222), (400), (440), and (622). The transistor according to claim 8.

10. The average hydrogen concentration in the second region is relatively higher than that in the first region. The transistor according to any one of claims 1 to 3.

11. At least one of the first electrode and the second electrode is at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N). The transistor according to any one of claims 1 to 3.

12. At least one of the first electrode and the second electrode is at least one selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), titanium (Ti), and titanium nitride (TiN). The transistor according to any one of claims 1 to 3.

13. The transistor according to any one of claims 1 to 3, further comprising a second insulating film provided between the third electrode and the crystalline oxide semiconductor.

14. The ratio of the average carrier concentration in the second region to the average carrier concentration in the first region (average carrier concentration in the second region / average carrier concentration in the first region) is 2 to 10 ４ The transistor according to any one of claims 1 to 3, wherein the ratio is as described above.

15. The ratio of the average carrier concentration of the second region to the average carrier concentration of the first region (average carrier concentration of the second region / average carrier concentration of the first region) is from 10 to 10 ４ The transistor according to claim 14, wherein the ratio is as defined above.

16. The average carrier concentration in the first region is 10 １４ to 10 １８ cm －３ and The average carrier concentration in the second region is 10 １７ ~10 ２２ cm －３ is The transistor according to any one of claims 1 to 3.

17. The ratio of the average hydrogen concentration in the second region to the average hydrogen concentration in the first region (average hydrogen concentration in the second region / average hydrogen concentration in the first region) is 5 to 5×10 ３ That is, The transistor according to any one of claims 1 to 3.

18. The transistor according to any one of claims 1 to 3, wherein the crystalline oxide semiconductor includes a body-centered cubic crystal structure.

19. The transistor according to any one of claims 1 to 3, wherein the crystalline oxide semiconductor contains indium oxide as a main component.

20. The transistor according to any one of claims 1 to 3, wherein the crystalline oxide semiconductor contains Ga or Al.

21. The transistor according to any one of claims 1 to 3, wherein the crystalline oxide semiconductor contains Ga.

22. The transistor according to any one of claims 1 to 3, wherein the crystalline oxide semiconductor contains Ga and Al.

23. The transistor according to any one of claims 1 to 3, wherein the crystalline oxide semiconductor is a polycrystalline oxide semiconductor.

24. The transistor according to any one of claims 1 to 3, wherein the crystalline oxide semiconductor is a single crystal oxide semiconductor.

25. The transistor according to any one of claims 1 to 3, wherein the crystalline oxide semiconductor is a crystalline oxide semiconductor formed by an atomic layer deposition method.

26. A semiconductor device including the transistor according to any one of claims 1 to 3.

27. The semiconductor device according to claim 26, which is a semiconductor memory device.

28. A first electrode, A second electrode, A third electrode located between the first electrode and the second electrode, A first insulating film located between the first electrode and the third electrode and / or between the second electrode and the third electrode, A crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode, Comprising The crystalline oxide semiconductor includes a body-centered cubic crystal structure, The crystalline oxide semiconductor includes an adjacent first region that does not contact the third electrode and an adjacent second region that contacts or does not contact the first insulating film, The average carrier concentration in the second region is relatively high compared to the first region, In the first region and the second region, the composition ratio of the metal elements constituting the crystalline oxide semiconductor is substantially the same, The first region includes a highly crystallized region having a relatively high crystallinity compared to the crystalline oxide semiconductor in the second region. In each FFT pattern obtained by performing a fast Fourier transform on an image obtained by irradiating the same area with an electron beam for each of the first region and the second region, the variation X of the FFT pattern calculated by the following formula is greater in the second region than in the first region. X = 1 / number of samples x Σ (luminance - average luminance value in FFT domain) ２ (However, in the above formula, the FFT region is the region of the FFT pattern obtained by performing a fast Fourier transform on the image, the luminance is the luminance of each spot in the FFT region, and the number of samplings is the number of irradiation times of the electron beam irradiated to obtain the image.) Transistor.

29. A first electrode; A second electrode; A third electrode positioned between the first electrode and the second electrode; A first insulating film positioned between the first electrode and the third electrode and / or between the second electrode and the third electrode; A crystalline oxide semiconductor that penetrates at least the first insulating film and connects the first electrode and the second electrode; Comprising: The crystalline oxide semiconductor includes a perovskite crystal structure. The crystalline oxide semiconductor includes a first region adjacent to the third electrode without contact and a second region adjacent to the first insulating film with or without contact. The average carrier concentration in the second region is relatively high compared to the first region. The average hydrogen concentration in the second region is relatively high compared to the first region. At least one of the first electrode and the second electrode is at least one selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), titanium (Ti), and titanium nitride (TiN). Transistor.

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