Imaging device

Abstract

Provided is an imaging device having a calculation function with a reduced circuit size. The imaging device has a plurality of pixel blocks. Each of the pixel blocks has: N (N is an integer of at least 1) first circuits; N second circuits; and a third circuit. Each of the first circuits has a photoelectric conversion device. The photoelectric conversion device has the function of converting incident light into an electric signal. The first circuit has the function of outputting a first signal, which is obtained by binarizing the electric signal, to the second circuit. Each of the second circuits has the function of outputting a second signal, which is obtained by multiplying the first signal by a weighting factor, to the third circuit. The N second signals are output to wires electrically connected to the third circuit, so that the second signals are added up. Moreover, the first circuit includes a transistor. The transistor is preferably an OS transistor.

Description

Technical Field

[0001] The present invention relates to an imaging device. In particular, it relates to an imaging device having an arithmetic function.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

Background Art

[0003] In the field of image recognition, a neural network is used. In image recognition, convolution operations are performed to detect the features of image data by multiplying the image data by weight coefficients called filters, adding them together (multiplication and addition operations), and further sliding and repeating the same operation. Among them, BNN (Binary Neural Network) can significantly reduce the circuits required for multiplication and addition operations by representing data in binary values.

[0004] In addition, a technique for adding an arithmetic function to an imaging device is disclosed in Patent Document 1.

[0005] On the other hand, a transistor having an oxide semiconductor or a metal oxide in the channel formation region of the transistor (also referred to as an oxide semiconductor transistor or an OS (Oxide Semiconductor) transistor) has a feature that the drain current (also referred to as the off-current) when the transistor is in the off state is very small (see, for example, Non-Patent Documents 1 and 2), and has attracted attention. For example, an imaging device having a configuration using an OS transistor in a pixel circuit is disclosed in Patent Document 2.

[0006] In addition, in oxide semiconductors, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure that are neither single crystal nor amorphous have been found (see Non-Patent Document 1 and Non-Patent Document 3). Non-Patent Document 1 and Non-Patent Document 3 disclose techniques for manufacturing transistors using oxide semiconductors having a CAAC structure.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0008]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0009] In BNN, since data is represented in binary values, for example, multiplication (product) in BNN can be performed using one XNOR circuit, and the circuit scale can be reduced. However, since a general logic circuit is used for addition (sum), the circuit scale could not be reduced.

[0010] In addition, there are cases where a high voltage is required for the photoelectric conversion device of the imaging device, and there are cases where a high breakdown voltage is required for the transistor that controls the photoelectric conversion device. A transistor with a high breakdown voltage needs to be manufactured using a process with a high breakdown voltage, and there is a problem that miniaturization is difficult.

[0011] One aspect of the present invention is an imaging device having an arithmetic function, and one of the problems is to provide an imaging device with a reduced circuit scale of the addition circuit. Or, one aspect of the present invention is an imaging device having an arithmetic function, and one of the problems is to provide an imaging device having a miniaturized transistor. Or, one aspect of the present invention is to provide a novel imaging device having an arithmetic function.

[0012] It should be noted that one aspect of the present invention does not necessarily need to solve all of the above problems, and it is sufficient if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. Other problems will naturally become clear from the description in the specification, claims, drawings, etc., and it is possible to extract these other problems from the description in the specification, claims, drawings, etc.

Means for Solving the Problems

[0013] One embodiment of the present invention is an imaging device having a plurality of pixel blocks. Each of the pixel blocks has N (N is an integer of 1 or more) first circuits, N second circuits, and a third circuit. Each of the first circuits has a photoelectric conversion device, and the photoelectric conversion device has a function of converting incident light into an electrical signal. The K-th (K is an integer from 1 to N) first circuit has a function of outputting a first signal obtained by binarizing the electrical signal to the K-th second circuit, and each of the second circuits has a function of outputting a second signal obtained by multiplying the first signal by a weighting coefficient to the third circuit. The N second signals are output to a wiring electrically connected to the third circuit, and addition is performed.

[0014] Also, in the above embodiment, the first circuit is provided laminated above the second circuit.

[0015] Also, in the above embodiment, the N first circuits are provided laminated above the N second circuits and the third circuit.

[0016] Also, in the above embodiment, each of the first circuits has a transistor, and the transistor has a metal oxide in the channel formation region.

Advantages of the Invention

[0017] According to one embodiment of the present invention, it is possible to provide an imaging device having a computing function and reducing the circuit scale of an addition circuit. Alternatively, according to one embodiment of the present invention, it is possible to provide an imaging device having a computing function and having miniaturized transistors. Alternatively, according to one embodiment of the present invention, it is possible to provide a novel imaging device having a computing function.

[0018] Note that the description of these effects does not prevent the existence of other effects. Also, one embodiment of the present invention does not necessarily have all of these effects. Other effects will be naturally apparent from the description in the specification, claims, drawings, etc., and it is possible to extract these other effects from the description in the specification, claims, drawings, etc.

Brief Description of the Drawings

[0019] FIG. 1 is a block diagram showing a configuration example of an imaging device. FIG. 2 is a diagram showing a configuration example of a pixel block. FIG. 3A is a schematic diagram showing a configuration example of a pixel. FIG. 3B is a circuit diagram showing a configuration example of a pixel. FIG. 4 is a timing chart showing an operation example of a pixel block. FIGS. 5A and 5B are schematic diagrams showing a configuration example of a pixel block. FIGS. 6A to 6D are diagrams for explaining the configuration of pixels of an imaging device. FIGS. 7A to 7C are diagrams for explaining the configuration of a photoelectric conversion device. FIG. 8 is a cross-sectional view for explaining a pixel. FIGS. 9A to 9C are diagrams for explaining an Si transistor. FIG. 10 is a cross-sectional view for explaining a pixel. FIG. 11 is a cross-sectional view for explaining a pixel. FIGS. 12A to 12D are diagrams for explaining an OS transistor. FIG. 13 is a cross-sectional view for explaining a pixel. FIG. 14 is a cross-sectional view for explaining a pixel. FIGS. 15A to 15C are perspective views (cross-sectional views) for explaining a pixel. FIGS. 16A to 16F are perspective views of a package and a module containing an imaging device. FIGS. 17A to 17F are diagrams for explaining an electronic device.

Modes for Carrying Out the Invention

[0020] [[ID=۴۳]] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different forms, and it is easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and scope. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0021] In addition, the multiple embodiments described below can be combined as appropriate. Also, when multiple configuration examples are shown within one embodiment, the configuration examples can be combined with each other as appropriate.

[0022] In the drawings attached to this specification, the components are classified by function and shown as independent blocks in a block diagram. However, in actuality, it is difficult to completely separate the components by function, and one component may be related to multiple functions.

[0023] Also, in the drawings and the like, the size, layer thickness, area, etc. may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings.

[0024] Also, in the drawings and the like, the same elements, elements having the same or similar functions, elements of the same material, or elements formed simultaneously may be given the same reference numerals, and repeated descriptions thereof may be omitted.

[0025] Also, in this specification and the like, the terms "film" and "layer" can be interchanged with each other. For example, in some cases, the term "conductive layer" can be changed to the term "conductive film". Or, for example, in some cases, the term "insulating film" can be changed to the term "insulating layer".

[0026] Also, in this specification and the like, terms indicating arrangements such as "above" and "below" do not limit the positional relationship of the components to be "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer", those including other components between the gate insulating layer and the gate electrode are not excluded.

[0027] Also, in this specification and the like, ordinal numbers such as "first", "second", "third", etc. are attached to avoid confusion of the components and do not numerically limit them.

[0028] Also, in this specification and the like, when the same reference numerals are used for a plurality of elements, when it is particularly necessary to distinguish them, the reference numerals may be described with identification symbols such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second wiring GL is described as wiring GL[2].

[0029] Also, in this specification and the like, when upper and lower limit numerical values are defined, a configuration that can be freely combined is also considered to be disclosed.

[0030] Also, in this specification and the like, "electrically connected" includes cases where it is connected via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical effect" includes electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitance elements, and other elements having various functions. Also, even when expressed as "electrically connected", in an actual circuit, there may be a case where there is no physical connection part and only the wiring extends.

[0031] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as a part of a "wiring", and vice versa.

[0032] Also, in this specification and the like, an "electrode" or "terminal" in an electric circuit refers to a part where current or potential input (or output), or signal reception (or transmission) occurs. Therefore, a part of the wiring may function as an electrode or a terminal.

[0033] Generally, a "capacitive element" has a configuration in which two electrodes face each other with an insulator (dielectric) in between. Also, in this specification and the like, the "capacitive element" includes not only those having a configuration in which two electrodes face each other with an insulator in between, but also those having a configuration in which two wirings face each other with an insulator in between, or those in which two wirings are arranged with an insulator in between. Further, the "capacitive element" is also referred to as a "capacitor" or simply "capacitance".

[0034] Also, in this specification and the like, the term "voltage" often refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage and potential difference can be used interchangeably.

[0035] Also, in this specification and the like, a transistor is an element having at least three terminals including a source, a drain, and a gate. And there is a channel formation region between the source (source terminal, source region, or source electrode) and the drain (drain terminal, drain region, or drain electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows.

[0036] Also, the functions of the source and the drain may be interchanged when using transistors of different polarities or when the direction of current changes in a circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

[0037] In addition, in this specification and the like, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). The off state, unless otherwise specified, for an n-channel type transistor means a state where the gate voltage Vgs with respect to the source is lower than the threshold voltage Vth, and for a p-channel type transistor means a state where the gate voltage Vgs with respect to the source is higher than the threshold voltage Vth. That is, the off-current of an n-channel type transistor may refer to the drain current when the gate voltage Vgs with respect to the source is lower than the threshold voltage Vth.

[0038] In the above description of the off-current, the drain and the source may be read as interchanged. That is, the off-current may refer to the source current when the transistor is in the off state. Also, in the same sense as the off-current, it may be referred to as the leakage current. Further, in this specification and the like, the off-current may refer to the current flowing between the source and the drain when the transistor is in the off state.

[0039] In addition, in this specification and the like, the on-current may refer to the current flowing between the source and the drain when the transistor is in the on state (also referred to as the conducting state).

[0040] In addition, in this specification and the like, metal oxide means an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like.

[0041] For example, when a metal oxide is used in the channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when the metal oxide has at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be called a metal oxide semiconductor. That is, a transistor having a metal oxide in the channel formation region can be called an "oxide semiconductor transistor" or an "OS transistor". Similarly, a "transistor using an oxide semiconductor" is also a transistor having a metal oxide in the channel formation region.

[0042] In addition, in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride. Details of the metal oxide will be described later.

[0043] (Embodiment 1) In this embodiment, a configuration example of an imaging device according to one aspect of the present invention will be described.

[0044] One aspect of the present invention is an imaging device having an arithmetic function. The imaging device has a function of performing a sum-of-products operation in which image data and weight coefficients are multiplied and added together in the BNN method. The imaging device has a plurality of pixels, and each of the pixels has a function of converting incident light into an electrical signal. In this embodiment, the image data is constituted by the electrical signals generated by each of the pixels.

[0045] <Configuration example of imaging device> FIG. 1 is a block diagram showing a configuration example of an imaging device 200 according to one aspect of the present invention.

[0046] The imaging device 200 includes a pixel array 210, a circuit 221, a circuit 222, a circuit 223, a circuit 231, and a circuit 232. The imaging device 200 also includes a wiring 201, a wiring 202, a wiring 204, and a wiring 205. In the drawings described in this specification and the like, the main signal flow is indicated by arrows or lines, and power lines and the like may be omitted.

[0047] In this specification and the like, in order to describe the input and output of signals and potentials between components, the expressions such as "electrode" or "terminal" may be used. Therefore, in an actual circuit, there may be no physical connection part such as an "electrode" or a "terminal", and they may be only electrically connected by wirings or the like.

[0048] The pixel array 210 has an imaging function and an arithmetic function. The circuits 221 and 222 have a selection function. The circuit 223 has a function of supplying a potential to a pixel and a selection function. For a circuit having a selection function, a shift register, a decoder, or the like can be used. The circuits 231 and 232 are not essential components, but the circuit 231 may have a function as a correlated double sampling circuit (CDS circuit), and the circuit 232 may have a function as an A / D converter.

[0049] The pixel array 210 includes a plurality of pixel blocks 211. Each pixel block 211 is electrically connected to the circuit 221 via the wiring 204 and electrically connected to the circuit 222 via the wiring 205. The wirings 204 and 205 can function as signal lines for controlling the conduction of transistors. Each pixel block 211 is also electrically connected to the circuit 223 via the wiring 201 and electrically connected to the circuit 231 via the wiring 202.

[0050] The circuit 232 is electrically connected to the circuit 231 via the wiring 207, and the circuit 232 has a function of outputting a signal DOUT to the outside of the imaging device 200 via the wiring 208.

[0051] As shown in FIG. 2, the pixel block 211 has a plurality of pixels 100 arranged in a matrix (also referred to as a matrix), and a circuit 110. Each pixel 100 is electrically connected to the circuit 110 via a wiring 101.

[0052] Each of the pixels 100 has a photoelectric conversion device and has a function of converting incident light into an electrical signal (referred to as a first signal). Further, the pixel 100 has a function of generating a second signal obtained by binarizing the first signal, and has a function of generating a third signal obtained by multiplying the second signal by a weight coefficient.

[0053] In FIG. 2, a case where the pixel block 211 has 3 rows and 3 columns (9 pixels) is shown, but this is only an example and is not limited thereto. For example, the pixel block 211 may have 2 rows and 2 columns (4 pixels), or may have 4 rows and 4 columns (16 pixels). Alternatively, the number of pixels 100 in the row direction and the column direction may be different. Alternatively, some of the pixels 100 may be shared by adjacent pixel blocks 211.

[0054] The 3 - row and 3 - column pixels 100 each output a third signal obtained by multiplying the second signal by a weight coefficient to the wiring 101, and the third signals output from the pixels 100 to the wiring 101 are added together in the wiring 101. As a result of the addition in the wiring 101, the generated signal is an analog signal, and the analog signal is read out by the circuit 110 and output to the wiring 202.

[0055] The circuit 110 has a switch SW3 and transistors 21 to 23.

[0056] One terminal of the gate of transistor 21 and one terminal of switch SW3 are electrically connected to wiring 101. One of the source or drain of transistor 21 is electrically connected to one of the source or drain of transistor 22. The other of the source or drain of transistor 22 is electrically connected to one of the source or drain of transistor 23 and to wiring 202. Note that transistors 21 to 23 can be p-channel type transistors.

[0057] The other terminal of switch SW3 is electrically connected to wiring 111. The other of the source or drain of transistor 21 is electrically connected to wiring 112. The gate of transistor 22 is electrically connected to wiring SELBL. The gate of transistor 23 is electrically connected to wiring VBL, and the other of the source or drain of transistor 23 is electrically connected to wiring 113.

[0058] Wirings 111 to 113 and wiring VBL can function as power supply lines or lines to which a potential is supplied. For example, wiring 111 and wiring VBL can function as lines to which a predetermined potential is supplied, wiring 112 can function as a low potential power supply line, and wiring 113 can function as a high potential power supply line. Note that the predetermined potential supplied to wiring 111 and wiring VBL can function as an adjustment potential or a bias potential in circuit 110. Also, wiring SELBL functions as a signal line for transmitting signal SELB.

[0059] <Configuration example of pixel 100> FIG. 3A is a schematic diagram showing a configuration example of pixel 100, and FIG. 3B is a circuit diagram showing a configuration example of pixel 100. As shown in FIG. 3A, pixel 100 has a structure in which circuit 100a is laminated above circuit 100b.

[0060] The circuit 100b can be configured using, for example, transistors formed on a substrate. As the substrate, a single-crystalline semiconductor substrate made of silicon, silicon carbide, etc., a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, etc. can be used. Also, as the substrate, an SOI substrate, a substrate provided with semiconductor elements such as a strained transistor or a FIN type transistor on a semiconductor substrate, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used. Further, a flexible substrate (flexible substrate) may be used as the substrate. In the present embodiment, the case where a single-crystalline silicon substrate is used as the substrate will be described. Note that a transistor having silicon in the channel formation region is called an Si transistor.

[0061] The circuit 100a is preferably configured using an OS transistor. Since the OS transistor can be formed using a technique such as a thin film method, the circuit 100a can be provided by being laminated above the circuit 100b. That is, the area of the pixel 100 can be reduced.

[0062] Alternatively, the circuit 100a may be configured using transistors formed on a substrate, similar to the circuit 100b. For example, the circuit 100a may be configured using transistors formed on a substrate different from the circuit 100b, and later, the substrate having the circuit 100b and the substrate having the circuit 100a may be bonded together.

[0063] Here, since the bandgap of the oxide semiconductor is 2 eV or more, the OS transistor has the characteristics of having a small leakage current due to thermal excitation and a very small off-current. The OS transistor can have an off-current per channel width of 1 μm, for example, 100 zA / μm or less, or 10 zA / μm or less, or 1 zA / μm or less, or 10 yA / μm or less. Further, the off-current of the OS transistor has the characteristic of being difficult to increase even in a high-temperature environment. For example, even in a temperature environment from room temperature to 200 °C, the off-current of the OS transistor hardly increases.

[0064] In addition, the OS transistor has characteristics such that the on-current is less likely to decrease even in a high-temperature environment and the breakdown voltage between the source and the drain is high. That is, by configuring the circuit 100a using the OS transistor, high reliability can be obtained even in a high-temperature environment. Further, by configuring the circuit 100a using the OS transistor, the circuit 100a can be made a highly reliable circuit even when a high voltage is required for a photoelectric conversion device (described later) included in the circuit 100a.

[0065] In addition, it is not necessary to use a process with a high breakdown voltage for the transistors constituting the circuit 100b. The transistors constituting the circuit 100b can be miniaturized.

[0066] Note that the metal oxide used for the channel formation region of the OS transistor is preferably an oxide semiconductor containing at least one of indium (In) and zinc (Zn). As such an oxide semiconductor, In-M-Zn oxide (element M is, for example, Al, Ga, Y, or Sn) is typical. By reducing impurities such as moisture and hydrogen that serve as electron donors (donors) and also reducing oxygen deficiency, the oxide semiconductor can be made an i-type (intrinsic) or substantially i-type. Such an oxide semiconductor can be called a highly purified oxide semiconductor. Details of the OS transistor will be described in Embodiment 2 and Embodiment 3.

[0067] <circuit 100a> The circuit 100a includes a photoelectric conversion device 121, transistors 11 to 15, and a capacitor C11.

[0068] One electrode of the photoelectric conversion device 121 is electrically connected to one of the source or drain of the transistor 11. The other of the source or drain of the transistor 11 is electrically connected to one of the source or drain of the transistor 12, the gate of the transistor 13, and one electrode of the capacitor C11. The one of the source or drain of the transistor 13 is electrically connected to one of the source or drain of the transistor 14. The other of the source or drain of the transistor 14 is electrically connected to one of the source or drain of the transistor 15 and the wiring 107.

[0069] The other electrode of the photoelectric conversion device 121 is electrically connected to a wiring 104. The other of the source and the drain of the transistor 12 is electrically connected to a wiring 102. The other electrode of the capacitor C11 is electrically connected to a wiring 105. The other of the source and the drain of the transistor 13 is electrically connected to a wiring 106. The other of the source and the drain of the transistor 15 is electrically connected to a wiring 103.

[0070] Note that the wirings 102 to 106 can function as power supply lines or wirings to which a potential is supplied. For example, the wirings 102 and 103 can function as high-potential power supply lines, the wiring 105 can function as a wiring to which a predetermined potential is supplied, and the wirings 104 and 106 can function as low-potential power supply lines. The wirings 102 and 103 may be electrically connected, and the wirings 104 and 106 may be electrically connected. Alternatively, the wirings 104 to 106 may be electrically connected.

[0071] A gate of the transistor 11 is electrically connected to a wiring TXL. A gate of the transistor 12 is electrically connected to a wiring RESL. A gate of the transistor 14 is electrically connected to a wiring EVAL. A gate of the transistor 15 is electrically connected to a wiring PREL.

[0072] Note that the wiring TXL has a function as a signal line for transmitting the signal TX, the wiring RESL has a function as a signal line for transmitting the signal RES, the wiring EVAL has a function as a signal line for transmitting the signal EVA, and the wiring PREL has a function as a signal line for transmitting the signal PRE.

[0073] Here, an electrical connection point between the other of the source or drain of the transistor 11, one of the source or drain of the transistor 12, one electrode of the capacitor C11, and the gate of the transistor 13 is referred to as a node NFD.

[0074] As the photoelectric conversion device 121, a photodiode can be used. Regardless of the type of photodiode, an Si photodiode having silicon in the photoelectric conversion layer, an organic photodiode having an organic photoconductive film in the photoelectric conversion layer, etc. can be used. Note that when it is desired to enhance the light detection sensitivity in low illuminance, it is preferable to use an avalanche photodiode. Further, as the photoelectric conversion device 121, a variable resistor utilizing the photoelectric effect may be formed using silicon, germanium, selenium, or the like.

[0075] The transistor 12 can have a function of initializing the potential of the node NFD. The transistor 11 can have a function of controlling the potential of the node NFD. The transistor 15 can have a function of initializing the potential of the wiring 107. The transistors 13 and 14 can have a function of controlling the potential of the wiring 107. Note that the transistors 11 to 15 can be n-channel type transistors.

[0076] Further, transistors 13 to 15 can form a dynamic logic inverter 120. Transistor 15 initializes the potential of wiring 107, and transistor 13 has its conduction state controlled according to the potential (first signal) of node NFD, so that the dynamic logic inverter 120 can have the function of outputting either the high-potential power supply supplied via wiring 103 or the low-potential power supply supplied via wiring 106 to wiring 107. That is, the dynamic logic inverter 120 can output a binary signal (second signal).

[0077] <Circuit 100b> Circuit 100b includes an XNOR circuit 122, a switch SW1, and a switch SW2, and a capacitor C12.

[0078] One input terminal of the XNOR circuit 122 is electrically connected to the wiring 107, the other input terminal of the XNOR circuit 122 is electrically connected to the wiring WL, and the output terminal of the XNOR circuit 122 is electrically connected to one terminal of the switch SW1. The other terminal of the switch SW1 is electrically connected to one electrode of the capacitor C12 and one terminal of the switch SW2. The other terminal of the switch SW2 is electrically connected to the wiring 101.

[0079] The other electrode of the capacitor C12 is electrically connected to the wiring 108. The wiring 108 can function as a wiring to which a potential is supplied. For example, the wiring 108 can be made to function as a wiring to which a predetermined potential is supplied.

[0080] Note that the wiring WL can function as a wiring that supplies a potential corresponding to a weight coefficient. That is, the XNOR circuit 122 can have a function of outputting a product of the signal (second signal) output to the wiring 107 and the weight coefficient. The signal output by the XNOR circuit 122 has a function of controlling the potential of one electrode of the capacitor C12 when the switch SW1 is in the conducting state, and after the switch SW1 becomes non-conducting, the switch SW2 can be made conducting. When the switch SW2 is in the conducting state, the potential (third signal) of one electrode of the capacitor C12 is output to the wiring 101.

[0081] <Operation example of pixel block> FIG. 4 is a timing chart showing an operation example of the pixel block 211.

[0082] The timing chart shown in FIG. 4 shows the signals TX, RES, PRE, EVA, SELB, and the states of the switches SW1 to SW3. Note that the signals TX, RES, PRE, EVA, SELB are digital signals represented by a high level or a low level (which may be represented as High or Low, H or L, 1 or 0, etc.). In the timing chart shown in FIG. 4, the switches SW1 to SW3 represent a conducting state at a high level and a non-conducting state at a low level.

[0083] Also, the timing chart shown in FIG. 4 is divided into an imaging period Pimg of the pixel block 211 and a readout period Pread of the pixel block 211. Further, the imaging period Pimg can be divided into periods P1 to P4, and the readout period Pread can be divided into periods P5 to P8.

[0084] During the imaging period Pimg, the switches SW1 to SW3 are in a non-conducting state (low level), and the signal SELB is at a high level. In the circuit 110, the transistor 22 is in a non-conducting state.

[0085] During period P1 of imaging period Pimg, signal TX, signal RES, and signal PRE are at high levels, and signal EVA is at a low level. Transistor 12 initializes the potential of node NFD with the high-potential power supply supplied to wiring 102, and transistor 15 initializes the potential of wiring 107 with the high-potential power supply supplied to wiring 103. Transistor 14 is in a non-conductive state.

[0086] During period P2 of imaging period Pimg, signal TX and signal RES are at low levels, signal PRE is at a high level, and signal EVA is at a low level.

[0087] During period P3 of imaging period Pimg, signal TX is at a high level and imaging is performed. Signal PRE is at a high level, and signal RES and signal EVA are at low levels.

[0088] During period P4 of imaging period Pimg, signal TX and signal PRE are at low levels, signal EVA is at a high level, and signal RES is at a low level. Transistor 14 becomes conductive, and transistors 13 and 14 set the potential of wiring 107 to a potential corresponding to the potential of node NFD.

[0089] During read period Pread, signal TX, signal RES, signal PRE, and signal EVA are at low levels. Transistors 11, 12, 14, and 15 are in non-conductive states.

[0090] During period P5 of read period Pread, signal SELB is at a low level, and switches SW1 to SW3 are in non-conductive states (low levels). In circuit 110, transistor 22 becomes conductive.

[0091] During period P6 of the read period Pread, switch SW1 and switch SW3 are in the conductive state (high level), switch SW2 is in the non-conductive state (low level), and signal SELB is at the low level. The potential of one electrode of capacitor C12 becomes the potential output by XNOR circuit 122, and the potential of wiring 101 becomes a predetermined potential supplied to wiring 111.

[0092] During period P7 of the read period Pread, switch SW1 and switch SW3 are in the non-conductive state (low level), switch SW2 is in the conductive state (high level), and signal SELB is at the low level. In each of the nine pixels 100 included in pixel block 211, the potential of one electrode of capacitor C12 is output to wiring 101. The potential output to wiring 101 is added in wiring 101 to generate an analog signal. Circuit 110 outputs a potential corresponding to the potential of wiring 101 to wiring 202.

[0093] During period P8 of the read period Pread, switch SW2 is in the non-conductive state (low level), signal SELB is at the high level, and switch SW1 and switch SW3 are in the non-conductive state (low level). In circuit 110, transistor 22 is in the non-conductive state.

[0094] <Imaging device> As described above, imaging device 200 includes a plurality of pixel blocks 211, and pixel block 211 includes a plurality of pixels 100 and a circuit 110. Each pixel 100 has a function of converting incident light into an electrical signal (first signal), a function of generating a second signal obtained by binarizing the first signal, and a function of generating a third signal obtained by multiplying the second signal by a weighting coefficient. Further, by each of the plurality of pixels 100 outputting the third signal to wiring 101, the third signal is added in wiring 101 to generate an analog signal. The analog signal is input to circuit 110.

[0095] That is, the pixel block 211 can have a function of performing a multiplication and addition operation that multiplies the first signal generated by the light incident on each of the pixels 100 by a weight coefficient in the BNN method. In the pixel block 211, since a plurality of pixels 100 output a third signal, an analog signal obtained by adding the third signals is generated, so that the circuit scale of the addition circuit can be reduced.

[0096] Further, in the pixel 100, by configuring the circuit 100a having a photoelectric conversion device using an OS transistor, the circuit 100a can be made a highly reliable circuit. Also, the transistors constituting the circuit 100b can be miniaturized. Therefore, in the schematic diagram showing the configuration example of the pixel 100 shown in FIG. 3A, the areas of the circuit 100a and the circuit 100b are made the same, but this is not always the case. Since the transistors constituting the circuit 100b can be miniaturized, the area of the circuit 100b can be made smaller than the area of the circuit 100a.

[0097] For example, FIG. 5A shows a schematic diagram showing a configuration example of the pixel block 211 when the areas of the circuit 100a and the circuit 100b are the same. In FIG. 5A, since the areas of the circuit 100a and the circuit 100b are the same, a state where the circuit 110 is provided outside the pixel 100 is shown. Next, FIG. 5B shows a schematic diagram showing a configuration example of the pixel block 211 when the area of the circuit 100b is smaller than the area of the circuit 100a. FIG. 5B shows a state where nine circuit 100bs and the circuit 110 are provided below nine circuit 100as. Note that the circuits provided below the nine circuit 100as are not limited to the nine circuit 100bs and the circuit 110, and other functional circuits may be provided.

[0098] Note that this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0099] (Embodiment 2) In this embodiment, a structural example of an imaging device according to an aspect of the present invention will be described.

[0100] <Structural Example> FIG. 6A is a diagram showing an example of the structure of a pixel of an imaging device, and it can be a stacked structure of layer 561 and layer 563.

[0101] Layer 561 has a photoelectric conversion device 121. The photoelectric conversion device 121 can have layer 565a and layer 565b as shown in FIG. 7A. In some cases, a layer may be equivalently referred to as a region.

[0102] The photoelectric conversion device 121 shown in FIG. 7A is a pn junction type photodiode. For example, a p-type semiconductor can be used for layer 565a and an n-type semiconductor can be used for layer 565b. Alternatively, an n-type semiconductor can be used for layer 565a and a p-type semiconductor can be used for layer 565b.

[0103] The above pn junction type photodiode can typically be formed using single crystal silicon.

[0104] Also, the photoelectric conversion device 121 included in layer 561 may be a stack of layer 566a, layer 566b, layer 566c, and layer 566d as shown in FIG. 7B. The photoelectric conversion device 121 shown in FIG. 7B is an example of an avalanche photodiode. Layer 566a and layer 566d correspond to electrodes, and layer 566b and layer 566c correspond to a photoelectric conversion section.

[0105] Layer 566a is preferably a low-resistance metal layer or the like. For example, aluminum, titanium, tungsten, tantalum, silver, or a stack thereof can be used.

[0106] For layer 566d, it is preferable to use a conductive layer having high light transmittance for visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, or graphene can be used. Note that a configuration in which layer 566d is omitted is also possible.

[0107] The layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction photodiode using, for example, a selenium-based material as the photoelectric conversion layer. It is preferable to use a selenium-based material that is a p-type semiconductor for layer 566b and a gallium oxide or the like that is an n-type semiconductor for layer 566c.

[0108] A photoelectric conversion device using a selenium-based material has the characteristic of high external quantum efficiency for visible light. In this photoelectric conversion device, by utilizing avalanche multiplication, the amplification of electrons with respect to the amount of incident light can be increased. Further, since the selenium-based material has a high light absorption coefficient, it has production advantages such as being able to fabricate the photoelectric conversion layer as a thin film. The thin film of the selenium-based material can be formed using a vacuum evaporation method, a sputtering method, or the like.

[0109] As the selenium-based material, crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, a compound of copper, indium, and selenium (CIS), or a compound of copper, indium, gallium, and selenium (CIGS) can be used.

[0110] The n-type semiconductor is preferably formed of a material having a wide bandgap and being transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed can be used. Further, these materials also have a function as a hole injection blocking layer and can also reduce the dark current.

[0111] Further, as shown in FIG. 7C, the photoelectric conversion device 121 included in layer 561 may be a laminate of layer 567a, layer 567b, layer 567c, layer 567d, and layer 567e. The photoelectric conversion device 121 shown in FIG. 7C is an example of an organic photoconductive film. Layer 567a is a lower electrode, layer 567e is a transparent upper electrode, and layers 567b, 567c, and 567d correspond to the photoelectric conversion unit.

[0112] Either one of the layers 567b and 567d of the photoelectric conversion unit can be a hole transport layer, and the other can be an electron transport layer. Also, the layer 567c can be a photoelectric conversion layer.

[0113] As the hole transport layer, for example, molybdenum oxide or the like can be used. As the electron transport layer, for example, C 60 、C 70 such as fullerenes, or their derivatives or the like can be used.

[0114] As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.

[0115] As the layer 563 shown in FIG. 6A, for example, a silicon substrate can be used. The silicon substrate has an Si transistor or the like. Using the Si transistor, a pixel circuit can be formed. Also, a circuit for driving a pixel circuit or the like, a readout circuit of the pixel circuit, an image processing circuit, a neural network, a communication circuit, etc. can be formed.

[0116] Also, a memory circuit such as a DRAM (Dynamic Random Access Memory), a CPU (Central Processing Unit), an MCU (Micro Controller Unit), etc. may be formed. In this embodiment, the circuit 100a and the circuit 100b described in Embodiment 1 are called pixel circuits, and the other above circuits are called functional circuits.

[0117] For example, in the transistors included in the circuit 100a, the circuit 100b, and the circuit 110, some or all of them can be provided in the layer 563.

[0118] Further, as shown in FIG. 6B, the layer 563 may be a stack of a plurality of layers. In FIG. 6B, three layers, i.e., layer 563a, layer 563b, and layer 563c, are illustrated, but it may also be two layers. Alternatively, the layer 563 may be a stack of four or more layers. These layers can be laminated using, for example, a bonding process or the like. With this configuration, the pixel circuit and the functional circuit can be dispersed in a plurality of layers and the pixel circuit and the functional circuit can be provided in an overlapping manner, so that a small-sized and highly functional imaging device can be manufactured.

[0119] Further, as shown in FIG. 6C, the pixel may have a stacked structure of the layer 561, the layer 562, and the layer 563.

[0120] The layer 562 can have an OS transistor. For example, the circuit 100a can be formed on the layer 562, and the circuit 100b can be formed on the layer 563. Also, one or more of the above-described functional circuits may be formed of an OS transistor. Alternatively, one or more of the functional circuits may be formed using the Si transistor included in the layer 563 and the OS transistor included in the layer 562. Alternatively, the layer 563 may be used as a support substrate such as a glass substrate, and the pixel circuit and the functional circuit may be formed of the OS transistors included in the layer 562.

[0121] For example, a normally-off CPU (also referred to as a "Noff-CPU") can be realized using an OS transistor and an Si transistor. Note that a Noff-CPU is an integrated circuit including a normally-off type transistor that is in a non-conductive state (also referred to as an off state) even when the gate voltage is 0V.

[0122] The Noff-CPU can stop the power supply to the unnecessary circuits within the Noff-CPU and put the circuits into a standby state. In the circuits where the power supply is stopped and in the standby state, no power is consumed. Therefore, the Noff-CPU can minimize the power consumption. Also, the Noff-CPU can retain the necessary information such as setting conditions for a long time even when the power supply is stopped. To resume from the standby state, it is only necessary to resume the power supply to the circuits, and there is no need to rewrite the setting conditions, etc. That is, a high-speed resume from the standby state is possible. Thus, the Noff-CPU can reduce the power consumption without significantly reducing the operating speed.

[0123] Also, as shown in FIG. 6D, the layer 562 may be a stack of a plurality of layers. In FIG. 6D, two layers, i.e., the layer 562a and the layer 562b, are illustrated, but a stack of three or more layers may also be possible. These layers can be formed, for example, by stacking them on the layer 563. Alternatively, they may be formed by bonding the layer formed on the layer 563 and the layer formed on the layer 561.

[0124] As the semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more can be used. Typically, it is an oxide semiconductor containing indium, and for example, CAAC-OS or CAC-OS described later can be used. In CAAC-OS, the atoms constituting the crystal are stable, and it is suitable for transistors that emphasize reliability. Also, since CAC-OS exhibits high mobility characteristics, it is suitable for transistors that perform high-speed driving.

[0125] Since the OS transistor has a large energy gap in the semiconductor layer, it exhibits extremely low off-current characteristics of several yA / μm (current value per 1 μm channel width). In addition, the OS transistor has characteristics different from those of Si transistors, such as no impact ionization, avalanche breakdown, and short-channel effect, and can form a high-voltage and highly reliable circuit. Also, variations in electrical characteristics due to non-uniform crystallinity, which are a problem in Si transistors, are less likely to occur in OS transistors.

[0126] The semiconductor layer of the OS transistor can be, for example, a film represented by an In-M-Zn oxide containing indium, zinc, and M (M is one or more selected from metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn oxide can be formed, for example, using a sputtering method, an ALD (Atomic layer deposition) method, or an MOCVD (Metal organic chemical vapor deposition) method. Also, the semiconductor layer may be formed using a plasma-utilized ALD (PEALD (Plasma Enhanced ALD)) method.

[0127] When forming the In-M-Zn oxide by sputtering, it is preferable that the atomic ratio of the metal elements in the sputtering target satisfies In≧M and Zn≧M. As such atomic ratios of the metal elements in the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 10:1:3, etc. are preferable. Note that the atomic ratio of the formed semiconductor layer includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0128] As the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, the carrier density of the semiconductor layer is 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, even more preferably 1×10 11 / cm 3 or less, still more preferably 1×10 10 / cm 3 less than, and an oxide semiconductor of 1×10 -9 / cm 3 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low density of defect levels and stable characteristics.

[0129] Note that it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Also, in order to obtain the required semiconductor characteristics of the transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic number ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer appropriate.

[0130] In the oxide semiconductor constituting the semiconductor layer, if silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases and it becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0131] In addition, when an alkali metal and an alkaline earth metal combine with an oxide semiconductor, carriers may be generated, which may increase the off-current of the transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (the concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0132] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, increasing the carrier density and making it easy to form an n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (the concentration obtained by secondary ion mass spectrometry) is preferably 5×10 18 atoms / cm 3 or less.

[0133] In addition, when hydrogen is contained in the oxide semiconductor constituting the semiconductor layer, it reacts with oxygen that binds to metal atoms to form water, and thus oxygen vacancies may be formed in the oxide semiconductor. If the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies may function as donors, and electrons as carriers may be generated. Also, a part of hydrogen may combine with oxygen that binds to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.

[0134] Defects with hydrogen incorporated due to oxygen deficiency can function as donors in oxide semiconductors. However, it is difficult to quantitatively evaluate such defects. Therefore, in oxide semiconductors, evaluation may be performed using carrier concentration instead of donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, carrier concentration assuming a state where no electric field is applied may be used instead of donor concentration. That is, the "carrier concentration" described in this specification and the like may sometimes be paraphrased as "donor concentration".

[0135] Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 . By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0136] Further, the semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among non-single crystal structures, the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels.

[0137] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Or, an oxide film having an amorphous structure is, for example, a completely amorphous structure and has no crystal part.

[0138] Note that the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have, for example, a single layer structure or a laminated structure including any two or more of the above-described regions.

[0139] Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

[0140] CAC-OS is, for example, a configuration of a material in which elements constituting an oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. Note that hereinafter, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region having the metal element is mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof, which is also referred to as a mosaic state or a patch state.

[0141] Note that the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be contained.

[0142] For example, CAC-OS in In-Ga-Zn oxide (CAC-OS may be particularly referred to as CAC-IGZO among CAC-OS) means indium oxide (hereinafter, InO X1 (where X1 is a real number greater than 0)), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (where X2, Y2, and Z2 are real numbers greater than 0)), and gallium oxide (hereinafter, GaOX3 (where X3 is a real number greater than 0), or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are real numbers greater than 0), etc., the material separates into a mosaic shape, and the mosaic-shaped InO X1 , or In X2 Zn Y2 O Z2 is in a configuration uniformly distributed in the film (hereinafter, also referred to as a cloud shape).

[0143] That is, CAC-OS is a composite oxide semiconductor having a configuration in which a region mainly composed of GaO X3 and a region mainly composed of In X2 Zn Y2 O Z2 , or InO X1 are mixed. In this specification, for example, when the atomic ratio of In to the element M in the first region is greater than the atomic ratio of In to the element M in the second region, it is said that the first region has a higher In concentration than the second region.

[0144] Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a representative example, InGaO3(ZnO) m1 (where m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≤ x0 ≤ 1, m0 is an arbitrary number).

[0145] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.

[0146] On the one hand, CAC-OS relates to the material composition of an oxide semiconductor. CAC-OS refers to a structure in which, in a material composition containing In, Ga, Zn, and O, regions observed as nanoparticle-like with Ga as the main component in part and regions observed as nanoparticle-like with In as the main component in part are randomly dispersed mosaically. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0147] Note that CAC-OS does not include a laminated structure of two or more kinds of films with different compositions. For example, a structure composed of two layers, a film with In as the main component and a film with Ga as the main component, is not included.

[0148] Note that GaO X3 as the main component region and In X2 Zn Y2 O Z2 or InO X1 as the main component region may not have a clear boundary observable.

[0149] Note that when one or more kinds selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. are included instead of gallium, CAC-OS refers to a structure in which, in part, regions observed as nanoparticle-like with the metal element as the main component and, in part, regions observed as nanoparticle-like with In as the main component are randomly dispersed mosaically.

[0150] CAC-OS can be formed by sputtering, for example, under conditions where the substrate is not intentionally heated. Also, when forming CAC-OS by sputtering, any one or more selected from among inert gases (typically argon), oxygen gas, and nitrogen gas may be used as the film-forming gas. Further, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable it is. For example, it is preferable that the flow rate ratio of oxygen gas is 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0151] CAC-OS has the characteristic that no distinct peak is observed when measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. That is, it can be seen from the X-ray diffraction measurement that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region.

[0152] Also, for example, in CAC-OS in In-Ga-Zn oxide, in the electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high luminance in a ring shape (ring region) and a plurality of bright spots are observed in the ring region. Therefore, it can be understood from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction.

[0153] Also, for example, in CAC-OS in In-Ga-Zn oxide, by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), GaO X3 regions that are the main component and In X2 Zn Y2 O Z2 or regions where InO X1 is the main component are unevenly distributed and have a mixed structure.

[0154] CAC-OS has a structure different from that of the IGZO compound with uniformly distributed metal elements and has properties different from those of the IGZO compound. That is, CAC-OS has a structure in which regions mainly composed of, for example, GaO X3 are phase-separated from regions mainly composed of In X2 Zn Y2 O Z2 , or InO X1 , and the regions with each element as the main component are mosaic-shaped.

[0155] Here, the regions mainly composed of In X2 Zn Y2 O Z2 , or InO X1 have higher conductivity compared to the regions mainly composed of GaO X3 and the like. That is, when carriers flow through the regions mainly composed of In X2 Zn Y2 O Z2 , or InO X1 , the conductivity as an oxide semiconductor is exhibited. Therefore, when the regions mainly composed of In X2 Zn Y2 O Z2 , or InO X1 are distributed in a cloud-like manner in the oxide semiconductor, high field-effect mobility (μ) can be realized.

[0156] On the other hand, the regions mainly composed of GaO X3 and the like have higher insulation compared to the regions mainly composed of In X2 Zn Y2 O Z2 , or InO X1 . That is, when the regions mainly composed of GaO X3 and the like are distributed in the oxide semiconductor, the leakage current can be suppressed and good switching operation can be realized.

[0157] Therefore, when CAC-OS is used in a semiconductor device, the insulation caused by GaO X3 and the like, and In X2 Zn Y2 O Z2 , or InO X1The conductivity caused by [reason] acts complementarily to achieve a high on-current (I on ), and a high field-effect mobility (μ).

[0158] In addition, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0159] <Stacked Structure 1> Next, the stacked structure of the imaging device will be described with reference to a cross-sectional view. Note that the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be further included. Or, some of the elements shown below may be omitted. Also, the stacked structure shown below can be formed using a bonding process, a polishing process, etc. as necessary.

[0160] FIG. 8 is an example of a cross-sectional view of a laminate having layers 560, 561, layer 563, and having a bonding surface between layer 563a and layer 563b that constitute layer 563. [[ID=IS]]

[0161] <Layer 563b> Layer 563b has elements of circuit 100b provided on silicon substrate 610. Here, transistors 17, 18, and 19 are shown as part of the elements of circuit 100b. Transistors 17, 18, and 19 can constitute, for example, an XNOR circuit 122.

[0162] In layer 563b, silicon substrate 610, insulating layers 611, 612, 613,614, 615, 616, 617, 618 are provided. Also, conductive layer 619 is provided. Insulating layer 611 has a function as a protective film. Insulating layers 612, 613, 614, 615, 616, 617 have functions as interlayer insulating films and planarizing films. Insulating layer 618 and conductive layer 619 have functions as bonding layers. Conductive layer 619 is electrically connected to transistor 19.

[0163] As the protective film, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. As the interlayer insulating film and the planarizing film, for example, an inorganic insulating film such as a silicon oxide film, an organic insulating film such as an acrylic resin or a polyimide resin can be used. As the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. The bonding layer will be described later.

[0164] In addition, as the conductor that can be used for the wiring, electrodes, and plugs used for the electrical connection between devices, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc. can be appropriately selected and used. The conductor is not limited to a single layer, and may be a plurality of layers composed of different materials.

[0165] <layer 563a> Layer 563a has the elements of circuit 100a. Here, as part of the elements of circuit 100a, transistor 11 and transistor 14 are shown. In the cross-sectional view shown in FIG. 8, their electrical connection is not shown.

[0166] In layer 563a, a silicon substrate 632, insulating layers 631, 633, 634, 635, 637, 638 are provided. Also, conductive layers 636, 639 are provided.

[0167] Insulating layer 631 and conductive layer 639 have the function as a bonding layer. Insulating layers 634, 635, 637 have the function as an interlayer insulating film and a planarizing film. Insulating layer 633 has the function as a protective film. Insulating layer 638 has the function of insulating the silicon substrate 632 and the conductive layer 639. Insulating layer 638 can be formed of the same material as the other insulating layers. Also, insulating layer 638 may be formed of the same material as insulating layer 631.

[0168] The conductive layer 639 is electrically connected to the gate of the transistor 14 and the conductive layer 619. Also, the conductive layer 636 is electrically connected to the wiring 104 (see FIG. 3).

[0169] The Si transistor shown in FIG. 8 is of a fin type having a channel formation region on a silicon substrate (silicon substrates 610, 632). A cross-section in the channel width direction (the cross-section of A1 - A2 shown in layer 563a of FIG. 8) is shown in FIG. 9A. Note that the Si transistor may be of a planar type as shown in FIG. 9B.

[0170] Alternatively, as shown in FIG. 9C, it may be a transistor having a semiconductor layer 545 of a silicon thin film. The semiconductor layer 545 can be, for example, single-crystalline silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on the silicon substrate 632.

[0171] <layer 561> Layer 561 has a photoelectric conversion device 121. The photoelectric conversion device 121 can be formed on layer 563a. In FIG. 8, as the photoelectric conversion device 121, a configuration using the organic photoconductive film shown in FIG. 7C as the photoelectric conversion layer is shown. Here, layer 567a is used as the cathode and layer 567e is used as the anode.

[0172] An insulating layer 651, 652, 653, 654, and a conductive layer 655 are provided in layer 561.

[0173] The insulating layers 651, 653, 654 have functions as an interlayer insulating film and a planarizing film. Also, the insulating layer 654 is provided to cover the end portion of the photoelectric conversion device 121 and also has a function of preventing a short circuit between layer 567e and layer 567a. The insulating layer 652 has a function as an element isolation layer. As the element isolation layer, it is preferable to use an organic insulating film or the like.

[0174] The layer 567a corresponding to the cathode of the photoelectric conversion device 121 is electrically connected to one of the source or drain of the transistor 11 included in the layer 563a. The layer 567e corresponding to the anode of the photoelectric conversion device 121 is electrically connected to the conductive layer 636 included in the layer 563a via the conductive layer 655.

[0175] <layer 560> The layer 560 is formed on the layer 561. The layer 560 has a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0176] The light-shielding layer 671 can suppress the inflow of light into adjacent pixels. As the light-shielding layer 671, a metal layer such as aluminum or tungsten can be used. Further, a dielectric film having a function as an antireflection film may be laminated on the metal layer.

[0177] A color filter can be used for the optical conversion layer 672. By assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel of the color filter, a color image can be obtained. For example, as shown in the perspective view (including a cross section) of FIG. 15A, the color filter 672R (red), the color filter 672G (green), and the color filter 672B (blue) can be assigned to different pixels.

[0178] Further, if a polarization element is used for the optical conversion layer 672, an imaging device that can obtain an image composed of light vibrating in a specific direction can be obtained. Furthermore, by performing arithmetic processing using the circuits 100a, 100b, and 110, for example, inspection of the object surface using a neural network can be performed with high performance.

[0179] Further, if a wavelength cut filter is used for the optical conversion layer 672, an imaging device that can obtain images in various wavelength regions can be obtained.

[0180] For example, if an infrared filter that blocks light with a wavelength equal to or shorter than that of visible light is used for the optical conversion layer 672, an infrared imaging device can be obtained. Also, if a filter that blocks light with a wavelength equal to or shorter than that of near-infrared light is used for the optical conversion layer 672, a far-infrared imaging device can be obtained. Further, if an ultraviolet filter that blocks light with a wavelength equal to or longer than that of visible light is used for the optical conversion layer 672, an ultraviolet imaging device can be obtained.

[0181] Note that a plurality of different optical conversion layers may be arranged within a single imaging device. For example, as shown in FIG. 15B, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an infrared filter 672IR can be assigned to different pixels, respectively. In this configuration, a visible light image and an infrared light image can be acquired simultaneously.

[0182] Alternatively, as shown in FIG. 15C, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an ultraviolet filter 672UV can be assigned to different pixels, respectively. In this configuration, a visible light image and an ultraviolet light image can be acquired simultaneously.

[0183] Also, if a scintillator is used for the optical conversion layer 672, an imaging device can be obtained that acquires an image visualizing the intensity of radiation used in an X-ray imaging device or the like. When radiation such as X-rays transmitted through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is acquired by detecting the light with the photoelectric conversion device 121. Further, an imaging device having such a configuration may be used for a radiation detector or the like.

[0184] A scintillator contains a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible light or ultraviolet light. For example, those obtained by dispersing Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc. in resins or ceramics can be used.

[0185] A microlens array 673 is provided on the optical conversion layer 672. Light passing through the individual lenses of the microlens array 673 passes through the optical conversion layer 672 directly below and is irradiated onto the photoelectric conversion device 121. By providing the microlens array 673, the condensed light can be incident on the photoelectric conversion device 121, so that photoelectric conversion can be performed efficiently. The microlens array 673 is preferably formed of a resin or glass that is highly transparent to light of the wavelength of the imaging target.

[0186] <Lamination> Next, the lamination of the layer 563b and the layer 563a will be described.

[0187] An insulating layer 618 and a conductive layer 619 are provided on the layer 563b. The conductive layer 619 has a region embedded in the insulating layer 618. Also, the surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that their heights match.

[0188] An insulating layer 631 and a conductive layer 639 are provided on the layer 563a. The conductive layer 639 has a region embedded in the insulating layer 631. Also, the surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that their heights match.

[0189] Here, the conductive layer June 19 and the conductive layer 639 preferably have the same metal element as the main component. Also, the insulating layer 618 and the insulating layer 631 are preferably composed of the same components.

[0190] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used for the conductive layers 619 and 639. From the ease of bonding, preferably Cu, Al, W, or Au is used. Also, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used for the insulating layers 618 and 631.

[0191] That is, the same metal material as described above is preferably used for the conductive layer 619 and the conductive layer 639. The same insulating material as described above is preferably used for the insulating layer 618 and the insulating layer 631. With this structure, the layer 563b and the layer 563a can be bonded together at the boundary between them.

[0192] The conductive layers 619 and 639 may have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 618 and 631 may also have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

[0193] This bonding makes it possible to obtain electrical connection between the conductive layer 619 and the conductive layer 639. Furthermore, it is possible to obtain connection between the insulating layer 618 and the insulating layer 631 with sufficient mechanical strength.

[0194] To bond metal layers together, surface activated bonding can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are then brought into contact and bonded. Alternatively, diffusion bonding can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods create bonds at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0195] Furthermore, to bond insulating layers together, a hydrophilic bonding method can be used, in which high flatness is achieved by polishing or other methods, then surfaces that have been hydrophilically treated with oxygen plasma or other methods are brought into contact with each other to form a temporary bond, and the final bond is then achieved by dehydrating them through heat treatment.Hydrophilic bonding also creates bonds at the atomic level, so it is possible to obtain mechanically excellent bonds.

[0196] When bonding the layer 563b and the layer 563a, an insulating layer and a metal layer are mixed on each bonding surface, so that, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0197] For example, methods such as cleaning the surface after polishing, performing an antioxidant treatment on the surface of the metal layer, and then performing a hydrophilic treatment before bonding can be used. Also, the surface of the metal layer may be made of a metal with poor oxidation resistance such as Au, and a hydrophilic treatment may be performed. Note that bonding methods other than those described above may also be used.

[0198] By the above lamination, the elements of layer 563b and the elements of layer 563a can be electrically connected.

[0199] <Modification Example of Stacked Structure 1> FIG. 10 is a modification example of the stacked structure shown in FIG. 8, in which the configuration of the photoelectric conversion device 121 included in layer 561 and a part of the configuration of layer 563a are different, and there is also a bonding surface between layer 561 and layer 563a.

[0200] Layer 561 includes a photoelectric conversion device 121, insulating layers 661, 662, 664, 665, and conductive layers 685, 686.

[0201] The photoelectric conversion device 121 is a pn junction type photodiode formed on a silicon substrate, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. The photoelectric conversion device 121 is an embedded type photodiode, and the dark current can be suppressed and the noise can be reduced by a thin p-type region (a part of layer 565b) provided on the surface side (current extraction side) of layer 565a.

[0202] The insulating layers 661, conductive layers 685, 686 have functions as bonding layers. The insulating layer 662 has functions as an interlayer insulating film and a planarization film. The insulating layer 664 has a function as an element isolation layer. The insulating layer 665 has a function of suppressing the outflow of carriers.

[0203] The silicon substrate is provided with grooves for separating pixels, and the insulating layer 665 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulating layer 665, it is possible to suppress the carriers generated in the photoelectric conversion device 121 from flowing out to adjacent pixels. In addition, the insulating layer 665 also has a function of suppressing the intrusion of stray light. Therefore, color mixing can be suppressed by the insulating layer 665. Note that an antireflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0204] The element isolation layer can be formed using the LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed using the STI (Shallow Trench Isolation) method or the like. As the insulating layer 665, for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic can be used. Note that the insulating layer 665 may have a multilayer structure. Note that a configuration without providing an element isolation layer can also be adopted.

[0205] The layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 121 is electrically connected to the conductive layer 685. The layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 686. The conductive layers 685 and 686 have regions embedded in the insulating layer 661. In addition, the surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that their heights are the same.

[0206] In the layer 563a, an insulating layer 638 is formed on the insulating layer 637. In addition, a conductive layer 683 electrically connected to one of the source or drain of the transistor 11 and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0207] The insulating layer 638 and the conductive layers 683 and 684 have the function as a bonding layer. The conductive layers 683 and 684 have regions embedded in the insulating layer 638. In addition, the surfaces of the insulating layer 638 and the conductive layers 683 and 684 are flattened so that their heights are the same.

[0208] Here, the conductive layers 683, 684, 685, and 686 are bonding layers similar to the aforementioned conductive layers 619 and 639. Also, the insulating layers 638 and 661 are bonding layers similar to the aforementioned insulating layers 618 and 631.

[0209] Therefore, by bonding the conductive layer 683 and the conductive layer 685, one of the source or drain of the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device and the transistor 11 can be electrically connected. Also, by bonding the conductive layer 684 and the conductive layer 686, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device and the wiring 104 (see FIG. 3) can be electrically connected. Further, by bonding the insulating layer 638 and the insulating layer 661, the electrical and mechanical bonding between the layer 561 and the layer 563a can be achieved.

[0210] <Stacked Structure 2> FIG. 11 is an example of a cross-sectional view of a laminate having layers 560, 561, 562, and 563 and not having a bonding surface. An Si transistor is provided in the layer 563. An OS transistor is provided in the layer 562. Since the configurations of the layer 563, the layer 561, and the layer 560 are the same as those shown in FIG. 8, the description is omitted here.

[0211] <Layer 562> The layer 562 is formed on the layer 563. The layer 562 has an OS transistor. Here, the transistor 11 and the transistor 14 are shown as part of the elements of the circuit 100a. In the cross-sectional view shown in FIG. 11, their electrical connection is not shown.

[0212] The layer 562 is provided with insulating layers 621, 622, 623, 624, 625, 626, and 628. Also, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to the wiring 104 (see FIG. 3).

[0213] The insulating layer 621 has a function as a blocking layer. The insulating layers 622, 623, 625, 626, and 628 have functions as an interlayer insulating film and a planarization film. The insulating layer 624 has a function as a protective film.

[0214] As the blocking layer, it is preferable to use a film having a function of preventing the diffusion of hydrogen. In an Si device, hydrogen is required to terminate dangling bonds, but hydrogen in the vicinity of an OS transistor becomes one of the factors generating carriers in the oxide semiconductor layer and deteriorates the reliability. Therefore, it is preferable to provide a hydrogen blocking film between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0215] As the blocking film, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0216] The gate of the transistor 14 is electrically connected to the wiring EVAL.

[0217] One of the source or drain of the transistor 11 is electrically connected to the layer 567a of the photoelectric conversion device 121 included in the layer 561. The conductive layer 627 is electrically connected to the layer 567e of the photoelectric conversion device 121 included in the layer 561.

[0218] The details of the OS transistor are shown in Fig. 12A. The OS transistor shown in Fig. 12A has a self-aligned structure in which an insulating layer is provided on a stack of an oxide semiconductor layer and a conductive layer, and source electrode 705 and drain electrode 706 are formed by providing an opening reaching the oxide semiconductor layer.

[0219] The OS transistor can be configured to include a channel formation region formed in an oxide semiconductor layer, a source region 703, and a drain region 704, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the opening.

[0220] As shown in FIG. 12B, the OS transistor may have a self-aligned structure in which the source region 703 and the drain region 704 are formed in the semiconductor layer using the gate electrode 701 as a mask.

[0221] Alternatively, as shown in FIG. 12C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0222] Although the OS transistor shows a structure having a back gate 535, it may also have a structure without a back gate. The back gate 535 may be electrically connected to the front gate of the transistor provided opposite thereto, as in the cross-sectional view in the channel width direction of the transistor shown in FIG. 12D. Note that FIG. 12D shows an example of the cross-section of B1 - B2 of the transistor in FIG. 12A, and the same applies to transistors with other structures. Also, it may be configured to supply a fixed potential different from that of the front gate to the back gate 535.

[0223] <Modification Example 1 of the Stacked Structure 2> FIG. 13 is a modification example of the stacked structure shown in FIG. 11, in which the configuration of the photoelectric conversion device 121 included in the layer 561 and a partial configuration of the layer 562 are different, and there is a bonding surface between the layer 561 and the layer 562.

[0224] The photoelectric conversion device 121 included in the layer 561 is a pn junction type photodiode formed on a silicon substrate and has the same configuration as that shown in FIG. 10.

[0225] In layer 562, an insulating layer 648 is formed on the insulating layer 628. Further, a conductive layer 688 electrically connected to one of the source or drain of the transistor 11, and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0226] The insulating layer 648, and the conductive layers 688 and 689 function as bonding layers. The conductive layers 688 and 689 have regions embedded in the insulating layer 648. Also, the surfaces of the insulating layer 648 and the conductive layers 688 and 689 are planarized so that their heights match respectively.

[0227] Here, the conductive layers 688 and 689 are bonding layers similar to the aforementioned conductive layers 619 and 639. Also, the insulating layer 648 is a bonding layer similar to the aforementioned insulating layers 618 and 631.

[0228] Therefore, by bonding the conductive layer 688 and the conductive layer 685, one of the source or drain of the transistor 11 can be electrically connected to the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device. Also, by bonding the conductive layer 689 and the conductive layer 686, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device can be electrically connected to the wiring 104 (see FIG. 3). Further, by bonding the insulating layer 648 and the insulating layer 661, electrical and mechanical bonding between the layer 561 and the layer 562 can be achieved.

[0229] When stacking a plurality of Si devices, polishing processes and bonding processes are required multiple times. Therefore, there are problems such as a large number of processes, the need for dedicated equipment, and low yield, and the manufacturing cost is also high. Since the OS transistor can be formed by stacking on a silicon substrate on which the device is formed, the bonding process can be reduced.

[0230] <Modification Example 2 of the Laminated Structure 2> FIG. 14 is a modification example of the laminated structure shown in FIG. 13, in which the configuration of the layer 561 and a part of the configuration of the layer 562 are different, and it has a bonding surface between the layer 561 and the layer 562.

[0231] In this modified example, the transistor 11 included in the circuit 100a is provided in the layer 561. In the layer 561, the transistor 11 is formed of an Si transistor. One of the source or drain of the transistor 11 is directly connected to the photoelectric conversion device 121, and the other of the source or drain acts as the node NFD.

[0232] In this case, in the layer 562, transistors are provided, excluding at least the transistor 11, among the transistors constituting the circuit 100a. FIG. 14 illustrates an example in which the transistors 13 and 14 are provided.

[0233] <Package, Module> FIG. 16A is an external perspective view of the upper surface side of a package containing an image sensor chip. The package includes a package substrate 410 for fixing the image sensor chip 450 (see FIG. 16C), a cover glass 420, an adhesive 430 for bonding the two, and the like.

[0234] FIG. 16B is an external perspective view of the lower surface side of the package. The lower surface of the package has a BGA (Ball Grid Array) with solder balls as bumps 440. Note that, not limited to BGA, it may have an LGA (Land Grid Array), a PGA (Pin Grid Array), or the like.

[0235] FIG. 16C is a perspective view of the package shown with a part of the cover glass 420 and the adhesive 430 omitted. Electrode pads 460 are formed on the package substrate 410, and the electrode pads 460 and the bumps 440 are electrically connected via through holes. The electrode pads 460 are electrically connected to the image sensor chip 450 by wires 470.

[0236] FIG. 16D is an external perspective view of the upper surface side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 for fixing an image sensor chip 451 (see FIG. 16F), a lens cover 421, a lens 435, and the like. An IC chip 490 (see FIG. 16F) having functions such as a drive circuit and a signal conversion circuit of the imaging device is also provided between the package substrate 411 and the image sensor chip 451, and has a configuration as a SiP (System in package).

[0237] FIG. 16E is an external perspective view of the lower surface side of the camera module. The lower surface and side surfaces of the package substrate 411 have a QFN (Quad flat no-lead package) configuration in which mounting lands 441 are provided. Note that this configuration is an example, and a QFP (Quad flat package) or the aforementioned BGA may be provided.

[0238] FIG. 16F is a perspective view of the module shown with a part of the lens cover 421 and the lens 435 omitted. The land 441 is electrically connected to the electrode pad 461, and the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 by a wire 471.

[0239] By housing the image sensor chip in a package having the above-described form, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0240] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0241] (Embodiment 3) As electronic devices that can use the imaging apparatus according to one embodiment of the present invention, there are a display device, a personal computer, an image storage device or an image playback device equipped with a recording medium, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a camera such as a digital still camera, a goggle type display (head-mounted display), a navigation system, an audio playback device (car audio, digital audio player, etc.), a copying machine, a facsimile machine, a printer, a printer multifunction machine, an automated teller machine (ATM), a vending machine, and the like. Specific examples of these electronic devices are shown in FIGS. 17A to 17F.

[0242] FIG. 17A shows an example of a mobile phone, which includes a housing 981, a display unit 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone is provided with a touch sensor on the display unit 982. Any operation such as making a call or inputting characters can be performed by touching the display unit 982 with a finger or a stylus. The imaging apparatus and its operation method according to one embodiment of the present invention can be applied to the mobile phone, and power consumption can be suppressed.

[0243] FIG. 17B shows a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, and the like. Information can be input and output by the touch panel function of the display unit 912. In addition, characters and the like can be recognized from an image acquired by the camera 919, and the characters can be output as audio by the speaker 913. The imaging apparatus and its operation method according to one embodiment of the present invention can be applied to the portable data terminal, and power consumption can be suppressed.

[0244] FIG. 17C is a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, etc. A rotation mechanism or the like is provided in the camera unit 952, and by installing it on the ceiling, imaging of the entire surrounding can be achieved. The imaging device and its operation method according to one embodiment of the present invention can be applied to the elements for image acquisition in the camera unit, and power consumption can be suppressed. Note that the surveillance camera is a common name and does not limit the use. For example, a device having the function of a surveillance camera is also called a camera or a video camera.

[0245] FIG. 17D is a video camera, which includes a first housing 971, a second housing 972, a display unit 973, operation keys 974, a lens 975, a connection part 976, a speaker 977, a microphone 978, etc. The operation keys 974 and the lens 975 are provided on the first housing 971, and the display unit 973 is provided on the second housing 972. The imaging device and its operation method according to one embodiment of the present invention can be applied to the video camera, and power consumption can be suppressed.

[0246] FIG. 17E is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light emitting part 967, a lens 965, etc. The imaging device and its operation method according to one embodiment of the present invention can be applied to the digital camera, and power consumption can be suppressed.

[0247] FIG. 17F is a wristwatch-type information terminal, which includes a display unit 932, a housing-cum-wristband 933, a camera 939, etc. The display unit 932 is provided with a touch panel for operating the information terminal. The display unit 932 and the housing-cum-wristband 933 have flexibility and excellent wearability on the body. The imaging device and its operation method according to one embodiment of the present invention can be applied to the information terminal, and power consumption can be suppressed.

[0248] This embodiment can be appropriately combined with the descriptions of other embodiments.

Description of Reference Numerals

[0249] C11: Capacitor, C12: Capacitor, DOUT: Signal, EVAL: Wiring, EVA: Signal, NFD: Node, RESL: Wiring, RES: Signal, PREL: Wiring, PRE: Signal, SELBL: Wiring, SELB: Signal, SW1: Switch, SW2: Switch, SW3: Switch, TXL: Wiring, TX: Signal, VBL: Wiring, WL: Wiring, 11: Transistor, 12: Transistor, 13: Transistor, 14: Transistor, 15: Transistor, 17: Transistor, 18: Transistor, 19: Transistor, 21: Transistor, 22: Transistor, 23: Transistor, 100: Pixel, 100a: Circuit, 100b: Circuit, 101: Wiring, 102: Wiring, 103: Wiring, 104: Wiring, 105: Wiring, 106: Wiring, 107: Wiring, 108: Wiring, 110: Circuit, 111: Wiring, 112: Wiring, 113: Wiring, 120: Dynamic Logic Inverter, 121: Photoelectric Conversion Device, 122: XNOR Circuit, 200: Imaging Device, 201: Wiring, 202: Wiring, 204: Wiring, 205: Wiring, 207: Wiring, 208: Wiring, 210: Pixel Array, 211: Pixel Block, 221: Circuit, 222: Circuit, 223: Circuit, 231: Circuit, 232: Circuit, 410: Package Substrate, 411: Package Substrate, 420: Cover Glass, 421: Lens Cover, 430: Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image Sensor Chip, 451: Image Sensor Chip, 460: Electrode Pad, 461: Electrode Pad, 470: Wire, 471: Wire, 490: IC Chip, 535: Back Gate, 545: Semiconductor Layer, 546: Insulating Layer, 560: Layer, 561: Layer, 562: Layer, 562a: Layer, 562b: Layer, 563: Layer, 563a: Layer, 563b: Layer, 563c: Layer, 565a: Layer, 565b: Layer, 566a: Layer, 566b: Layer, 566c: Layer, 566d: Layer, 567a: Layer, 567b: Layer, 567c: Layer, 567d: Layer, 567e: Layer, 610: Silicon Substrate, 611: Insulating Layer, 612: Insulating Layer, 613: Insulating Layer, 614: Insulating Layer, 615: Insulating Layer, 616: Insulating Layer, 617: Insulating Layer, 618: Insulating Layer, 619: Conductive Layer, 621: Insulating Layer, 622: Insulating Layer, 623: Insulating Layer, 624: Insulating Layer, 625: Insulating Layer, 626: Insulating Layer, 627: Conductive Layer, 628: Insulating Layer, 631: Insulating Layer,632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer, 637: insulating layer, 638: insulating layer, 639: conductive layer, 648: insulating layer, 651: insulating layer, 652: insulating layer, 653: insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer, 662: insulating layer, 664: insulating layer, 665: insulating layer, 671: light-shielding layer, 672 : optical conversion layer, 672B: color filter, 672G: color filter, 672IR: infrared filter, 672R: color filter, 672UV: ultraviolet filter, 673: microlens array, 683: conductive layer, 684: conductive layer, 685: conductive layer, 686: conductive layer, 688: conductive layer, 689: conductive layer, 701: gate electrode, 702: gate insulating film, 703: source region, 704: drain region, 705: source electrode, 706: drain electrode, 707: oxide semiconductor layer, 911: housing, 912: display unit, 913: speaker, 919: camera, 932: display unit, 933: housing / wristband, 939: camera, 951: support base, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting unit, 971: housing, 972: housing, 973: display unit, 974: operation keys, 975: lens, 976: connection unit, 977: speaker, 978: microphone, 981: housing, 982: display unit, 983: operation button, 984: external connection port, 985: speaker, 986: microphone, 987: camera,

Claims

1. having a plurality of pixel blocks, wherein the plurality of pixel blocks are arranged in a matrix, each of the pixel blocks having N (N is an integer of 1 or more) first circuits, N second circuits, a third circuit, and a first wiring electrically connected to the third circuit, each of the N first circuits having a photoelectric conversion device, the photoelectric conversion device having a function of converting incident light into an electrical signal, the K-th (K is an integer of 1 or more and N or less) first circuit having a function of outputting a first signal obtained by binarizing the electrical signal to the K-th second circuit, each of the N second circuits having a function of multiplying the first signal by a weight coefficient to generate a second signal and a function of outputting the second signal to the first wiring, the N second signals being added by being output to the first wiring, the third circuit having a function of outputting a third signal corresponding to the signal output to the first wiring, an imaging device, wherein a plurality of the third circuits included in one column of the plurality of pixel blocks have a function of outputting the third signal from a common second wiring.

2. The imaging device according to claim 1, wherein the K-th first circuit is provided by being stacked above the K-th second circuit.

3. The imaging device according to claim 1, wherein the N first circuits are provided by being stacked above the N second circuits and the third circuit.

4. The imaging device according to any one of claims 1 to 3, wherein each of the first circuits has a transistor, the transistor having a metal oxide in a channel formation region.

Images