Semiconductor device

Abstract

To provide a semiconductor device enabling the breakdown voltage of the termination region and the snapback characteristic be controlled.SOLUTION: A semiconductor device comprises a semiconductor part, a first electrode, a first control electrode, at least one second control electrode, and a control pad. The semiconductor part has an active region and a termination region. The first electrode is provided on a surface of the semiconductor part and located on the active region. The first control electrode is provided in the active region of the semiconductor part, facing the semiconductor part via a first insulating film. The second control electrode is provided on the termination region of the semiconductor part via a second insulating film and arranged to surround the first electrode. The control pad is provided separated from the first electrode on the surface of the semiconductor part, and electrically connected to the second control electrode. The semiconductor part includes a first semiconductor layer extending from the active region to the termination region. The second control electrode faces a part of the first semiconductor layer via the second insulating film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments relate to semiconductor devices.

Background Art

[0002] Power control semiconductor devices are required to have a large breakdown withstand voltage. For this purpose, it is important to appropriately control the breakdown voltage in the termination region and the so-called snap-back characteristics.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments provide a semiconductor device capable of controlling the breakdown voltage and snap-back characteristics in the termination region.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a semiconductor portion, a first electrode, a first control electrode, at least one second control electrode, a first control pad, and a second control pad. The semiconductor portion has an active region and a termination region, and in the surface of the semiconductor portion, the termination region surrounds the active region. The first electrode is provided on the surface of the semiconductor portion and is located on the active region. The first control electrode is provided in the active region of the semiconductor portion and faces the semiconductor portion via a first insulating film. The second control electrode is provided on the termination region of the semiconductor portion via a second insulating film. The first control pad is provided on the surface of the semiconductor portion at a distance from the first electrode and is electrically connected to the first control electrode. The second control pad is provided on the surface of the semiconductor portion at a distance from the first electrode and the first control pad and is electrically connected to the second control electrode. The semiconductor portion includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, and another fourth semiconductor layer. The first semiconductor layer extends from the active region to the termination region, the second semiconductor layer is provided between the first semiconductor layer and the first electrode in the active region, and faces the first control electrode via the first insulating film. The third semiconductor layer is partially provided between the second semiconductor layer and the first electrode and is electrically connected to the first electrode. The fourth semiconductor layer is provided on the first semiconductor layer in the termination region and surrounds the active region in the surface of the semiconductor portion. The another fourth semiconductor layer is provided on the first semiconductor layer at a distance from the fourth semiconductor layer in the termination region and surrounds the second semiconductor layer and the fourth semiconductor layer in the surface of the semiconductor portion. The second control electrode faces a part of the first semiconductor layer located between the fourth semiconductor layer and the another fourth semiconductor layer via the second insulating film.

Brief Description of the Drawings

[0006]

Figure 1

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BEST MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Also, even when representing the same part, the dimensions and ratios may be represented differently depending on the drawings.

[0008] Furthermore, the arrangement and configuration of each part will be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are perpendicular to each other and represent the X direction, Y direction, and Z direction, respectively. Also, there are cases where the Z direction is described as upward and the opposite direction as downward.

[0009] Figures 1(a) and (b) are schematic diagrams showing the semiconductor device 1 according to the embodiment. Figure 1(a) is a plan view showing the surface of the semiconductor device 1. Figure 1(b) is a cross-sectional view taken along the line A-A shown in Figure 1(a). The semiconductor device 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0010] As shown in Figure 1, the semiconductor device 1 includes a semiconductor part 10, an emitter electrode 20 (first electrode), a first control pad 30, a second control pad 40, a field plate 50, and an EQPR (Equivalent Potential Ring) electrode 60. The emitter electrode 20, the first control pad 30, the second control pad 40, the field plate 50, and the EQPR electrode 60 are, for example, metal layers containing aluminum or the like, and are provided on the surface of the semiconductor part 10.

[0011] The semiconductor part 10 includes, for example, an active region AR and a termination region TR. The termination region TR surrounds the active region AR within the surface of the semiconductor part 10. The semiconductor part 10 is, for example, silicon.

[0012] The emitter electrode 20 is provided on the active region AR. The first control pad 30 is, for example, a gate pad. The first control pad 30 is provided separated from the emitter electrode 20, for example, on the active region AR. A control wiring 33 is connected to the first control pad 30. The control wiring 33 is provided separated from the emitter electrode 20 and surrounds the emitter electrode 20.

[0013] The second control pad 40 is provided, for example, on the termination region TR. The second control pad 40 is provided separated from the emitter electrode 20 and the first control pad 30.

[0014] The field plate 50 is provided in the terminal region TR. The field plate 50 is provided separately from the first control pad 30, the control wiring 33, and the second control pad 40. The field plate 50 is provided, for example, outside the first control pad 30 and the control wiring 33 so as to surround the active region AR. In other words, the first control pad 30 and the control wiring 33 are located between the field plate 50 and the active region AR. In this example, the second control pad 40 and the field plate 50 are arranged so as to surround the active region AR.

[0015] The EQPR electrode 60 is provided outside the second control pad 40 and the field plate 50. That is, the second control pad 40 and the field plate 50 are located between the first control pad 30 and the control wiring 33 and the EQPR electrode 60. The EQPR electrode 60 is provided separately from the second control pad 40 and the field plate 50. The EQPR electrode 60 extends along the outer edge of the semiconductor part 10 and surrounds the second control pad 40 and the field plate 50.

[0016] As shown in FIG. 1(b), the semiconductor device 1 further includes a first control electrode 70, a second control electrode 80, and a collector electrode 90.

[0017] The first control electrode 70 is provided in the active region AR. The first control electrode 70 is, for example, a gate electrode. The first control electrode 70 is provided, for example, in the semiconductor part 10 between the emitter electrode 20 and the collector electrode 90. The first control electrode 70 is, for example, polysilicon having conductivity.

[0018] The first control electrode 70 is electrically insulated from the semiconductor part 10 by the first insulating film 73. The first insulating film 73 is, for example, a gate insulating film. Also, the first control electrode 70 is electrically insulated from the emitter electrode 20 by the interlayer insulating film 75. The first insulating film 73 and the interlayer insulating film 75 are, for example, silicon oxide films.

[0019] The second control electrode 80 is provided on the terminal region TR. The second control electrode 80 faces the surface of the semiconductor portion 10 via the second insulating film 85. The second control electrode 80 contains the same material as the first control electrode 70. The second control electrode 80 is, for example, polysilicon having conductivity. The second insulating film 85 is formed simultaneously with the first insulating film 73 and has a film thickness substantially the same as that of the first insulating film 73. The second insulating film 85 is, for example, a silicon oxide film.

[0020] The collector electrode 90 is provided on the back surface of the semiconductor portion 10. The collector electrode 90 is, for example, a metal layer containing nickel or the like.

[0021] The semiconductor portion 10 includes, for example, an n-type base layer 11, a p-type collector layer 17, a first guard ring layer 21, a second guard ring layer 23, and an EQPR layer 25. Hereinafter, the first conductivity type will be described as n-type and the second conductivity type as p-type. The first guard ring layer 21 and the second guard ring layer 23 are, for example, p-type silicon layers. The EQPR layer 25 is, for example, an n-type silicon layer.

[0022] The n-type base layer 11 (the first semiconductor layer) extends from the active region AR to the terminal region TR. The p-type collector layer 17 is provided between the n-type base layer 11 and the collector electrode 90. The collector electrode 90 is electrically connected to the p-type collector layer 17. The collector electrode 90 is, for example, ohmically connected to the p-type collector layer 17.

[0023] The first guard ring layer 21 (the fourth semiconductor layer) is provided on the n-type base layer 11 and surrounds the active region AR. The first guard ring layer 21 is provided, for example, between the n-type base layer 11 and the emitter electrode 20 and is electrically connected to the emitter electrode 20.

[0024] The second guard ring layer 23 (another fourth semiconductor layer) is provided between the n-type base layer 11 and the field plate 50 in the termination region TR. The second guard ring layer 23 is electrically connected to the field plate 50. The second guard ring layer 23 is provided outside the first guard ring layer 21 so as to surround the active region AR and the first guard ring layer 21. The second guard ring layer 23 is provided spaced apart from the first guard ring layer 21.

[0025] The EQPR layer 25 is provided between the n-type base layer 11 and the EQPR electrode 60. The EQPR electrode 60 is electrically connected to the EQPR layer 25. The EQPR layer 25 contains n-type impurities at a higher concentration than the concentration of the n-type impurities in the n-type base layer 11.

[0026] The second guard ring layer 23 is provided between the first guard ring layer 21 and the EQPR layer 25 on the surface side of the semiconductor part 10. The second control electrode 80 is provided to face a part of the n-type base layer 11 located between the first guard ring layer 21 and the second guard ring layer 23 via the second insulating film 85.

[0027] The semiconductor device 1 includes a plurality of second guard ring layers 23 and a plurality of field plates 50. The plurality of second guard ring layers 23 are each electrically connected to the plurality of field plates 50. The semiconductor device 1 further includes another second control electrode 80, and the another second control electrode 80 is provided to face another part of the n-type base layer 11 located between adjacent second guard ring layers 23 via another second insulating film 85.

[0028] The semiconductor device 1 further includes a resin layer 87 that covers the termination region TR. The emitter electrode 20 is exposed in the opening of the resin layer 87. The resin layer 87 is, for example, silicone and covers the termination region TR.

[0029] FIG. 2 is a schematic cross-sectional view showing the semiconductor device 1 according to the embodiment. FIG. 2 is a schematic diagram showing a cross-section of the active region AR in the semiconductor device 1.

[0030] As shown in FIG. 2, the emitter electrode 20 is provided on the surface 10F of the semiconductor portion 10. The collector electrode 90 is provided on the back surface 10B of the semiconductor portion 10. Also, the first control electrode 70 is disposed, for example, inside a trench TG provided on the surface 10F side of the semiconductor portion 10.

[0031] A first insulating film 73 is provided between the semiconductor portion 10 and the first control electrode 70. The first insulating film 73 is formed, for example, by thermally oxidizing the semiconductor portion 10. At this time, the termination region TR of the semiconductor portion 10 is also thermally oxidized, and a second insulating film 85 is formed. The second insulating film 85 is formed simultaneously with the first insulating film 73 and has a film thickness substantially the same as that of the first insulating film 73. The film thicknesses of the first insulating film 73 and the second insulating film 85 are, for example, 300 nanometers or less. That is, the first insulating film 73 and the second insulating film 85 have a thickness that induces an inversion layer or an accumulation layer at the interface between the semiconductor portion 10 and the first insulating film 73 and at the interface between the semiconductor portion 10 and the second insulating film 85, respectively.

[0032] An interlayer insulating film 75 is provided between the emitter electrode 20 and the first control electrode 70. The first control electrode 70 is electrically insulated from the emitter electrode and is electrically connected to the first control pad via the control wiring 33. The first control electrode 70 is electrically connected to the control wiring 33, for example, through a contact hole provided in the interlayer insulating film 75 at a portion not shown.

[0033] As shown in FIG. 2, the semiconductor portion 10 further includes a p-type base layer 13, an n-type emitter layer 15, and a p-type emitter layer 19.

[0034] The p-type base layer 13 (second semiconductor layer) is provided between the n-type base layer 11 and the emitter electrode 20. The p-type base layer 13 faces the first control electrode 70 through the first insulating film 73.

[0035] The n-type emitter layer 15 (third semiconductor layer) is provided between the p-type base layer 13 and the emitter electrode 20. The n-type emitter layer 15 is partially provided on the p-type base layer 13. The n-type emitter layer 15 is in contact with the first insulating film 73. The n-type emitter layer 15 is in contact with and electrically connected to the emitter electrode 20. The emitter electrode 20 is, for example, ohmically connected to the n-type emitter layer 15.

[0036] The p-type emitter layer 19 is partially provided between the p-type base layer 13 and the emitter electrode 20. The n-type emitter layer 15 and the p-type emitter layer 19 are arranged side by side on the p-type base layer 13. The p-type emitter layer 19 contains p-type impurities with a higher concentration than the concentration of the p-type impurities in the p-type base layer 13. The p-type emitter layer 19 is, for example, ohmically connected to the emitter electrode 20. The emitter electrode 20 is electrically connected to the p-type base layer 13 through the p-type emitter layer 19.

[0037] Figs. 3(a) and (b) are other schematic cross-sectional views showing the semiconductor device 1 according to the embodiment. Fig. 3(a) is a plan view showing the surface side of the semiconductor part 10. Fig. 3(b) is a cross-sectional view taken along the line B-B shown in Fig. 3(a).

[0038] As shown in Fig. 3(b), the semiconductor device 1 includes a plurality of second control electrodes 80A to 80G. Further, the semiconductor part 10 includes a plurality of second guard ring layers 23A to 23G. The second guard ring layers 23A to 23G are arranged in order in the direction from the first guard ring layer 21 toward the EQPR layer 25. The second control electrodes 80A to 80G are respectively provided so as to face a part of the n-type base layer 11 through the second insulating film 85.

[0039] The second control electrode 80A faces the first portion 11A of the n-type base layer 11 located between the first guard ring layer 21 and the second guard ring layer 23A.

[0040] The second control electrode 80B faces the second portion 11B of the n-type base layer 11 located between the second guard ring layer 23A and the second guard ring layer 23B.

[0041] The second control electrode 80C faces the third portion 11C of the n-type base layer 11 located between the second guard ring layer 23B and the second guard ring layer 23C.

[0042] The second control electrode 80D faces the fourth portion 11D of the n-type base layer 11 located between the second guard ring layer 23C and the second guard ring layer 23D.

[0043] The second control electrode 80E faces the fifth portion 11E of the n-type base layer 11 located between the second guard ring layer 23D and the second guard ring layer 23E.

[0044] The second control electrode 80F faces the sixth portion 11F of the n-type base layer 11 located between the second guard ring layer 23E and the second guard ring layer 23F.

[0045] The second control electrode 80G faces the seventh portion 11G of the n-type base layer 11 located between the second guard ring layer 23F and the second guard ring layer 23G.

[0046] In this example, the second control electrodes 80A, 80B, and 80C are electrically connected to the second control pad 40 through contact holes provided in the interlayer insulating film 75. That is, the semiconductor device 1 is configured to be able to control the potentials of the second control electrodes 80A, 80B, and 80C through the second control pad 40. On the other hand, during the operation of the semiconductor device 1, the second control electrodes 80D, 80E, 80F, and 80G have floating potentials.

[0047] Figs. 4(a) to 4(c) are schematic cross-sectional views showing semiconductor devices 2, 3, and 4 according to the first modification of the embodiment. Figs. 4(a) to 4(c) are cross-sectional views taken along the line A-A shown in Fig. 1(a).

[0048] The semiconductor device 2 shown in Fig. 4(a) includes the second control electrodes 80A, 80B, and 80C. The semiconductor device 2 is not provided with the second control electrodes 80D, 80E, 80F, and 80G (see Fig. 1(b)).

[0049] The semiconductor device 3 shown in FIG. 4(b) includes second control electrodes 80B and 80G. The semiconductor device 3 is not provided with second control electrodes 80A, 80C, 80D, 80E, and 80F (see FIG. 1(b)).

[0050] The semiconductor device 4 shown in FIG. 4(c) includes second control electrodes 80B and 80C. The semiconductor device 4 is not provided with second control electrodes 80A, 80D, 80E, 80F, and 80G (see FIG. 1(b)).

[0051] The arrangement of the second control electrodes 80A to 80G is not limited to the above example, and at least one of the second control electrodes 80A to 80G may be provided.

[0052] FIGS. 5(a) and 5(b) are schematic views showing a semiconductor device 4 according to a first modification of the embodiment. FIG. 5(a) is a plan view showing the surface side of the semiconductor portion 10. FIG. 5(b) is a cross-sectional view taken along the line C-C shown in FIG. 5(a).

[0053] As shown in FIG. 5(b), the second control electrodes 80B and 80C are electrically connected to the second control pad 40 through contact holes provided in the interlayer insulating film 75. That is, the semiconductor device 4 is configured to be able to control the potentials of the second control electrodes 80B and 80C through the second control pad 40.

[0054] FIGS. 6(a) and 6(b) are schematic views showing a semiconductor device 5 according to a second modification of the embodiment. FIG. 6(a) is a plan view showing the surface side of the semiconductor portion 10. FIG. 6(b) is a cross-sectional view taken along the line D-D shown in FIG. 6(a).

[0055] As shown in FIG. 6(a), the semiconductor device 5 includes second control pads 40A and 40B. The second control pads 40A and 40B are arranged side by side on the termination region TR and are spaced apart from each other. The second control pads 40A and 40B are provided on the interlayer insulating film 47 and are electrically insulated from the semiconductor portion 10.

[0056] As shown in FIG. 6(b), the semiconductor device 5 includes second control electrodes 80A to 80G. The second control electrodes 80A, 80B, 80C, and 80D are electrically connected to the second control pad 40A. Also, the second control electrodes 80F and 80G are electrically connected to the second control pad 40B.

[0057] In the semiconductor device 5, the potentials of the second control electrodes 80A, 80B, 80C, and 80D are controlled via the second control pad 40A. Also, the potentials of the second control electrodes 80F and 80G are controlled via the second control pad 40B. In this example, the potentials of the second control electrodes 80F and 80G can be controlled independently of the potentials of the second control electrodes 80A, 80B, 80C, and 80D.

[0058] On the other hand, during the operation of the semiconductor device 5, the potential of the second control electrode 80E becomes a floating potential. That is, the potential of the second control electrode 80E changes according to the respective potentials of the n-type base layer 11, the second guard ring layers 23D and 23E, the second control electrode 80D, and the second control electrode 80F.

[0059] FIGS. 7(a) and (b) are schematic views showing a semiconductor device 6 according to a third modification of the embodiment. FIG. 7(a) is a plan view showing the surface side of the semiconductor portion 10. FIG. 7(b) is a cross-sectional view taken along the line E-E shown in FIG. 7(a).

[0060] As shown in FIG. 7(a), the second control pad 40 is provided within the active region AR. For this reason, the field plate 50 is provided so as to surround the active region AR without interruption.

[0061] As shown in FIG. 7(b), the semiconductor device 6 includes second control electrodes 80A to 80D. In this example, the second control electrodes 80E to 80G are not provided. The second control electrodes 80A and 80B are electrically connected to the second control pad 40 via the control wiring 41. The control wiring 41 is provided within the interlayer insulating film 75.

[0062] In the semiconductor device 6, the potentials of the second control electrodes 80A and 80B are controlled via the second control pad 40. Further, during the operation of the semiconductor device 5, the respective potentials of the second control electrodes 80C and 80D become floating potentials.

[0063] FIGS. 8(a) and 8(b) are schematic views showing a semiconductor device 7 according to a fourth modification of the embodiment. FIG. 8(a) is a plan view showing the front surface side of the semiconductor portion 10. FIG. 8(b) is a cross-sectional view taken along the line F-F shown in FIG. 8(a).

[0064] As shown in FIG. 8(a), the semiconductor device 7 includes second control pads 40A and 40B. The second control pad 40A is provided on the active region AR. The second control pad 40B is provided on the termination region TR.

[0065] As shown in FIG. 8(b), the semiconductor device 7 includes second control electrodes 80A to 80D. In this example, the second control electrodes 80E to 80G are not provided. The second control electrodes 80A and 80B are electrically connected to the second control pad 40A via the control wiring 41. Also, the second control electrodes 80C and 80D are electrically connected to the second control pad 40B via contact holes provided in the interlayer insulating film 75.

[0066] In the semiconductor device 7, the potentials of the second control electrodes 80A and 80B are controlled via the second control pad 40A. Also, the potentials of the second control electrodes 80C and 80D are controlled via the second control pad 40B. Also in this example, the potentials of the second control electrodes 80C and 80D can be controlled independently of the potentials of the second control electrodes 80A and 80B.

[0067] FIGS. 9(a) to 9(c) are schematic views showing a semiconductor device 8 according to a fifth modification of the embodiment. FIG. 9(a) is a plan view showing the upper surface side of the semiconductor portion 10. FIG. 9(b) is a cross-sectional view taken along the line G-G shown in FIG. 9(a). FIG. 9(c) is a cross-sectional view taken along the line H-H shown in FIG. 9(a).

[0068] As shown in Fig. 9(a), the semiconductor device 8 includes second control pads 40A to 40D. The second control pads 40A and 40C are provided on the active region AR. The second control pad 40C is provided separately from the second control pad 40A. The second control pads 40B and 40D are provided on the termination region TR. The second control pad 40B is provided separately from the second control pad 40D.

[0069] As shown in Figs. 9(b) and (c), the second control pads 40A to 40D are electrically insulated from the semiconductor portion 10 by the interlayer insulating film 75. The semiconductor device 8 includes second control electrodes 80A to 80E and 80G. In this example, the second control electrode 80F is not provided.

[0070] As shown in Fig. 9(b), the second control electrodes 80A and 80B are electrically connected to the second control pad 40A via the control wiring 41. Also, the second control electrode 80G is electrically connected to the second control pad 40B via a contact hole provided in the interlayer insulating film 75.

[0071] As shown in Fig. 9(c), the second control electrode 80C is electrically connected to the second control pad 40C via the control wiring 43. Also, the second control electrodes 80D and 80E are electrically connected to the second control pad 40B via a contact hole provided in the interlayer insulating film 75.

[0072] In the semiconductor device 8, the potentials of the second control electrodes 80A and 80B are controlled via the second control pad 40A. The potential of the second control electrode 80C is controlled via the second control pad 40C. Also, the potentials of the second control electrodes 80D and 80E are controlled via the second control pad 40D, and the potential of the second control electrode 80G is controlled via the second control pad 40B.

[0073] Even in this example, the potentials of the second control electrodes 80A and 80B can be controlled independently of the potentials of the second control electrodes 80C, 80D, 80E, and 80G. Also, the potential of the second control electrode 80C can be controlled independently of the potentials of the second control electrodes 80A, 80B, 80D, 80E, and 80G. The potentials of the second control electrodes 80D and 80E can be controlled independently of the potentials of the second control electrodes 80A, 80B, 80C, and 80G. Furthermore, the potential of the second control electrode 80G can be controlled independently of the potentials of the second control electrodes 80A to 80E.

[0074] Figs. 10(a) to (c) are schematic diagrams showing the operation of the semiconductor device 1 according to the embodiment. Figs. 10(a) and (b) are partial cross-sectional views in the terminal region TR. Fig. 10(c) is a graph showing the voltage-current characteristics of the terminal region TR. The horizontal axis represents voltage, and the vertical axis represents current.

[0075] As shown in Fig. 10(a), when the potential of the second control electrode 80 is set to a negative potential with respect to the n-type base layer 11, a p-type inversion layer is induced at the interface between the n-type base layer 11 and the second insulating film 85. Therefore, the hole current Ih flows through the p-type inversion layer.

[0076] On the other hand, as shown in Fig. 10(b), when the potential of the second control electrode 80 is set to a positive potential with respect to the n-type base layer 11, a depletion region is formed at the interface between the n-type base layer 11 and the second insulating film 85, and the hole current Ih flows through a region away from the interface between the n-type base layer 11 and the second insulating film 85.

[0077] Thus, by controlling the potential of the second control electrode 80, the path of the hole current Ih flowing through the terminal region TR can be changed, and for example, impact ionization in the n-type base layer 11 can be suppressed.

[0078] As shown in FIG. 10(c), by controlling the potential of the second control electrode 80, the voltage-current characteristics in the terminal region can be changed. That is, by suppressing impact ionization in the terminal region TR, the avalanche breakdown voltage can be increased. Thereby, the snapback characteristics can be improved and the breakdown tolerance can be enhanced.

[0079] FIG. 11 is a schematic diagram showing a control method of the semiconductor device 1 according to the embodiment. FIG. 11 is a time chart showing the gate voltage Vg1 applied to the first control electrode 70 and the gate voltage Vg2 applied to the second control electrode 80.

[0080] For example, at time T1, a gate voltage Vg1 (positive voltage) higher than the threshold is applied to the first control electrode 70, and the semiconductor device 1 transitions (turns on) from the off state to the on state. Further, at time T2, the gate voltage Vg1 is lowered to a voltage lower than the threshold, for example, 0V, and the semiconductor device 1 transitions (turns off) from the on state to the off state.

[0081] On the other hand, the gate voltage Vg2 applied to the second control electrode 80 is held at, for example, 0V until time T3, which is after time T1 and before time T2 (Case1). Further, at time T3, the gate voltage Vg2 is lowered to a negative voltage. Thereafter, at time T4, which is after time T2, the gate voltage Vg2 returns to, for example, 0V.

[0082] According to such control, in the turn-off process of the semiconductor device 1, a p-type inversion layer is induced at the interface between the n-type base layer 11 and the second insulating film 85. Thereby, impact ionization in the terminal region TR can be suppressed and the breakdown tolerance of the semiconductor device 1 can be improved.

[0083] Also, as another control method (Case2), the gate voltage Vg2 may be held at a negative voltage and the gate voltage Vg2 may be further lowered to a lower voltage at time T3. Thereby, there may be a case where the breakdown tolerance of the semiconductor device 1 can be further improved.

[0084] Figs. 12(a) to 12(e) are other schematic views showing a method for controlling a semiconductor device according to an embodiment. Figs. 12(a) to 12(e) represent control examples of the second control electrodes 80A to 80Z. In the figure, the second control electrodes 80A to 80C, 80P to 80R, and 80X to 80Z are shown. Between the second control electrode 80C and the second control electrode 80P, at least one second control electrode 80 is provided. Between the second control electrode 80R and the second control electrode 80X, at least one second control electrode 80 is provided.

[0085] As shown in Fig. 12(a), a negative potential is applied to the second control electrode 80B, and a positive potential is applied to each of the other second control electrodes 80A, 80C to 80Z, or a floating potential is set.

[0086] As shown in Fig. 12(b), a negative potential is applied to the second control electrode 80Q, and a positive potential is applied to each of the other second control electrodes 80A to 80P, 80R to 80Z, or a floating potential is set.

[0087] As shown in Fig. 12(c), a negative potential is applied to the second control electrode 80Q, and the other second control electrodes 80A to 80P, 80R to 80Z are set to a floating potential FL.

[0088] As shown in Fig. 12(d), a negative potential is applied to the second control electrode 80Q, a positive potential Va is applied to the second control electrodes 80A, 80C to 80P, and the second control electrodes 80R to 80Z are set to a floating potential FL.

[0089] As shown in Fig. 12(e), a negative potential is applied to the second control electrode 80Q, different positive potentials Vd to Vf are applied to the second control electrodes 80A to 80C, respectively, a positive potential Vc is applied to the second control electrodes 80R, 80R, different positive potentials Va, Vb are applied to the second control electrodes 80X and 80Z, respectively, and the second control electrode 80Y is set to a floating potential FL.

[0090] Thus, by changing the potential applied to the plurality of second control electrodes 80, it is possible to control the avalanche breakdown voltage and snapback characteristics in the termination region TR of the semiconductor device 1. For example, impact ionization is likely to occur in the vicinity of the second control electrode 80 biased to a negative potential. In the region where the other second control electrodes 80 are provided, impact ionization is suppressed. That is, in the termination region TR, the region where avalanche breakdown occurs can be appropriately controlled.

[0091] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0092] 1, 2, 3, 4, 5, 6, 7, 8… semiconductor device, 10… semiconductor part, 10B… back surface, 10F… front surface, 11… n-type base layer, 11A… first part, 11B… second part, 11C… third part, 11D… fourth part, 11E… fifth part, 11F… sixth part, 11G… seventh part, 13… p-type base layer, 15… n-type emitter layer, 17… p-type collector layer, 19… p-type emitter layer, 20… emitter electrode, 21… first guard ring layer, 23, 23A, 23B, 23C, 23D, 23E, 23F, 23G… second guard ring layer, 25… EQPR layer, 30… first control pad, 33, 41, 43… control wiring, 40, 40A, 40B, 40C, 40D… second control pad, 47… interlayer insulating film, 50… field plate, 60… EQPR electrode, 70… first control electrode, 73… first insulating film, 75… interlayer insulating film, 80, 80A, 80B, 80C, 80D, 80F, 80G, 80P, 80Q, 80R, 80X, 80Y, 80Z… second control electrode, 85… second insulating film, 87… resin layer, 90… collector electrode, AR… active region, Ih… hole current, TG… trench, TR… termination region, Va, Vb, Vc, Vd, Ve, Vf… positive potential, FL… floating potential

Claims

1. A semiconductor part having an active region and a terminal region, wherein, within the surface of the semiconductor part, the terminal region surrounds the active region, and the semiconductor part and a first electrode provided on the surface of the semiconductor part and located above the active region, a first control electrode provided in the active region of the semiconductor part and facing the semiconductor part via a first insulating film, at least one second control electrode provided on the terminal region of the semiconductor part via a second insulating film, a first control pad provided on the surface of the semiconductor part at a distance from the first electrode and electrically connected to the first control electrode, a second control pad provided on the surface of the semiconductor part at a distance from the first electrode and the first control pad and electrically connected to the second control electrode, comprising the semiconductor part a first semiconductor layer of a first conductivity type extending from the active region to the terminal region, in the active region, a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first electrode and facing the first control electrode via the first insulating film, a third semiconductor layer of the first conductivity type partially provided between the second semiconductor layer and the first electrode and electrically connected to the first electrode, in the terminal region, a fourth semiconductor layer of the second conductivity type provided on the first semiconductor layer and surrounding the active region within the surface of the semiconductor part, in the terminal region, another fourth semiconductor layer provided on the first semiconductor layer at a distance from the fourth semiconductor layer and surrounding the second semiconductor layer and the fourth semiconductor layer within the surface of the semiconductor part, including the second control electrode faces a part of the first semiconductor layer located between the fourth semiconductor layer and the another fourth semiconductor layer via the second insulating film, a semiconductor device.

2. further comprising another second control electrode provided in the terminal region, the semiconductor part includes a plurality of the fourth semiconductor layers spaced apart from each other, the another second control electrode faces another part of the first semiconductor layer located between two adjacent fourth semiconductor layers among the plurality of fourth semiconductor layers via a second insulating film different from the second insulating film, the semiconductor device according to claim 1.

3. the another second control electrode is electrically connected to the second control pad, the semiconductor device according to claim 2.

4. provided on the surface of the semiconductor portion, further comprising a third control pad spaced apart from the first electrode, the first control pad, and the second control pad, The semiconductor device according to claim 2, wherein the another second control electrode is electrically connected to the third control pad.

5. The semiconductor device according to claim 2, wherein the fourth semiconductor layer provided at the position closest to the second semiconductor layer among the plurality of fourth semiconductor layers is provided to be connected to the second semiconductor layer.

6. The semiconductor device according to claim 1, wherein the second insulating film has a film thickness substantially the same as that of the first insulating film.

7. The semiconductor device according to claim 1, wherein the second control electrode contains the same material as the first control electrode.

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