Atomic Layer Deposition and Etching for Reducing Roughness

Abstract

To provide methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch methods.SOLUTION: A method of reducing sidewall roughness of high aspect ratio features comprises: providing a mask on a substrate, and then depositing a conformal layer on the mask by ALD to reduce roughness; etching a layer underlying the mask to form patterned features having the reduced roughness; etching the substrate to a first depth to form features at the first depth in the substrate, and then depositing a conformal layer by ALD on sidewalls of the features to protect the sidewalls and reduce the roughness during a subsequent etch process. The ALD and etch steps may be performed in a plasma chamber.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of priority to U.S. Patent Application No. 15 / 820,110, filed November 21, 2017, entitled "ATOMIC LAYER DEPOSITION AND ETCH FOR REDUCING ROUGHNESS", which is hereby incorporated by reference in its entirety for all purposes.

[0002] The present disclosure generally relates to integrated deposition and etching methods in the fabrication of semiconductor devices, and more particularly to integrated atomic layer deposition (ALD) and etching methods for controlling critical dimensions in the fabrication of integrated circuits.

Background Art

[0003] As device and feature sizes continue to shrink in the semiconductor industry, patterning of features with small critical dimensions continues to increase in importance in the fabrication of advanced integrated circuits (ICs). Current patterning methods can result in non - uniform surfaces and roughness, which can have an adverse effect on the performance of transistors or devices, and current processing techniques for reducing roughness can have an undesirable effect on the critical dimensions of pattern features.

Summary of the Invention

[0004] The present disclosure relates to a method for reducing roughness by patterning. The method includes depositing, in a plasma chamber, a first conformal layer on a pattern mask layer of a substrate by atomic layer deposition (ALD), where the substrate includes a first material layer and a pattern mask layer on the first material layer, and the pattern mask layer has a first roughness before depositing the first conformal layer. The method further includes etching the first material layer to form a plurality of first pattern features of the first material layer defined by the pattern mask layer, where the plurality of first pattern features have a second roughness that is smaller than the first roughness of the pattern mask layer after etching the first material layer.

[0005] In some implementations, the first roughness corresponds to a first line edge roughness (LER) and a first line width roughness (LWR), the second roughness corresponds to a second LER and a second LWR, the second LER is about 2.0 nm or less, and the second LWR is about 2.0 nm or less. In some implementations, the thickness of the first conformal layer is between about 0.5 nm and about 5 nm. In some implementations, the pattern mask layer is configured to define one or more one-dimensional (1-D) features from a first material layer and one or more two-dimensional (2-D) features from the first material layer, and the critical dimension (CD) bias between the one or more 1-D features and the one or more 2-D features is substantially the same after etching the first material layer. In some implementations, the pattern mask layer includes one or more sparse features within a sparse feature region and one or more dense features within a dense feature region having a feature density greater than the sparse feature region, and the CD bias between the one or more sparse features and the one or more dense features is substantially the same after etching the first material layer. In some implementations, the method further includes a second material layer underlying the first material layer. The method further includes depositing a second conformal layer on exposed surfaces of the plurality of first pattern features, the pattern mask layer, and the second material layer by ALD in a plasma chamber, and etching the second material layer of the substrate to form a plurality of second pattern features defined by the plurality of first pattern features in the plasma chamber. In some implementations, the plurality of second pattern features have a third roughness that is smaller than each of the first roughness and the second roughness. In some implementations, the critical dimension of the plurality of first pattern features is about 20 nm or less. In some implementations, depositing the first conformal layer by ALD includes introducing a precursor that adsorbs onto the pattern mask layer into the plasma chamber, converting the precursor by plasma to form a first conformal layer of a certain adsorption limit amount, repeating the operation of introducing the precursor, and converting the precursor until a first conformal layer of a desired thickness is deposited on the pattern mask layer.

[0006] The present disclosure also relates to a method for reducing sidewall roughness. The method includes etching a substrate to a first depth in a plasma chamber to form a plurality of structures at the first depth. The method further includes depositing a first passivation layer on sidewalls of a plurality of features by atomic layer deposition (ALD) in the plasma chamber. The method further includes etching the plurality of features in the plasma chamber to a second depth greater than the first depth, and the first passivation layer is configured to substantially reduce sidewall roughness after etching to the second depth.

[0007] In some implementations, one or both of the LWR and LER values of the sidewalls are about 1.5 nm or less after etching a plurality of features to a second depth. In some implementations, the plurality of features includes shallow trench isolation (STI) features. In some implementations, the aspect ratio of the depth to width of each of the plurality of features is 10:1 or greater. In some implementations, each of the first depth and the second depth is greater than about 100 nm. In some implementations, the plurality of features includes one or more sparse features within a sparse feature region and one or more dense features within a dense feature region having a greater feature density than the sparse feature region, and the thickness of the first passivation layer along the sidewalls of the plurality of features is substantially the same within the sparse feature region and the dense feature region. In some implementations, the plurality of features is defined by a plurality of structures, one or more of the first structures includes a first material, one or more of the second structures includes a second material different from the first material, and the thickness of the first passivation layer along the sidewalls of the plurality of features is substantially the same for one or more of the first structures and one or more of the second structures. In some implementations, the method further includes depositing a second passivation layer on the sidewalls of the plurality of features by ALD in a plasma chamber and etching the plurality of features in the substrate to a third depth greater than the second depth in the plasma chamber, and the second passivation layer is configured to substantially reduce the sidewall roughness after etching through the substrate to the third depth. In some implementations, the first passivation layer includes silicon oxide (SiO x ).

[0008] These and other aspects are further described below with reference to the drawings.

Brief Description of the Drawings

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[0024] Introduction In the following description, numerous specific details are set forth to provide a thorough understanding of the described embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. The disclosed embodiments are described with reference to specific embodiments, but it is understood that the disclosed embodiments are not intended to be limiting.

[0025] In the present disclosure, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art will understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of the many stages of fabricating an integrated circuit on a silicon wafer. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm or 300 mm or 450 mm. The following detailed description assumes that the present disclosure is implemented on a wafer. However, the present disclosure is not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces on which the present disclosure may be utilized include various articles such as printed circuit boards.

[0026] Integrated Etching / ALD Processing Apparatus As the size of features shrinks, the pitch becomes smaller, and the complementary metal-oxide semiconductor (CMOS) technology scale moves to smaller nodes, thin conformal deposition techniques continue to increase in importance. Atomic layer deposition (ALD) is a film-forming technique and is well-suited for depositing thin conformal films because ALD deposits a single thin layer of material. The thickness of the thin conformal film is limited by the amount of one or more precursor reactants that can adsorb on the substrate surface prior to the film-forming chemical reaction itself (i.e., the adsorption-limiting layer). Each layer formed by ALD is thin and conformal, and the resulting film substantially conforms to the shape of the underlying device structures and features.

[0027] Conventionally, ALD methods and etching methods are performed on separate tools or platforms. For example, the etching process is not performed in the ALD chamber, and the ALD process is not performed in the etching chamber. Plasma-etching chambers that perform the deposition process use plasma-induced deposition methods to form films, and these films are not conformal and are affected by the aspect ratio.

[0028] FIG. 1 is a schematic diagram of an exemplary processing apparatus that performs an etching operation and an ALD operation according to some implementations. The processing apparatus 100 may be an inductively coupled plasma processing apparatus. The processing apparatus 100 includes a plasma chamber 132 such as a plasma-etching chamber. In some implementations, the Kiyo (trademark) reactor manufactured by Lam Research Corporation, Fremont, Calif., is an example of a suitable reactor that may be used as the plasma-etching chamber.

[0029] Details regarding the processing apparatus 100 that performs the etching operation and the ALD operation are described in U.S. Patent Application No. 15 / 669,871, filed Aug. 4, 2017, Zhou et al., titled "INTEGRATED ATOMIC LAYER PASSIVATION IN TCP ETCH CHAMBER AND IN-SITU ETCH-ALP METHOD", the entire disclosure of which is incorporated by reference for all purposes.

[0030] The plasma chamber 132 may include an overall chamber structure, which may be defined by a chamber wall 114 and a window 106. The window 106 may be made of quartz or other dielectric materials. In some implementations, the plasma chamber 132 includes a substrate support 116 disposed inside the plasma chamber 132. In some implementations, the substrate support 116 is an electrostatic chuck that supports the substrate 112, and deposition / etching processes are performed on the electrostatic chuck. The electrostatic chuck may include electrostatic electrodes for fixing and releasing the substrate 112. A filter and a DC clamp power supply (not shown) may be provided for this purpose. Other control systems for lifting the substrate 112 from the substrate support 116 may also be provided. The substrate support 116 is configured to receive and hold the substrate 112.

[0031] In some implementations, the substrate support 116 may include a heater for heating the substrate 112 (not shown). The substrate support 116 may be operated with a temperature increase, such as between about 20°C and about 150°C. The temperature is determined according to the process operation and a specific recipe. In some implementations, the plasma chamber 132 may operate at a specific pressure, such as between about 1 mTorr and about 1 Torr.

[0032] In some implementations, the processing apparatus 100 may include a radio frequency (RF) power supply 120, which may be used to bias / charge the substrate support 116. The RF power supply 120 can be defined by one or more RF generators. When providing multiple RF generators, different frequencies may be used to achieve various tuning characteristics. A bias matching circuit 118 is coupled between the RF power supply 120 and the substrate support 116. In this way, the RF power supply 120 is connected to the substrate support 116.

[0033] Coil 134 is disposed across window 106. Coil 134 is made of a conductive material and may include at least one complete turn. The coil 134 shown in FIG. 1 includes at least three turns. RF power supply 121 is configured to supply RF power to coil 134. Matching circuit 102 is coupled between RF power supply 121 and coil 134. In this way, RF power supply 121 is connected to coil 134. In some implementations, an optional Faraday shield (not shown) is disposed between coil 134 and window 106. The Faraday shield may be maintained in a spaced relationship with respect to coil 134. The Faraday shield may be disposed directly above window 106. The Faraday shield can prevent metal or other species from depositing on window 106 of plasma chamber 132.

[0034] RF power is supplied from RF power supply 121 to coil 134, causing an RF current to flow through coil 134. The RF current flowing through coil 134 can generate an electromagnetic field around coil 134. The electromagnetic field generates an induced current in plasma chamber 132, and the induced current acts on the gas(es) present in plasma chamber 132 to generate plasma. Various ions and / or radicals from the plasma can interact with substrate 112 to perform a deposition operation or an etching operation.

[0035] In some implementations, processing apparatus 100 optionally includes a plasma grid (not shown), which may be used to divide plasma chamber 132 into an upper portion and a lower portion. The plasma grid may be used to limit the amount of hot electrodes in the lower portion of plasma chamber 132. In some implementations, processing apparatus 100 is designed to operate such that the plasma present in the lower portion of plasma chamber 132 is an ion-ion plasma and the plasma present in the upper portion of plasma chamber 132 is an electron-ion plasma.

[0036] The processing gas may be introduced into the plasma chamber 132 from the upper part of the plasma chamber 132 through the first gas injector 104 and / or from the side part of the plasma chamber 132 through the second gas injector 110. The processing gas may include a vaporized liquid precursor or a vaporized solid precursor, and the solid precursor may be vaporized in a solid supply source evaporator (not shown) upstream of the processing apparatus 100. One or more reaction gases may be supplied through the first gas injector 104 and / or the second gas injector 110. In some implementations, the gas injectors 104, 110 may be replaced with a showerhead. It will be understood that additional or other gas supplies may be made to supply different gases to the plasma chamber 132 for various types of operations.

[0037] The various ways of injecting gas(es) into the plasma chamber 132 indicate that the processing gas, the vaporized liquid precursor, and / or the vaporized solid precursor may be supplied to the plasma chamber 132 from various locations. In some implementations, only the first gas injector 104 is used. In some implementations, only the second gas injector 110 is used. In other implementations, both the first gas injector 104 and the second gas injector 110 are used. In some implementations, the manifold 122 controls which gas is supplied to each of the various gas lines. The manifold 122 enables any type of gas (reaction gas, carrier gas, precursor gas, etc.) to be supplied from any of the various gas lines. In some implementations, the carrier gas can include gases such as oxygen (O2), nitrogen (N2), and helium (He). The gas may be introduced into the plasma chamber 132 without mixing or may be mixed with other gases before being introduced into the plasma chamber 132.

[0038] The manifold 122 may be used to select, switch, and / or mix the outputs from each of the delivery systems within the delivery system 128. The delivery system 128 may include, in some implementations, an etching gas delivery system 127 and a liquid delivery system 129. The etching gas delivery system 127 may be configured to output an etching agent gas. Examples of etching agent gases include, but are not limited to, chlorine (Cl2), hydrogen bromide (HBr), and sulfur hexafluoride (SF6). The liquid delivery system 129 may be configured to supply a liquid precursor, which is vaporized and delivered in the form of vapor in an ALD process. The vaporized liquid precursor may be introduced into the plasma chamber 132 and adsorbed on the surface of the substrate 112. A plasma may be used to convert the adsorbed precursor and form a film with a limited adsorption amount. An exemplary liquid precursor may have a chemical composition of the formula: C x H y N z O a Si b and may have.

[0039] The vacuum pump 130 may be connected to the plasma chamber 132 and used to draw the process gas out of the plasma chamber 132 and maintain a specific pressure within the plasma chamber 132. A valve 126 may be disposed between the exhaust pump 124 and the vacuum pump 130 to control the amount of vacuum suction applied to the plasma chamber 132. In some implementations, the vacuum pump 130 may be a one- or two-stage mechanical dry pump and / or a turbomolecular pump. In some implementations, the vacuum pump 130 may be started each time after the completion of the ALD process to purify the plasma chamber 132.

[0040] When installed in a clean room or a fabrication facility, the processing apparatus 100 may be coupled to a facility (not shown). The facility includes piping that provides control of process gas, vacuum, temperature, and environmental particle control. These facilities may be coupled to the processing apparatus 100 when installing the target fabrication facility. Further, the processing apparatus 100 may be coupled to a transfer chamber, which enables a robot to transfer substrates using automation and move them in and out of the plasma chamber 132.

[0041] In some implementations, the system controller 108 (one or more physical or logical controllers) controls some or all of the operations of the processing device 100. The system controller 108 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connectors, a stepper motor controller board, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions may be stored on a memory device associated with the system controller 108, and the memory device may be provided on a network. In some implementations, the system controller 108 executes system control software.

[0042] The system control software may include instructions for controlling any one or more of the following chamber operating conditions: gas mixing and / or composition, chamber pressure, chamber temperature, wafer / wafer support temperature, bias applied to the substrate (which may be zero in various implementations), frequency and power applied to the coil or other plasma generating component, substrate position, substrate movement speed, and other parameters of a particular process performed by the tool, at any one or more application timings and / or magnitudes. The system control software may be configured in any suitable manner. For example, subroutines or control objects of various processing tool components may be written with the control operations of the processing tool components required for the execution of various processing tool steps. The system control software may be encoded in any suitable computer-readable programming language.

[0043] In some embodiments, the system control software includes input / output control (IOC) sequencing instructions that control the various parameters described above. For example, each stage of the semiconductor manufacturing process may include one or more instructions executed by the system controller 108. Instructions for setting process conditions for a particular stage may be included, for example, within the corresponding recipe stage. In some implementations, the recipe stages may be sequentially configured to cause steps in an additive process to be executed in a particular order during these process stages. For example, the recipe may be configured to perform an etching operation and may include one or more cycles of an ALD process that are performed between each of the etching operations.

[0044] In some implementations, the system controller 108 is configured by instructions that perform one or more of the following operations: an etching operation in the plasma chamber 132 to etch a first layer of the substrate 112 to form a feature mask pattern, the feature mask pattern having a width smaller than a desired width of a plurality of structures formed by the feature mask pattern; a deposition operation in the plasma chamber 132 to deposit a first passivation layer on the feature mask pattern by ALD, the first passivation layer being deposited to a thickness that increases the width of the feature mask pattern to the desired width; and an etching operation in the plasma chamber 132 to etch a second layer of the substrate 112 to form a plurality of structures having the desired width. The etching operation and the deposition operation are performed without introducing a vacuum break within the plasma chamber 132. In some implementations, the system controller 108 is further configured to perform the following operation: an operation of repeating ALD-based deposition and etching within the plasma chamber 132.

[0045] In some embodiments, other computer software and / or programs may be implemented. For this purpose, examples of programs or program portions include a substrate placement program, a process gas composition control program, a pressure control program, a heater control program, and an RF power supply control program.

[0046] In some cases, the system controller 108 controls the gas concentration, the movement of the substrate, and / or the power supplied to the coil 134 and / or the substrate support 116. The system controller 108 may control the gas concentration, for example, by opening and closing the relevant valves to generate one or more inlet gas flows that provide the required reaction gas(es) at an appropriate concentration(s). The movement of the substrate may be controlled, for example, by directing the substrate placement system to move as required. The power supplied to the coil 134 and / or the substrate support 116 may be controlled to supply a specific RF power level. When using a grid, the RF power may be adjusted by the system controller 108 to generate an electron-ion plasma in the upper portion of the plasma chamber 132 and an ion-ion plasma in the lower portion of the plasma chamber 132. Further, the system controller 108 may be configured to supply power to the substrate support 116 under conditions such that an electron-ion plasma is not generated in the lower portion of the plasma chamber 132.

[0047] The system controller 108 may control these and other aspects based on sensor outputs (e.g., when power, potential, pressure, etc. reach specific thresholds), the timing of operations (e.g., opening a valve at a specific time within a process), or commands received from the user.

[0048] In some implementations, the system controller 108 is part of the system, and the system may be part of the above examples. Such a system can include semiconductor processing equipment, which can include one or more processing tools, one or more chambers, and one or more platforms for processing and / or specific processing components (such as a wafer stage, a gas flow system, etc.). These systems may be integrated with electronics that control the operation of the system before, during, and after the processing of semiconductor wafers or substrates. These electronics may be referred to as "controllers" and may control various components or sub-components of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 108 may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, the setting of temperatures (e.g., heating and / or cooling), the setting of pressures, the setting of vacuums, the setting of power, the setting of RF generators, the setting of RF matching circuits, the setting of frequencies, the setting of flow rates, the setting of fluid delivery, the setting of positions and motions, substrate transfer in and out tools, and other transfer tools, and / or load locks connected or interfaced to a particular system.

[0049] Broadly speaking, the system controller 108 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software, which receives instructions, issues instructions, controls operations, enables cleaning operations, enables end-point measurement, and the like. The integrated circuits may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors that execute program instructions (e.g., software). The program instructions may be instructions communicated to the system controller 108 in the form of various individual settings (or program files), and define operation parameters for performing specific processes on, or for, or with respect to, a semiconductor substrate. The operation parameters may, in some embodiments, be part of a recipe defined by a process engineer to achieve one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a substrate.

[0050] In some implementations, the system controller 108 may be part of a computer or coupled to a computer, which may be integrated with the system, coupled to the system, networked to the system in other ways, or a combination thereof. For example, the system controller 108 may be all or part of a "cloud" or fab host computer system that enables remote access to substrate processing. The computer may enable remote access to the system, monitor the current progress of manufacturing operations, investigate the history of past manufacturing operations, investigate trends or performance metrics from multiple manufacturing operations, change the parameters of the current process, set process steps to follow the current process, or initiate new processes. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables the input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the system controller 108 receives instructions in the form of data, and the instructions specify parameters for each of the process steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool configured to be interfaced or controlled by the system controller 108. Thus, as described above, the system controller 108 may be distributed, for example, by comprising one or more discrete controllers, which are networked together and work towards a common purpose such as the processes and controls described herein. An example of a distributed system controller 108 for such a purpose is one or more integrated circuits located above the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and are combined to control processes above the chamber.

[0051] While not limiting, exemplary systems may include a plasma etching chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a clean chamber or module, an angled edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etching (ALE) chamber or module, an ion implantation chamber or module, an assembly line chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacture of semiconductor substrates.

[0052] As described above, depending on the process step or steps to be performed by the tool, system controller 108 may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another system controller 108, or tools used in material handling to transport the substrate container between locations of tools or between load ports within a semiconductor manufacturing facility.

[0053] Line - width roughness and line - edge roughness Patterning methods are used in many semiconductor manufacturing processes to achieve desired features. Masks, such as photoresist patterning, act to pattern underlying layers to form desired features including 1 - D features (lines, trenches, etc.) and 2 - D features (e.g., holes, squares, etc.). However, the edges of masks are typically not straight and lead to deviations from linearity. Deviations from linearity can result in the generation of non - linearities within the pattern features and may adversely affect the performance of the device. Such deviations can be characterized as line - width roughness (LWR) and / or line - edge roughness (LER).

[0054] As the critical dimension (CD) becomes smaller within a semiconductor device, lithography methods for achieving small CDs and controlling LER and LWR are becoming increasingly difficult. The impact of LER / LWR is amplified with smaller CDs. LWR refers to the deviation of the line width measured over a given length. LWR is generally quantified as the 3σ deviation of the width. LER refers to the deviation of the line edge and may be understood as the deviation of the edge from a straight line when viewed from above - below. LWR and LER values may be calculated according to a given inspection length or area using known methods. Failure to control LWR and / or LER can have a significant impact on the resulting semiconductor device, and conventional lithography techniques are typically insufficient to address these issues.

[0055] As an example, conventional photolithography techniques use patterning and etching methods to define features of a semiconductor device. In these methods, a photoresist material is deposited on a substrate and then exposed to light filtered by a reticle. The reticle is generally a glass plate patterned by the shape of the features that block the light propagating through the reticle. After passing through the reticle, the light contacts the surface of the photoresist material, changing the chemical composition of the photoresist material to allow a developer to remove a portion of the photoresist material. The developer is applied to the photoresist material to remove a portion of the photoresist material. In the case of a positive photoresist material, the exposed area is removed, and in the case of a negative photoresist material, the unexposed area is removed. The patterned photoresist material is used as a mask for etching the underlying layer.

[0056] Due to the limitations of the chemical properties of the photoresist, the wavelength or light source in the optical system, and / or the limitations of resolution, the patterned photoresist material may contain some amount of LWR and / or LER. Without being limited to any theory, this may be due to photoresist molecules, which form a random pattern throughout the patterned photoresist material after exposure and development, lacking uniformity. The LWR and / or LER within the patterned photoresist material may be transferred to the underlying layer in subsequent etching processes, which may reduce the resolution of the photolithography process.

[0057] LWR and / or LER may affect the performance of various semiconductor devices. For example, in the case of planar or three-dimensional CMOS devices and interconnect structures, higher LWR / LER values may result in, among other things, reduced resolution, non-uniform CDs, slower speeds, yield losses, increased resistivity, and reduced performance. With regard to process integration, higher LWR / LER values may cause features to merge, in which case the CD spacing is small, resulting in a short circuit and ultimately device failure.

[0058] When forming a fin field-effect transistor (FinFET), larger LWR / LER may degrade the performance of the device, reduce the transistor speed, and increase the power consumption because the surface roughness acts as a scattering center for charge carriers. With regard to the patterning process, large LWR / LER may result in line breaks or bridges, causing non-fidelity to the local pattern. Using such patterning in subsequent interconnect metal filling results in open / short circuits due to defects caused by such breaks / bridges, rendering the semiconductor device inoperable.

[0059] Improvements to LWR and / or LER are typically achieved using one of several strategies, including the development of new resists with smaller inherent roughness, the optimization of lithography processes including dose optimization and resist optimization, and the application of post-development smoothing processes. Dose optimization may involve exposing the resist material at high exposure doses to reduce the randomness of resist development, which is often a trade-off with throughput and cost. Resist optimization may involve changing resist process parameters such as developer concentration and development time, or changing the chemical formula of the resist, which is often slow, expensive, and involves long cycle times.

[0060] Conventional post-development smoothing processes may include plasma processes that smooth the resist pattern as shown in FIG. 2, or deposition / etch processes that smooth the resist pattern as shown in FIG. 3. While the above-described post-development smoothing processes may reduce LWR and / or LER, problems that may occur with such post-development smoothing processes include limitations in the adjustment window due to selectivity issues, limitations in the adjustment window due to CD or CD loading requirements, reduction in selectivity, reduction in mask height, and dense-sparse CD loading.

[0061] FIG. 2 is a schematic diagram of a mask that undergoes a conventional plasma pretreatment to reduce roughness within the mask. In step 210, prior to plasma processing, a mask 204, such as a photoresist mask, may be patterned on a substrate 202 having a profile exhibiting roughness including LWR and LER. In some implementations, the mask 204 includes one or more feet 206 that protrude laterally from the mask 204. In step 220, after plasma processing, the mask 204 may have a rounded profile and the roughness may be smoothed. The plasma processing may or may not enlarge the one or more feet 206. The plasma processing may use mild plasma conditions such that the plasma is not too rapid in etching the mask 204. Without being limited to any theory, the plasma “chemically treats” the mask 204, causing the molecules of the mask 204 to reflux, reducing the roughness, thereby resulting in a rounded profile. The non-etching plasma may be isotropic. Examples of non-etching plasmas that reduce the roughness of the mask 204 include hydrogen (H2) plasma, argon (Ar) plasma, or combinations thereof. In step 230, after anisotropic etching, the one or more feet 206 may be removed from the mask 204. Anisotropic etching may use directed ions 208 to etch or “trim” the one or more feet 206. In other cases, the presence of the one or more feet 206 may increase the LWR of the mask 204.

[0062] The plasma processing shown in FIG. 2 may reduce the LWR and / or LER of the mask, but the plasma processing may reduce the height of the mask, change the shape of the resist, and reduce the etch selectivity. This may reduce the resistance performance of the mask to the etching operation. Further, the plasma processing may have a limited adjustment window due to selectivity issues. The resist is typically softened by the plasma processing and the height is significantly reduced. When the resist softens and is more shortened, it may not withstand subsequent etching steps when transferring the pattern downward. This may result in pattern inaccuracy and an increase in LWR / LER due to mask consumption.

[0063] Figure 3 is a schematic diagram of a mask that undergoes a conventional plasma deposition, plasma, etching, sequence to reduce roughness within the mask. In step 310, prior to anisotropic etching and plasma deposition, a mask 304, such as a photoresist mask, may be patterned on a substrate 302 having a profile exhibiting roughness including LWR and LER. In some implementations, mask 304 includes one or more feet 306 that protrude laterally from mask 304. In step 320, after anisotropic etching, one or more feet 306 may be removed from mask 304. Anisotropic etching may use directed ions 308 to etch or "trim" one or more feet 306. In other cases, one or more feet 306 may contribute to the LWR of mask 304. In step 330, after plasma deposition, an inactivation layer 312 may be deposited on the sidewalls and upper surface of mask 304. Inactivation layer 312 smooths the sidewalls and surface of mask 304 and reduces roughness. Inactivation layer 312 may be deposited using a chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) process. However, such deposition processes typically deposit non-conformal films. CVD or PECVD processes are dependent on the aspect ratio and deposit more material within more open spaces or wider pitches than within less open spaces or narrower pitches. Further, when using CVD or PECVD processes, the amount of CD bias within a 1-D feature (e.g., a line) may differ from the CD bias within a 2-D feature (e.g., a via). After plasma deposition, a plasma etching operation (not shown) is performed to trim the deposited inactivation layer 312. The CD of mask 304 may be controlled by the plasma etching operation to trim inactivation layer 312.

[0064] The plasma deposition, plasma, etching, sequence shown in FIG. 3 may be carried out in the same chamber or tool. The plasma deposition, plasma, etching sequence in FIG. 3 reduces roughness but may result in CD loading, with more material deposited in sparse features than in dense features and more material deposited in 2-D features than in 1-D features. CD loading between sparse and dense features is shown in FIGS. 4A-4C.

[0065] FIGS. 4A-4C are schematic diagrams of sparse and dense substrate features that are deposited and etched using a conventional deposition method in a plasma chamber. The deposition and etching operations may correspond to the deposition and etching operations that reduce roughness on the mask described in FIG. 3.

[0066] FIG. 4A shows a partially fabricated device structure 410 including a substrate 402 and feature mask patterns 404a, 404b. The feature mask patterns 404a, 404b may be patterned and defined after etching in the plasma chamber. The feature mask patterns 404a, 404b may be distinguished between the dense feature 404a in the dense feature region of the substrate 402 and the sparse feature 404b in the sparse feature region of the substrate 402, with the dense feature 404a having a higher feature density than the sparse feature 404b. The dense feature 404a within the dense feature region may define a gap having a higher aspect ratio than the sparse feature 404b within the sparse feature region. The feature mask patterns 404a, 404b may have the same or substantially similar CDs as shown in FIG. 4A.

[0067] FIG. 4B shows a partially fabricated device structure 420 including a substrate 402, feature mask patterns 404a, 404b, and a first passivation layer 406 deposited over the feature mask patterns 404a, 404b. The first passivation layer 406 may be deposited using a conventional deposition method such as CVD or PECVD in a plasma chamber. Alternatively, the first passivation layer 406 may be deposited using a plasma-based “flash” passivation technique, and a portion of the feature mask patterns 404a, 404b may be consumed through oxidation or nitridation. As shown in FIG. 4B, the thickness of the first passivation layer 406 is greater over the sparse features 404b in the sparse feature region than over the dense features 404a in the dense feature region. The sparse features 404b receive more deposition than the dense features 404a. Thus, the CD gain is greater in the sparse feature region than in the dense feature region. The partially fabricated device structure 420 represents the device structure 410 after deposition using a conventional deposition method in a plasma chamber.

[0068] FIG. 4C shows a partially fabricated device structure 430 including a substrate 402, feature mask patterns 404a, 404b, a first passivation layer 406 deposited over the feature mask patterns 404a, 404b, and a plurality of features 408 within the substrate 402. The plurality of features 408 may be formed after an etching process in a plasma chamber. The etching process may anisotropically etch a layer of material within the substrate 402 to a desired depth. The plurality of features 408 may be defined by a plurality of structures 409 underlying the feature mask patterns 404a, 404b. The aspect ratio of the features 408 may be higher in the dense feature region of the substrate 402 than in the sparse feature region. As shown in FIG. 4C, the CD bias or CD loading in the sparse feature region is greater than the CD bias or CD loading in the dense feature region. The partially fabricated device structure 430 represents the device structure 420 after etching in a plasma chamber.

[0069] In-situ ALD and etching for roughness reduction Embodiments of the present disclosure relate to a method for reducing roughness using in-situ ALD and etching. In some embodiments, the in-situ ALD operation and etching operation may be performed by depositing a conformal layer on a mask and etching a layer under the mask to form features with reduced LWR and / or LER. In some embodiments, the in-situ ALD operation and etching operation may be performed by depositing a passivation layer on one or more structures and etching a layer under the one or more structures to form high aspect ratio features with improved sidewall roughness. In some embodiments, the cycle of the ALD step and the etching step is performed in the plasma processing apparatus described in FIG. 1. The ALD cycle performed in the same plasma processing apparatus as the etching results in conformal deposition and is used to reduce roughness within the features of the semiconductor device.

[0070] ALD is a technique for depositing thin material layers using sequential self-limiting reactions. Typically, an ALD cycle involves delivering and adsorbing at least one reactant to the substrate surface, and then reacting the adsorbed reactant with one or more reactants to form a partial film layer. Unlike CVD techniques, the ALD method uses a surface self-limiting deposition reaction that deposits the film in layer-by-layer units. A typical ALD cycle may include: (i) introducing a precursor material, delivering it to and adsorbing it on the substrate surface; (ii) removing excess precursor material from the chamber, leaving a self-limiting monolayer on the substrate surface; (iii) delivering a reactant material and reacting it with the adsorbed precursor material; and (iv) removing unreacted reactant material or reacting by-products from the chamber. The introduction step may adsorb the precursor material in a self-limiting manner, and when the active sites are occupied by the precursor material, little or no additional precursor material is adsorbed on the substrate surface. The reactant material may similarly react with the precursor material in a self-limiting or adsorption-stopping manner. The removal step may be optionally performed to remove excess precursor material, reaction by-products, and / or unreacted reactant material from the chamber, thereby completing the ALD cycle. Using ALD, highly conformal films with high step coverage can be provided even for high aspect ratio features. Thus, a uniform amount of material can be deposited between sparse and dense features, minimizing CD loading between sparse and dense features.

[0071] Figures 5A - 5C are schematic diagrams of sparse and dense substrate features undergoing deposition and etching using an ALD method and an etching method according to some implementations. Comparing between the sparse and dense features in the conventional etching - deposition - etching method shown in Figures 4A - 4C and the ALD etching - deposition - etching method shown in Figures 5A - 5C reveals the effect of CD bias / loading in sparse - dense feature cases.

[0072] FIG. 5A shows a partially fabricated device structure 510 including a substrate 502 and feature mask patterns 504a, 504b. The feature mask patterns 504a, 504b may be patterned and defined after etching in a plasma chamber. The feature mask patterns 504a, 504b may be distinguished between the dense features 504a in the dense feature region of the substrate 502 and the sparse features 504b in the sparse feature region of the substrate 502, and the dense features 504a have a higher feature density than the sparse features 504b. The dense features 504a within the dense feature region may define a gap having a higher aspect ratio than the sparse features 504b within the sparse feature region. The feature mask patterns 504a, 504b may have the same or substantially the same CD as shown in FIG. 5A.

[0073] FIG. 5B shows a partially fabricated device structure 520 including a substrate 502, feature mask patterns 504a, 504b, and a first passivation layer 506 deposited on the feature mask patterns 504a, 504b. The first passivation layer 506 may be deposited using an ALD method. As shown in FIG. 5B, the thickness of the first passivation layer 506 is relatively uniform over the sparse features 504b in the sparse feature region and over the dense features 504a in the dense feature region. As shown in FIG. 5B, the CD bias / loading between the dense features 504a in the dense feature region and the sparse features 504b in the sparse feature region is the same or substantially the same. For the CD bias / loading between the dense features 504a and the sparse features 504b using ALD, "substantially the same" refers to a value within 0.5 nm of the stated value throughout this disclosure. The partially fabricated device structure 520 represents the device structure 510 after deposition using the ALD method. In some implementations, the ALD process may be an in-situ ALD process performed in the same chamber as a subsequent etching process.

[0074] FIG. 5C shows a partially fabricated device structure 530 including a substrate 502, feature mask patterns 504a, 504b, a first passivation layer 506 conformally deposited over the feature mask patterns 504a, 504b, and a plurality of features 508 within the substrate 502. The plurality of features 508 may be formed after an etching process in a plasma chamber. The etching process may anisotropically etch a layer of material within the substrate 502 to a desired depth. The plurality of features 508 may be defined by a plurality of structures 509 underlying the feature mask patterns 504a, 504b. The aspect ratio of the features 508 may be higher within the dense feature region of the substrate 502 than within the sparse feature region. As shown in FIG. 5C, the CD bias / loading between the dense feature region and the sparse feature region is the same or substantially similar. The partially fabricated device structure 530 represents the device structure 520 after etching in a plasma chamber.

[0075] It will be appreciated that implementations of the present disclosure for reducing roughness may be implemented using ALD outside of the in-situ or in-situ ALD. Implementations using ALD outside of the in-situ and etching may reduce roughness including LWR and LER, while ALD outside of the in-situ and etching may have undesirable results and effects on the resulting semiconductor device.

[0076] FIG. 6A is an exemplary process flow for substrate transfer using an etching method and an ALD method in-situ. It will be appreciated that such a process flow in FIG. 6A is not limited to the multiple patterning scheme described above and may be applicable to other schemes using an etching method and an ALD method. In FIG. 6A, the substrate is prepared in an etching chamber at block 601, undergoes an etching step, is transferred to a clean chamber at block 603, undergoes a cleaning step, is transferred to an ALD chamber at block 605, undergoes an ALD step, is transferred again to the same or a different clean chamber at block 607, undergoes a cleaning step, and is transferred again to the same or a different etching chamber at block 609. When implementing an etching-deposition-etching sequence, the substrate may undergo four substrate transfers through three to five different chambers. In some implementations, the etching step at block 601 may define a mask, the ALD step at block 605 may reduce the roughness of the mask, and the etching step at block 609 may define a structure with reduced roughness.

[0077] Using separate chambers for deposition and etching increases the processing time, processing steps, and cost, thereby adversely affecting the processing capacity. Further, using separate chambers requires transferring the substrate from one chamber to another, which involves a vacuum break and increases the possibility of unwanted materials or particles entering and contacting the substrate. This can result in a loss of material functionality and / or integrity on the substrate. Further, as shown in FIG. 6A, a cleaning process is generally required between the etching process and the deposition process, and the cleaning process may affect the material properties and structure on the substrate. For example, a cleaning process with diluted hydrofluoric (HF) acid may affect the mask structure and may adversely affect the performance.

[0078] While reducing roughness, a plasma etching chamber may be utilized and adapted to perform deposition in order to avoid problems associated with the implementation of etching and deposition steps with different tools. Typical deposition methods may include CVD and PECVD methods. However, as described above, such deposition methods typically deposit non-conformal films. More specifically, these deposition methods are determined by the aspect ratio and deposit more material at more open spacers or at wider pitches, resulting in non-conformal deposition across structures or features of different aspect ratios. Thus, when the CD bias for sparse features exceeds the CD bias for dense features, more deposition occurs within the sparse features than within the dense features.

[0079] Some implementations of the present disclosure relate to the integration of an ALD step and an etching step in a plasma chamber. By using in-situ ALD rather than performing ALD in a separate chamber or using CVD / PECVD in the same chamber, stand-alone ALD tools and additional cleaning tools are eliminated. Further, the processing time and cost are reduced by eliminating additional substrate transfer and cleaning times. Further, using in-situ ALD avoids vacuum breakage during substrate transfer, which may expose the substrate to undesirable materials, atmospheres, and / or moisture (e.g., between deposition and cleaning outside of in-situ). In-situ ALD also reduces the effects of non-uniform deposition across structures or features of different aspect ratios. In-situ ALD may refer to ALD performed in a plasma etching chamber, such as the plasma chamber within the processing apparatus 100 of FIG. 1 above.

[0080] Figure 6B is an exemplary process flow for substrate transfer using an integrated etching method and an ALD method. It should be understood that such a process flow in Figure 6B is not limited to the multiple patterning method described above, but may also be applied to other methods using an etching method and an ALD method. In Figure 6B, the substrate is prepared in the etching chamber, undergoes an etching step at block 651, is maintained in the same etching chamber to undergo an ALD step at block 653, is maintained in the same etching chamber to undergo an etching step at block 655, and is transported to the clean chamber to undergo a cleaning step at block 657. When implementing an etching-deposition-etching sequence, the substrate can undergo one substrate transfer through two different chambers. In some implementations, the etching step at block 651 may define a mask, the ALD step at block 653 may reduce the roughness of the mask, and the etching step at block 655 may define a structure with reduced roughness.

[0081] Figure 7 is a flowchart of an exemplary method for reducing roughness within a pattern feature by using an etching method and an ALD method according to some implementations. The operations in method 700 may be performed in a different order and / or with different, fewer, or additional operations. Figure 7 will be described with reference to Figures 8A through 8D.

[0082] In block 710 of method 700, the lithography operation and / or the etching operation is optionally performed on the mask layer to form a pattern mask layer on the substrate. The lithography operation may include exposure and development operations performed on the resist material of the mask layer. The etching operation may remove portions of the mask layer, such as one or more feet protruding laterally within the mask layer. In some implementations, the mask layer may include a photoresist material. The pattern mask layer may have a certain amount of roughness after the lithography and / or etching operations. In method 700, after the lithography and / or etching operations to form the pattern mask layer, the in-situ ALD operation and the etching operation of the present disclosure are performed.

[0083] In some implementations, the pattern mask layer includes a photoresist material. In some implementations, the pattern mask layer includes a hard mask material. Examples of hard mask materials include, but are not limited to, silicon oxide, silicon nitride, or silicon oxynitride. It will be understood that the pattern mask layer may include a resist material, but the pattern mask layer does not necessarily include a resist material. In some implementations, the pattern mask layer may be defined after a single or multiple patterning processes. A resist or photoresist layer may serve as a mask defining one or more underlying structures in a patterning process, and the one or more underlying structures may serve as a pattern mask layer for subsequent in-situ ALD operations and etching operations. Or the one or more underlying structures may serve as a mask defining further underlying structures, and the further underlying structures may serve as the pattern mask layer described in block 710. This means that the pattern mask layer used in in-situ ALD and etching may be formed at any point during a single or multiple patterning processes. This formation at any point may be done because the in-situ ALD operations and etching operations described below in method 700 may not be compatible with a particular resist material or other materials of the substrate.

[0084] In some implementations, the pattern mask layer on the substrate may be configured to define one or more one-dimensional (1-D) features in the underlying material layer and one or more two-dimensional (2-D) features in the underlying material layer. Accordingly, the pattern mask layer may be patterned by 1-D and 2-D structures that define 1-D and 2-D features in the underlying material layer. The 1-D features may be defined with respect to a single direction, and examples of 1-D features may include interconnect lines and trenches. The 2-D features may be defined with respect to two orthogonal directions, and examples of 2-D features may include contact holes, vias, squares, and blocks.

[0085] In some implementations, the pattern mask layer may have one or more sparse features in a sparse feature region and one or more dense features in a dense feature region, and the dense feature region has a higher feature density than the sparse feature region. The one or more dense features may result in features (e.g., trenches, recesses, holes, etc.) having an aspect ratio higher than that of the one or more sparse features.

[0086] The pattern mask layer may have a roughness associated with the pattern mask layer, and the pattern edges within the pattern mask layer have a deviation from linearity. This deviation may be represented by LER and / or LWR values. In some implementations, the LER value of the pattern mask layer for a given inspection region may be greater than about 3.0 nm or greater than about 1.0 nm, and the LWR value of the pattern mask layer for a given inspection region may be greater than about 4.0 nm, greater than about 3.0 nm, or greater than about 1.5 nm. However, it will be understood that the LER value and LWR value of the pattern mask layer may depend on the pattern formed within the pattern mask layer.

[0087] FIG. 8A is a schematic diagram showing side and top views of an exemplary partially fabricated semiconductor device with a pattern mask layer and underlying material layers. The partially fabricated semiconductor device 810 includes a pattern mask layer 806, which includes 1-D structures 802 and 2-D structures 804. The 1-D structures 802 may define lines in the underlying layer, and the 2-D structures 804 may define blocks in the underlying layer. Structures are formed directly below the pattern mask layer 806 using the pattern mask layer 806, although the patterns within the pattern mask layer 806 may be inverted to obtain trenches and / or holes rather than the lines and blocks in FIGS. 8A-8D. The partially fabricated semiconductor device 810 includes a first material layer 812 below the pattern mask layer 806, a second material layer 814 below the first material layer 812, and a third material layer 816 below the second material layer 814. Each of the material layers 812, 814, and 816 may include a semiconductor material, a dielectric material, or a conductive material. The composition of the first material layer 812 is different from the composition of the second material layer 814, and the composition of the second material layer 814 is different from the composition of the third material layer 816. As shown in FIG. 8A, the outer shapes of the 1-D structures 802 and the 2-D structures 804 exhibit serrated edges and other non-linearity that indicates roughness within the pattern mask layer 806. In some implementations, the roughness of the pattern mask layer 806 may be calculated by calculating LWR and / or LER values after defining a given inspection length or area. A typical inspection length is greater than about 50 nm or greater than about 100 nm. If the roughness of the pattern mask layer 806 is not smoothed, this roughness may be transferred to subsequent layers within the partially fabricated semiconductor device 810, degrading performance.

[0088] Returning to FIG. 7, in block 720 of method 700, a first conformal layer is deposited on the pattern mask layer of the substrate by atomic layer deposition (ALD) within a plasma chamber. The substrate includes a first material layer and a pattern mask layer spanning the first material layer. The pattern mask layer has a first roughness prior to deposition of the first conformal layer. The plasma chamber may be configured to perform subsequent etching processes. Aspects of the plasma chamber may be described with respect to the processing apparatus 100 of FIG. 1.

[0089] In some implementations of method 700, a substrate is provided in a plasma chamber. The substrate may be disposed on a substrate support in the plasma chamber. In some implementations, the substrate may be a semiconductor substrate including a silicon substrate, such as a 200 mm, 300 mm, or 450 mm substrate. In some implementations, the substrate is provided in the plasma chamber with a pattern mask layer.

[0090] The first conformal layer may be deposited by ALD on the exposed surfaces of the pattern mask layer and a first material layer underlying the pattern mask layer. The exposed surface of the pattern mask layer includes the sidewalls of the features of the pattern mask layer. The first conformal layer on the pattern mask layer smooths the rough edges and gaps of the pattern mask layer, thereby reducing the first roughness associated with the pattern mask layer.

[0091] In some implementations, the first conformal layer includes a passivation material such as an oxide or a nitride. For example, the first conformal layer includes silicon oxide (SiO x ). The passivation material of the first conformal layer may serve to protect the pattern mask layer, including the sidewalls of the pattern mask layer, during subsequent etching processes such as the etching process described in block 730.

[0092] In some implementations, the first conformal layer is relatively thin and has a thickness sufficient to reduce the first roughness associated with the pattern mask layer. For example, the first conformal layer has a thickness between about 0.2 nm and about 10 nm, or between 0.5 nm and about 5 nm.

[0093] As described above, ALD is a technique for depositing thin material layers using sequential self-limiting reactions. ALD may be used to provide high step coverage on highly conformal films, even in the case of high aspect ratio features. The first conformal layer may be conformally deposited by ALD and may have a high step coverage, such as greater than 85%, greater than 90%, or greater than 95%. The ALD process for depositing the first conformal layer may be performed in one or more cycles, each cycle creating an adsorption-limited amount of material on the patterned mask layer. Each cycle may include a dosing step that delivers a controlled amount of precursor material to the substrate surface and adsorbs it onto the substrate surface in a self-limiting manner. This is also known as "soaking" to saturate the substrate surface. Each cycle may further include a conversion step after the dosing step that provides a reactant material on the substrate surface to react with the precursor material and form an adsorption-limited amount of material (e.g., a passivation material). The reactant material may include a reactive gas, and an RF power source generates a plasma of the reactive gas in the plasma chamber. The reactive gas may include, for example, an oxygen-containing gas (e.g., O2) or a nitrogen-containing gas (e.g., N2 or NH3). The radical and other charged species of the reactive gas react with the precursor material to convert the precursor material into an adsorption-limited amount of material (e.g., a passivation material). In some implementations, the reactive gas is exposed to the delivery of RF power for a relatively short amount of time, such as between about 0.5 seconds and about 5 seconds, to generate a plasma and convert the precursor material. This is known as a "flash" operation that uses a plasma from the RF power delivered for a relatively short amount of time on the substrate surface to convert the precursor material. In some implementations, a purge step may remove excess precursor material, reaction by-products, and / or unreacted reactant material from the plasma chamber to complete the cycle. In some implementations, the dosing step and the conversion step may be repeated until the desired thickness of the first conformal layer is deposited.

[0094] The deposition of the first conformal layer is independent of the aspect ratio and pitch. The thickness of the first conformal layer on the pattern mask layer is relatively uniform, depositing approximately the same amount of material across different CDs, different aspect ratios, different pitches, different depths, and different 1-D / 2-Ds. This minimizes CD loading, depth loading, and 1-D / 2-D CD bias loading. For example, the CD bias between one or more 1-D features and one or more 2-D features is substantially the same after depositing the first conformal layer. The CD bias between one or more sparse features and one or more dense features is substantially the same after depositing the first conformal layer. With respect to the CD bias between 1-D / 2-D features, "substantially the same" throughout this disclosure refers to a value that is plus or minus 5% of the stated value.

[0095] FIG. 8B is a schematic diagram showing a side view and a top view of an exemplary partially fabricated semiconductor device from FIG. 8A after depositing a first conformal layer on a pattern mask layer. The partially fabricated semiconductor device 820 includes a pattern mask layer 806 having a first conformal layer 808 deposited thereon. The first conformal layer 808 is deposited on the exposed surfaces of the pattern mask layer 806 and the first material layer 812, including the sidewalls and the top surface of the pattern mask layer 806 and the first material layer 812. The first conformal layer 808 results in a relatively linear outer shape so as to cover the outer shape of the 1-D structure 802 and the outer shape of the 2-D structure 804. The serrated edges and other non-linearities of the 1-D structure 802 and the 2-D structure 804 are corrected by the first conformal layer 808. The roughness of the pattern mask layer 806 is reduced by the first conformal layer 808. In some implementations, the LWR and / or LER values of the pattern mask layer 806 are reduced by the first conformal layer 808 for the same inspection length or region as the LWR and / or LER values calculated on the pattern mask layer 806 before depositing the first conformal layer 808. The first conformal layer 808 not only improves the roughness of the pattern mask layer 806, but also improves the roughness in a state where the effects on CD bias / loading and depth bias / loading can be ignored. The same or substantially similar thickness of the first conformal layer 808 is deposited on the exposed surface of the partially fabricated semiconductor device 820 regardless of the aspect ratio, pitch, depth, and 1-D / 2-D CD. In some implementations, the first conformal layer 808 has a thickness between about 0.5 nm and about 5 nm and includes silicon oxide (SiO x ).

[0096] Referring to FIG. 7, in block 730 of method 700, the first material layer is etched in a plasma chamber to form a plurality of first pattern features of the first material layer defined by the pattern mask layer. The plurality of first pattern features have a second roughness that is smaller than the first roughness of the pattern mask layer after etching the first material layer. The etching operation in block 730 may be performed in the same plasma chamber as the deposition in block 720 without introducing a vacuum break between the operations.

[0097] Etching may anisotropically etch through a first layer to form features within the first layer. The etching may be selective to the etching material of the first material layer with respect to the materials of surrounding layers. In this way, the etching performed at block 730 selectively etches the first material layer without etching the first conformal layer and / or the pattern mask layer. In some implementations, the etching may remove the first material layer to a first depth, which is less than the final depth. For example, the first depth may be 20%, 30%, 40%, 50%, 60%, etc. of the final depth, any suitable percentage of the final depth. Thus, multiple etchings may be performed to reach the final depth.

[0098] Deposition of the first conformal layer to smooth the first roughness of the pattern mask layer eliminates or minimizes the transfer of the roughness (i.e., the first roughness) to underlying material layers. The roughness may be improved such that the LWR and / or LER values corresponding to the second roughness are less than the LWR and / or LER values corresponding to the first roughness. In some implementations, the LWR and / or LER values from the first roughness to the second roughness may be improved by at least 40%, at least 50%, at least 60% or at least 75%. For example, to illustrate a 40% improvement in roughness, after ALD and etching, the LWR value is 2.5 nm on the pattern mask layer over a given inspection length / area, and the LWR value is 1.5 nm on a plurality of first pattern features. In some implementations, the LWR value associated with the second roughness is about 2.0 nm or less or about 1.5 nm or less for a given inspection length or area, and the LER value associated with the second roughness is about 2.0 nm or less or about 1.5 nm or less for a given inspection length or area. This is in contrast to the LWR value associated with the first roughness being about 2.5 nm or more or about 2.0 nm or more for the same inspection length or area, and the LER value associated with the first roughness being about 2.5 or about 2.0 nm or more for the same inspection length or area. In some implementations, the CD of a plurality of first pattern features is about 20 nm or less.

[0099] The plurality of first pattern features may include various shape features, and the various shape features include, but are not limited to, interconnect lines, contacts, vias, trenches, recesses, spaces, holes, blocks, squares, etc. The plurality of first pattern features may include 1-D and / or 2-D features. The CD of the plurality of first pattern features may refer to a structure (e.g., a line, a block), but it will be understood that the associated CD may be a space CD related to a space (e.g., a recess, a hole).

[0100] Improvement in the roughness of the underlying material layer is achieved, and the impact on the through-pitch loading is minimal. The deposition of the first conformal layer to minimize the impact on CD loading, depth loading, and 1-D / 2-D CD bias loading is independent of the aspect ratio and pitch, and the impact on CD loading, depth loading, and 1-D / 2-D CD bias loading caused by the etching of the first material layer to form the plurality of first pattern features is minimal. Therefore, the CD bias between one or more sparse features and one or more dense features is substantially the same after the etching of the first material layer, and the CD bias between one or more 1-D features and one or more 2-D features is substantially the same after the deposition of the first conformal layer. Therefore, the pattern mask layer transfers the pattern, defines the plurality of first pattern features within the first material layer, has less roughness, and is free of CD bias loading.

[0101] Improvement in the roughness of the underlying material layer is achieved with minimal impact on selectivity and throughput. In contrast to applications that use plasma processing methods on the mask to reduce roughness, the deposition of the first conformal layer by ALD and subsequent etching do not affect the chemical properties of the pattern mask layer that affect selectivity. The deposition of the first conformal layer by ALD also does not affect the shape of the pattern mask layer. An effect on the shape of the pattern mask layer can occur with plasma processing methods that reduce roughness. Further, in contrast to applications that use lithography optimizations such as dose optimization and / or resist optimization, the deposition of the first conformal layer by ALD and subsequent etching do not require long cycle times that adversely affect throughput. Instead, roughness reduction by ALD and subsequent etching may be performed without changing the conditions or parameters of the lithography method.

[0102] In some implementations, the etching operation performed at block 730 is not selective to the first conformal layer, and the first conformal layer is preserved during etching. The first conformal layer may be etched at an etching rate that is substantially slower than the first material layer. In some implementations, the etching operation performed at block 730 is selective to the first conformal layer during etching. The first conformal layer need not necessarily include an inerting material that resists the etching operation at block 730. A particular thickness of the first conformal layer may be consumed by etching at block 730. The CD gain due to the deposition of the first conformal layer may be removed or controlled by etching.

[0103] In some implementations, the deposition-etch sequence after the etching operation at block 730 is repeated until a desired depth or final depth is reached. The deposition-etch sequence may be repeated through the first material layer, the second material layer, or the third material layer and similar layers hereinafter. Method 700 may further include depositing, by ALD, a second conformal layer on the exposed surfaces of the plurality of first pattern features, the pattern mask layer, and the second material layer, and etching the second material layer of the substrate to form a plurality of second pattern features by the plurality of first pattern features. The plurality of second pattern features may have a third roughness that is smaller than each of the first roughness and the second roughness. The third roughness may correspond to a specific LWR / LER value. In some implementations, the LWR value associated with the third roughness is about 2.0 nm, 1.5 nm, or 1.0 nm or less with respect to the inspection length / area of the first roughness and the second roughness, and the LER value associated with the third roughness is about 2.0 nm, 1.5 nm, or 1.0 nm or less with respect to the inspection length / area of the first roughness and the second roughness. In some implementations, the deposition of the second conformal layer by ALD and the etching of the second material layer may be performed in the same plasma chamber as the deposition at block 720 and the etching at block 730 without introducing a vacuum break between operations. Repeating the in-situ ALD operation and the etching operation can result in continuous improvement of LWR / LER without applying CD bias loading.

[0104] FIG. 8C is a schematic diagram showing a side view and a top view of an exemplary partially fabricated semiconductor device from FIG. 8B after etching a first material layer to form a plurality of first pattern features. The partially fabricated semiconductor device 830 is below the pattern mask layer 806 and includes a plurality of first pattern features 822, 824 defined by the pattern mask layer 806. The plurality of first pattern features 822, 824 are formed from the first material layer 812 in FIGS. 8A-8B by selective etching of the first material layer. The etching is not selective to the removal of the second material layer 814 or the pattern mask layer 806. The etching may be performed in the same plasma chamber as the deposition of the first conformal layer 808 in FIG. 8B. The plurality of first pattern features 822, 824 may include 1-D features 822 defined by the 1-D feature 802 and 2-D features 824 defined by the 2-D feature 804. In some implementations, the 1-D features 822 include interconnect lines and the 2-D features 824 include blocks or contact vias. The plurality of first pattern features 822, 824 have a roughness less than that of the pattern mask layer before depositing the first conformal layer 808. In some implementations, the LWR and / or LER values are improved within the plurality of first pattern features 822, 824 over the same given inspection length or area as the pattern mask layer. The plurality of first pattern features 822, 824 may exhibit some roughness in FIG. 8C, but the pattern transferred to the plurality of first pattern features 822, 824 has a roughness smaller than that of the mask. In some implementations, the first conformal layer 808 is removed after etching the first material layer 812. The roughness is improved in the plurality of first pattern features 822, 824, and the effects on CD bias / loading and depth bias / loading are negligible.

[0105] FIG. 8D is a schematic diagram showing a side view and a top view of an exemplary partially fabricated semiconductor device from FIG. 8C after etching a second material layer to form a plurality of second pattern features. The partially fabricated semiconductor device 840 includes a plurality of first pattern features 822, 824 and a plurality of second pattern features 832, 834 that are below the first pattern features 822, 824 and are defined by the first pattern features 822, 824. The plurality of second pattern features 832, 834 are formed from the second material layer 814 in FIGS. 8A - 8C by selective etching of the second material layer 814. The etching is not selective to the third material layer 816. In some implementations, the deposition - etching sequence may be performed when forming the plurality of second pattern features 832, 834. The deposition operation may deposit a second conformal layer (not shown) on the exposed surfaces of the plurality of first pattern features 822, 824 and the second material layer 814 by ALD. The deposition operation may be performed in the same plasma chamber as the etching operation in FIG. 8C and the subsequent etching operation in FIG. 8D. The second conformal layer may further reduce the roughness of the plurality of first pattern features 822, 824. In this way, the roughness of the plurality of first pattern features 822, 824 is prevented from being transferred to the plurality of second pattern features 832, 834. However, it will be understood that the deposition operation may be omitted before etching the second material layer 814. The plurality of second pattern features 832, 834 may include 1 - D features 832 and 2 - D features 834. In some implementations, the LWR and / or LER values are improved within the second pattern features 832, 834 over the same given inspection length or area as the plurality of first pattern features 822, 824. In some implementations, the pattern mask layer 806 is removed after etching the second material layer 814. The roughness is improved in the plurality of second pattern features 832, 834, and the effects on CD bias / loading and depth bias / loading are negligible.In some implementations, the in-situ ALD operation and the etching operation may be repeated within the partially fabricated semiconductor device 840 until reaching the desired depth or layer while improving the LWR / LER. More cycles of the in-situ ALD operation and the etching operation can result in a reduction of the LWR / LER value. Alternatively, the in-situ ALD operation and the etching operation may be performed at any point where it is desirable to reduce the LWR / LER in the etching process, where the in-situ ALD operation and the etching operation are adapted to different underlying material layers (e.g., the third material layer 816), etc. The in-situ ALD operation and the etching operation are not necessarily performed on each underlying material layer.

[0106] The above-described ALD operation and etching operation for improving roughness may improve the roughness on the soft mask and the hard mask. FIGS. 9A-9C are schematic diagrams of an exemplary method of patterning features with a hard mask by using an integrated ALD method and an etching method according to some implementations. FIG. 9D is a schematic diagram showing a top view of the hard mask used in FIGS. 9A-9C before the ALD process. FIG. 9E is a schematic diagram showing a top view of the hard mask used in FIG. 9D after the ALD process.

[0107] The partially fabricated semiconductor device 910 in FIG. 9A includes a hard mask 902, a first material layer 912 underlying the hard mask layer 902, and a second material layer 914 underlying the first material layer 912. The hard mask 902 may include a hard mask material such as silicon oxide, silicon nitride, or silicon oxynitride. In some implementations, the hard mask 902 may have one or more sparse features in the sparse feature region and one or more dense features in the dense feature region. In FIG. 9D, the hard mask 902 exhibits a serrated non-linear edge with several gaps.

[0108] The partially fabricated semiconductor device 920 in FIG. 9B includes a hard mask 902 coated with a conformal layer 904, a first material layer 912 under the hard mask 902, and a second material layer 914 under the first material layer 912. The conformal layer 904 is deposited using ALD as described above. The conformal layer 904 is deposited by ALD on the sidewalls of the hard mask 902 and on the upper surface of the first material layer 912 and the hard mask 902. The conformal layer 904 may be deposited uniformly across one or more sparse features and one or more dense features of the hard mask 902. The conformal layer 904 reduces the roughness of the hard mask 902, and the impact on process throughput, selectivity, and through-pitch loading is minimal. In FIG. 9E, the conformal layer 904 fills the gaps in the hard mask 902 and smoothes the jagged non-linear edges.

[0109] The partially fabricated semiconductor device 930 in FIG. 9C includes a hard mask 902, a pattern feature 922 under the hard mask 902, and a second material layer 914 under the pattern feature 922. The pattern feature 922 is formed after anisotropic etching through the first material layer 912 and may be defined by the hard mask 902. The anisotropic etching may be performed in the same chamber or tool as the deposition of the first conformal layer 904 in FIG. 9B. In some implementations, the conformal layer 904 may remain on the sidewalls of the hard mask 902 after anisotropic etching. In some implementations, the pattern feature 922 may include a conductive material such as tungsten. The conformal layer 904 reduces the roughness of the hard mask 902, so that the roughness transferred to the pattern feature 922 after anisotropic etching is less. In some implementations, the LWR / LER value in the pattern feature 922 is less than the LWR / LER value in the hard mask 902.

[0110] Implementations of the present disclosure may use an integrated ALD operation and etching operation to reduce the sidewall roughness of high aspect ratio features. In some implementations, the cycle of ALD steps and etching steps to reduce sidewall roughness is performed within the plasma processing apparatus described in FIG. 1.

[0111] Protecting the sidewalls is difficult to achieve in high aspect ratio features. Protecting the sidewalls promotes preferential etching at the bottom of the feature as opposed to the sidewalls of the feature. Without sidewall protection, the feature begins to take on a non-uniform profile and the sidewall protection is insufficient.

[0112] Conventional techniques that provide sidewall protection involve plasma-based “flash” passivation. Plasma-based “flash” passivation may refer to colliding a gas such as oxygen (O2), nitrogen (N2), or sulfur dioxide (SO2) to generate a plasma of dissociative radicals, reacting with the surface, and generating a passivation layer of material (e.g., an oxide or nitride) on the surface. Plasma-based “flash” passivation techniques generally minimize the effects of mask faceting, erosion, and bottom trimming due to lateral etching. Plasma-based “flash” passivation methods can consume material on the exposed surface of high aspect ratio features and form a passivation layer of material. In some implementations, the gas is exposed to RF power delivery for a relatively short amount of time, such as between about 0.5 seconds and about 5 seconds, to generate a plasma for plasma-based “flash” passivation. The dissociative radicals react with the exposed surface to form a passivation layer of material, which protects the sidewalls of the high aspect ratio features during etching. In some implementations, the plasma in the plasma-based “flash” passivation technique is used to etch the underlying material while also reacting with the sidewalls of the high aspect ratio features to form a passivation layer of material for sidewall protection.

[0113] However, depositions using plasma-based “flash” inactivation techniques can be dependent on aspect ratio and material. More inactivation material may be deposited near the opening of a high aspect ratio feature than near the bottom of a high aspect ratio feature, and more inactivation material may be deposited on sparse features than on dense features. Non-uniform amounts of inactivation material may be deposited on structures made from various materials. Further, roughness can be introduced on the sidewalls of high aspect ratio features due to non-uniform distribution of the inactivation material formed along the sidewalls of high aspect ratio features. Roughness on the sidewalls of high aspect ratio features can be detrimental to the performance of semiconductor devices (e.g., transistor performance).

[0114] Features within a substrate of a semiconductor device may include high aspect ratio features. High aspect ratio features are features having an aspect ratio of at least about 5:1, at least about 10:1, at least about 15:1, at least about 20:1, at least about 30:1, at least about 40:1, at least about 50:1, or at least about 100:1. For example, a feature having a high aspect ratio may be at least 10:1. In some implementations, the aspect ratio is measured as a comparison of the depth of the feature to the critical dimension of the feature (which is often the width / diameter of the feature). The aspect ratio used herein is measured based on the critical dimension proximate to the opening of the feature. In some implementations, the critical dimension of the feature may be about 20 nm or less.

[0115] The features described in the context of reducing sidewall roughness are recesses within the substrate surface. The features can have many different shapes including, but not limited to, cylindrical, rectangular, square, other polygonal recesses, trenches, etc.

[0116] The formation of high aspect ratio features on a substrate may be performed in multiple etching steps. In other words, high aspect ratio features may be formed by etching to a desired depth and subsequent one or more additional etching steps to reach the final depth. In some implementations, each etching step may etch to a depth of at least 50 nm or at least 100 nm.

[0117] Figures 10A - 10B are schematic diagrams of high aspect ratio features of various materials undergoing passivation and etching using conventional passivation methods in a plasma chamber. As described above, conventional passivation methods in a plasma chamber may include the plasma - based "flash" passivation method described above.

[0118] Figure 10A is a schematic diagram of a partially fabricated semiconductor device 1010 including a substrate 1002, which includes a plurality of structures 1004, 1006 defining one or more features 1008. The partially fabricated semiconductor device 1010 may further include a mask 1012 defining one or more features 1008 on the structures 1004, 1006. The one or more features 1008 are formed or defined after etching through the substrate 1002 or a layer (not shown) of the substrate 1002. By etching through the substrate 1002, the one or more features 1008 may be etched to a depth of 50 nm or more or 100 nm or more. In some implementations, the partially fabricated semiconductor device 1010 may be a transistor device such as a fin field effect transistor (FinFET) device. The structures 1004, 1006 may act as fins of the FinFET device. In some implementations, the structures 1004, 1006 may include a material having semiconductor properties such as silicon, germanium, or a combination thereof. For example, the plurality of structures 1004, 1006 may include a first structure 1004 having a first material and a second structure 1006 having a second material, the first material including silicon and the second material including silicon-germanium. In some implementations, the one or more features 1008 are shallow trench isolation (STI) features of the partially fabricated semiconductor device 1010.

[0119] In FIG. 10A, a first passivation layer 1014 is formed on the sidewalls of the first structure 1004, and a second passivation layer 1016 is formed on the sidewalls of the second structure 1006. The first passivation layer 1014 and the second passivation layer 1016 may be formed using a conventional passivation method such as the above-described plasma-based "flash" passivation technique. For example, an oxygen "flash" passivation technique can use oxygen plasma to react with the materials on the sidewalls of the first structure 1004 and the second structure 1006 to produce an oxide passivation material for the first passivation layer 1014 and the second passivation layer 1016. Each of the first passivation layer 1014 and the second passivation layer 1016 is an oxide (SiOx ) or a nitride (e.g., Si x N y ) may be included.

[0120] The amount of the passivation material deposited on the sidewalls of one or more features 1008 may depend on the aspect ratio and the material. The passivation materials of the first passivation layer 1014 and the second passivation layer 1016 may be deposited more near the openings of one or more features 1008 than at the bottoms of one or more features 1008. Various amounts of the passivation material in the first passivation layer 1014 and the second passivation layer 1016 may be formed in each of the first structure 1004 and the second structure 1006. How much the sidewalls of the first structure 1004 and the second structure 1006 are consumed within the conventional passivation method may vary depending on the materials of the first structure 1004 and the second structure 1006. Further, the passivation material with a non-uniform distribution is deposited along the sidewalls of one or more features 1008 by using the conventional passivation method as shown in FIG. 10A. This results in sidewall roughness within the partially fabricated semiconductor device 1010.

[0121] Figure 10B is a schematic diagram of a partially fabricated semiconductor device 1020 after etching through a substrate 1002 of the partially fabricated semiconductor device 1010 in Figure 10A. The etching in Figure 10A etches through the substrate 1002 to form one or more features 1008 to a first depth, and the etching in Figure 10B may etch through the substrate 1002 to a second depth, where the second depth is greater than the first depth. In some implementations, each of the first depth and the second depth can be 50 nm or more, or 100 nm or more. The first passivation layer 1014 and the second passivation layer 1016 protect the sidewalls of one or more features 1008 from lateral etching during the etching in Figure 10B. The etching in Figure 10B is anisotropic and may be selective to the removal of the material of the substrate 1002 with respect to the first passivation layer 1014 and the second passivation layer 1016. The etching rate of the material of the substrate 1002 is substantially greater than the etching rates of the first passivation layer 1014 and the second passivation layer 1016. Nevertheless, as shown in Figure 10B, the first passivation layer 1014 and the second passivation layer 1016 are ultimately removed, and the sidewalls of one or more features 1008 are exposed to lateral etching. Due to the non-uniform distribution of the passivation material along the sidewalls of one or more features 1008, different amounts of material are etched laterally along the sidewalls. As shown in Figure 10B, sidewall roughness is presented within the sidewalls of one or more features 1008. After etching, more roughness is presented in the upper portions of one or more features 1008 than in the bottom portions of one or more features 1008. In some implementations, the sidewall roughness may correspond to one or both of the LWR and LER values, and one or both of the LWR and LER are about 2.0 nm or more with respect to the inspection length of a given region.

[0122] FIG. 11 is a flowchart of an exemplary method for reducing sidewall roughness of high aspect ratio features using an integrated etching method and an ALD method according to some implementations. The operations in method 1100 may be performed in a different order and / or may be performed with different, fewer, or additional operations. FIG. 11 will be described with reference to FIGS. 12A-12C.

[0123] In block 1110 of method 1100, the substrate is etched in a plasma chamber to a first depth to form a plurality of features at the first depth. The substrate may be a substrate for a semiconductor device, such as a transistor device (e.g., a FinFET device). In some implementations, the substrate is prepared in a plasma chamber. The substrate may be disposed on a substrate support in the plasma chamber. In some implementations, the substrate may be a semiconductor substrate including a silicon substrate, such as a 200 mm, 300 mm, or 450 mm substrate. The plasma chamber may be configured to perform subsequent deposition and etching processes. The aspects of the plasma chamber may be described with respect to the processing apparatus 100 of FIG. 1.

[0124] The plurality of features formed in the substrate may be high aspect ratio features. In some implementations, the high aspect ratio features have a depth-to-width aspect ratio of at least about 5:1, at least about 10:1, at least about 15:1, at least about 20:1, at least about 30:1, at least about 40:1, at least about 50:1, or at least about 100:1. For example, the high aspect ratio features have a depth-to-width aspect ratio of 10:1 or more. In some implementations, the critical dimension of the features is about 20 nm or less.

[0125] The etching to the first depth may etch through the substrate and may partially etch to a target depth or a final depth. Thus, the etching to the target depth or the final depth may occur over multiple etching steps. In some implementations, the first depth of the plurality of features is at least about 50 nm or at least about 100 nm.

[0126] A plurality of features may be defined by a plurality of structures of a substrate after etching to a first depth. The plurality of structures may correspond to fins of a semiconductor device, interconnect lines, electrodes, contacts, vias, etc. For example, the plurality of structures may correspond to fins of a FinFET device. In some implementations, the plurality of structures may include one or more first structures having a first material and one or more second structures having a second material. Each of the first material and the second material may include silicon, germanium, and combinations thereof. For example, the first material may include silicon, and the second material may include silicon-germanium.

[0127] In some implementations, the plurality of features may have different aspect ratios. In some implementations, the plurality of features includes one or more sparse features within a sparse feature region and one or more dense features within a dense feature region having a feature density greater than that of the sparse features.

[0128] FIG. 12A is a schematic diagram of a partially fabricated semiconductor device 1210 including a substrate 1202, the substrate 1202 including a plurality of structures 1204, 1206 that define one or more features 1208. The partially fabricated semiconductor device 1210 may further include a mask 1212 that defines one or more features 1208 over the structures 1204, 1206. The one or more features 1208 are defined after etching through the substrate 1202 or a layer (not shown) of the substrate 1202. In some implementations, the layer of the substrate 1202 may be a gate layer of a FinFET device. By etching through the substrate 1202, the one or more features 1208 may be etched to a first depth of at least about 50 nm or at least about 100 nm. In some implementations, the structures 1204, 1206 may act as fins of a FinFET device. In some implementations, the structures 1204, 1206 may include a material having semiconductor characteristics, such as silicon, germanium, or a combination thereof. For example, the plurality of structures 1204, 1206 may include a first structure 1204 having a first material and a second structure 1206 having a second material, the first material including silicon and the second material including silicon-germanium. In some implementations, the one or more features 1208 are STI features of the partially fabricated semiconductor device 1210.

[0129] Returning to FIG. 11, at block 1120 of method 1100, a first passivation layer is deposited on the sidewalls of the plurality of features by ALD. The first passivation layer may be deposited on the exposed surface of the substrate, including the exposed surfaces of the plurality of structures, by ALD. The exposed surfaces of the plurality of structures include the sidewalls of the plurality of features. The first passivation layer may be deposited conformally and provide high step coverage even for high aspect ratio features. The step coverage of the plurality of features may be greater than 85%, greater than 90%, or greater than 95%. The deposition operation at block 1120 is performed in the same plasma chamber as the etching operation at block 1110 without introducing a vacuum break between operations. Performing the ALD and the etching operation in the same plasma chamber reduces additional cleaning steps and transfers that would otherwise result in higher costs and undesirable CD / mask losses.

[0130] The first passivation layer may serve to protect the sidewalls of the feature mask pattern during subsequent etching processes, such as the etching process described at block 1130. In some implementations, the first passivation layer includes a passivation material such as an oxide or a nitride. For example, the first passivation layer includes silicon oxide (SiO x ).

[0131] In some implementations, the first passivation layer is relatively thin. For example, the first passivation layer has a thickness between about 0.2 nm and about 10 nm, or between 0.5 nm and about 5 nm.

[0132] As described above, ALD is a technique for depositing thin material layers using sequential self-limiting reactions. The ALD method for conformally depositing the first passivation layer may be performed in one or more cycles, and each cycle generates an adsorption-limiting amount of material on the sidewalls of a plurality of features. Each cycle may include an input step of delivering a controlled amount of precursor material to the substrate surface and adsorbing it on the substrate surface in a self-limiting manner. This is also known as "soaking" the substrate surface for saturation. Each cycle may further include a conversion step after the input step, providing a reactant material on the substrate surface to react with the precursor material and forming an adsorption-limiting amount of passivation material. The reactant material may include a reaction gas, and an RF power source generates a plasma of the reaction gas in the plasma chamber. The reaction gas may include, for example, an oxygen-containing gas (e.g., O2) or a nitrogen-containing gas (e.g., N2 or NH3). The reactive gas of radicals and other charged species reacts with the precursor material and converts the precursor material into an adsorption-limiting amount of passivation material. In some implementations, the reaction gas is exposed to the delivery of RF power for a relatively short amount of time, such as between about 0.5 seconds and about 5 seconds, to generate a plasma and convert the precursor material. This is known as a "flash" operation that uses a plasma from the RF power delivered for a relatively short amount of time on the substrate surface to convert the precursor material. In some implementations, a removal step may remove excess precursor material, reaction by-products, and / or unreacted reactant material from the plasma chamber to complete the cycle. In some implementations, the input step and the conversion step may be repeated until the desired thickness of the first passivation layer is deposited.

[0133] The deposition of the first passivation layer is independent of the aspect ratio, pitch, and material. The thickness of the first passivation layer along the sidewalls of the plurality of features is relatively uniform, depositing approximately the same amount of material across different CDs, different aspect ratios, different pitches, different depths, and different materials. For different aspect ratios, the CD bias between one or more sparse features in the sparse feature region and one or more dense features in the dense feature region is substantially the same after depositing the first passivation layer. Thus, the thickness of the first passivation layer along the sidewalls of the plurality of features is substantially the same within the sparse feature region and the dense feature region. Regarding the CD bias between the sparse feature and the dense feature, "substantially the same" throughout this disclosure refers to a value that is plus or minus 5% of the stated value. For different materials, the CD bias between one or more first structures having a first material and one or more second structures having a second material is substantially the same after depositing the first passivation layer. Thus, the thickness of the first passivation layer along the sidewalls of the plurality of features is substantially the same for one or more first structures and one or more second structures. Regarding the CD bias between structures of different materials, "substantially the same" throughout this disclosure refers to a value that is plus or minus 5% of the stated value.

[0134] FIG. 12B is a schematic diagram of a partially fabricated semiconductor device 1220 after depositing a first passivation layer 1214 on the exposed surface of the partially fabricated semiconductor device 1210 of FIG. 12A. The first passivation layer 1214 is deposited on the sidewalls of one or more features 1208, including on the sidewalls of the first structure 1204 and the second structure 1206. The first passivation layer 1214 may be deposited on the sidewalls and the upper surface of the mask 1212 and on the upper surface of the substrate 1202. The first passivation layer 1214 may be conformally deposited on the sidewalls of one or more features 1208 using the ALD method described above. In some implementations, the first passivation layer 1214 is an oxide (e.g., SiO x ) or a nitride (e.g., Si x N y) may be included. In some implementations, the thickness of the first passivation layer 1214 may be between about 0.5 nm and about 5 nm.

[0135] The amount of passivation material deposited on the sidewalls of one or more features 1208 is independent of the aspect ratio and the material. Thus, the thickness of the first passivation layer 1214 is substantially the same near the openings of the one or more features 1208 as compared to the bottom of the one or more features 1208, and the thickness of the first passivation layer 1214 is substantially the same on the first structure 1204 and the second structure 1206. Further, as shown in FIG. 12B, a relatively uniform distribution of passivation material is deposited on the sidewalls of the one or more features 1208 using the ALD method described above. This results in relatively smooth sidewalls within the partially fabricated semiconductor device 1220.

[0136] Returning to FIG. 11, in block 1130 of method 1100, a plurality of features are etched to a second depth greater than the first depth, and the first passivation layer is configured to substantially reduce sidewall roughness after etching to the second depth. The etching operation in block 1130 is performed in the same plasma chamber as the deposition operation in block 1120 without introducing a vacuum break between operations. Performing the ALD operation and the etching operation in the same plasma chamber reduces additional cleaning steps and transfers that could otherwise result in higher costs and undesirable CD / mask losses.

[0137] Etching may be anisotropic etching to a second depth through a plurality of features. Etching may remove material of the substrate or a layer of the substrate. Etching may be selective to the removal of the material of the substrate with respect to the material of the first passivation layer. In this way, the etching performed at block 1130 etches the material of the substrate at a rate substantially faster than the material of the first passivation layer. In some implementations, the second depth may be equal to the target depth or the final depth. In some implementations, the second depth may be less than the target depth or the final depth. For example, the second depth may be any suitable percentage of the final depth, such as 30%, 40%, 50%, 60%, 70%, 80%, etc. of the final depth. The first depth may be an even smaller percentage with respect to the final depth. Thus, multiple etching may be performed to reach the final depth. The aspect ratio of the plurality of features may be measured at the final depth, and the aspect ratio of the plurality of features may be at least 10:1.

[0138] After etching to the second depth, the first passivation layer is configured to substantially avoid lateral etching of the sidewalls of the plurality of features and substantially reduce the sidewall roughness within the sidewalls. Typically, conventional passivation techniques such as plasma-based "flash" passivation techniques result in sidewall roughness as shown in FIGS. 10A-10B. In some implementations, the sidewall roughness may correspond to one or both of the LWR and LER values for a given inspection area. In some implementations, conventional passivation techniques such as plasma-based "flash" passivation techniques result in LWR and / or LER values that are about 2.0 nm or greater. The LWR and / or LER values may be calculated for a given inspection length or area. However, since the first passivation layer is deposited uniformly along the sidewalls of the plurality of features using in-situ ALD and etching, a relatively smooth sidewall surface is achieved after etching at block 1130. In some implementations, the in-situ ALD and etching techniques described in blocks 1120 and 1130 result in LWR and / or LER values that are about 1.5 nm or less. As used herein, substantially reduced sidewall roughness may correspond to LWR and / or LER values that are about 1.5 nm or less. The LWR and / or LER values may be calculated for a given inspection length or area and may be the same when comparing conventional passivation techniques to the in-situ ALD and etching techniques of the present disclosure. For example, the sidewall roughness in high aspect ratio features may correspond to an LWR value that is about 1.5 nm or less for inspection lengths of 50 nm or greater or 100 nm or greater. Generally, the sidewall roughness can be improved by at least 25% between conventional passivation techniques and the in-situ ALD and etching techniques of the present invention for a given inspection length or area.

[0139] In some implementations, the etching operation performed at block 1130 is not selective to the first passivation layer, and the first passivation layer is preserved during the etching. In other words, the first passivation layer is removed at a substantially slower rate than the surrounding materials. That being said, a specific thickness or entirety of the first passivation layer may be consumed by the etching at block 1130. Since the first passivation layer is conformal along the sidewalls of the plurality of features, the amount of the first passivation layer removed by the etching at block 1130 is substantially the same along the sidewalls of the plurality of features. This means that the thickness of the first passivation layer near the opening of the feature is substantially the same as the thickness of the first passivation layer near the bottom of the feature. The amount of the first passivation layer removed by the etching at block 1130 is independent of the aspect ratio and the material.

[0140] In some implementations, the deposition-etching sequence after the etching at block 1130 is repeated until a desired depth or a final depth is reached. The deposition-etching sequence may be repeated at least two times, at least four times, or at least five times to reach the final depth. This deposition-etching sequence may be repeated within the same plasma chamber without introducing a vacuum break between the operations. Thus, method 1100 includes depositing a second passivation layer on the sidewalls of the plurality of features by ALD in a plasma chamber and etching the plurality of features to a third depth greater than a second depth in the plasma chamber. The second passivation layer may be configured to substantially avoid lateral etching of the sidewalls of the plurality of features and substantially reduce the sidewall roughness after etching to the third depth. In some implementations, the substantially reduced sidewall roughness in high aspect ratio features may correspond to an LWR value of about 1.5 nm or less for an inspection length of 50 nm or more or 100 nm or more.

[0141] FIG. 12C is a schematic diagram of a partially fabricated semiconductor device 1230 after etching to a second depth greater than the first depth shown in the partially fabricated semiconductor device 1220 of FIG. 12B. In some implementations, each of the first depth and the second depth may be at least about 50 nm or at least about 100 nm. In some implementations, the second depth may correspond to a desired depth or a final depth, or may correspond to a ratio of the desired depth or the final depth. The first passivation layer 1214 protects the sidewalls of one or more features 1208 during etching and minimizes the generation of sidewall roughness within the sidewalls of the one or more features 1208. The etching in FIG. 12C is anisotropic and may be selective to the material of the substrate 1202 with respect to the first passivation layer 1214. The etching rate of the substrate 1202 is substantially greater than the etching rate of the first passivation layer 1214. Nevertheless, as shown in FIG. 12C, the first passivation layer 1214 is ultimately removed and the sidewalls of the one or more features 1208 are exposed to lateral etching. However, when the first passivation layer 1214 is deposited conformally, the sidewalls of the one or more features 1208 exhibit a smooth profile. The first passivation layer 1214 not only acts as a protective layer against lateral etching, but also substantially limits the generation of roughness within the sidewalls of the one or more features 1208. In some implementations, the sidewall roughness may correspond to one or both of the LWR and LER values, and one or both of the LWR and LER are about 1.5 nm or less.

[0142] Connection The above embodiments have been described in some detail for purposes of clarity of understanding, but it will be apparent that certain changes and modifications may be made within the scope of the appended claims. Note that there are many alternative ways to implement the methods, systems, and apparatuses of this embodiment. Accordingly, this embodiment should be regarded as illustrative and not restrictive, and the embodiments should not be limited to the details shown herein. The present disclosure can be realized in, for example, the following forms. [Form 1] A method comprising: depositing a first conformal layer on a pattern mask layer of a substrate by atomic layer deposition (ALD) in a plasma chamber, wherein the substrate includes a first material layer and the pattern mask layer on the first material layer, and the pattern mask layer has a first roughness before depositing the first conformal layer; etching the first material layer in the plasma chamber to form a plurality of first pattern features of the first material layer defined by the pattern mask layer; wherein the plurality of first pattern features have a second roughness smaller than the first roughness of the pattern mask layer after etching the first material layer. [Form 2] The method according to Form 1, wherein the first roughness corresponds to a first line edge roughness (LER) and a first line width roughness (LWR), the second roughness corresponds to a second LER and a second LWR, the second LER is about 2.0 nm or less, and the second LWR is about 2.0 nm or less. [Form 3] The method according to Form 1, wherein the thickness of the first conformal layer is between about 0.5 nm and about 5 nm. [Form 4] The method according to Form 1, further comprising: performing a lithography operation and an etching operation on a mask layer to form the pattern mask layer. [Form 5] The method according to Form 1, wherein the pattern mask layer includes a photoresist material. [Form 6] The method according to Form 1, wherein the pattern mask layer includes a hard mask material. [Form 7] The method according to Form 1, wherein the pattern mask layer is configured to define one or more one-dimensional (1-D) features from the first material layer and one or more two-dimensional (2-D) features from the first material layer, and a critical dimension (CD) bias between the one or more 1-D features and the one or more 2-D features is substantially the same after etching the first material layer. [Form 8] The method according to Form 1, wherein the pattern mask layer includes one or more sparse features in a sparse feature region and one or more dense features in a dense feature region having a feature density greater than that of the sparse feature region, and a CD bias between the one or more sparse features and the one or more dense features is substantially the same after etching the first material layer. [Form 9] The method according to any one of Forms 1 to 8, wherein the substrate further includes a second material layer under the first material layer, and the method includes depositing a second conformal layer on exposed surfaces of the plurality of first pattern features, the pattern mask layer, and the second material layer by ALD in the plasma chamber; etching the second material layer of the substrate to form a plurality of second pattern features defined by the plurality of first pattern features in the plasma chamber The method further includes. [Form 10] The method according to Form 9, wherein the plurality of second pattern features have a third roughness smaller than each of the first roughness and the second roughness. [Form 11] The method according to Form 10, wherein the third roughness corresponds to a third LER and a third LWR, the third LER is about 1.5 nm or less, and the third LWR is about 1.5 nm or less. [Form 12] The method according to any one of Forms 1 to 8, wherein a critical dimension of the plurality of first pattern features is about 20 nm or less. [Form 13] The method according to any one of Forms 1 to 8, wherein the first conformal layer includes silicon oxide (SiO x ) [Form 14] The method according to any one of Forms 1 to 8, wherein the deposition of the first conformal layer by ALD is (a) Introducing a precursor that adsorbs onto the pattern mask layer into the plasma chamber; (b) Converting the precursor by plasma to form the first conformal layer with a certain adsorption limit; (c) Repeating the operations of introducing the precursor and converting the precursor until the first conformal layer with a desired thickness is deposited on the pattern mask layer A method comprising the above. [Embodiment 15] A method comprising: Etching the substrate to a first depth in a plasma chamber to form a plurality of features at the first depth; Depositing a first passivation layer on sidewalls of the plurality of features by atomic layer deposition (ALD) in the plasma chamber; Etching the plurality of features to a second depth greater than the first depth in the plasma chamber A method, wherein the first passivation layer is configured to substantially reduce sidewall roughness after etching to the second depth. [Embodiment 16] The method according to Embodiment 15, wherein one or both of the LWR and LER values of the sidewalls are about 1.5 nm or less after etching the plurality of features to the second depth. [Embodiment 17] The method according to Embodiment 15, wherein the plurality of features include shallow trench isolation (STI) features. [Embodiment 18] The method according to Embodiment 15, wherein the aspect ratio of the depth to width of each of the plurality of features is 10:1 or more. [Embodiment 19] The method according to Embodiment 15, wherein the critical dimension of the plurality of features is about 20 nm or less. [Embodiment 20] The method according to Embodiment 15, wherein each of the first depth and the second depth is about 100 nm or more. [Embodiment 21] The method according to any one of Embodiments 15 to 20, wherein the plurality of features include one or more sparse features in a sparse feature region and one or more dense features in a dense feature region having a feature density greater than that of the sparse feature region, and the thickness of the first passivation layer along the sidewalls of the plurality of features is substantially the same in the sparse feature region and the dense feature region. [Embodiment 22] The method according to any one of Forms 15 to 20, wherein the plurality of features are defined by a plurality of structures, one or more first structures include a first material, one or more second structures include a second material different from the first material, and the thickness of the first passivation layer along the sidewalls of the plurality of features is substantially the same for the one or more first structures and the one or more second structures. [Form 23] The method according to any one of Forms 15 to 20, wherein the plurality of features are defined by a plurality of structures, and each of the structures includes silicon, germanium, or a combination thereof. [Form 24] The method according to any one of Forms 15 to 20, depositing a second passivation layer on the sidewalls of the plurality of features by ALD in the plasma chamber; etching the plurality of features in the plasma chamber to a third depth greater than the second depth in the substrate; The method further includes, wherein the second passivation layer is configured to substantially reduce sidewall roughness after etching the plurality of features to the third depth. [Form 25] The method according to any one of Forms 15 to 20, wherein depositing and etching the plurality of features by ALD in the plasma chamber is performed without introducing a vacuum break during the operation. [Form 26] [[ID=eleven]]The method according to any one of Forms 15 to 20, wherein the first passivation layer includes silicon oxide (SiO x [[ID=twelve]])

Claims

**Claim 1** A method comprising: etching a substrate to a first depth in a plasma chamber to form a plurality of features at the first depth; depositing a first passivation layer on sidewalls of the plurality of features by atomic layer deposition (ALD) in the same plasma chamber without introducing a vacuum break; etching the plurality of features to a second depth greater than the first depth in the same plasma chamber without introducing the vacuum break; wherein the first passivation layer is configured to substantially reduce sidewall roughness after etching to the second depth. **Claim 2** The method of claim 1, wherein one or both of the LWR and LER values of the sidewalls are about 1.5 nm or less after etching the plurality of features to the second depth. **Claim 3** The method of claim 1, wherein the plurality of features includes shallow trench isolation (STI) features. **Claim 4** The method of claim 1, wherein the aspect ratio of depth to width of each of the plurality of features is 10:1 or greater. **Claim 5** The method of claim 1, wherein the critical dimension of the plurality of features is about 20 nm or less. **Claim 6** The method of claim 1, wherein each of the first depth and the second depth is about 100 nm or greater. **Claim 7** The method according to any one of claims 1 to 6, wherein the plurality of features includes one or more sparse features in a sparse feature region and one or more dense features in a dense feature region having a feature density greater than that of the sparse feature region, and the thickness of the first passivation layer along the sidewalls of the plurality of features is substantially the same in the sparse feature region and the dense feature region. **Claim 8** The method according to any one of claims 1 to 6, wherein the plurality of features is defined by a plurality of structures, one or more first structures include a first material, one or more second structures include a second material different from the first material, and the thickness of the first passivation layer along the sidewalls of the plurality of features is substantially the same in the one or more first structures and the one or more second structures. **Claim 9** A method according to any one of claims 1 to 6, wherein the plurality of features are defined by a plurality of structures, and each of the structures includes silicon, germanium, or a combination thereof.

10. A method according to any one of claims 1 to 6, depositing, in the plasma chamber, a second passivation layer on sidewalls of the plurality of features by ALD; etching, in the plasma chamber, the plurality of features to a third depth greater than the second depth in the substrate; further comprising, wherein the second passivation layer is configured to substantially reduce sidewall roughness after etching the plurality of features to the third depth.

11. The method according to any one of claims 1 to 6, wherein the first inactivation layer contains silicon oxide (SiO x ).

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