Power semiconductor device

Abstract

The power semiconductor device (10) comprises a semiconductor body (11) having a first major surface (12) and a second major surface (13), a gate insulator (14) disposed on the first major surface (12), and a gate electrode (15) separated from the semiconductor body (11) by the gate insulator (14). The semiconductor body (11) comprises a drift layer (16) of a first conductivity type, a well layer (27) of a second conductivity type different from the first conductivity type and forming a first junction (18) with the drift layer (16), a source region (20) of the first conductivity type forming a second junction (21) with the well layer (27), and an island region (30) of the second conductivity type to which the source region (20) is attached such that the source region (20) separates the island region (30) and the well layer (27) over at least 50% of an island surface area of ​​the island region (30) in the semiconductor body (11).

Description

Technical Field

[0001] The present disclosure relates to power semiconductor devices.

Background Art

[0002] Power semiconductor devices are realized, for example, as metal-oxide-semiconductor field-effect transistors, abbreviated as MOSFETs. MOSFETs can be based on wide bandgap materials such as, for example, silicon carbide materials, abbreviated as SiC materials. Currently, 650V and 1200V rated SiC MOSFETs are commercially available. The SiC market is mainly driven by low voltage devices, but the use of SiC power MOSFETs above 3.3 kV in medium voltage and high voltage systems such as traction applications is also attracting more attention. When implemented in either planar or trench cell designs, SiC MOSFETs offer excellent static losses, fast dynamic performance, and adequate reliability. In terms of fault handling capabilities, SiC MOSFETs still do not reach the typical industry standard values shown by Si-compatible products. This is usually related to a strong trade-off between conduction losses and short-circuit withstand, abbreviated as SCWT.

[0003] U.S. Patent Application Publication No. 2017 / 0229535 relates to a semiconductor device having a source region having a source contact region, a source extension region, and a source resistance control region.

Summary of the Invention

Problems to be Solved by the Invention

[0004] There is a need for a power semiconductor device that improves the trade-off between conduction loss and short-circuit withstand.

Means for Solving the Problems

[0005] According to one embodiment, a power semiconductor device includes a semiconductor body having first and second main surfaces, a gate insulator disposed on the first main surface of the semiconductor body, and a gate electrode separated from the semiconductor body by the gate insulator. The semiconductor body includes a drift layer of a first conductivity type, a well layer of a second conductivity type different from the first conductivity type and forming a first junction with the drift layer, a source region of the first conductivity type forming a second junction with the well layer, and an island region of the second conductivity type. The source region is attached to the island region such that the source region separates the island region from the well layer at a part of the island surface area of the island region, illustratively at least 50% of the island surface area of the island region.

[0006] In one example, the island surface area is the complete surface of the island region. The island surface area includes the surfaces of each side of the island region. Thus, the island surface area includes the areas of the bottom surface, top surface, and side surfaces of the island region. The island region is, for example, a rectangular parallelepiped such as a non-rectangular parallelepiped. The rectangular parallelepiped can have rounded corners and / or edges. The rectangular parallelepiped has six faces or sides. The island surface area illustratively includes the surfaces of the six sides of the island region.

[0007] "Attach" shall mean that the island region can be disposed within the source region such that the island region is embedded within the source region. Thus, the island region may be completely surrounded by the source region on each side surface of the island region. The source region can separate the island region from the well layer at 100% of the island surface area. This means that the island region can be surrounded by the source region in each of the three dimensions of the island region. The island region can be realized as an embedded region or an embedded layer.

[0008] Alternatively, "attaching" means that the island region extends to the first main surface, but the island region can be disposed on the source region such that the island region and the well layer are separated at at least 50% or at least 70% or at least 80% or at least 90% or 100% of the island surface area. In one example, the separation of the island region from the well layer is realized partially by the source region and partially by electrodes such as isolators and / or source electrodes. For this reason, the island region is not completely embedded in or surrounded by the source region. This means that the island region is not surrounded by the source region in each of the three dimensions of the island region. However, in one example, the island region is surrounded by the source region in two dimensions of the island region, and the two dimensions are parallel to the first main surface, for example, and can be seen in a top view, for example.

[0009] The expression "attaching" particularly means that the island region is adjacent to the source region.

[0010] Exemplarily, the island region reduces the cross-section of the source region. Therefore, in the form of the source region and the island region, the source resistance value may be slightly increased. The island region changes the source resistance so as to increase the short-circuit tolerance without significantly affecting the on-resistance.

[0011] In one example, the island region is surrounded by the source region on the first main surface of the semiconductor body. The island region extends to the first main surface.

[0012] In one example, the island region is surrounded by the source region within the semiconductor body in a plane parallel to the first main surface of the semiconductor body. The island region extends to the first main surface or does not extend.

[0013] According to at least one embodiment, the well layer includes a well region that separates the source region and the drift layer, and a well contact region on the first main surface. The well contact region has a maximum doping concentration higher than that of the well region.

[0014] According to at least one embodiment, the power semiconductor device includes a source electrode disposed on at least a part of the source region and at least a part of the well contact region. The source electrode forms an ohmic contact with the source region and the well contact region.

[0015] According to at least one embodiment, the source electrode does not have an ohmic contact with the island region.

[0016] According to at least one alternative embodiment, the source electrode is additionally disposed on at least a part of the island region. Also, the source electrode forms an ohmic contact with the island region.

[0017] According to at least one embodiment, the power semiconductor device is a field effect transistor or an insulated gate bipolar transistor, abbreviated as IGBT. For example, the power semiconductor device described herein can be, for example, an MIS-based (metal-insulator-semiconductor) or MOS-based (metal-oxide-semiconductor) or junction field effect transistor, abbreviated as JFET, or included therein. The device may be a trench or planar device. The semiconductor body can be based on a wide bandgap material such as silicon carbide or gallium nitride, or silicon. Thus, the power semiconductor device is a device selected from, or can be present in, the group consisting of, for example, metal oxide semiconductor field effect transistors (MOSFETs), metal insulator semiconductor field effect transistors (MISFETs), junction field effect transistors (JFETs), and insulated gate bipolar transistors (IGBTs).

[0018] According to at least one embodiment, the semiconductor body further comprises a collector layer. The collector layer has the same conductivity type as the well region. The collector layer may be disposed on a second main surface (referred to as the lower side) of the semiconductor body opposite to the first main surface (referred to as the upper side of the semiconductor body). One collector layer may exist for all source regions. The collector layer may be referred to as a back surface layer. The collector electrode can be applied directly to the collector layer. If there is a collector layer, the power semiconductor device can be an IGBT.

[0019] According to at least one embodiment, the semiconductor further comprises at least one drain region. The drain region has the same conductivity type as at least one source region. For example, the drain region is a layer on the second main surface. The drain region may be named or may be formed by the back surface layer. For example, the drift region is located between the first main surface and the drain region. One common drain region may exist for all source regions. The drain electrode may be in direct contact with at least one drain region. If a drain region exists, the power semiconductor device can be a MOSFET or a MISFET or a JFET. The drain layer has a higher doping concentration than the drift layer.

[0020] The semiconductor body is made of, for example, a wide bandgap material. The wide bandgap material is, for example, one of silicon carbide SiC, gallium nitride GaN, and gallium oxide Ga2O3, or another wide bandgap material. The power MISFET or the power MOSFET is based on a wide bandgap material, for example, a silicon carbide material. Therefore, the power semiconductor device can be realized as a SiC MOSFET or a SiC MISFET.

[0021] According to at least one embodiment, the power semiconductor device is a power device. For example, the power semiconductor device is configured for a maximum voltage of at least 0.1 kV or at least 0.5 kV.

[0022] In one example, the island region is realized by a shallow implantation of the second conductivity type. The second conductivity type is, for example, p-type conductivity or p-doping.

[0023] In one example, a MOSFET or MISFET includes a shallow p-implantation to enhance the short-circuit capability. A p-island is additionally implanted into the source region to provide an improved trade-off between conduction loss and SCWT. The increased source resistance due to the additional p+ implantation reduces the SCWT without significantly increasing the on-state resistance.

[0024] The present disclosure includes several aspects. All features described with respect to one aspect are disclosed herein with respect to other aspects as well, even if each feature is not explicitly recited in the context of a particular aspect.

[0025] The accompanying drawings are included to provide further understanding. In the figures, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the figures are exemplary representations and are not necessarily drawn to scale.

Brief Description of the Drawings

[0026]

Figure 1A

Figure 1B

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Figure 2B

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Figure 2E

Figure 2F

Figure 2G

Figure 2H

Figure 3

Figure 4A

Figure 4B

Figure 5A

Figure 5B

Figure 5C

Figure 5D

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Figure 6C

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DETAILED DESCRIPTION OF THE INVENTION

[0027] Figures 1A and 1B are a perspective view and a top view of the power semiconductor device 10. The power semiconductor device 10 is realized as a MOSFET or a MISFET such as, for example, a SiC MOSFET or a SiC MISFET. A typical perspective view of the power semiconductor device 10 realized as a MOSFET or a MISFET is shown in FIG. 1A, and a top view of its source design is shown in FIG. 1B. The power semiconductor device 10 includes a semiconductor body 11, a gate insulator 14, and a gate electrode 15. The semiconductor body 11 is realized as a wide bandgap substrate, for example, a silicon carbide semiconductor substrate. The semiconductor body 11 includes a first main surface 12 and a second main surface 13. Silicon carbide is abbreviated as SiC. The gate insulator 14 is disposed on or above the first main surface 12 of the semiconductor body 11. The gate electrode 15 is disposed on or above the gate insulator 14.

[0028] The semiconductor body 11 includes a drift layer 16 of a first conductivity type, a well layer 27 of a second conductivity type, and a source region 20 of the first conductivity type. The second conductivity type is different from the first conductivity type. The well layer 27 may include a well region 17 and a well contact region 19 that are both of the second conductivity type. The well layer 27 separates the source region 20 from the drift layer 16. The well region 17 forms a first junction 18 with the drift layer 16. The well contact region 19 is, for example, inside the well region 17. Alternatively, the well contact region 19 may have the same depth as the well region 17 or even a greater depth. The source region 20 forms a second junction 21 with the well layer 27, and thus the well region 17 and the well contact region 19.

[0029] The semiconductor body 11 includes a back surface layer 23 of a first conductivity type located on the second main surface 13. The power semiconductor device 10 includes a drain electrode 24 disposed on the back surface layer 23. The back surface layer 23 realizes, for example, a drain region. The drain electrode 24 forms an ohmic contact with the back surface layer 23. The drift layer 16 includes a junction field effect transistor region 25 (abbreviated as JFET region) adjacent to the well region 17. When the power semiconductor device 10 is in a conductive state, a region located inside the well region 17 and between the source region 20 and the JFET region 25 forms a channel 26. The channel 26 is located inside the well region 17 at the interface with the gate insulator 14.

[0030] The semiconductor body 11 includes a further well layer 27' of a second conductivity type and further source regions 20', 20" of a first conductivity type. The further well layer 27' includes a further well region 17' of a second conductivity type and a further well contact region 19* of a second conductivity type. The power semiconductor device 10 is symmetric, for example, with respect to a center line passing through the center of the gate electrode 15. Therefore, in the following figures, since the "right side portion" corresponds to the "left side portion", only the "left side portion" of the power semiconductor device 10 will be discussed.

[0031] The power semiconductor device 10 includes, for example, a gate having parallel stripes as shown in FIG. 1A, or a mesh gate having cells. The cells are in one of the forms of a square, rectangle or hexagon, or have another form.

[0032] For example, the power semiconductor device 10 has a cell design. This may mean that, in a top view, the gate electrode 15 is, for example, but not limited to, square or substantially square in shape. Otherwise, the power semiconductor device 10 may have a stripe design such that the gate electrode 15 is considerably longer than the width. In both the cell design and the stripe design, a plurality of gate electrodes 15 may be present.

[0033] For example, the gate electrode 15 has a planar configuration. Therefore, the gate electrode 15 is located on the first main surface 12 (referred to as the upper side) of the semiconductor body 11, and the first main surface 12 is planar. In this case, neither the gate electrode 15 nor the gate insulator 14 penetrates into the semiconductor body 11.

[0034] According to an alternative, not shown embodiment, the gate electrode 15 has a trench configuration. In this case, the gate electrode 15 extends into a trench of the semiconductor body 11. For example, the gate insulator 14 covers the sidewalls and the bottom of the trench. The gate electrode 15 is disposed on the gate insulator 14 within the trench. Thereby, the gate insulator 14 insulates the gate electrode 15 from any doped layer within the semiconductor body 11.

[0035] In the examples shown in FIGS. 1A and 1B, the first conductivity type is n-doped and the second conductivity type is p-doped. In one example, the structure of one cell of the power semiconductor device 10 is shown in FIG. 1A. The power semiconductor device 10 includes, for example, several cells corresponding to the cell shown in FIG. 1A and described in detail in the following figures.

[0036] In an alternative embodiment, in the example shown in FIG. 5B, the first conductivity type is p-doped and the second conductivity type is n-doped. Therefore, in the figure, n and p are interchanged.

[0037] For example, the maximum doping concentration of the source region 20, the back surface layer 23, or the drain region and the well contact region 19 is in the range of 1·10 18 cm -3 ~5·10 20 cm -3 . Also, the maximum doping concentration of the well region 17 may be 1·10 16 cm -3 or more. Depending on the voltage class of the power semiconductor device 10, the maximum doping concentration of the drift region 16 may be in the range of 1·10 14 cm -3 ~1·10 17 cm -3 .

[0038] As shown in FIG. 1B, the power semiconductor device 10 includes a source electrode 22 disposed on at least a part of the source region 20 and at least a part of the well contact region 19. The source electrode 22 forms an ohmic contact with the source region 20 and the well contact region 19. The gate electrode 15 and the source electrode 22 are drawn with hatching in FIGS. 1B, 2A to 2H, 5A and 5B. The gate electrode 15 is on the gate insulator 14 on the semiconductor body 11. The source electrode 22 is on the semiconductor body 11. The gate electrode 15 and the gate insulator 14 overlap the source region 20. A part of the gate electrode 15 is above a part of the source region 20 but not in contact.

[0039] FIG. 2A is a top view of the power semiconductor device 10 according to an embodiment which is a further development of the embodiment shown in FIGS. 1A and 1B. The semiconductor body 11 includes an island region 30 of a second conductivity type. The island region 30 is surrounded by the source region 20 in a plane parallel to the first main surface 12 of the semiconductor body 11. For this reason, the island region 30 is surrounded by the source region 20 in at least two dimensions (that is, a dimension parallel to the long side of the island region 30 and a dimension perpendicular to the first main surface 12). On the first main surface 12, the source region 20 separates the island region 30 and the junction field effect transistor region 25. On the first main surface 12, the source region 20 separates the island region 30 and the well contact region 19. The island region 30 shown in FIG. 2A has two long sides both attached to the region of the source region 20. The sides of the two long sides of the island region 30 are attached to the region of the source region 20.

[0040] Exemplarily, the source region 20 is also attached to the bottom surface of the island region 30 (for example, as shown in FIG. 3). For this reason, the island region 30 is surrounded by the source region 20 in three dimensions (that is, a dimension parallel to the width of the island region 30, a dimension parallel to the long side of the island region 30, and a dimension perpendicular to the first main surface 12).

[0041] As a result, the power semiconductor device 10 is realized as, for example, a SiC MOSFET or a SiC MISFET with a p+ implantation added to the source region 20. The island region 30 forms a third junction 31 with the source region 20. The well region 17, the well contact region 19, the source region 20, and the island region 30 are located on the first main surface 12. In one example, the well contact region 19 and the island region 30 are highly p-doped, and the well region 17 is p-doped, that is, less doped than the island region 30 or the well contact region 19. The source region 20 and the back surface layer 23 are highly n-doped, and the drift layer 16 is weakly n-doped, that is, less doped than the source region 20. In one example, the well contact region 19 and the island region 30 have the same maximum doping concentration. Alternatively, the well contact region 19 and the island region 30 have different maximum doping concentrations. The well contact region 19 and the island region 30 do not necessarily have to be doped at the same doping level.

[0042] The island region 30 may be disposed in the source region 20 on the first main surface 12. In another embodiment, the island region 30 is disposed within the source region 20 such that the source region 20 completely surrounds the island region 30.

[0043] The active region of the semiconductor device is the region between the main electrode (which may be the source electrode 22) on the first main surface 12 and the back surface electrode (which may be the drain electrode 24 or the collector electrode) on the back surface side of the semiconductor body. The island region 30 is disposed in the active region.

[0044] The island region 30 has a cuboid shape such as a rectangular parallelepiped. In a top view, the island region 30 has a rectangular shape. The rectangle may have rounded corners or sharp corners. The two long sides of the rectangle of the island region 30 are completely adjacent to the source region 20. In one example, the material (not shown) of the smaller side of the rectangle of the island region 30 is a further part of the source region 20 or is formed by an isolator or an isolation structure. Alternatively, the island region 30 forms a ring structure. The island region 30 is formed in a rectangle in a plane parallel to the first main surface 12.

[0045] The island region 30 is realized as a shallow region. A part of the source region 20 is below the "bottom" of the island region 30. The depth of the island region 30 is less than the depth of the source region 20. The depth is measured starting from the first main surface 12. Thus, a part of the source region 20 between the well contact region 19 and the island region 30 is connected to and / or has a conductive path to a part of the source region 20 between the well region 17 and the island region 30. Further, a part of the source region 20 between the well contact region 19 and the island region 30 is connected to and / or has a conductive path to a part of the source region 20 between the channel 26 and the island region 30. The island region 30 is not in conductive contact with the drift layer 16 through a semiconductor region. The island region 30 is not in conductive contact with the well layer 27 through a semiconductor region. The island region 30 is not in conductive contact with the well contact region 19 through a semiconductor region. The island region 30 is not in conductive contact with the well region 17 through a semiconductor region.

[0046] A further well region 17’ (not shown) corresponds to the well region 17. A further well contact region 19* (not shown) corresponds to the well contact region 19. A further source region 20’ (not shown) corresponds to the source region 20. A further island region (not shown) of the semiconductor body 11 corresponds to the island region 30. As shown in FIGS. 2A to 2D, the source electrode 22 has no ohmic contact with the island region 30. That is, the island region 30 is not electrically connected to a fixed potential. The island region 30 is electrically floating. Since MOSFETs and MISFETs are fabricated using additional p+ implants to the source region 20, the resistance of the source region 20 may increase.

[0047] FIG. 2B is a top view of the power semiconductor device 10 according to an embodiment which is a further development of the embodiments shown in FIGS. 1A, 1B, and 2A. The source region 20 has a form of finger structures meshing with each other or includes finger structures meshing with each other. The well layer 27 is located between the fingers 32, 32’ of the finger structures meshing with each other. The well contact region 19 is located between the fingers 32, 32’ of the finger structures meshing with each other. The source region 20 includes stripes 33. The fingers 32, 32’ of the finger structures meshing with each other are connected to the stripes 33 in the connection region. The fingers 32, 32’ extend from this stripe 33 in the direction of the well contact region 19 and / or the source electrode 22. The source region 20 has M fingers 32, 32’. In FIG. 2B, the number M is 2. For example, the number M is at least 2 or more. In any case, the number of fingers is such that the finger structures meshing with each other extend over the entire stripe length of the stripe 33 or over a part of the entire stripe length.

[0048] The island region 30 is completely surrounded by the source region 20 on the first main surface 12 of the semiconductor body 11. The island region 30 is located within the stripe 33 of the connection region on the first main surface 12. The island region 30 is close to the first part and the second part of the well contact regions 19, 19'. The island region 30 is close to exactly one finger 32 of the finger structures that mesh with each other. The distance D is considered to be the minimum distance from the island region 30 to the well contact region 19 and the well contact region 19'. The distance D can be 0.05 μm or more.

[0049] The maximum doping concentration of the island region 30 is 0.5·10 18 cm -3 ~2·10 21 cm -3 within the range, or 10 18 cm -3 ~10 20 cm -3 within the range.

[0050] In the top view shown in FIG. 2B, the island region 30 has, for example, a rectangular form. In one example, the rectangle has a square form. The semiconductor body 11 includes N island regions 30, 30'. For example, the island regions of the N island regions 30, 30' are formed identically. The number M of fingers 32, 32' is equal to the number N of island regions 30, 30'. Alternatively, the number M of fingers 32, 32' is greater than the number N of island regions 30, 30'. In FIG. 2B, the number N is 2. Alternatively, the number N of island regions 30, 30' is at least 1 or at least 2, or more.

[0051] The N island regions 30, 30' have the source region 20 attached thereto such that the source region 20 separates the island regions of the N island regions 30, 30' from the well layer 27 at least in part, e.g., at least 50%, of the island surface area of the N island regions 30, 30'. In one example, the source region 20 separates each of the island regions of the N island regions 30, 30' from the well layer 27 at least in part, e.g., at least 50%, of the island surface area of the island region 30.

[0052] FIG. 2C is a top view of the power semiconductor device 10 according to an embodiment which is a further development of the above-described embodiment. The island region 30 is located within the fingers 32 of the intermeshing finger structure on the first main surface 12. The island region 30 is located between two portions of the well contact regions 19, 19'. In the top view shown in FIG. 2C, the island region 30 has a rectangular form.

[0053] FIG. 2D is a top view of the power semiconductor device 10 according to an embodiment which is a further development of the above-described embodiment. The island region 30 is located within the fingers 32 of the intermeshing finger structure on the first main surface 12. In the top view shown in FIG. 2D, the island region 30 has a trapezoidal form. The width of the trapezoid is smaller near the stripe 33. Alternatively, the width of the trapezoid is larger near the stripe 33. The island region 30 is formed in a trapezoidal shape in a plane parallel to the first main surface 12.

[0054] The island region 30 has a rectangular form as shown in FIGS. 2A to 2C or a trapezoidal form as shown in FIG. 2D on the first main surface 12 of the semiconductor body 11. Other forms of the island region 30 are possible, e.g., circular, elliptical, triangular, rhombic, pentagonal, hexagonal, etc. in a top view.

[0055] In FIGS. 2A to 2D, the island region 30 is floating, that is, not electrically connected to any of the electrodes. The island region 30 has no metal connection. The island region 30 is surrounded by the source region 20 inside the semiconductor body 11. The island region 30 is covered by an isolator (not shown) on the first main surface 12. Each of the N island regions 30, 30' is floating. In one example, the island regions 30, 30' of the N island regions are realized identically.

[0056] FIGS. 2E to 2H are top views of the power semiconductor device 10 according to an embodiment which is a further development of the above-described embodiment shown in FIGS. 2A to 2D, for example. The source electrode 22 is disposed on at least a part of the island region 30. The source electrode 22 forms an ohmic contact with the island region 30. The island region 30 is electrically connected to the source region 20 and the well contact region 19 by the source electrode 22.

[0057] Different layouts for source design having some configurations of additional shallow p+ implants or implants for realizing the island region 30 or the island regions 30, 30' are shown in FIGS. 2A to 2H (top views). The n+ and p+ regions can have a simple stripe-like design as shown in FIGS. 2A and 2E, or can have a three-dimensional non-uniform design as shown in FIGS. 2B to 2D and FIGS. 2F to 2H. For example, the p+ region is segmented and includes additional implant islands 30, 30'.

[0058] The power semiconductor device 10 implements several of the following features. - The well contact region 19 realized by the p+ region and the source region 20 realized by the n+ region can have a "finger"-like design as shown in FIGS. 2B to 2D and FIGS. 2F to 2H.

[0059] The island regions 30, 30' realized by the -p+ islands can be implanted near the fingers 32, 32' of the source region 20 realized by the n+ fingers, as shown in FIGS. 2B and 2F.

[0060] The island regions 30, 30' realized by the -p+ regions can be arranged between the p+ portions of the well contact region 19 and can have different shapes as shown in FIGS. 2B to 2D and FIGS. 2F to 2H.

[0061] The island regions 30, 30' realized by the additional p+ implant can be left floating (as shown in FIGS. 2A to 2D) or can be short-circuited to the source region 20 via the source electrode 22 to realize metal contact as shown in FIGS. 2E to 2H. For any of the described layouts, if the doping profile of the island can be equally selected for the well contact region, the proposed design does not require an additional mask for manufacturing, and the additional p+ implant can be realized during the contact process step.

[0062] In one example, the mask for realizing the well contact region 19 includes a further structure for realizing the island region 30. The island region 30 and the well contact region 19 are implanted together in a common implantation process.

[0063] In an alternative embodiment, the set of masks for manufacturing the power semiconductor device 10 includes a mask for realizing the island region 30. The island region 30 is implanted in an implantation process separately from other implantation processes, such as the implantation process of the well contact region 19. In this case, the doping profile of the island region 30 can be different from the doping profile of the well contact region 19.

[0064] In the region below the island region 30, a part of the source region 20 separates the island region 30 and the well region 17.

[0065] The depth of the p+ island region 30 can be used as a design parameter and can be up to 95% of the depth of the n+ source region 20. The dimensions of the p+ stripes / regions and their distances to the p+ fingers can vary, similar to their doping. The distance D is the minimum distance from the island region 30 to the well contact region 19 and can be used as an additional design parameter. The maximum doping concentration of the island region 30 is from 0.5×10 18 cm -3 to 10 21 cm -3 and this can also be used as a design parameter. The overlay of the upper metal realizing the source electrode 22 with the source region 20 and / or the island regions 30, 30' (referred to as additional p+ implantations) can also be used as a design parameter.

[0066] Figures 2A to 2H show a portion of the power semiconductor device 10. This portion can be at least one portion of a MOSFET or MISFET having parallel stripes and a MOSFET or MISFET having a mesh gate.

[0067] Figure 3 is a cross-sectional view of a power semiconductor device 10 according to a different embodiment which is a further development of the above embodiment. Figure 3 shows the source design of the layout of Figure 2A or Figure 2E when the value of the implantation length L is different. The island region 30 is realized as a shallow region having a thickness smaller than the thickness of the source region 20. The thickness of the island region 30 is, for example, less than 95% or less than 50% of the thickness of the source region 20 in this case. In one example, the thickness of the island region 30 is smaller than the thickness of the well contact region 19.

[0068] The source region length LS is an extension of the source region 20 parallel to the flow of the main current in the source region 20. The source region length LS is the distance from the well contact region 19 to the channel region 26, for example, the shortest distance from the well contact region 19 to the channel region 26. The island region length L is an extension of the island region 30 in the direction between the well contact region 19 and the channel region 26 (both the channel region 26 and the well contact region 19 have a gap with the island region 30). The extension of the source region 20 having the source region length LS is parallel to the extension of the island region 30 having the island region length L. The source region length LS is in the same direction as the island region length L. The island region length L has a value within the range of 5% or more and 95% or less of the source region length LS. According to the example shown in FIG. 3, the source region 20 separates the island region 30 from the well layer 27 at at least 50% (for example, more than 50%) of the island surface area of the island region 30. The island surface area of the island region 30 may be completely (i.e., 100%) separated from the well layer 27. A part of the island surface area is covered by the source region 20, and a part is covered by electrodes (not shown) such as an isolator and / or the source electrode 22.

[0069] The layouts of FIGS. 2A and 2E have been investigated by technology computer-aided design (TCAD) simulations considering, as an example, the structures representing devices rated at 1.2 kV for different values of the island region length L (about 20% of LS, 40% of LS, and 75% of LS). The depth of the island region 30, also called the thickness or implantation depth of the island region 30, is set to 30% of the source region depth, and its maximum doping concentration is 10 20 cm -3 is set.

[0070] Figures 4A and 4B show the simulated characteristics of the power semiconductor device 10 according to an embodiment which is a further development of the above-described embodiment. In Figure 4A, the static output characteristics (left side) and short-circuit waveforms (right side) of the source design of Figure 2E (data marked as P or P1, P2, P3) are compared with the reference MOSFET structure (data marked as R). Data was generated for different values of the island region length L (i.e., approximately 20%, 40%, and 75% of the source region length LS) by simulation. The reference MOSFET is simulated using the same parameters as the proposed design (regarding doping, dimensions, etc.), but without an island region.

[0071] On the left side, the drain current density JD is shown as a function of the drain-source voltage VDS. The following parameters were used: gate-source voltage VGS = 15V, temperature T = 300K. The drain current density JD is normalized to 1 with respect to the maximum values in Figures 4A and 4B. On the right side, the drain current density JD during the electrothermal short-circuit simulation is shown as a function of time t. The following parameters were used: gate-source voltage VGS = -10V / +15V, temperature T = 300K, drain-source voltage VDS = 600V. These parameters for the characteristics on the left and right sides were also used in Figures 4B and 7.

[0072] The static output characteristics (left side) and short-circuit waveforms (right side) in Figure 4A are obtained using the source design of Figure 2E for grounded p+ injection. Compared with the reference MOSFET, the maximum reduction in the peak value of the drain current density JD during short-circuit is achieved at L = 75%LS (the data is marked as P3) and is approximately 15%. The reductions when using L = 20%LS (the data is marked as P1) and L = 40%LS (the data is marked as P2) are approximately the same.

[0073] The static output characteristics (left side) and short-circuit waveforms (right side) of FIG. 4B are obtained using the source design of FIG. 2A for floating p+ implantation. The reduction in the peak value of the drain current density JD compared to the reference MOSFET is approximately the same for three different values of L, and is about 14% in one example.

[0074] Two cases are considered, both for grounded p+ implantation and floating p+ implantation. The resulting output waveforms and short-circuit waveforms are reported in FIGS. 4A and 4B respectively. There is little difference in the static performance compared to the reference design (left side), but for the maximum drain current density during short circuit (right side), a reduction of up to 15% can be achieved, for example. Also, the breakdown voltage is not affected by the additional implantation into the source region 20.

[0075] FIG. 5A is a top view of the power semiconductor device 10 according to an embodiment which is a further development of the above-described embodiment. The island region 30 is completely surrounded by the source region 20 on the first main surface 12 of the semiconductor body 11. N island regions 30, 30', 30" are arranged, for example, in a straight line or on a ring line. The gap between two adjacent island regions 30, 30' is the distance D1. The distance D1 is, for example, greater than 0.05 μm or greater than 0.5 μm.

[0076] FIG. 5B is a top view of the power semiconductor device 10 according to an embodiment which is a further development of the above-described embodiment, as shown, for example, in FIG. 2A. The first conductivity type is p-doped and the second conductivity type is n-doped.

[0077] FIG. 5C is a top view of the island region 10 according to an embodiment which is a further development of the above-described embodiment. The island region 30 is formed in a polygon such as a hexagon, illustratively a regular hexagon, when viewed from above the first main surface 12 or in a plane parallel to the first main surface 12. The polygon may have other forms such as a triangle, a quadrilateral, a pentagon, a heptagon, etc.

[0078] FIG. 5D is a top view of the island region 10 according to an embodiment which is a further development of the above embodiment. The island region 30 is formed in an oval shape such as an ellipse in a top view in a plane on or parallel to the first main surface 12.

[0079] FIG. 5E is a top view of the island region 10 according to an embodiment which is a further development of the above embodiment. The island region 30 is formed in an oval shape such as a circle in a top view in a plane on or parallel to the first main surface 12. A circle is a special form of an ellipse. The island region 30 has a form of a cylinder (for example, in a perspective view). The embodiments of the island region 30 shown in FIGS. 5C to 5E can be arranged in the island regions of the N island regions 30, 30', 30" shown in FIGS. 2A to 2H and FIG. 5A or each island region.

[0080] FIG. 6A is a perspective view, and FIGS. 6B and 6C are cross-sectional views of a simulated structure of the power semiconductor device 10 according to an embodiment which is a further development of the embodiment shown above in FIG. 2C. The simulated current density streamlines of the proposed design are reported in FIG. 6A as a 3D view and in FIGS. 6B and 6C as 2D cross-sections. FIG. 6B shows a cross-section marked AA in FIG. 6A. FIG. 6C shows a cross-section marked BB in FIG. 6A. The current path is shown as a line with an arrow. In the region 34, the lines are very dense. The region 34 is the region where the current density is the highest. The 3D view shows how the p+ shallow implant restricts the current during the short circuit, thus increasing the source resistance and resulting in a self-limiting effect. In FIGS. 6A to 6C, the simulated current density (measured in Acm -2 during the short circuit pulse corresponding to the current peak of the proposed design in FIG. 2C is shown.

[0081] As shown in FIG. 6A, a high current density exists in the source region 20 within the gap between the island region 30 and the well contact region 19. Further, as shown in FIG. 6B, a high current density exists inside the source region 20 under the island region 30, which means within the portion of the source region 20 that fills the gap between the island region 30 and the well region 17. The high current density in the increased region 34 relative to other regions of the source region 20 has a positive effect during a short circuit. Advantageously, the island region 30 results in a decrease in the peak value JSAT of the drain current density JD during a short circuit, as shown in FIG. 7. However, the region 34 has little or no adverse effect on the overall on-state resistance of the device 10 during normal operation.

[0082] FIG. 7 shows the characteristics of the power semiconductor device 10 according to an embodiment that is a further development of the above-described embodiment. In FIG. 7, the static output characteristics (left side) and short-circuit waveforms (right side) (data marked with P) of the source design of FIG. 2C represented by the perspective view of FIG. 6 are compared with the reference MOSFET structure (data marked with R).

[0083] On the left side, the drain current density JD is shown as a function of the drain-source voltage VDS. In the structure having the proposed source design of FIG. 2C, the rating of the drain current density is less than 2.5%, that is, the increase in the specific on-resistance is less than 2.5%. The percentage value of 2.5% is only an example of the analyzed case. The following parameters were used: gate-source voltage VGS = 15V, temperature T = 300K. The drain current density JD is normalized to 1 with respect to the maximum value.

[0084] On the right side, the drain current density JD during an electrothermal short-circuit simulation is shown as a function of time t. In the analyzed example, in the proposed design, the decrease in the peak value of the drain current density JD compared to the reference MOSFET is approximately 24%. The following parameters were used: gate-source voltage VGS = -10V / +15V, temperature T = 300K, drain-source voltage VDS = 600V.

[0085] FIG. 7 shows the simulated isothermal output JD-VDS curves and electrothermal short-circuit waveforms (with VGS varying from -10V to +15V) of the device 10 of FIG. 2C compared to a standard MOSFET design. The resistance value RON increases slightly, but JSAT, which is the peak value of the drain current density JD during short circuit, decreases significantly. Since the energy received by the power semiconductor device 10 during short circuit is directly related to the maximum value of JSAT, the proposed design improves the short-circuit tolerance without significantly affecting the conduction loss.

[0086] While the present disclosure is susceptible to various modifications and alternative forms, specific details thereof have been shown by way of example in the drawings and are described in detail. It should be understood, however, that the intention is not to limit the present disclosure to the particular embodiments described. Rather, the intention is to cover all modifications, equivalents, and alternative forms falling within the scope of the disclosure as defined by the appended claims.

[0087] The embodiments shown in FIGS. 1-7 above represent exemplary embodiments of an improved power semiconductor device, and thus they do not constitute a complete list of all embodiments by an improved power semiconductor device. An actual power semiconductor device may be different from the embodiments shown with respect to, for example, arrangement, device, structure, layout, and layers.

Description of Reference Numerals

[0088] Reference Numeral 10 Power semiconductor device 11 Semiconductor body 12 First main surface 13 Second main surface 14 Gate insulator 15 Gate electrode 16 Drift layer 17, 17’ Well region 18, 18’ First junction 19, 19’, 19” Well contact region 19* Further well contact region 20, 20’, 20” source regions 21 Second junction 22 Source electrode 23 Back surface layer 24 Drain electrode 25 Junction field effect transistor region 26 Channel 27, 27’ Well layer 30, 30’ Island regions 31 Third junction 32, 32’ Fingers 33 Strip 34 Region D Distance JD Drain current density L Island region length LS Source region length t Time VDS Drain-source voltage

Claims

1. A power semiconductor device (10), comprising: - A semiconductor body (11) having a first main surface (12) and a second main surface (13); - A gate insulator (14) disposed on the first main surface (12); - A gate electrode (15) separated from the semiconductor body (11) by the gate insulator (14). The semiconductor body (11) includes: - A drift layer (16) of a first conductivity type; - A well layer (27) of a second conductivity type, different from the first conductivity type, forming a first junction (18) with the drift layer (16); - A source region (20) of the first conductivity type, forming a second junction (21) with the well layer (27); - A second-conductivity-type island region (30) in which the source region (20) separates the island region (30) and the well layer (27) at at least 50% of the island surface area of the island region (30) within the semiconductor body (11). The source region (20) has a form of intermeshing finger structures. The well layer (27) is located between fingers (32, 32') of the intermeshing finger structures. A power semiconductor device (10).

2. A power semiconductor device (10), comprising: - A semiconductor body (11) having a first main surface (12) and a second main surface (13); - A gate insulator (14) disposed on the first main surface (12); - A gate electrode (15) separated from the semiconductor body (11) by the gate insulator (14). The semiconductor body (11) includes: - A drift layer (16) of a first conductivity type; - A well layer (27) of a second conductivity type, different from the first conductivity type, forming a first junction (18) with the drift layer (16); - A source region (20) of the first conductivity type, forming a second junction (21) with the well layer (27); - A second-conductivity-type island region (30) in which the source region (20) separates the island region (30) and the well layer (27) at at least 50% of the island surface area of the island region (30) within the semiconductor body (11). The island region (30) is formed as any one of a group consisting of a rectangle, a trapezoid, a hexagon, a circle, and an ellipse in a plane parallel to the first main surface (12). A power semiconductor device (10).

3. The well layer (27) includes a well region (17) that separates the source region (20) from the drift layer (16), and a well contact region (19) on the first main surface (12) having a maximum doping concentration higher than that of the well region (17). The power semiconductor device (10) according to claim 1 or 2.

4. The distance (D) from the island region (30) to the well contact region (19) is greater than 0.05 μm. The power semiconductor device (10) according to claim 3.

5. The power semiconductor device (10) includes a source electrode (22) disposed on at least a part of the source region (20) and at least a part of the well contact region (19). The source electrode (22) forms an ohmic contact with the source region (20) and the well contact region (19). The source electrode (22) has no ohmic contact with the island region (30). The power semiconductor device (10) according to claim 3.

6. The power semiconductor device (10) includes a source electrode (22) disposed on at least a part of the source region (20), at least a part of the well layer (27), and at least a part of the island region (30). The source electrode (22) forms an ohmic contact with the source region (20), the well layer (27), and the island region (30). The power semiconductor device (10) according to claim 3.

7. The island region (30) is not in conductive contact with the drift layer (16) via a semiconductor region and is not in conductive contact with the well layer (27) via a semiconductor region. The power semiconductor device (10) according to claim 1 or 2.

8. The island region (30) is located within the fingers (32) of the meshing finger structure on the first main surface (12). The power semiconductor device (10) according to claim 1.

9. The source region (20) includes a stripe (33). The fingers (32, 32') of the meshing finger structure are connected to the stripe (33) within the connection region. The island region (30) is located within the stripe (33) within the connection region in the first main surface (12). The power semiconductor device (10) according to claim 1.

10. The maximum doping concentration of the island region (30) is 0.5×10 １８ cm －３ to 2×10 ２１ cm －３ within the range of, The power semiconductor device (10) according to claim 1 or 2.

11. - The semiconductor body (11) is a wide bandgap material, or silicon carbide, or silicon, or - The power semiconductor device (10) is at least one of a field effect transistor or an insulated gate bipolar transistor. The power semiconductor device (10) according to claim 1 or 2.

12. The thickness of the island region (30) is less than 95% of the thickness of the source region (20). The power semiconductor device (10) according to claim 1 or 2.

13. The semiconductor body (11) includes N island regions (30). The power semiconductor device (10) according to claim 1 or 2.

14. The island region length (L) of the island region (30) has a value within the range of 5% or more and 95% or less of the source region length (LS) of the source region (20). The power semiconductor device (10) according to claim 1 or 2.

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