Transistor and semiconductor device

Abstract

A transistor comprising a first electrode and a second electrode, a first crystalline oxide semiconductor provided in contact with the first electrode and / or the second electrode, a second crystalline oxide semiconductor connecting the first electrode and the second electrode via the first crystalline oxide semiconductor, and a third electrode adjacent to the second crystalline oxide semiconductor without contacting the second crystalline oxide semiconductor, wherein the first electrode and the second electrode are laminated via at least a first insulating film, and the lattice constant of the first crystalline oxide semiconductor is larger than the lattice constant of the second crystalline oxide semiconductor.

Description

Technical Field

[0001] The present invention relates to a transistor and a semiconductor device. Specifically, the present invention relates to a transistor and a semiconductor device capable of improving contact resistance.

Background Art

[0002] Transistors having an amorphous oxide semiconductor layer such as indium gallium zinc oxide (IGZO) as a channel are known (Patent Documents 1 and 2). When such an oxide semiconductor layer is used as a channel, a high-resistance metal oxide layer may be formed between the oxide semiconductor layer and the metal electrode, increasing the contact resistance between the oxide semiconductor layer and the metal electrode. In order to suppress the increase in contact resistance, Patent Documents 1 and 2 propose interposing a specific oxide layer between the oxide semiconductor layer and the metal electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

[0004] However, in conventional technologies including Patent Documents 1 and 2, there is still room for further improvement from the viewpoint of improving contact resistance in transistors.

[0005] One object of the present invention is to provide a transistor and a semiconductor device capable of improving contact resistance.

Means for Solving the Problems

[0006] As a result of intensive studies, the inventors of the present invention have found that by using a crystalline oxide semiconductor (second crystalline oxide semiconductor) as the oxide semiconductor, interposing a crystalline oxide semiconductor (first crystalline oxide semiconductor) between the oxide semiconductor and the electrode, and forming the lattice constant of the first crystalline oxide semiconductor to be larger than the lattice constant of the second crystalline oxide semiconductor, the contact resistance can be improved, and thus the present invention has been completed. According to the present invention, the following transistors and the like can be provided. 1. A first electrode and a second electrode, A first crystalline oxide semiconductor provided in contact with the first electrode and / or the second electrode, A second crystalline oxide semiconductor connecting the first electrode and the second electrode via the first crystalline oxide semiconductor, A third electrode adjacent to the second crystalline oxide semiconductor without contact therewith, Comprising: The first electrode and the second electrode are laminated via at least a first insulating film, The lattice constant of the first crystalline oxide semiconductor is larger than the lattice constant of the second crystalline oxide semiconductor, Transistor. 2. The transistor according to 1, wherein the first crystalline oxide semiconductor has a higher average carrier concentration than the second crystalline oxide semiconductor. 3. The transistor according to 1 or 2, wherein the composition of the metal elements constituting the first crystalline oxide semiconductor and the composition of the metal elements constituting the second crystalline oxide semiconductor are substantially the same. 4. The transistor according to 3, wherein the composition ratio of the metal elements constituting the first crystalline oxide semiconductor and the composition ratio of the metal elements constituting the second crystalline oxide semiconductor are substantially the same. 5. The transistor according to any one of 1 to 4, wherein the ratio of the lattice constant of the second crystalline oxide semiconductor to the lattice constant of the first crystalline oxide semiconductor is 0.940 or more and 0.999 or less. 6. The transistor according to any one of 1 to 5, wherein the thickness of the first crystalline oxide semiconductor is 2 nm or more and 100 nm or less. 7. The transistor according to any one of 1 to 6, further comprising a second insulating film provided between the third electrode and the second crystalline oxide semiconductor. 8. The transistor according to any one of 1 to 7, wherein the second crystalline oxide semiconductor penetrates at least the first insulating film. 9. The first electrode and the third electrode are laminated with each other with the first insulating film interposed therebetween, The third electrode and the second electrode are laminated with each other with a third insulating film interposed therebetween, The transistor according to any one of 1 to 8, wherein the second crystalline oxide semiconductor penetrates the first insulating film, the third electrode, and the third insulating film and is provided in a columnar shape. 10. The second crystalline oxide semiconductor penetrates the first electrode and the first insulating film and is provided in a columnar shape, The transistor according to any one of 1 to 6, further comprising a second insulating film on an inner peripheral surface and a bottom surface of a recess formed from one end side to the other end side of the columnar second crystalline oxide semiconductor, The third electrode is provided so as to fill the recess in which the second insulating film is formed. 11. The transistor according to any one of 1 to 10, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N). 12. The transistor according to any one of 1 to 11, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor includes a perovskite crystal structure. 13. The transistor according to any one of 1 to 12, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains indium oxide as a main component. 14. The transistor according to any one of 1 to 13, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains Ga or Al. 15. The transistor according to any one of 1 to 13, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains Ga. 16. The transistor according to any one of 1 to 13, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains Ga and Al. 17. The transistor according to any one of 1 to 16, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a polycrystalline oxide semiconductor. 18. The transistor according to any one of 1 to 16, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a single-crystalline oxide semiconductor. 19. The transistor according to any one of 1 to 18, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a crystalline oxide semiconductor formed by an atomic layer deposition method. 20. A semiconductor device including the transistor according to any one of 1 to 19. 21. The semiconductor device according to 20, which is a semiconductor memory device. 22. a first electrode and a second electrode, a first crystalline oxide semiconductor provided in contact with the first electrode and / or the second electrode, a second crystalline oxide semiconductor connecting the first electrode and the second electrode via the first crystalline oxide semiconductor, a third electrode adjacent to the second crystalline oxide semiconductor without contacting the second crystalline oxide semiconductor, and comprising: the first electrode and the second electrode are stacked via at least a first insulating film, the lattice constant of the first crystalline oxide semiconductor is larger than the lattice constant of the second crystalline oxide semiconductor, the composition ratio of the metal elements constituting the first crystalline oxide semiconductor and the composition ratio of the metal elements constituting the second crystalline oxide semiconductor are substantially the same, the ratio of the lattice constant of the second crystalline oxide semiconductor to the lattice constant of the first crystalline oxide semiconductor is 0.940 or more and 0.999 or less, the thickness of the first crystalline oxide semiconductor is 2 nm or more and 100 nm or less, the first crystalline oxide semiconductor and the second crystalline oxide semiconductor include a Bixbyite crystal structure, a transistor.

[0007] According to the present invention, it is possible to provide a transistor and a semiconductor device capable of improving contact resistance.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

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Figure 8

Embodiments for Carrying Out the Invention

[0009] Hereinafter, the transistor and semiconductor device of the present invention will be described in detail. In addition, in this specification, "x to y" represents a numerical range of "x or more and y or less". The upper limit value and the lower limit value described with respect to the numerical range can be arbitrarily combined. Also, among the individual embodiments of the aspects according to the present invention described below, those that do not contradict each other can be combined with two or more, and an embodiment obtained by combining two or more embodiments is also an embodiment of the aspect according to the present invention.

[0010] 1. Transistor A transistor according to an aspect of the present invention is a first electrode and a second electrode, a first crystalline oxide semiconductor provided in contact with the first electrode and / or the second electrode, a second crystalline oxide semiconductor connecting the first electrode and the second electrode via the first crystalline oxide semiconductor, a third electrode adjacent to the second crystalline oxide semiconductor without contact therewith, and includes the first electrode and the second electrode are laminated via at least a first insulating film, the lattice constant of the first crystalline oxide semiconductor is larger than the lattice constant of the second crystalline oxide semiconductor. According to the transistor of this aspect, an effect of improving the contact resistance can be obtained. More specifically, in this embodiment, the transistor uses a crystalline oxide semiconductor (second crystalline oxide semiconductor) as the oxide semiconductor connecting the first electrode and the second electrode, and also interposes a crystalline oxide semiconductor (first crystalline oxide semiconductor) between the oxide semiconductor and the electrode, and the lattice constant of the first crystalline oxide semiconductor is larger than the lattice constant of the second crystalline oxide semiconductor. This utilizes the fact that the resistance value of the first crystalline oxide semiconductor with a relatively large lattice constant decreases compared to the second crystalline oxide semiconductor with a relatively small lattice constant. Usually, when forming an oxide semiconductor on a metal electrode, a high-resistance metal oxide layer is formed at the interface between the electrode (first electrode and / or second electrode) and the oxide semiconductor, and the contact resistance tends to increase. However, in this embodiment, since the resistance value of the first crystalline oxide semiconductor in the region in contact with the electrode (first electrode and / or second electrode) is low as described above, the contact resistance of the transistor can be improved.

[0011] (First Embodiment) Hereinafter, with reference to FIGS. 1 and 2, an example (first embodiment) of the transistor according to this embodiment will be described. FIG. 1 is a schematic perspective view showing a cross section of the transistor according to the first embodiment. FIG. 2 is a schematic cross-sectional view of the transistor. In this embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, first crystalline oxide semiconductors 151a and 151b, a second crystalline oxide semiconductor 152, a first insulating film 14a, and a third insulating film 14b. The first electrode 11 and the second electrode 12 are laminated with at least the first insulating film 14a (here, the first insulating film 14a and the third insulating film 14b) interposed therebetween. Note that the “lamination” as used herein may mean that at least a part of the first electrode 11 and at least a part of the second electrode 12 are arranged along a direction orthogonal to the plane direction of a substrate (not shown) that supports the transistor 10. Further, although not shown, when a plurality of transistors 10 are arranged in series in a planar manner (in the X-Y direction) (when the plurality of transistors 10 form a transistor array), at least a part of the first electrode 11 and at least a part of the second electrode 12 may be arranged along a direction orthogonal to the plane direction (Z direction) in that case. At least a part of the first insulating film 14a may be interposed between the first electrode 11 and the second electrode 12. The third electrode is provided adjacent to the second crystalline oxide semiconductor 152 without contacting it. The third electrode 13 is located between the first electrode 11 and the second electrode 12.

[0012] Of the first insulating film 14a and the third insulating film 14b, the first insulating film 14a is located between the first electrode 11 and the third electrode 13. Thus, the first electrode 11 and the third electrode 13 are electrically insulated from each other by the first insulating film 14a. Also, the third insulating film 14b is located between the second electrode 12 and the third electrode 13. Thus, the second electrode 12 and the third electrode 13 are electrically insulated from each other by the third insulating film 14b.

[0013] Note that in the region shown in FIG. 2, the third electrode 13 is arranged between the first insulating film 14a and the third insulating film 14b. However, outside the region shown in FIG. 2, the first insulating film 14a and the third insulating film 14b may be in contact with each other to form one layer. In this case, in the region, the third electrode 13 may not be arranged between the first insulating film 14a and the third insulating film 14b.

[0014] The second crystalline oxide semiconductor 152 is provided so as to penetrate at least the first insulating film 14a and connect the first electrode 11 and the second electrode 12. The second crystalline oxide semiconductor 152 may penetrate the third electrode 13 and / or the third insulating film 14b in addition to the first insulating film 14a. Here, the second crystalline oxide semiconductor 152 is provided in a columnar shape penetrating the first insulating film 14a, the third electrode 13, and the third insulating film 14b in this order. In this case, the third electrode 13 preferably surrounds the side of the second crystalline oxide semiconductor 152 (the periphery in the direction perpendicular to the length direction) over the entire circumference at a part in the length direction of the second crystalline oxide semiconductor 152 (the central part in the example of FIG. 2) via the second insulating film 16 described later. Thereby, even if the channel length of the crystalline oxide semiconductor 15 described later becomes short, it becomes easy to prevent leakage current. At the same time, it is also advantageous in terms of miniaturization. Note that the length direction of the crystalline oxide semiconductor 15 here may be the vertical direction in FIG. 2 (the direction connecting the first electrode and the second electrode), may be the direction along the channel length described later, may be the thickness direction of the laminate in which the first insulating film 14a, the third electrode 13, and the first insulating film 14b are laminated in this order, and may be the height direction of the columnar structure when the crystalline oxide semiconductor 15 is columnar.

[0015] The transistor 10 further includes a second insulating film 16 provided between at least the third electrode 13 and the second crystalline oxide semiconductor 152. By being provided between the third electrode 13 and the second crystalline oxide semiconductor 152, the second insulating film 16 may insulate the third electrode 13 and the second crystalline oxide semiconductor 152. The second insulating film 16 may be provided, for example, also between the first insulating film 14a and / or the third insulating film 14b and the second crystalline oxide semiconductor 152 in addition to between the third electrode 13 and the second crystalline oxide semiconductor 152. Here, the second insulating film 16 is provided so as to surround the side surface of the columnar second crystalline oxide semiconductor 152 over the entire circumference.

[0016] The first crystalline oxide semiconductors 151a and 151b are provided in contact with the first electrode 11 and the second electrode 12, respectively. Specifically, the first crystalline oxide semiconductor 151a is laminated on the surface of the first electrode 11 on the side of the second crystalline oxide semiconductor 152. Further, the first crystalline oxide semiconductor 151b is laminated on the surface of the second electrode 12 on the side of the second crystalline oxide semiconductor 152. The second crystalline oxide semiconductor 152 connects the first electrode 11 and the second electrode 12 via the first crystalline oxide semiconductors 151a and 151b. The second crystalline oxide semiconductor 152 is preferably provided in contact with the first crystalline oxide semiconductors 151a and 151b.

[0017] In a certain aspect, the transistor 10 has a through hole that penetrates a laminate in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are laminated in this order in the thickness direction of the laminate (the vertical direction in FIGS. 1 and 2). The inner peripheral surface of the through hole is covered with a cylindrical second insulating film 16, and it can also be said that the inside of the cylindrical second insulating film 16 is filled with the second crystalline oxide semiconductor 152.

[0018] The dimensions of the transistor 10 may be appropriately designed according to its application and the like. The channel length of the second crystalline oxide semiconductor 152 is, for example, 1 nm to 10 μm, preferably 2 to 1000 nm, more preferably 3 to 100 nm, still more preferably 4 to 50 nm, still more preferably 5 to 30 nm, and still more preferably 6 to 20 nm. Note that the channel length of the second crystalline oxide semiconductor 152 is the length of the second crystalline oxide semiconductor 152 along the thickness direction of the laminate (the vertical direction in FIGS. 1 and 2) in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are laminated in this order, and may coincide with the distance between the first electrode 11 and the second electrode 12 (or the distance between the first crystalline oxide semiconductors 151a and 151b). When the second crystalline oxide semiconductor 152 is columnar, the channel length of the second crystalline oxide semiconductor 152 corresponds to the height of the columnar structure. The channel length of the second crystalline oxide semiconductor 152 may be measured by processing the corresponding portion with a focused ion beam (FIB) to expose it and observing the cross section with a transmission electron microscope (TEM).

[0019] The channel width of the second crystalline oxide semiconductor 152 is, for example, 1 nm or more and 1000 nm or less, preferably 2 nm or more and 500 nm or less. Note that the channel width of the second crystalline oxide semiconductor 152 is the length of the second crystalline oxide semiconductor 152 along a direction perpendicular to the thickness direction of the laminate in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are laminated in this order (for example, the left - right direction in FIG. 2). As shown in FIGS. 1 and 2, when the channel width of the second crystalline oxide semiconductor 152 is not constant with respect to the channel length direction, the channel width of the second crystalline oxide semiconductor 152 may be the average width along the channel length direction. The average width along the channel length direction is the average value when the channel width is measured at 10 or more positions along the channel length direction. When the second crystalline oxide semiconductor 152 is columnar, the channel width of the second crystalline oxide semiconductor 152 corresponds to the lateral width of the columnar structure. Note that when the channel width of the second crystalline oxide semiconductor 152 varies depending on the observation direction (for example, when the channel width is different between the case of observing from a direction perpendicular to the plane of FIG. 2 and the case of observing from the left - right direction of FIG. 2), the channel width when observed from at least one direction may be within the above range.

[0020] The thickness of the second insulating film 16 is, for example, 1 Å or more and 500 nm or less, preferably 1 nm or more and 100 nm or less. In order to suppress the capacitance of the second insulating film 16 from becoming a parasitic component, the thickness of the second insulating film 16 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0021] The thickness of the first crystalline oxide semiconductors 151a and 151b is, for example, 1 Å or more and 500 nm or less, preferably 1 nm or more and 200 nm or less, more preferably 2 nm or more and 100 nm or less. When the thickness of the first crystalline oxide semiconductors 151a and 151b is within the above range, the contact resistance between the electrodes (the first electrode and / or the second electrode) and the second crystalline oxide semiconductor can be further reduced.

[0022] The channel width of the second crystalline oxide semiconductor 152, the thickness of the second insulating film 16, and the thicknesses of the first crystalline oxide semiconductors 151a and 151b may be measured in the same manner as the channel length of the second crystalline oxide semiconductor 152.

[0023] In the transistor 10, the first electrode 11 can function as a source electrode, and the second electrode 12 can function as a drain electrode. In other examples, the first electrode 11 can function as a drain electrode, and the second electrode 12 can function as a source electrode. The third electrode 13 can function as a gate electrode. The first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 can function as a channel (current path) of the transistor 10. For example, when a gate voltage is applied to the third electrode 13 which is a gate electrode, the first electrode 11 and the second electrode 12 are electrically connected by the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152, and the transistor 10 is in an ON state. Also, when no gate voltage is applied, the electrical connection between the first electrode 11 and the second electrode 12 by the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 is released, and the transistor 10 is in an OFF state.

[0024] In this specification and the like, "electrically connected" includes a case where connection is made through "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between connection targets.

[0025] This aspect features that the lattice constants of the first crystalline oxide semiconductors 151a and 151b are larger than the lattice constant of the second crystalline oxide semiconductor 152. This utilizes the fact that the first crystalline oxide semiconductors 151a and 151b having relatively large lattice constants have a higher average carrier concentration and a lower resistance value compared to the second crystalline oxide semiconductor 152 having a relatively small lattice constant. Generally, when forming an oxide semiconductor on a metal electrode, a high-resistance metal oxide layer is formed at the interface between the electrode (the first electrode 11 and / or the second electrode 12) and the oxide semiconductor, and the contact resistance is likely to increase. However, in this embodiment, since the resistance values of the first crystalline oxide semiconductors 151a and 151b in the regions in contact with the electrode (the first electrode 11 and / or the second electrode 12) are low as described above, the contact resistance of the transistor 10 can be improved. Incidentally, the lattice constant of the crystalline oxide semiconductor may be measured by micro-area XRD (micro-area X-ray diffraction method) or electron beam diffraction method for the micro-region at the relevant location. Examples of the electron beam diffraction method include SEM-EDX (scanning electron microscope energy dispersive X-ray spectroscopy) and TEM-EDX (transmission electron microscope energy dispersive X-ray spectroscopy), and TEM-EDX is preferred.

[0026] In one embodiment, the ratio of the lattice constant of the second crystalline oxide semiconductor 152 to the lattice constant of the first crystalline oxide semiconductors 151a and 151b (lattice constant of the second crystalline oxide semiconductor / lattice constant of the first crystalline oxide semiconductor) is, for example, 0.940 or more and 0.999 or less, preferably 0.950 or more and 0.990 or less, and more preferably 0.960 or more and 0.985 or less.

[0027] The crystalline oxide semiconductors used as the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 may be any crystalline oxides that can function as semiconductors. The first crystalline oxide semiconductor 151a, the first crystalline oxide semiconductor 151b, and the second crystalline oxide semiconductor 152 may each independently be selected from the crystalline oxide semiconductors exemplified below. The first crystalline oxide semiconductor 151a and the first crystalline oxide semiconductor 151b may be the same or different.

[0028] Examples of the crystalline oxide semiconductor specifically include metal oxides. Examples of the metal contained in the metal oxide include In, Ga, Zn, Al, Sn, etc. Specific examples of the metal oxide include indium oxide (IO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium aluminum oxide (IGAO), indium gallium tin zinc oxide (IGTZO), indium tin zinc oxide (ITZO), etc.

[0029] In one embodiment, the crystalline oxide semiconductor contains indium atoms (In). In one embodiment, the ratio of indium atoms to all metal atoms contained in the crystalline oxide semiconductor is 80 atomic% or more, 90 atomic% or more, or 95 atomic% or more. Incidentally, the content (atomic ratio) of each metal element in the crystalline oxide semiconductor can be analyzed by TEM-EDS (Energy Dispersive X-ray Spectroscopy) measurement using an electron microscope.

[0030] In one embodiment, the crystalline oxide semiconductor contains indium oxide as a main component. "Containing indium oxide as a main component" means that more than 50% by mass of the material constituting the crystalline oxide semiconductor is indium oxide.

[0031] In one embodiment, the crystalline oxide semiconductor contains indium oxide (IO), indium gallium oxide (IGO), or indium gallium aluminum oxide (IGAO). In one embodiment, the content of indium oxide in the crystalline oxide semiconductor may be 55% by mass or more, 60% by mass or more, 70% by mass or more, 80% by mass or more, 90% by mass or more, 95% by mass or more, 97% by mass or more, 98% by mass or more, or 99% by mass, or may be 100% by mass.

[0032] In one embodiment, the crystalline oxide semiconductor further contains a trivalent metal. As the trivalent metal, Ga and Al are preferable, and Ga is more preferable. In one embodiment, the crystalline oxide semiconductor further contains Ga or Al, may contain Ga, may contain Al, or may contain Ga and Al. In one embodiment, the atomic ratio of the trivalent metal to all the metal elements contained in the crystalline oxide semiconductor ([trivalent metal] / ([trivalent metal] + [all metal elements other than trivalent metal]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%. Here, "trivalent metal" may be read as Ga and Al. In one embodiment, the atomic ratio of Ga to all the metal elements contained in the crystalline oxide semiconductor ([Ga] / ([Ga] + [all metal elements other than Ga]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%. In one embodiment, the atomic ratio of Al to all the metal elements contained in the crystalline oxide semiconductor ([Al] / ([Al] + [all metal elements other than Al]) × 100) may be 0 to 30 at%, 1 to 25 at%, 2 to 22 at%, or 3 to 20 at%.

[0033] In one embodiment, the crystalline oxide semiconductor further contains one or more additive elements selected from B, Si, Sc, Zn, Ce, Y, Zr, Sn, Sm, Hf, Ta, and Yb. In one embodiment, the atomic ratio of the total amount of the additive elements to all the metal elements contained in the crystalline oxide semiconductor ([total amount of additive elements] / ([total amount of additive elements] + [all metal elements other than additive elements]) × 100) is 0 to 10 at%, and may be 0.1 to 8 at%, 0.5 to 5 at%, or 1 to 3 at%.

[0034] In one embodiment, the crystalline oxide semiconductor includes a perovskite crystal structure. The presence or absence of the perovskite structure can be determined based on the X-ray diffraction pattern in X-ray diffraction (XRD) or the electron beam diffraction spots in electron beam diffraction. In one embodiment, the crystalline oxide semiconductor includes an In2O3 phase having a body-centered cubic crystal structure.

[0035] In one embodiment, the crystalline oxide semiconductor is a polycrystalline oxide semiconductor or a single-crystalline oxide semiconductor. In one embodiment, the crystalline oxide semiconductor is a polycrystalline oxide semiconductor. In one embodiment, the crystalline oxide semiconductor is a single-crystalline oxide semiconductor.

[0036] Here, whether the crystalline oxide semiconductor is a polycrystalline oxide semiconductor or a single-crystalline oxide semiconductor may be confirmed, for example, by the electron backscatter diffraction method (EBSD). When the crystal orientations measured by EBSD are aligned and no grain boundaries are confirmed, it may be determined that it is a single-crystalline oxide semiconductor. Also, when grain boundaries are confirmed, it may be determined that it is a polycrystalline oxide semiconductor. When the crystal orientation difference between two adjacent measurement points exceeds 5°, a grain boundary may be defined to exist therebetween.

[0037] The method of making the lattice constants of the first crystalline oxide semiconductors 151a and 151b larger than the lattice constant of the second crystalline oxide semiconductor 152 is not particularly limited. For example, as the first crystalline oxide semiconductors 151a and 151b, a method of using a crystalline oxide semiconductor having a lattice constant larger than the lattice constant of the second crystalline oxide semiconductor is exemplified. In this case, the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 can be combined with crystalline oxide semiconductors having different compositions from each other. In one embodiment, by using, as the first crystalline oxide semiconductors 151a and 151b, a crystalline oxide semiconductor doped with an element having a small atomic radius as the second crystalline oxide semiconductor 152, the lattice constant of the second crystalline oxide semiconductor 152 may be relatively reduced. Further, for example, there is a method of varying the formation conditions of the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 such that the lattice constants of the first crystalline oxide semiconductors 151a and 151b are larger than the lattice constant of the second crystalline oxide semiconductor 152. In this case, the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 may have substantially the same composition or may be different from each other. In one embodiment, the first crystalline oxide semiconductors 151a and 151b are formed by a vapor phase crystallization method, and the second crystalline oxide semiconductor 152 is formed by a solid phase crystallization method, so that the lattice constant of the second crystalline oxide semiconductor 152 may be relatively reduced.

[0038] Note that, in this specification, the solid phase crystallization method is a method of forming a crystalline oxide semiconductor by annealing after forming an amorphous oxide semiconductor, and the vapor phase crystallization method means a method of directly forming a crystallized oxide semiconductor without forming an amorphous oxide semiconductor. Compared with the crystalline oxide semiconductor formed by the solid phase crystallization method, in the crystalline oxide semiconductor formed by the vapor phase crystallization method, the strain in the crystal becomes relatively large, and the lattice constant and the carrier concentration become relatively large. The solid phase crystallization method and the vapor phase crystallization method may be selected by appropriately adjusting the formation conditions of the oxide semiconductor described later. Specifically, by selecting the conditions under which the oxide semiconductor crystallizes at a low temperature, a crystalline oxide semiconductor by the vapor phase crystallization method is formed.

[0039] A crystalline oxide semiconductor containing In2O3 will be described as a specific example. For example, taking (i) In2O3 formed by a vapor phase crystallization method, (ii) In2O3 formed by a solid phase crystallization method, and (iii) In2O3 doped (solid solution substitution) with Ga and / or Al as examples, their lattice constants are (i) > (ii) > (iii), and the average carrier concentration is (i) > (ii) > (iii). It can be said that the higher the average carrier concentration, the lower the resistance value. Here, the layer of In2O3 preferably has a bixbyite crystal structure.

[0040] Furthermore, when discussing In2O3 doped (substituted by solid solution) with (iii) Ga and / or Al in more detail, the lattice constant tends to decrease as the content of Ga and Al (atomic ratio to In) increases. Also, when the contents of Ga and Al are comparable, the lattice constant is larger when formed by the vapor-phase crystallization method than when formed by the solid-phase crystallization method.

[0041] For example, as the first crystalline oxide semiconductors 151a and 151b, vapor-phase crystallized In2O3 is used, and as the second crystalline oxide semiconductor 152, solid-phase crystallized In2O 3、 Or In2O3 doped (substituted by solid solution) with Ga and / or Al can be used. Also, for example, as the first crystalline oxide semiconductors 151a and 151b, vapor-phase crystallized In2O3 or solid-phase crystallized In2O3 can be used, and as the second crystalline oxide semiconductor 152, In2O3 doped (substituted by solid solution) with Ga and / or Al can be used. Also, for example, as the first crystalline oxide semiconductors 151a and 151b, a vapor-phase crystallized oxide semiconductor (which may be, for example, In2O3 or In2O3 doped (substituted by solid solution) with Ga and / or Al) can be used, and as the second crystalline oxide semiconductor 152, a solid-phase crystallized oxide semiconductor (which may be, for example, In2O3 or In2O3 doped (substituted by solid solution) with Ga and / or Al) can be used. In this case, the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 may have substantially the same composition of metal elements.

[0042] For example, the composition of the metal elements constituting the first crystalline oxide semiconductors 151a and 151b and the composition of the metal elements constituting the second crystalline oxide semiconductor 152 may be substantially the same. The composition ratios of the metal elements constituting these crystalline oxide semiconductors may also be substantially the same. Further, the composition of the metal elements constituting the first crystalline oxide semiconductor 151a and the composition of the metal elements constituting the second crystalline oxide semiconductor 152 may be substantially the same. The composition ratios of the metal elements constituting these crystalline oxide semiconductors may also be substantially the same. Also, the composition of the metal elements constituting the first crystalline oxide semiconductor 151b and the composition of the metal elements constituting the second crystalline oxide semiconductor 152 may be substantially the same. The composition ratios of the metal elements constituting these crystalline oxide semiconductors may also be substantially the same. Further, the composition of the metal elements constituting the first crystalline oxide semiconductor 151a and the composition of the metal elements constituting the first crystalline oxide semiconductor 151b may be substantially the same. The composition ratios of the metal elements constituting these crystalline oxide semiconductors may also be substantially the same. In this specification, "the composition of the metal elements is the same" means that the types of the metal elements constituting the crystalline oxide semiconductor are the same. At this time, the content ratios of the respective metal elements constituting the crystalline oxide semiconductor may be the same. Also, "the composition of the metal elements is'substantially' the same" means that the composition of the metal elements is the same except for inevitable impurities. Examples of the inevitable impurities include eluted components from electrodes and the like. Also, "the composition ratio of the metal elements is the same" means that the types of the metal elements constituting the crystalline oxide semiconductor are the same and the content ratios are also the same. Also, "the composition of the metal elements is'substantially' the same" means that the composition ratio of the metal elements is the same except for inevitable impurities. Even with a combination of crystalline oxide semiconductors having substantially the same composition of metal elements, the lattice constant can be adjusted by varying the film formation process as described above. By applying crystalline oxide semiconductors having substantially the same composition of metal elements to the respective members described above, the manufacturing efficiency can be improved.

[0043] Each of the first electrode 11, the second electrode 12, and the third electrode 13 is not particularly limited as long as it is a conductor. Examples of the conductor include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N).

[0044] Each of the first insulating film 14a, the third insulating film 14b, and the second insulating film 16 is not particularly limited as long as it is a film containing an insulator or made of an insulator. Examples of the insulator include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Further, each of the first insulating film 14a, the third insulating film 14b, and the second insulating film 16 may be a laminated film of the above materials. Note that the insulating film may contain La, N, Zr, or the like. The insulators included in the first insulating film 14a, the third insulating film 14b, and the second insulating film 16 may be the same as or different from each other.

[0045] In this embodiment, the first crystalline oxide semiconductors 151a and 151b are farther from the third electrode 13 than the second crystalline oxide semiconductor 152. Therefore, even when a gate voltage is applied to the third electrode 13, carriers are not easily induced in the vicinity of the first crystalline oxide semiconductors 151a and 151b, and contact resistance is likely to occur. However, as described above, since the lattice constants of the first crystalline oxide semiconductors 151a and 151b are larger than the lattice constant of the second crystalline oxide semiconductor 152, the average carrier concentration of the first crystalline oxide semiconductors 151a and 151b selectively increases, preventing the vicinity of the first crystalline oxide semiconductors 151a and 151b from having contact resistance. This also contributes to the improvement of the contact resistance of the transistor 10.

[0046] By selectively increasing the average carrier concentration due to the relatively large lattice constants of the first crystalline oxide semiconductors 151a and 151b, the average carrier concentration of the first crystalline oxide semiconductors 151a and 151b can be made higher than the average carrier concentration of the second crystalline oxide semiconductor 152. Note that the average carrier concentration is the average value of the carrier concentrations in each oxide semiconductor. When the oxide semiconductor is an n-type semiconductor, the carrier concentration is the electron density. When the oxide semiconductor is a p-type semiconductor, the carrier concentration is the hole density. In addition, the fact that the average carrier concentration of the first crystalline oxide semiconductors 151a and 151b is higher than the average carrier concentration of the second crystalline oxide semiconductor 152 can be determined by the tunnel current flowing when scanning the surface of each region using STEM (scanning tunneling electron microscope). When using STEM, a two-dimensional carrier concentration distribution can be observed with a spatial resolution of 1 nm. Therefore, not only the relative magnitudes of the average carrier concentrations in the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 but also the absolute values of the average carrier concentrations in each region can be obtained.

[0047] In one embodiment, the average carrier concentration in the second crystalline oxide semiconductor 152 is 10 14 ~10 18 cm -3 is. In one embodiment, the average carrier concentration in the first crystalline oxide semiconductor 151a and / or the first crystalline oxide semiconductor 151b is 10 17 cm -3 or more, preferably 10 17 to 10 22 cm -3 . In one embodiment, the ratio of the average carrier concentration of the first crystalline oxide semiconductor 151a to the average carrier concentration of the second crystalline oxide semiconductor 152 (average carrier concentration of the first crystalline oxide semiconductor 151a / average carrier concentration of the second crystalline oxide semiconductor 152), and / or the ratio of the average carrier concentration of the first crystalline oxide semiconductor 151b to the average carrier concentration of the second crystalline oxide semiconductor 152 (average carrier concentration of the first crystalline oxide semiconductor 151b / average carrier concentration of the second crystalline oxide semiconductor 152) is 2 to 10 4 , preferably 5 to 5×10 3 , more preferably 10 to 3×10 3 . In one embodiment, the average carrier concentration in the second crystalline oxide semiconductor 152 is 10 14 to 10 18 cm -3 , the average carrier concentration in the first crystalline oxide semiconductor 151a and / or the first crystalline oxide semiconductor 151b is 10 17 cm -3 or more, preferably 10 17 to 10 22 cm -3 , and the ratio of the average carrier concentration of the first crystalline oxide semiconductor 151a to the average carrier concentration of the second crystalline oxide semiconductor 152 (average carrier concentration of the first crystalline oxide semiconductor 151a / average carrier concentration of the second crystalline oxide semiconductor 152), and / or the ratio of the average carrier concentration of the first crystalline oxide semiconductor 151b to the average carrier concentration of the second crystalline oxide semiconductor 152 (average carrier concentration of the first crystalline oxide semiconductor 151b / average carrier concentration of the second crystalline oxide semiconductor 152) is 2 to 10 4 , preferably 5 to 5×10 3 , more preferably 10 to 3×10 3 .

[0048] Hereinafter, an example of a method for manufacturing the transistor 10 according to the present embodiment will be described, but the manufacturing method is not limited to this example.

[0049] FIG. 3 is a diagram for explaining an example of a method for manufacturing the transistor 10 according to the present embodiment. FIG. 3(a) shows a state in which the first crystalline oxide semiconductor 151a, the second electrode 12, and the insulating film 19 that supports the second electrode 12 in FIGS. 1 and 2 are formed. Although not shown in FIG. 3(a), the second electrode 12 and the insulating film 19 may be further formed on another substrate. Further, the second electrode 12 may be connected to an element outside the transistor according to the present embodiment. The insulating film 19 and the second electrode 12 can be formed by known methods. The first crystalline oxide semiconductor 151a can be formed, for example, by setting the composition or applying a vapor phase crystallization process so that its lattice constant becomes relatively large. Specific forming methods will be described later.

[0050] Next, as shown in FIG. 3(b), the third insulating film 14b, the third electrode 13, and the first insulating film 14a are formed in this order. At this time, as will be described later, the third electrode 13 may be formed so as to be connected to a word line. Alternatively, the third electrode 13 itself may be used as a word line.

[0051] The third insulating film 14b is formed, for example, by forming a film containing an insulator as described above by various methods such as chemical vapor deposition (CVD) method, plasma CVD (PECVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, sol-gel method, coating method, etc.

[0052] The third electrode 13 is formed, for example, by forming a conductor as described above such as tungsten. The third electrode 13 may be patterned into an arbitrary shape. The third electrode 13 may form a pattern during film formation, or may form a pattern by etching after film formation.

[0053] The first insulating film 14a is formed by depositing a film containing the above-mentioned insulator by various methods such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, coating method, etc.

[0054] 3(c), through-holes H are formed by etching so as to penetrate the first insulating film 14a, the third electrode 1, and the third insulating film 14b. Various methods such as dry etching and wet etching may be used for the etching to form the through-holes H. Furthermore, before etching, a resist may be formed on the first insulating film 14a to define the region where the through-holes H are to be formed.

[0055] Next, as shown in FIG. 3(d), a second insulating film 16 including the above-described insulator is formed by various methods such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, coating method, etc.

[0056] Next, as shown in FIG. 3(e), a second crystalline oxide semiconductor 152 is formed in the through-hole H in which the second insulating film 16 has been formed. The second crystalline oxide semiconductor 152 can be formed by, for example, setting the composition or applying a solid-phase crystallization process so that its lattice constant is relatively small. As the solid-phase crystallization process, sputtering film formation or atomic layer deposition (ALD) is preferable. Specific formation methods will be described later. When solid-phase crystallization is performed by sputtering, the substrate temperature is set relatively low, and water is introduced into the gas as needed to initially obtain an amorphous film. Then, heat treatment is performed to crystallize the film, resulting in a crystal with few defects. In the case of ALD film formation, complete crystallization during film formation can also be prevented by setting the substrate temperature relatively low.

[0057] Next, as shown in FIG. 3(f), a first crystalline oxide semiconductor 151a is formed on the upper layer of the second crystalline oxide semiconductor 152, and a first electrode 11 is further formed on the upper layer of the first crystalline oxide semiconductor 151a. Regarding the method for forming the first crystalline oxide semiconductor 151a, the description given for the method for forming the first crystalline oxide semiconductor 151b is incorporated. The first crystalline oxide semiconductor 151a may be patterned into an arbitrary shape. The first crystalline oxide semiconductor 151a may form a pattern during film formation, or may form a pattern by etching after film formation. The first electrode 11 can be formed by a known method. The first electrode 11 may be patterned into an arbitrary shape. The first electrode 11 may form a pattern during film formation, or may form a pattern by etching after film formation.

[0058] In the above manner, a transistor 10 as shown in FIGS. 1 and 2 is obtained.

[0059] Examples of the method for forming the first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 include chemical vapor deposition (CVD) method, plasma CVD (PECVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, sol-gel method, coating method, etc. Note that CVD methods include metal-organic CVD (MO-CVD), inductively coupled plasma CVD (ICP-CVD), mist CVD, etc. PVD methods include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, ion plating, etc.

[0060] The first crystalline oxide semiconductors 151a and 151b and the second crystalline oxide semiconductor 152 may be crystalline oxide semiconductors formed by a vapor-phase crystallization method or may be crystalline oxide semiconductors formed by a solid-phase crystallization method. That is, the oxide semiconductor formed by the above method may be amorphous or crystalline. When an amorphous oxide semiconductor is formed, the oxide semiconductor is crystallized in any subsequent step.

[0061] When a crystalline oxide semiconductor is formed by a solid-phase crystallization method, after forming an amorphous oxide semiconductor, a post-annealing described below is performed to form a crystalline oxide semiconductor. A crystalline oxide semiconductor may be formed by performing post-annealing after forming the amorphous oxide semiconductor, or post-annealing may be further performed after the oxide semiconductor is crystallized to form a crystalline oxide semiconductor. Alternatively, a crystalline oxide semiconductor may be formed without post-annealing, or post-annealing may be performed after forming the crystalline oxide semiconductor to adjust the crystallinity of the crystalline oxide semiconductor.

[0062] The crystalline oxide semiconductor may be subjected to post-annealing. The post-annealing can be performed, for example, after forming the oxide semiconductor film, after forming the subsequent first electrode 11 or before forming the first electrode 11. The state of the oxide semiconductor before post-annealing may be amorphous or crystalline. The annealing atmosphere may contain nitrogen or oxygen and may be under vacuum or in air. The annealing temperature is preferably 250°C or higher and 600°C or lower, more preferably 300°C or higher and 500°C or lower, and still more preferably 350°C or higher and 450°C or lower. The annealing time is 5 minutes or more and 2 hours or less, preferably 30 minutes or more and 1 hour or less.

[0063] In the above manufacturing method, the second crystalline oxide semiconductor 152 is formed in the through-hole H on which the second insulating film 16 is formed. Therefore, as a method for forming the second crystalline oxide semiconductor 152, an atomic layer deposition method (ALD) is preferable. The atomic layer deposition (ALD) method defines one cycle as a process of alternately exposing a raw material (which may be referred to as a precursor or a precurser) containing a metal element that constitutes a film formation target (here, the second crystalline oxide semiconductor 152) and an oxidizing agent to the substrate surface. One atomic layer is formed in one cycle, and a thin film is formed by repeating this cycle until a desired film thickness is achieved. Therefore, by using ALD, a dense second crystalline oxide semiconductor 152 can be formed even in a region near the first crystalline oxide semiconductor 151b away from the opening in the through-hole H on which the second insulating film 16 is formed. Thereby, the contact resistance between the second crystalline oxide semiconductor 152 and the first crystalline oxide semiconductor 151b can be further reduced. Also, the first crystalline oxide semiconductors 151a and 151b may be formed using the atomic layer deposition method (ALD).

[0064] One atomic layer deposition cycle of ALD may include the following four steps. (1) Vaporize the precursor (precurser) in a container containing the precursor as the raw material, introduce it into the chamber, apply a predetermined system pressure, react it with the OH groups on the substrate surface or the film surface for a predetermined time, and adsorb the single molecules. When the vapor pressure of the precursor is low, the container containing the precursor may be heated to promote vaporization. When the vapor pressure of the precursor is high, the container containing the precursor may be cooled to suppress vaporization for adjustment. (2) Remove unreacted raw materials and by-produced gases from the chamber by purging with an inert gas to deposit one atomic layer. (3) Introduce a reactive gas into the chamber and oxidize the metal of the precursor using heat, plasma, or the like. (4) Remove unreacted oxidizing agents and by-produced gases by purging with an inert gas. After step (4), return to step (1), and repeat steps (1) to (4) until a desired film thickness is achieved.

[0065] When performing ALD, various ALD apparatuses can be used. Specifically, for example, apparatuses capable of supplying a precursor by bubbling, apparatuses having a vaporization chamber, etc. can be mentioned. Further, apparatuses capable of performing plasma treatment or the like on a reactive gas (oxidizing agent) can be mentioned. Note that not only single-wafer apparatuses equipped with a film formation chamber but also apparatuses capable of simultaneously processing multiple wafers using a batch furnace may be used.

[0066] Examples of the types of ALD precursors include organometals (e.g., AlMe3), metal hydrides (e.g., AsH3), metal alkoxides (e.g., Ti(OCHMe2)4), metal amides (e.g., Ti(NMe2)4), β-diketonates (e.g., Co(acac)2), metallocenes (e.g., MgCp2), metal amidines, etc. As the metal compounds used as ALD precursors, various types are commercially available, and precursors and oxidizing agents capable of forming the target film formation object may be selected.

[0067] Examples of the precursor include one or more selected from the group consisting of compounds used as organic ligands such as alkyl compounds, alcohol compounds, glycol compounds, β-diketone compounds, cyclopentadiene compounds, organic amine compounds, etc., and compounds of silicon or metal.

[0068] Examples of the metal species of the precursor include lithium, sodium, potassium, magnesium, calcium, strontium, barium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, iron, ruthenium, cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, zinc, boron, aluminum, silicon, indium, gallium, germanium, tin, lead, antimony, bismuth, scandium, ruthenium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

[0069] When the oxide semiconductor 15 contains indium atoms (In), a precursor containing In may be used. Further, when the oxide semiconductor 15 contains other metals, a precursor containing the metal may be used. When forming an oxide semiconductor using two or more metals, there are a method of vaporizing and supplying each component independently (sometimes referred to as the "single-source method") and a method of vaporizing and supplying a mixed raw material in which a multi-component raw material is previously mixed in a desired composition (sometimes referred to as the "cocktail-source method"). In the case of the single-source method, each precursor to be used is preferably a precursor having similar thermal and / or oxidative decomposition behavior. In the case of the cocktail-source method, as each precursor, in addition to having similar thermal and / or oxidative decomposition behavior, a compound that does not cause alteration due to chemical reaction or the like during mixing is preferred.

[0070] Examples of the compounds used as the organic ligand of the precursor are as follows. Also, depending on the valence of the central metal, a plurality of the following ligands can coordinate. In the precursor, when a plurality of ligands coordinate to the central metal, these plurality of ligands may be the same as each other, or two or more types of ligands may be combined.

[0071] Examples of the alkyl compounds used as the organic ligand of the precursor include methyl, ethyl, propyl, isopropyl, butyl, sec-butyl, isobutyl, tert-butyl, pentyl, isopentyl, tert-pentyl, and the like.

[0072] Examples of the alcohol compounds used as the organic ligand of the precursor include alkyl alcohols such as methanol, ethanol, propanol, isopropyl alcohol, butanol, sec-butyl alcohol, isobutyl alcohol, tert-butyl alcohol, pentyl alcohol, isopentyl alcohol, tert-pentyl alcohol; ether alcohols such as 2-methoxyethanol, 2-ethoxyethanol, 2-butoxyethanol, 2-(2-methoxyethoxy)ethanol, 2-methoxy-1-methylethanol, 2-methoxy-1,1-dimethylethanol, 2-ethoxy-1,1-dimethylethanol, 2-isopropoxy-1,1-dimethylethanol, 2-butoxy-1,1-dimethylethanol, 2-(2-methoxyethoxy)-1,1-dimethylethanol, 2-propoxy-1,1-diethylethanol, 2-s-butoxy-1,1-diethylethanol, 3-methoxy-1,1-dimethylpropanol; dialkylamino alcohols such as dimethylaminoethanol, ethylmethylaminoethanol, diethylaminoethanol, dimethylamino-2-pentanol, ethylmethylamino-2-pentanol, dimethylamino-2-methyl-2-pentanol, ethylmethylamino-2-methyl-2-pentanol, diethylamino-2-methyl-2-pentanol, and the like.

[0073] Examples of glycol compounds used as organic ligands of the precursor include 1,2 - ethanediol, 1,2 - propanediol, 1,3 - propanediol, 2,4 - hexanediol, 2,2 - dimethyl - 1,3 - propanediol, 2,2 - diethyl - 1,3 - propanediol, 1,3 - butanediol, 2,4 - butanediol, 2,2 - diethyl - 1,3 - butanediol, 2 - ethyl - 2 - butyl - 1,3 - propanediol, 2,4 - pentanediol, 2 - methyl - 1,3 - propanediol, 2 - methyl - 2,4 - pentanediol, 2,4 - hexanediol, 2,4 - dimethyl - 2,4 - pentanediol, etc.

[0074] Examples of β - diketone compounds used as organic ligands of the precursor include alkyl - substituted β - diketones such as acetylacetone, hexane - 2,4 - dione, 5 - methylhexane - 2,4 - dione, heptane - 2,4 - dione, 2 - methylheptane - 3,5 - dione, 5 - methylheptane - 2,4 - dione, 6 - methylheptane - 2,4 - dione, 2,2 - dimethylheptane - 3,5 - dione, 2,6 - dimethylheptane - 3,5 - dione, 2,2,6 - trimethylheptane - 3,5 - dione, 2,2,6,6 - tetramethylheptane - 3,5 - dione, octane - 2,4 - dione, 2,2,6 - trimethyloctane - 3,5 - dione, 2,6 - dimethyloctane - 3,5 - dione, 2,9 - dimethylnonane - 4,6 - dione, 2 - methyl - 6 - ethyldecane - 3,5 - dione, 2,2 - dimethyl - 6 - ethyldecane - 3,5 - dione; fluorine - substituted alkyl β - diketones such as 1,1,1 - trifluoropentane - 2,4 - dione, 1,1,1 - trifluoro - 5,5 - dimethylhexane - 2,4 - dione, 1,1,1,5,5,5 - hexafluoropentane - 2,4 - dione, 1,3 - dipentafluorhexylpropane - 1,3 - dione; ether - substituted β - diketones such as 1,1,5,5 - tetramethyl - 1 - methoxyhexane - 2,4 - dione, 2,2,6,6 - tetramethyl - 1 - methoxyheptane - 3,5 - dione, 2,2,6,6 - tetramethyl - 1-(2 - methoxyethoxy)heptane - 3,5 - dione, etc.

[0075] Examples of the cyclopentadiene compound used as the organic ligand of the precursor include cyclopentadiene, methylcyclopentadiene, ethylcyclopentadiene, propylcyclopentadiene, isopropylcyclopentadiene, butylcyclopentadiene, sec-butylcyclopentadiene, isobutylcyclopentadiene, tert-butylcyclopentadiene, dimethylcyclopentadiene, tetramethylcyclopentadiene, and the like.

[0076] Examples of the organic amine compound used as the organic ligand of the precursor include methylamine, ethylamine, propylamine, isopropylamine, butylamine, sec-butylamine, tert-butylamine, isobutylamine, dimethylamine, diethylamine, dipropylamine, diisopropylamine, ethylmethylamine, propylmethylamine, isopropylmethylamine, and the like.

[0077] In addition, metal halogen compounds (such as InCl3, InBr3, InF3, etc.) may be used as the precursor. When a plurality of halogens are coordinated to the metal, these plurality of halogens may be the same as each other, or two or more kinds of halogens may be combined. Further, a part of the halogen may be replaced by hydrogen.

[0078] Examples of the indium-containing precursor include, for example, InCl3, TMIn (trimethyl indium), TEIn (triethyl indium), InCp (cyclopentadienyl indium(I)), InEtCp (ethylcyclopentadienyl indium(I)), In(acac)3 (indium acetylacetonate), In(tmhd)3 (indium 2,2,6,6-tetramethyl-3,5-heptanedionate), In[[( iExamples include [PrN)2CNR2]3 (R = Me) (indium-tris-guanidinates), Et2InN(TMS)2 (diethyl[bis-(trimethylsilyl)amido]indium), INCA (diethyl[1,1,1-trimethyl-N-(trimethylsilyl)silanaminato]indium), DADI ([3-(dimethylamino)propyl]dimethyl indium), In(dmamp)3 ((1-dimethylamino-2-methyl-2-propoxy)indium), Me2In(EDPA) (dimethyl(N-ethoxy-2,2-dimethylpropanamido)indium), tris(N,N’-diisopropylacetamidinato)indium(III), etc.

[0079] These ALD precursors may be used alone or in combination of two or more.

[0080] The above-mentioned precursors can be produced according to known production methods. For example, when an alcohol compound is used as an organic ligand, the precursor can be produced by reacting the metal inorganic salt or its hydrate described above with the alkali metal alkoxide of the alcohol compound. Here, examples of the metal inorganic salt or its hydrate include metal halides, nitrates, etc. Examples of the alkali metal alkoxide include sodium alkoxide, lithium alkoxide, potassium alkoxide, etc.

[0081] Examples of the oxidizing agent used in ALD include H2O, O2, O3, O2 plasma, H2O plasma, hydrogen peroxide (H2O2), etc. These oxidizing agents may be used alone or in combination of two or more.

[0082] When using two or more oxidizing agents, the two or more oxidizing agents may be used simultaneously, or they may be used individually while changing the two or more oxidizing agents. For example, by using two types of O2 plasma and H2O plasma as oxidizing agents, both the advantages of high mobility obtained when using O2 plasma and the effects of reducing carbon concentration and improving the stability of mobility against heat treatment obtained when using H2O plasma can be utilized. By using two or more oxidizing agents, high mobility and low carbon concentration can be adjusted. Depending on the intended effect, the usage ratio, usage order, number of cycles, etc. of O2 plasma and H2O plasma may be appropriately selected.

[0083] The pressure of the system (inside the film formation chamber) in step (1) may be appropriately set according to the type of precursor, substrate temperature, etc. For example, 1 to 10,000 Pa is preferable, 10 to 1,000 Pa is more preferable, 50 to 500 Pa is even more preferable, and 80 to 120 Pa is particularly preferable.

[0084] In one embodiment, in the film formation step, H2O plasma is used as the oxidizing agent. In one embodiment, in the film formation step, O2 plasma is used as the oxidizing agent. In one embodiment, in the film formation step, O3 is used as the oxidizing agent. By using these oxidizing agents, the effect of being able to control the electrical characteristics of the oxide semiconductor film in a good state can be obtained.

[0085] To vaporize the precursor, the container containing the precursor may be heated at a temperature at which the precursor is sufficiently vaporized as necessary. When using a precursor with a high vapor pressure, the container containing the precursor may be cooled as necessary. In one embodiment, the container containing the indium-containing precursor (for example, triethylindium) is heated in the range of 25 to 150 °C. The above temperature is preferably in the range of 50 to 150 °C, more preferably in the range of 75 to 125 °C.

[0086] In the above manufacturing method, the substrate temperature during film formation is usually in the range of 50 to 600 °C, preferably 85 to 500 °C, more preferably 80 to 350 °C, and even more preferably 100 to 250 °C.

[0087] In addition, the growth rate of the oxide semiconductor film per ALD process cycle varies depending on the precursor used during film formation, the types of reactive gases, and the substrate temperature during film formation.

[0088] The growth rate per ALD process cycle is called Growth per cycle (GPC), and can be calculated, for example, by measuring the film thickness of the oxide semiconductor when repeating 30 ALD cycles. Here, GPC varies depending on the combination of the precursor, the oxidizing agent, and the substrate temperature, and also varies depending on the type of substrate. Therefore, since the above cycle number varies depending on many factors such as the types of precursors and oxidizing agents used and their combinations, the type of substrate, the substrate temperature during film formation, the desired film thickness, etc., it can be appropriately set in consideration of these factors.

[0089] When using O3 as the oxidizing agent, the substrate temperature during film formation is preferably above 100 °C, more preferably 110 to 250 °C, 120 to 230 °C, 130 to 220 °C. When using H2O plasma and O2 plasma as the oxidizing agent, the substrate temperature during film formation is preferably 100 to 150 °C.

[0090] Examples of the inert gas for purging unreacted raw materials and unreacted oxidizing agents include argon, nitrogen, etc., and in the method of this embodiment, argon or nitrogen is preferred.

[0091] In the above step (3), it is preferable to generate plasma of the reactive gas (oxidizing agent).

[0092] In this embodiment, it is preferable to adjust the formation conditions of the crystalline oxide semiconductor so that the lattice constants of the first crystalline oxide semiconductors 151a and 151b are larger than the lattice constant of the second crystalline oxide semiconductor 152. Examples of the formation conditions include conditions during film formation of the oxide semiconductor, the composition of the oxide semiconductor, the presence or absence of post-annealing after forming the oxide semiconductor, and the conditions thereof.

[0093] (Second Embodiment) Next, with reference to FIGS. 4 and 5, another example (second embodiment) of the transistor according to this aspect will be described. FIG. 4 is a schematic perspective view showing a cross section of a transistor according to the second embodiment. FIG. 5 is a schematic cross-sectional view of the transistor. In FIGS. 4 and 5, the same reference numerals as those in FIGS. 1 and 2 denote the same configurations, and the descriptions given for FIGS. 1 and 2 are incorporated herein by reference unless otherwise specified.

[0094] In the second embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, first crystalline oxide semiconductors 151a and 151b, a second crystalline oxide semiconductor 152, a first insulating film 14, and a second insulating film 16. At least a part of the third electrode 13 is located between the first electrode 11 and the second electrode 12. At least a part of the third electrode 13 may be located on the side opposite to the second electrode 12 of the first electrode 11, or on the side opposite to the first electrode 11 of the second electrode 12. The first insulating film 14 is located between the first electrode 11 and the second electrode 12. Here, the first electrode 11 and the second electrode 12 are stacked via the first insulating film 14. Thereby, the first electrode 11 and the second electrode 12 are electrically insulated by the first insulating film 14. The third electrode 13 is provided so as to be adjacent to the second crystalline oxide semiconductor 152 without contact. Specifically, the third electrode 13 is adjacent to the second crystalline oxide semiconductor 152 via a second insulating film 16 located between the third electrode 13 and the second crystalline oxide semiconductor 152. The second insulating film 16 may be provided between the third electrode 13 and the second crystalline oxide semiconductor 152 to insulate the third electrode 13 and the second crystalline oxide semiconductor 152.

[0095] The second crystalline oxide semiconductor 152 penetrates at least the first insulating film 14. Here, the second crystalline oxide semiconductor 152 is provided in a columnar shape penetrating the first electrode 11 and the first insulating film 14 in this order. A recess is formed in the columnar second crystalline oxide semiconductor 152 from one end side (the upper side in FIGS. 4 and 5) toward the other end side (the lower side in FIGS. 4 and 5), and a second insulating film 16 is formed on the inner peripheral surface and the bottom surface of the recess. The third electrode 13 is provided so as to fill the recess in which the second insulating film 16 is formed.

[0096] The first crystalline oxide semiconductors 151a and 151b are provided in contact with the first electrode 11 and the second electrode 12, respectively. Specifically, the first crystalline oxide semiconductor 151a is laminated on the surface of the first electrode 11 on the side of the second crystalline oxide semiconductor 152. Also, the first crystalline oxide semiconductor 151b is laminated on the surface of the second electrode 12 on the side of the second crystalline oxide semiconductor 152. The second crystalline oxide semiconductor 152 connects the first electrode 11 and the second electrode 12 via the first crystalline oxide semiconductors 151a and 151b. The second crystalline oxide semiconductor 152 is preferably provided in contact with the first crystalline oxide semiconductors 151a and 151b.

[0097] The dimensions of the transistor 10 may be appropriately designed according to its application and the like. The channel length of the second crystalline oxide semiconductor 152 is, for example, 1 nm or more and 10 μm or less, preferably 2 nm or more and 1000 nm or less. Note that the channel length of the second crystalline oxide semiconductor 152 is the length of the second crystalline oxide semiconductor 152 along the thickness direction (the vertical direction in FIGS. 4 and 5) of the laminate in which the first electrode 11, the first insulating film 14, and the second electrode 12 are laminated in this order, and may coincide with the depth of the recess of the second crystalline oxide semiconductor 152.

[0098] The thickness of the second crystalline oxide semiconductor 152 is, for example, 1 nm or more and 500 nm or less, preferably 1 nm or more and 100 nm or less. The thickness of the second crystalline oxide semiconductor 152 may be the average thickness along the channel length direction. The average thickness along the channel length direction is the average value when the thickness is measured at 10 or more locations along the channel length direction.

[0099] The thickness of the second insulating film 16 is, for example, 1 Å or more and 500 nm or less, preferably 1 nm or more and 100 nm or less. In order to suppress the capacitance of the second insulating film 16 from becoming a parasitic component, the thickness of the second insulating film 16 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0100] The thicknesses of the first crystalline oxide semiconductors 151a and 151b are, for example, 1 Å or more and 500 nm or less, preferably 1 nm or more and 200 nm or less, more preferably 2 nm or more and 100 nm or less. When the thicknesses of the first crystalline oxide semiconductors 151a and 151b are within the above ranges, the contact resistance between the electrodes (the first electrode and / or the second electrode) and the second crystalline oxide semiconductor can be further reduced.

[0101] The channel length and channel width of the second crystalline oxide semiconductor 152, the thickness of the second insulating film 16, and the thicknesses of the first crystalline oxide semiconductors 151a and 151b may be measured by the same method as in the first embodiment.

[0102] Also in the second embodiment, the lattice constants of the first crystalline oxide semiconductors 151a and 151b are larger than the lattice constant of the second crystalline oxide semiconductor 152. Therefore, as described in the first embodiment, since the resistance values of the first crystalline oxide semiconductors 151a and 151b in the region (the region that is inherently likely to have contact resistance) in contact with the electrodes (the first electrode 11 and / or the second electrode 12) are low, the contact resistance of the transistor 10 can be improved.

[0103] Regarding the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, the first crystalline oxide semiconductors 151a and 151b, the second crystalline oxide semiconductor 152, and the second insulating film 16, the description in the first embodiment may be incorporated by reference.

[0104] The manufacturing method of the transistor 10 according to the second embodiment is not particularly limited. In particular, except for the formation of the first crystalline oxide semiconductors 151a and 151b, it can be manufactured by a known method while referring to the manufacturing method according to the first embodiment. For example, the transistor 10 according to the second embodiment may be manufactured as follows. After forming a laminate of the second electrode 12, the first insulating film 14, and the first electrode 11, a through hole is formed so as to penetrate the first electrode 11 and the first insulating film 14. After forming the first crystalline oxide semiconductors 151a and 151b on the first electrode 11 and the second electrode 12, respectively, the second crystalline oxide semiconductor 152 is formed. Thereafter, the second insulating film 16 and the third electrode 13 are formed. Incidentally, the first crystalline oxide semiconductors 151a and 151b can be formed, for example, by the ALD method, the CVD method, the PVD method, the LPCVD method, the PECVD method, etc. after forming the first electrode 11 and the second electrode. In particular, according to the ALD method, a film can be preferably formed even inside the through hole, and the film formation rate is higher on the electrodes (the first electrode 11 and the second electrode 12) than on the insulating film (the first insulating film 14). Therefore, the first crystalline oxide semiconductor 151a can be selectively formed on the first electrode 11, and the first crystalline oxide semiconductor 151b can be selectively formed on the second electrode. The reason why the film formation rate is higher on the electrodes than on the insulating film is that the reactivity between the precursor and the electrode is higher than the reactivity between the precursor and the insulating film. Regarding the formation methods of the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, the first crystalline oxide semiconductors 151a and 151b, the second crystalline oxide semiconductor 152, and the second insulating film 16, the description in the first embodiment may be incorporated by reference.

[0105] Next, with reference to FIGS. 6 and 7, a further other example (third embodiment) of the transistor according to this aspect will be described. FIG. 6 is a schematic perspective view showing a cross section of the transistor according to the third embodiment. FIG. 7 is a schematic cross-sectional view of the transistor. In FIGS. 6 and 7, the same reference numerals as those in FIGS. 1 and 2 denote the same configurations, and the descriptions made for FIGS. 1 and 2 are incorporated by reference unless otherwise specified.

[0106] In the third embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, first crystalline oxide semiconductors 151a and 151b, second crystalline oxide semiconductors 152 and 152', and a first insulating film 14. The third electrode 13 is positioned between the first electrode 11 and the second electrode 12. The first insulating film 14 is positioned between the first electrode 11 and the third electrode 13. Here, the first electrode 11 and the second electrode 12 are laminated with each other via the first insulating film 14. As a result, the first electrode 11 and the second electrode 12 are electrically insulated from each other by the first insulating film 14. The third electrode 13 is provided so as to be adjacent to the second crystalline oxide semiconductors 152 and 152' without contacting them. Specifically, the third electrode 13 is adjacent to the second crystalline oxide semiconductors 152 and 152' via the first insulating film 14 positioned between the third electrode 13 and the second crystalline oxide semiconductors 152 and 152'. In this sense, it can also be said that the first insulating film 14 in the third embodiment also serves as the second insulating film 16 in the first and second embodiments.

[0107] The first crystalline oxide semiconductors 151a and 151b are respectively provided in contact with the first electrode 11 and the second electrode 12. Specifically, the first crystalline oxide semiconductor 151a is laminated on the surface of the first electrode 11 on the side of the second crystalline oxide semiconductors 152 and 152'. Also, the first crystalline oxide semiconductor 151b is laminated on the surface of the second electrode 12 on the side of the second crystalline oxide semiconductors 152 and 152'. The second crystalline oxide semiconductors 152 and 152' connect the first electrode 11 and the second electrode 12 via the first crystalline oxide semiconductors 151a and 151b, respectively. The second crystalline oxide semiconductors 152 and 152' are preferably provided in contact with the first crystalline oxide semiconductors 151a and 151b. In the examples of FIGS. 6 and 7, the case where the first crystalline oxide semiconductors 151a and 151b are provided on the entire surface of the first electrode 11 and the second electrode 12 on the side of the second crystalline oxide semiconductors 152 and 152' (including the portion connected to the first insulating film 14) is shown. However, in other examples, the first crystalline oxide semiconductors 151a and 151b may be provided only on the portion of the surface of the first electrode 11 and the second electrode 12 on the side of the second crystalline oxide semiconductors 152 and 152' that is connected to the second crystalline oxide semiconductors 152 and 152'.

[0108] The dimensions of the transistor 10 may be appropriately designed according to its use and the like. The channel length of the second crystalline oxide semiconductors 152 and 152' is, for example, 1 nm or more and 10 μm or less, preferably 2 nm or more and 1000 nm or less. Note that the channel length of the second crystalline oxide semiconductor 152 is the length of the second crystalline oxide semiconductors 152 and 152' along the thickness direction (the vertical direction in FIGS. 6 and 7) of the laminate in which the first electrode 11, the first insulating film 14, and the second electrode 12 are laminated in this order, and may coincide with the distance between the first electrode 11 and the second electrode 12 (or the distance between the first crystalline oxide semiconductors 151a and 151b).

[0109] The thickness of the second crystalline oxide semiconductors 152 and 152' is, for example, 1 nm or more and 500 nm or less, preferably 1 nm or more and 100 nm or less. The thickness of the second crystalline oxide semiconductor 152 may be the average thickness along the channel length direction. The average thickness along the channel length direction is the average value when the thickness is measured at 10 or more locations along the channel length direction.

[0110] The thickness of the first insulating film 14 is, for example, 1 Å or more and 500 nm or less, preferably 1 nm or more and 100 nm or less. In order to suppress the capacitance of the first insulating film 14 from becoming a parasitic component, the thickness of the first insulating film 14 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0111] The thicknesses of the first crystalline oxide semiconductors 151a and 151b are, for example, 1 Å or more and 500 nm or less, preferably 1 nm or more and 200 nm or less, more preferably 2 nm or more and 100 nm or less. When the thicknesses of the first crystalline oxide semiconductors 151a and 151b are within the above ranges, the contact resistance between the electrodes (the first electrode and / or the second electrode) and the second crystalline oxide semiconductor can be further reduced.

[0112] The channel lengths and thicknesses of the second crystalline oxide semiconductors 152 and 152', the thickness of the first insulating film 14, and the thicknesses of the first crystalline oxide semiconductors 151a and 151b may be measured by the same method as in the first embodiment.

[0113] Also in the third embodiment, the lattice constants of the first crystalline oxide semiconductors 151a and 151b are larger than the lattice constants of the second crystalline oxide semiconductors 152 and 152'. Therefore, as described in the first embodiment, since the resistance values of the first crystalline oxide semiconductors 151a and 151b in the region (the region that is inherently likely to have contact resistance) in contact with the electrodes (the first electrode 11 and / or the second electrode 12) are low, the contact resistance of the transistor 10 can be improved.

[0114] Regarding the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, the first crystalline oxide semiconductors 151a and 151b, and the second crystalline oxide semiconductor 152, the descriptions in the first embodiment and the second embodiment may be incorporated by reference.

[0115] The manufacturing method of the transistor 10 according to the third embodiment is not particularly limited, and can be manufactured by a known method (for example, the method described in International Publication No. 2020 / 076850, etc.) while referring to the manufacturing method according to the first embodiment, particularly excluding the formation of the first crystalline oxide semiconductors 151a and 151b. The first crystalline oxide semiconductors 151a and 151b can be formed, for example, in the same manner as described in the first embodiment. Regarding the formation methods of the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, the first crystalline oxide semiconductors 151a and 151b, and the second crystalline oxide semiconductor 152, the descriptions in the first embodiment and the second embodiment may be incorporated by reference.

[0116] In each of the embodiments described above, the case where the transistor includes the first crystalline oxide semiconductor for each of the first electrode and the second electrode has been mainly shown, but the present invention is not limited thereto. For example, the transistor may include the first crystalline oxide semiconductor for only one of the first electrode and the second electrode. Further, the second insulating film 16 may be omitted. Further, as long as the effects of the present embodiment are achieved, the transistor may have a structure other than the structures shown in FIGS. 1 to 7.

[0117] 2. Semiconductor device A semiconductor device according to an aspect of the present invention includes a transistor according to an aspect of the present invention. The semiconductor device may include one or more transistors according to an aspect of the present invention. The semiconductor device according to the present aspect can improve the contact resistance in the transistor, and thus has excellent electrical characteristics and high reliability. The type of the semiconductor device is not particularly limited, but from the viewpoint of significantly exhibiting the above-described effects, a semiconductor memory device such as a volatile memory such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM); a mask ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory (NOR type flash memory, NAND type flash memory), MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), ReRAM (Resistive RAM), etc. is preferred. Alternatively, the semiconductor device according to this aspect may be a logic device such as TTL (Transistor-Transistor Logic), CMOS (Complementary Metal-Oxide-Semiconductor), BiCMOS, PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), MPU (Microprocessor Unit). In addition, since the vertical structure as shown in each embodiment can be applied to the transistor according to one aspect of the present invention, it is suitable for arranging a plurality of transistors at high density in a semiconductor memory device, and also contributes to the miniaturization of the semiconductor memory device. In addition, since the transistor according to one aspect of the present invention uses an oxide semiconductor as a channel, the leakage current tends to be small. Therefore, by using it in a semiconductor memory device, the capacitance of the capacitor can be reduced or the capacitor can be omitted. As a result, by using the transistor according to one aspect of the present invention, the semiconductor memory device can be miniaturized.

[0118] FIG. 8 is a diagram showing an example of a circuit configuration of a semiconductor memory device including a transistor according to one aspect of the present invention. As shown in FIG. 8, the semiconductor memory device 50 includes a transistor 10, a capacitor 51, a word line WL, and a bit line BL. The source electrode of the transistor 10 is connected to the bit line BL. The drain electrode of the transistor 10 is connected to one end of the capacitor 51. The gate electrode of the transistor 10 is connected to the word line WL. The other end of the capacitor 51 is grounded. The bit line BL may be connected to the first electrode 11 of the transistor 10 or may be connected to the second electrode 12. The word line WL may be connected to the third electrode 13 of the transistor 10. One end of the capacitor 51 may be connected to the first electrode 11 of the transistor 10 or may be connected to the second electrode 12.

[0119] In the example of FIG. 8, one memory cell 52 is formed by the transistor 10 and the capacitor 51. The memory cell 52 can store data based on the charge held by the capacitor 51. Note that the configuration of the memory cell 52 is not limited to this example, and in other examples, the capacitor 51 may be omitted. When the capacitor 51 is omitted, data can be stored based on the charge held in the transistor 10 itself. Also, the memory cell 52 may be configured by combining two or more transistors. When the transistor 10 itself is provided with a function of holding charge, for example, one or more of the configurations described below can be applied. (1) A high-k insulator such as hafnium oxide (HfO2) or zirconium oxide (ZrO2) is used for the second insulating film. (2) A ferroelectric such as (Pb,La)(Zr,Ti)O3 (PLZT), SrTiO3 (STO), or yttria-stabilized zirconia (YSZ) is used for the second insulating film. (3) An element that forms a level within the gap of the second crystalline oxide semiconductor is added to the second crystalline oxide semiconductor, and hysteresis is utilized. (4) The parasitic capacitance formed by arranging a part of the source electrode and / or drain electrode and a part of the gate electrode to face each other via an insulating film is utilized. Further, in the above (4), for example, it is possible to utilize a parasitic capacitance formed by arranging a part of one of the source electrode and the drain electrode and a part of the gate electrode so as to face each other with an insulating film interposed therebetween. At this time, the other of the source electrode and the drain electrode can be arranged away from the gate electrode (for example, the distance between the other of the source electrode and the drain electrode and the gate electrode may be longer than the distance between one of the source electrode and the drain electrode and the gate electrode).

[0120] The semiconductor memory device 50 can read the data stored in the memory cell 52 to the bit line BL by controlling the word line WL, and can also write the data transferred to the bit line BL into the memory cell 52. The semiconductor memory device 50 includes a memory cell array (not shown) composed of a plurality of memory cells 52.

[0121] Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art can easily make many changes to these exemplary embodiments and / or examples without substantially departing from the novel teachings and effects of the present invention. Therefore, many of these changes are included in the scope of the present invention. The contents of the documents described in this specification are all incorporated by reference.

Description of Reference Numerals

[0122] 10: Transistor 11: First electrode 12: Second electrode 13: Third electrode 14, 14a: First insulating film 14b: Third insulating film 151a, 151b: First crystalline oxide semiconductor 152, 152’: Second crystalline oxide semiconductor 16: Second insulating film 19: Insulating film 50: Semiconductor memory device 51: Capacitor 52: Memory cell WL: Word line BL: Bit line

Claims

1. A first electrode and a second electrode, a first crystalline oxide semiconductor provided in contact with the first electrode and / or the second electrode, a second crystalline oxide semiconductor connecting the first electrode and the second electrode via the first crystalline oxide semiconductor, a third electrode adjacent to the second crystalline oxide semiconductor without contact therewith, comprising: the first electrode and the second electrode are laminated via at least a first insulating film, a lattice constant of the first crystalline oxide semiconductor is larger than a lattice constant of the second crystalline oxide semiconductor, a transistor.

2. The transistor according to claim 1, wherein the first crystalline oxide semiconductor has a higher average carrier concentration than the second crystalline oxide semiconductor.

3. The transistor according to claim 1 or 2, wherein a composition of metal elements constituting the first crystalline oxide semiconductor and a composition of metal elements constituting the second crystalline oxide semiconductor are substantially the same.

4. The transistor according to claim 3, wherein a composition ratio of metal elements constituting the first crystalline oxide semiconductor and a composition ratio of metal elements constituting the second crystalline oxide semiconductor are substantially the same.

5. The transistor according to claim 1 or 2, wherein a ratio of the lattice constant of the second crystalline oxide semiconductor to the lattice constant of the first crystalline oxide semiconductor is 0.940 or more and 0.999 or less.

6. The transistor according to claim 1 or 2, wherein a thickness of the first crystalline oxide semiconductor is 2 nm or more and 100 nm or less.

7. The transistor according to claim 1 or 2, further comprising a second insulating film provided between the third electrode and the second crystalline oxide semiconductor.

8. The transistor according to claim 1 or 2, wherein the second crystalline oxide semiconductor penetrates at least the first insulating film.

9. the first electrode and the third electrode are laminated via the first insulating film, the third electrode and the second electrode are laminated via a third insulating film, The transistor according to claim 1 or 2, wherein the second crystalline oxide semiconductor penetrates the first insulating film, the third electrode, and the third insulating film and is provided in a columnar shape.

10. the second crystalline oxide semiconductor penetrates the first electrode and the first insulating film and is provided in a columnar shape, further comprising a second insulating film on an inner peripheral surface and a bottom surface of a recess formed from one end side to the other end side of the columnar second crystalline oxide semiconductor. The transistor according to claim 1 or 2, wherein the third electrode is provided so as to fill the recess in which the second insulating film is formed.

11. The transistor according to claim 1 or 2, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (Ni3N).

12. The transistor according to claim 1 or 2, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor includes a cubic crystal structure.

13. The transistor according to claim 1 or 2, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains indium oxide as a main component.

14. The transistor according to claim 1 or 2, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains Ga or Al.

15. The transistor according to claim 1 or 2, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains Ga.

16. The transistor according to claim 1 or 2, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor contains Ga and Al.

17. The transistor according to claim 1 or 2, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a polycrystalline oxide semiconductor.

18. The transistor according to claim 1 or 2, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a single crystal oxide semiconductor.

19. The transistor according to claim 1 or 2, wherein at least one selected from the group consisting of the first crystalline oxide semiconductor and the second crystalline oxide semiconductor is a crystalline oxide semiconductor formed by an atomic layer deposition method.

20. A semiconductor device including the transistor according to claim 1 or 2.

21. The semiconductor device according to claim 20, which is a semiconductor memory device.

22. A first electrode and a second electrode; A first crystalline oxide semiconductor provided in contact with the first electrode and / or the second electrode; A second crystalline oxide semiconductor connecting the first electrode and the second electrode via the first crystalline oxide semiconductor; A third electrode adjacent to the second crystalline oxide semiconductor without contacting the second crystalline oxide semiconductor; Comprising: The first electrode and the second electrode are laminated via at least a first insulating film; The lattice constant of the first crystalline oxide semiconductor is larger than the lattice constant of the second crystalline oxide semiconductor; The composition ratio of the metal elements constituting the first crystalline oxide semiconductor and the composition ratio of the metal elements constituting the second crystalline oxide semiconductor are substantially the same; The ratio of the lattice constant of the second crystalline oxide semiconductor to the lattice constant of the first crystalline oxide semiconductor is 0.940 or more and 0.999 or less; The thickness of the first crystalline oxide semiconductor is 2 nm or more and 100 nm or less; The first crystalline oxide semiconductor and the second crystalline oxide semiconductor include a bicrystal structure; Transistor.

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