Back-contact cells and solar modules

Abstract

To provide a back contact cell and a solar cell module, capable of enhancing the efficiency and a reliability of the cell as well as increasing the open circuit voltage of the cell.SOLUTION: A back contact cell includes: a semiconductor substrate which has a front surface and a back surface opposite to each other, and in which the back surface includes a plurality of adjacent and alternately arranged segment units, segment spaces are formed between the respective segment units and a backlight surface, the segment spaces each further include a first space, a second space, a third space and a fourth space; a first passivation layer, located only in each first space; a first doped semiconductor layer, located only in each first space, and being adjacent to a side of the first passivation layer away from the semiconductor substrate; a second passivation layer, located only in each second space to each fourth space; and a second doped semiconductor layer located only in each second space to each fourth space and being adjacent to a side of the second passivation layer away from the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application mainly relates to the technical field of photovoltaic power generation, and particularly relates to back-contact batteries and solar cell modules.

Background Art

[0002] With the maturity and continuous exploration of PERC (Passivated emitter and rear contact) cell technology, it is gradually approaching the theoretical limit of its conversion efficiency. The industry has begun to seek next-generation technologies, and the currently promoted mainstream technologies are TOPCon, HJT, IBC, etc.

[0003] Different from conventional cells with double-sided electrode contacts, the biggest feature of back-contact cells is that the metal electrodes are located on the back of the cell, there is no shielding of the metal electrodes on the front, and the light utilization rate is improved. Therefore, the short-circuit current and conversion efficiency are higher. However, the passivation performance and open-circuit voltage of back-contact cells are generally poor, and the photoelectric conversion efficiency is not high. Therefore, how to further improve the performance of back-contact cells is a technical problem that should be urgently solved in this field.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The technical problem to be solved in this application is to provide a back-contact battery and a solar cell module that can increase the open-circuit voltage of the battery and improve the efficiency and reliability of the battery.

Means for Solving the Problems

[0005] To solve the above technical problems, the present application provides a semiconductor substrate having opposing front and back surfaces, wherein the front surface is close to the light-receiving surface of the back-contact battery, the back surface is close to the backlight surface of the back-contact battery, the back surface is provided with a plurality of segment units arranged adjacent to each other in sequence, and each segment unit includes a first segment, a second segment, a third segment, and a fourth segment arranged adjacent to each other in sequence and alternately. A first space, a second space, a third space, and a fourth space are respectively formed between the first segment to the fourth segment and the back surface, and the first space to the fourth space commonly constitute the segment space between each segment unit and the backlight surface. The semiconductor substrate is further provided with a first passivation layer located only in the first space in each segment space, a first doped semiconductor layer located only in the first space in each segment space and adjacent to the side of the first passivation layer away from the semiconductor substrate, a second passivation layer located only in the second space, the third space, and the fourth space in each segment space, and a second doped semiconductor layer located only in the second space, the third space, and the fourth space in each segment space and adjacent to the side of the second passivation layer away from the semiconductor substrate, thereby providing a back-contact battery.

[0006] In one embodiment of the present application, the semiconductor substrate further includes a substrate doping layer having the same conductivity type as the semiconductor substrate at a position adjacent to each of the first segments.

[0007] In one embodiment of the present application, an insulating layer is further provided at positions in the first space, the second space, and the fourth space in each segment space, located on the side of the first doped semiconductor layer away from the semiconductor substrate in the first space, and adjacent to the back surface of the semiconductor substrate in the second space and the fourth space.

[0008] In one embodiment of the present application, the semiconductor device further comprises a doped oxide layer located in the first space of each of the segment spaces and adjacent to the insulating layer and between the side of the first doped semiconductor layer away from the semiconductor substrate.

[0009] In one embodiment of the present application, the device further includes conductive layers located in the first space, the second space, the third space, and the fourth space in each of the segment spaces, wherein in the first space, at least a portion of the conductive layers is adjacent to the insulating layer on a side away from the semiconductor substrate, and at least another portion of the conductive layers is adjacent to the first doped semiconductor layer on a side away from the semiconductor substrate, and in the second to fourth spaces, at least a portion of the conductive layers is adjacent to the second doped semiconductor layer on a side away from the semiconductor substrate.

[0010] In one embodiment of the present application, the semiconductor device further includes a first electrode and a second electrode located in the first space and the third space, respectively, in each of the segment spaces, wherein the first electrode is located on the side of the conductive layer away from the semiconductor substrate in the first space, and the second electrode is located on the side of the conductive layer away from the semiconductor substrate in the third space.

[0011] In one embodiment of the present application, the conductive layer forms a contact groove recessed into the semiconductor substrate within the first space in each of the segment spaces, the first electrode contacts the conductive layer within the contact groove, and the contact groove contacts the conductive layer on a surface closer to the semiconductor substrate or extends into the first doped semiconductor layer.

[0012] In one embodiment of the present application, the first segment, the second segment, the third segment, and the fourth segment have a first distance L1, a second distance L2, a third distance L3, and a fourth distance L4 from the front surface of the semiconductor substrate, respectively, where L3 is less than or equal to L2, L3 is less than or equal to L4, L2 is less than or equal to L1, and L4 is less than or equal to L1.

[0013] In one embodiment of the present application, the battery structures in the second space and the fourth space corresponding to the second segment and the fourth segment are the same, and L2 is equal to L4. In one embodiment of the present application, the semiconductor device further comprises a front passivation layer located between the front surface of the semiconductor substrate and the light-receiving surface and adjacent to the front surface, the front passivation layer comprising intrinsic amorphous silicon, alumina, silicon nitride, silicon oxynitride, and / or silicon oxide.

[0014] In one embodiment of the present application, the semiconductor device further comprises a front region reduction layer adjacent to the side of the front region passivation layer facing away from the semiconductor substrate, the front region reduction layer comprising silicon nitride, silicon oxynitride, silicon oxide and / or a transparent conductive layer.

[0015] In one embodiment of the present application, the front surface of the semiconductor substrate has a pile structure, and the pile structure comprises pyramidal piles and / or corrosion pit piles.

[0016] In one embodiment of the present application, the back surface of the semiconductor substrate has the pile structure and / or the polishing surface structure, the third segment is a pile structure or a polishing surface structure, and the first segment, the second segment and the fourth segment are polishing surface structures.

[0017] In one embodiment of the present application, the first passivation layer comprises a tunneling oxide layer, and the first doped semiconductor layer comprises doped polycrystalline silicon, and the first doped semiconductor layer has the same doping type as the semiconductor substrate.

[0018] In one embodiment of the present application, the device further comprises at least one separation groove located in each of the segment spaces, the separation groove being located only in the first space or being located in both the second space and the fourth space.

[0019] In one embodiment of the present application, the semiconductor device further includes two isolation trenches located in the second space and the fourth space in each segment space, and the two isolation trenches penetrate up to the inside of the insulating layer in a direction gradually approaching the semiconductor substrate.

[0020] In one embodiment of the present application, the semiconductor device further includes two isolation grooves located within the first space in each of the segment spaces, the two isolation grooves being located on both sides of the contact groove, and the two isolation grooves penetrating up to the interior of the insulating layer in a direction gradually approaching the semiconductor substrate.

[0021] In another aspect, the present application further provides a solar cell module comprising a plurality of series and / or parallel connected back-contact cells as proposed by any of the embodiments of the present application. Compared with the prior art, the present application has the following advantages: The proposed back-contact battery is designed with an alternating segment unit structure on the back of the battery, with different battery feature layers arranged at different segments and spatial positions within each segment unit, and with different contact groove and separation groove positions, which effectively improves the open-circuit voltage of the battery and ensures higher conversion efficiency and reliability of the battery.

[0022] The accompanying drawings are included to provide a further understanding of the present application, constitute a part of this application, illustrate examples of the present application, and together with the description, serve to explain the principles of the present application. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a schematic diagram illustrating the configuration of a back-contact battery according to an embodiment of the present application; [Figure 2] FIG. 2 is a schematic diagram of a back-contact battery according to another embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0024] In order to more clearly explain the technology of the embodiments of the present application, the drawings necessary for the description of the embodiments will be briefly described below. Obviously, the drawings in the following description are merely some examples or embodiments of the present application, and those of ordinary skill in the art can also apply the present application to other similar scenarios based on these drawings without paying inventive efforts. Unless it is clear from the language or otherwise described, the same symbols in the drawings represent the same structures or operations.

[0025] As used herein and in the claims, unless the context clearly indicates otherwise, terms such as "a," "one," "an," "one," and / or "the" do not specifically refer to the singular but may also include the plural. Generally, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, and do not constitute an exclusive list of these steps and elements; a method or apparatus may include other steps or elements.

[0026] Unless otherwise specified, the relative arrangement of components and steps, numerical expressions, and values described in these examples do not limit the scope of the present application. It should be understood, however, that the dimensions of the various parts shown in the drawings are not drawn to scale for ease of illustration. Techniques, methods, and apparatus known to those of ordinary skill in the relevant arts may not be discussed in detail, but, where appropriate, such techniques, methods, and apparatus are deemed part of the granted patent specification. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, not limiting. Thus, other examples of the illustrative embodiments may have different values. It should be noted that in the following drawings, like symbols and letters indicate similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0027] In the specification of the present application, it should be understood that the directions or positional relationships indicated by directional terms such as "front, rear, top, bottom, left, right", "lateral direction, longitudinal direction, vertical, horizontal", and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for facilitating the description of the present application and simplifying the description. These directional terms do not indicate or imply that the specified device or element must have a specific direction or be configured and operate in a specific direction without further explanation, and thus should not be understood as limiting the protection scope of the present application. The directional term "inside, outside" means the inside and outside of the contour of each component itself.

[0028] For the sake of facilitating the description, the spatial positional relationship between one component or feature shown in the drawings and another component or feature can be described herein using spatial relational terms such as "above...", "above...", "upper surface of...", "on the upper surface". It will be understood that these spatial relational terms are intended to include directions other than the direction shown in the drawings for the components during use or operation. For example, if the components in the drawings are inverted, a component described as "above another component or structure" or "on another component or structure" will be positioned as "below another component or structure" or "under another component or structure". Therefore, the exemplary term "above..." can include two directions, namely "above..." and "below...". The component may also be positioned in other different ways (rotated by 90 degrees or in other orientations), and the spatial relative description used herein may be appropriately explained.

[0029] It should also be noted that the use of terms such as "first" and "second" to define components is merely to facilitate distinguishing between corresponding components, and that unless otherwise stated, the terms do not have any special meaning and therefore should not be understood as limiting the scope of protection of the present application. Furthermore, although the terms used in the present application are selected from well-known terms, some terms described in the specification of the present application have been selected by the applicant at his / her own discretion, and their detailed meanings will be explained in the relevant parts of the description of this specification. It is also required to understand the present application not only by the actual terms used but also by the meanings contained in each term.

[0030] In one embodiment of the present invention, referring to FIG. 1, a back-contact battery 10 is proposed, which can improve the open circuit voltage of the battery, and thereby enhance the efficiency and reliability of the battery.

[0031] 1, the back-contact cell 10 mainly comprises a semiconductor substrate 100, a first passivation layer 111, a first doped semiconductor layer 112, a second passivation layer 121, and a second doped semiconductor layer 122. Specifically, the semiconductor substrate 100 has opposing front and back surfaces 101 and 102, with the front surface 101 being closer to the light-receiving surface of the back-contact cell 10 (i.e., the top surface of the entire back-contact cell 10 faces the outermost surface of the light source), and the back surface 102 being closer to the backlight surface of the back-contact cell 10 (i.e., the back surface of the entire back-contact cell 10 faces the outermost surface of the light source). Combining with FIG. 1, it can be seen that the back surface 102 comprises a plurality of segment units 20 arranged adjacent to each other in sequence. Further, referring to FIG. 1, each segment unit 20 includes a first segment 21, a second segment 22, a third segment 23, and a fourth segment 24, which are adjacently arranged alternately, and a first space 210, a second space 220, a third space 230, and a fourth space 240 are formed between the first segment 21 to the fourth segment 24 and the rear surface 102, respectively, and the first space 210 to the fourth space 240 collectively form a segment space 200 between each segment unit 20 and the backlight surface.

[0032] In this application, the division of the back surface 102 into multiple segment units 20, further subdivided into first to fourth segments 21 to 24, and the formation of first to fourth spaces 210 to 240 within the space are intended to facilitate the explanation of the location of each feature layer on the back surface 102, particularly the location of the first isolation groove 161 and the second isolation groove 162 (described further below). The division of these segments and spaces is not an inherent attribute of the back-contact battery 10. Furthermore, because the conclusion of these divisions is not based on battery attributes but belongs to an artificial division scheme, Figure 1 merely illustrates the morphological characteristics (e.g., a right angle) of the intersecting interfaces between adjacent segments. In actual production, these intersecting interfaces will vary depending on the actual deposition and etching conditions of each feature layer. Therefore, those skilled in the art will understand that the intersecting interfaces of each segment should not be unreasonably limited to those shown in Figure 1.

[0033] 1, the first passivation layer 111 is located only in the first space 210 in each segment space 200. The first doping semiconductor layer 112 is located only in the first space 210 in each segment space 200 and is adjacent to the side of the first passivation layer 111 that faces away from the semiconductor substrate 100. Based on this, the second passivation layer 121 is located only in the second space 220, the third space 230, and the fourth space 240 in each segment space 200. The second doping semiconductor layer 122 is located only in the second space 220, the third space 230, and the fourth space 240 in each segment space 200 and is adjacent to the side of the second passivation layer 121 that faces away from the semiconductor substrate 100.

[0034] Based on such a design concept, the first passivation layer 111 in the present application can actually be implemented as a tunneling oxide layer. The first doped semiconductor layer 112 comprises doped polycrystalline silicon, and the first doped semiconductor layer 112 has the same doping type as the semiconductor substrate 100. On the other hand, in this embodiment, the second passivation layer 121 comprises intrinsic amorphous silicon. Correspondingly, the second doped semiconductor layer 122 comprises doped amorphous silicon or doped microcrystalline silicon, and the second doped semiconductor layer 122 has a doping type opposite to that of the semiconductor substrate 100. Thereby, based on the separation and transition of the second segment 22 and the corresponding second space 220, the battery passivation performance is improved on one side (the first space 210) of the second space 220, and the open-circuit voltage of the battery is increased on the other side (the third space) of the second space 220, thereby improving the efficacy and stability of the back-contact battery 10.

[0035] Preferably, in this embodiment, the semiconductor substrate 100 further comprises a substrate doping layer 113 of the same material and conductivity type as the semiconductor substrate 100 at a position adjacent to each first segment 21. As is apparent from FIG. 1, since the substrate doping layer 113 is located on the side close to the semiconductor deposit 100 on the back surface 102, the lower surface of the substrate doping layer 113 is also the first segment 21 on the back surface 102. By providing the substrate doping layer 113, a back electric field can be formed in the semiconductor substrate 100. Exemplarily, when manufacturing the first doped semiconductor layer 112, especially when doping, the doping source is pushed into the semiconductor substrate 100 to form the substrate doping layer 113.

[0036] Furthermore, the back-contact battery 10 of this embodiment is located in the first space 210 within each segment space 200, and further includes a doped oxide layer 114 adjacent to the side of the first doped semiconductor layer 112 away from the semiconductor substrate 100. Exemplarily, the doped oxide layer 114 has the same doping material as the first doped semiconductor layer 112, and the doped oxide layer 114 can select doped silicon oxide. In addition, in some other embodiments of the present application, the doped oxide layer 114 may not be provided. Specifically, during the manufacture of the battery, especially when doping the first doped semiconductor layer 112, the doped oxide layer 114 can be directly formed, so in some embodiments, the layer can be removed in an additional step. In contrast, in this embodiment, by retaining this doped oxide layer 114, the process flow can be simplified and the production cost can be reduced. In addition to this, the back-contact battery 10 is located in the first space 210, the second space 220, and the fourth space 240 within each segment space 200, adjacent to the side of the doped oxide layer 114 away from the semiconductor substrate 100 in the first space 210, and further includes an insulating layer 13 adjacent to the back surface of the semiconductor substrate in the second space 220 and the fourth space 240. Exemplarily, the insulating layer 13 may be composed of one or more of compounds such as silicon nitride, silicon oxynitride, and silicon oxide. In this embodiment, by providing this insulating layer 13, it is possible to effectively avoid the occurrence of electrical connection and short circuit in different polarity regions on the back surface 102.

[0037] In addition to the above configuration, the back-contact battery 10 further includes a conductive layer 14 located in the first space 210, the second space 220, the third space 230, and the fourth space 240 within each segment space 200. Specifically referring to FIG. 1, in the first space 210, at least a part of the conductive layer 14 is adjacent to the side of the insulating layer 13 away from the semiconductor substrate 100, and at least some other part of the conductive layer 14 is adjacent to the side of the first doped semiconductor layer 112 away from the semiconductor substrate 100. On the other hand, among the second space 220 to the fourth space 240, at least a part of the conductive layer 14 is adjacent to the side of the second doped semiconductor layer 122 away from the semiconductor substrate 100.

[0038] In addition, in this embodiment, the back-contact battery 10 further includes a first electrode 151 and a second electrode 152 located in the first space 210 and the third space 230, respectively, within each segment space 200, with the first electrode 151 located on the side of the conductive layer 14 in the first space 210 away from the semiconductor substrate 100, and the second electrode 152 located on the side of the conductive layer 14 in the third space 230 away from the semiconductor substrate 100.

[0039] More preferably, in this embodiment, the conductive layer 14 forms a contact groove 140 recessed into the semiconductor substrate 100 within the first space 210 in each segment space 200, the first electrode 151 contacts the conductive layer 14 within the contact groove 140, and the contact groove 140 contacts the conductive layer 14 on the surface facing the semiconductor substrate 100. However, the present application is not limited to the example shown in FIG. 1 , and in some other embodiments of the present application, the contact slot extends into the first doped semiconductor layer 112. It is understood that, when manufacturing a back-contact cell 10, the cell can be completed by bonding the layers together through etching and deposition on the back surface 102. To form the contact groove 140, for example, the doped oxide layer 114 and insulating layer 13 already fabricated within the first space 210 can be locally etched to form the shape of the contact groove 140 before depositing the conductive layer 14. Examples of local etching methods include laser ablation-combined wet etching, printed corrosive ink-combined wet etching, etc. As a result, as the conductive layer 14 continues to be deposited, it forms groove-like features in the etched areas, creating contact grooves 140 .

[0040] Furthermore, as can be seen from FIG. 1 , the back surface 102 has a topographical feature characterized by undulations. Specifically, the first distance L1, the second distance L2, the third distance L3, and the fourth distance L4 from the first segment 21, the second segment 22, the third segment 23, and the fourth segment 24 to the front surface 101 of the semiconductor substrate 100 are defined, respectively. For example, since the front surface 101 has a pile structure, the lower edge of the pile structure is selected as the reference line to define the above-mentioned distances. However, the present application is not limited thereto. In other embodiments of the present application, other reference line determination methods may be used depending on the shape of the front surface 101. However, as long as the first to fourth segments 21 to 24 adopt the same reference line determination method, the relative magnitude relationships of the distances L1 to L4 from the first segment 21, the second segment 22, the third segment 23, and the fourth segment 24 to the front surface 101 of the semiconductor substrate 100 described herein will not change.

[0041] Specifically, in some embodiments herein, L3 is equal to or less than L2, L3 is equal to or less than L4, L2 is equal to or less than L1, and L4 is equal to or less than L1. Preferably, in some embodiments herein, the corresponding second spaces 220 and fourth spaces 240 of the second segment 22 and the fourth segment 24 have the same battery structure, and L2 is equal to L4. Therefore, in such embodiments, the second spaces 220 and the fourth spaces 240 can be collectively understood as separation or transition regions of the back-contact battery 10. Specifically, the second spaces 220 can be understood as a separation or transition region between the feature regions of the first spaces 210 and the third spaces 230 of each adjacent segment space 200, while the fourth spaces 240 can be understood as a separation or transition region between the feature region of the third space 230 of the preceding segment space 200 and the feature region of the first space 210 of the following segment space 200, for each adjacent two segment spaces 200.

[0042] In different embodiments proposed in the present application, the back contact battery further separates at least one isolation groove located within each segment space, which is located only within the first space or in both the second space and the fourth space. This will be further described in detail with reference to the drawings below.

[0043] Exemplarily, FIG. 1 shows a case where the isolation grooves are located in both the second space 220 and the fourth space 240. In this embodiment, the number of isolation grooves is two, namely the first isolation groove 161 and the second isolation groove 162 respectively. Referring to FIG. 1, it can be seen that the first isolation groove 161 is located in the second space 220 and the second isolation groove 162 is located in the fourth space 240. Further, the first isolation groove 161 and the second isolation groove 162 sequentially penetrate the conductive layer 14, the second doped semiconductor layer 122, and the second passivation layer 121 in a direction gradually approaching the semiconductor substrate 100, and finally reach the lower end of the insulating layer 13. However, the present application is not limited thereto. Exemplarily, based on a further deformation of FIG. 1, the first isolation groove 161 can continue to extend upward to the inside of the insulating layer 131 but does not penetrate the insulating layer 131. In this embodiment, the first isolation groove 161 and the second isolation groove 162 are respectively provided in the second space 220 and the fourth space 240 that do not include the first electrode 151 and the second electrode 152, so that each segment unit 20 can perform a more complete separation between two polar regions in the corresponding segment space 200.

[0044] On the other hand, Figure 2 shows another embodiment in which the separation grooves are located at different positions. The back-contact battery 10' shown in Figure 2 differs from the back-contact battery 10 shown in Figure 1 only in the positions of two separation grooves (third separation groove 161' and fourth separation groove 162'), and the same reference numerals are used for other similar parts. In the embodiment shown in Figure 2, the two separation grooves are located within the first space 210 of each segment space 200. As can be seen from Figure 2, the third separation groove 161' and the fourth separation groove 162' are located on both sides of the contact groove 140, respectively, and the two separation grooves penetrate up to the interior of the insulating layer in a direction gradually approaching the semiconductor substrate. Unlike the embodiment shown in Figure 1, in this embodiment, the separation grooves are positioned to match the position of the contact groove 140, allowing for appropriate fabrication processing.

[0045] Having described the back structure of the back-contact cell 10 above, we will now describe the front structure of the back-contact cell 10. On the front surface 101, the back-contact cell further comprises a front passivation layer 16 located between the front surface 101 and the light-receiving surface of the semiconductor substrate 100 and adjacent to the front surface 101, where the front passivation layer 16 may be composed of one or more of materials such as intrinsic amorphous silicon, alumina, silicon nitride, silicon oxynitride, and silicon oxide.

[0046] Additionally, according to FIG. 1 , the back-contact cell 10 further comprises a front resistive layer 17 on the front passivation layer 16 adjacent to the side of the front passivation layer 16 facing away from the semiconductor substrate 100, wherein the front resistive layer 17 can be composed of one or more of silicon nitride, silicon oxynitride, silicon oxide, and a transparent conductive layer.

[0047] Meanwhile, the front surface 101 of the semiconductor substrate 100 has a pile structure, which may be a pyramidal pile or a corrosion pit pile, or a combination of both, which can better reduce the reflection loss of incident light and increase light absorption. Correspondingly, the back surface 102 of the semiconductor substrate 100 has a pile structure, a polished surface structure, or a combination of both. Preferably, referring to the embodiment shown in FIG. 1, on the back surface 102, the third segment 23 has a pile structure or a polished surface structure, and the first segment 21, the second segment 22, and the fourth segment 24 have polished surface structures. This design method can improve the passivation effect and simplify the process technology.

[0048] Based on the manufacturing technology of back-contact batteries, considering comprehensively the battery performance improvement effect, process cost, etc., a plurality of first to fourth spaces arranged alternately adjacent to each other are designed on the backlight surface side of the solar cell. Each space has the same or different battery structures. Here, the performance of the battery is mainly reflected by the characteristic layers in the first space and the third space. The first space is set as a laminated structure having a first passivation layer (for example, a tunnel oxide layer) and a doped semiconductor layer (for example, doped polycrystalline silicon), which has good passivation contact characteristics, can reduce the carrier recombination rate in the metal electrode contact region, and can improve the open-circuit voltage of the battery. Furthermore, in the third space, a laminated structure having a second passivation layer (for example, intrinsic amorphous silicon) and a second doped semiconductor layer (for example, doped amorphous silicon / doped microcrystalline silicon, etc.) is provided, and the open-circuit voltage of the battery can be further increased by utilizing the characteristics such as its low surface recombination rate. Moreover, there are the second space and the fourth space, where the battery structures may be the same or different. The functions of these two spaces are to isolate the first space and the third space with opposite polarities, avoid the occurrence of short-circuit and leakage phenomena, and ensure higher conversion efficiency and reliability of the battery. In addition, considering further elements such as the feasibility of the technology and the simplification of the process, the present application also proposes the specific position characteristics of other characteristic layers (such as insulation layers, conductive layers, etc.) and the separation tank, thereby ensuring the improvement of the battery performance and further ensuring the reliability of the battery under the premise of permission and controllability of the technical scope.

[0049] The present application further proposes a solar cell module comprising the back-contact battery proposed by any of the above embodiments of the present application, which are connected in series and / or in parallel. Since other details regarding the solar cell module are not the focus of the present application, they will not be elaborated here.

[0050] While the basic concepts have been described above, it will be apparent to those skilled in the art that the above disclosure is merely illustrative and not limiting of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are proposed herein and therefore fall within the spirit and scope of the exemplary embodiments of the present application.

[0051] At the same time, the present application uses specific terms to describe embodiments of the present application. For example, "one embodiment," "one embodiment," and / or "some embodiments" refer to features, configurations, or characteristics associated with at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment," "one embodiment," or "one alternative embodiment" mentioned more than once in different places in this specification do not necessarily refer to the same embodiment. Furthermore, some features, configurations, or characteristics in one or more embodiments of the present application may be combined as appropriate.

[0052] For the same reason, in the foregoing description of the embodiments of the present application, multiple features may be combined into one embodiment, drawing, or description thereof in order to simplify the disclosed language and facilitate understanding of one or more embodiments of the present application. However, this method of disclosure does not imply that the subject matter of the present application requires more features than are recited in the claims. In fact, an embodiment may have fewer features than all of the features of a single embodiment disclosed above.

[0053] In some examples, numbers are used to describe the number of components or attributes. It should be understood that the numbers describing such examples are, in some instances, modified using the modifiers "about," "approximately," or "approximately." Unless otherwise specified, "about," "approximately," or "approximately" means that the numerical value can vary by ±20%. Accordingly, in some examples, the numerical parameters used in the specification and claims are approximations, and these approximations may vary depending on the characteristics required for a particular example. In some examples, the numerical parameters should be calculated using a given number of significant digits and ordinary methods of conserving digits. In some examples, the numerical fields and parameters used to determine the breadth of ranges are approximations; however, in certain examples, such numerical values are set as precisely as possible within the ranges possible.

[0054] Although the present application has been described with reference to the present specific embodiments, it should be noted that a person of ordinary skill in the art should recognize that the above embodiments are only used to describe the present application, and various equivalent modifications or substitutions are possible without departing from the spirit of the present application; therefore, any modifications or variations of the above embodiments within the spirit of the present application should fall within the scope of the claims of the present application. [Explanation of symbols]

[0055] 10 Rear contact battery 13 Insulating layer 14 Conductive layer 16 Front passivation layer 17 Frontal rice production reduction layer 20 segment units 21 First Segment 22 Second Segment 23 Third Segment 24 4th Segment 100 Semiconductor substrate 101 Front 102 Back 111 First passivation layer 112 First doped semiconductor layer 113 Substrate doping layer 114 Doping oxide layer 121 Second passivation layer 122 Second doping semiconductor layer 140 Contact groove 140 151 1st electrode 152 2nd electrode 161 1st separation groove 161' 3rd separation groove 162 2nd separation groove 162' 4th separation groove 200 Segment Space 210 1st space 220 2nd space 230 Third space 240 4th space

Claims

1. A semiconductor substrate having opposing front and back surfaces, with the front surface close to the light-receiving surface of a back-contact battery and the back surface close to the backlight surface of the back-contact battery, the back surface comprising a plurality of segment units arranged adjacent to each other in sequence, and each segment unit comprising a first segment, a second segment, a third segment, and a fourth segment arranged adjacent to each other in sequence and alternately, a first space, a second space, a third space, and a fourth space being formed between the first segment to the fourth segment and the back surface respectively, the first space to the fourth space commonly constituting the segment space between each segment unit and the backlight surface. A first passivation layer located only in the first space in each of the segment spaces. A first doped semiconductor layer located only in the first space in each of the segment spaces and adjacent to the side of the first passivation layer away from the semiconductor substrate. A second passivation layer located only in the second space, the third space, and the fourth space in each of the segment spaces. A second doped semiconductor layer located only in the second space, the third space, and the fourth space in each of the segment spaces and adjacent to the side of the second passivation layer away from the semiconductor substrate. An insulating layer located in the first space, the second space, and the fourth space in each of the segment spaces, located on the side of the first doped semiconductor layer away from the semiconductor substrate in the first space, and adjacent to the back surface of the semiconductor substrate in the second space and the fourth space. A back-contact battery characterized by comprising the above.

2. The back-contact battery according to claim 1, wherein the semiconductor substrate further comprises a substrate doping layer having the same conductivity type as the semiconductor substrate at positions adjacent to each of the first segments.

3. The back-contact battery according to claim 1, further comprising a doped oxide layer located adjacent to the side between the side of the first doped semiconductor layer away from the semiconductor substrate and the insulating layer in the first space in each of the segment spaces.

4. The back-contact battery further comprises a conductive layer located in the first space, the second space, the third space, and the fourth space in each of the segment spaces. In the first space, at least a part of the conductive layer is adjacent to the side of the insulating layer away from the semiconductor substrate, and at least another part of the conductive layer is adjacent to the side of the first doped semiconductor layer away from the semiconductor substrate. The back contact battery according to claim 1, wherein in the second to fourth spaces, at least a part of the conductive layer is adjacent to the side of the second doped semiconductor layer away from the semiconductor substrate.

5. The back contact battery according to claim 4, further comprising a first electrode and a second electrode respectively located in the first space and the third space in each segment space, wherein the first electrode is located on the side of the conductive layer away from the semiconductor substrate in the first space, and the second electrode is located on the side of the conductive layer away from the semiconductor substrate in the third space.

6. The conductive layer forms a contact groove recessed in the semiconductor substrate within the first space in each segment space, the first electrode contacts the conductive layer within the contact groove, the contact groove contacts the conductive layer on the surface closer to the semiconductor substrate, or extends into the interior of the first doped semiconductor layer. The back contact battery according to claim 5, characterized in that.

7. From the first segment, the second segment, the third segment, and the fourth segment to the front surface of the semiconductor substrate, they have first distance L1, second distance L2, third distance L3, and fourth distance L4 respectively, where L3 is less than or equal to L2, L3 is less than or equal to L4, L2 is less than or equal to L1, and L4 is less than or equal to L1. The back contact battery according to claim 1, characterized in that.

8. The battery structures in the second space and the fourth space corresponding to the second segment and the fourth segment are the same, and the back contact battery according to claim 7, characterized in that L2 is equal to L4.

9. The back contact battery according to claim 1, further comprising a front passivation layer located between the front surface of the semiconductor substrate and the light receiving surface and adjacent to the front surface, wherein the front passivation layer comprises at least one of intrinsic amorphous silicon, alumina, silicon nitride, nitrogen oxide, and silicon oxide.

10. The back contact cell according to claim 9, further comprising a front antireflection layer adjacent to the side of the front passivation layer away from the semiconductor substrate, wherein the front antireflection layer comprises at least one of silicon nitride, silicon oxynitride, silicon oxide, and a transparent conductive layer.

11. The back contact cell according to claim 10, wherein the front surface of the semiconductor substrate has a pile structure, and the pile structure comprises pyramid piles and / or etched pit piles.

12. The back contact cell according to claim 11, wherein the back surface of the semiconductor substrate has the pile structure and / or a polished surface structure, the third segment has a pile structure or a polished surface structure, and the first segment, the second segment, and the fourth segment have a polished surface structure.

13. The back contact cell according to claim 1, wherein the first passivation layer comprises a tunneling oxide layer, the first doped semiconductor layer comprises doped polycrystalline silicon, and the first doped semiconductor layer has the same doping type as the semiconductor substrate.

14. The back contact cell according to claim 13, wherein the second passivation layer comprises intrinsic amorphous silicon, the second doped semiconductor layer comprises doped amorphous silicon and / or doped microcrystalline silicon, and the second doped semiconductor layer has a doping type opposite to that of the semiconductor substrate.

15. The back contact cell according to any one of claims 1 to 14, further comprising at least one isolation groove located in each of the segment spaces, wherein the isolation groove is located only in the first space or in both the second space and the fourth space.

16. The back contact cell according to claim 3, further comprising two isolation grooves located in the second space and the fourth space in each segment space, wherein the two isolation grooves penetrate up to the inside of the insulating layer at most in a direction approaching the semiconductor substrate.

17. The back contact cell according to claim 6, further comprising two isolation grooves located in the first space in each segment space, wherein the two isolation grooves are located on both sides of the contact groove respectively, and the two isolation grooves penetrate up to the inside of the insulating layer at most in a direction approaching the semiconductor substrate.

18. A solar cell module comprising the back contact battery according to any one of claims 1 to 14, 16, and 17, connected in series and / or in parallel.

19. A solar cell module comprising the back contact battery according to claim 15, connected in series and / or in parallel.

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