Semiconductor device

Abstract

To provide a technique of suppressing a switching loss while reducing an on-resistance.SOLUTION: A semiconductor device includes: a semiconductor substrate having an element region and a peripheral region; and a plurality of trenches extending in a first direction in an upper surface of the semiconductor substrate and arranged in a second direction with a space in between. The element region includes: an n-type source region; a p-type contact region; a p-type body region; an n-type drift region; a p-type bottom region; and a plurality of p-type connection regions. The bottom region is arranged in the lower part of the trenches with intervals in between from the bottom surface of the trenches. The connection region is connected to the body region and the bottom region, extend in the first direction, and are arranged in the second direction with intervals in between. The element region has an outside part located on both sides of the element region in the second direction and the center part arranged between the outside parts. The interval of the connection region in the outside part in the second direction is larger than the interval of the connection region in the center part in the second region.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device.

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, a plurality of trenches provided on the upper surface of the semiconductor substrate, a gate insulating film covering the inner surface of the trenches, and a gate electrode disposed in the trenches. In this semiconductor device, the semiconductor substrate has an n-type source region, a p-type contact region, a p-type body region, an n-type drift region, a p-type bottom region, and a plurality of p-type connection regions. The source region is exposed on the upper surface of the semiconductor substrate and is in contact with the gate insulating film. The contact region is exposed on the upper surface of the semiconductor substrate. The body region is in contact with the gate insulating film below the source region and is in contact with the contact region. The drift region is in contact with the gate insulating film below the body region. The bottom region is disposed below the trenches at a distance from the bottom surface of the trenches. Each connection region connects the body region and the bottom region, extends parallel to the trenches, and is disposed at intervals in a direction orthogonal to the direction in which the trenches extend.

[0003] When the semiconductor device of Patent Document 1 is turned off, a depletion layer extends from the bottom region into the drift region. The depletion layer extending from the bottom region into the drift region suppresses the electric field concentration at the lower end of the trenches.

[0004] In the semiconductor device of Patent Document 1, a parasitic pn diode (hereinafter referred to as a body diode) is formed by the p-type contact region and body region and the n-type drift region. In the operation of the semiconductor device, when a forward bias voltage is applied to the body diode, the body diode turns on and holes flow from the contact region through the body region into the drift region. Then, when the voltage applied to the body diode switches to a reverse bias, in the process of the body diode turning off, the holes accumulated in the drift region flow through the body region to the contact region. That is, a recovery current flows.

[0005] In the semiconductor device of Patent Document 1, a bottom region connected to the body region via a connection region is provided inside the drift region. Therefore, when reverse-biased, holes accumulated in the drift region easily flow from the drift region into the bottom region, and most of the holes flow into the body region via the bottom region and the connection region.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] In the semiconductor device of Patent Document 1, when the semiconductor device is turned on, the depletion layer that has spread from the connection region into the drift region contracts. Until the depletion layer completely contracts, the path through which the main current of the semiconductor device flows is restricted by the depletion layer. In the semiconductor device of Patent Document 1, since the connection regions are densely arranged, the on-resistance is high immediately after the semiconductor device is turned on.

[0008] If the connection regions are sparsely arranged to reduce the on-resistance, when the voltage applied to the body diode switches to reverse bias, the current density becomes high at each connection region when holes accumulated in the drift region flow toward the body region. Therefore, the electrical resistance when the recovery current flows increases, and the temperature of the semiconductor device rises. As a result, the switching loss increases.

[0009] This specification provides a technique for reducing switching loss while reducing on-resistance.

Means for Solving the Problems

[0010] The semiconductor devices (10, 100, 200, 300) disclosed in this specification include a semiconductor substrate (12) having an element region (62) and a peripheral region (64) disposed around the element region, and are provided on the upper surface (12a) of the semiconductor substrate. Each of them extends in a first direction on the upper surface and is arranged at intervals in a second direction orthogonal to the first direction on the upper surface. A plurality of trenches (22), a gate insulating film (24) covering the inner surface of each trench, and a gate electrode (26) disposed in each trench and insulated from the semiconductor substrate by the gate insulating film. The element region is exposed on the upper surface of the semiconductor substrate, and an n-type source region (30) in contact with the gate insulating film in each trench, a p-type contact region (31) exposed on the upper surface of the semiconductor substrate, a p-type body region (32) in contact with the gate insulating film in each trench below the source region and in contact with the contact region, an n-type drift region (34) in contact with the gate insulating film in each trench below the body region and separated from the source region by the body region, a p-type bottom region (36) disposed at the lower part of the trench at a distance from the bottom surface of the trench and surrounded by the drift region around it, and a plurality of p-type connection regions (38) each connecting the body region and the bottom region, each extending in the first direction and arranged at intervals in the second direction. The element region has an outer portion (62a) located at both ends of the element region in the second direction and a central portion (62b) disposed between the outer portions. The interval in the second direction of the connection regions in the outer portion is wider than the interval in the second direction of the connection regions in the central portion.

[0011] In this semiconductor device, in the direction in which the element region and the connection regions are arranged, the element region has an outer portion located at both ends of the element region and a central portion disposed between the outer portions. And the interval between the connection regions in the outer portion is wider than the interval between the connection regions in the central portion. Since the interval between the connection regions is wide in the outer portion, the on-resistance is low. Therefore, the on-resistance of the entire element region can be reduced. Further, the outer portion is adjacent to the peripheral region. In the peripheral region, it is difficult to apply a voltage to the body diode, so it is difficult for holes to accumulate in the drift region during forward bias. That is, since almost no holes flow into the outer portion from the peripheral region, the density of holes accumulated in the drift region during forward bias is low in the outer portion. Therefore, the recovery current is small in the outer portion, and even if the interval between the connection regions in the outer portion is widened, the temperature of the semiconductor device is unlikely to rise. For this reason, the switching loss of the entire element region is small. As described above, in this semiconductor device, the switching loss can be reduced while reducing the on-resistance.

Brief Description of the Drawings

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Mode for Carrying Out the Invention

[0013] In a semiconductor device according to an example disclosed in this specification, the interval in the second direction of the connection region in the outer portion may become wider as it approaches the end portion of the element region.

[0014] The amount of holes accumulated in the drift region during forward biasing of the body diode decreases as it approaches the end portion of the element region. In the above configuration, by widening the interval of the connection region as it approaches the end portion of the element region, reduction of on-resistance and reduction of switching loss can be more preferably achieved.

[0015] In a semiconductor device according to an example disclosed in this specification, each of the bottom regions may extend in the second direction and be arranged at intervals in the first direction.

[0016] In such a configuration, the direction in which the bottom region extends and the direction in which the connection region extends intersect. Therefore, for example, compared with a configuration in which the bottom region and the connection region extend in parallel, the bottom region and the connection region can be more reliably connected.

[0017] In a semiconductor device according to an example disclosed in this specification, the outer portion may further include a plurality of p-type connection auxiliary regions each connecting the body region and the bottom region and arranged at intervals in the first direction.

[0018] In such a configuration, in the outer portion, when the body diode is reverse-biased, in addition to the connection region, holes flow from the bottom region to the body region through the connection auxiliary region. Since the holes can flow branching into many paths, the switching loss can be further reduced. Further, since the connection auxiliary regions are arranged at intervals in the first direction, the range of the depletion layer extending from the connection auxiliary region into the drift region is narrow, and it is difficult to limit the path of the main current when the semiconductor device is turned on. Therefore, an increase in the on-resistance can be suppressed.

[0019] In a semiconductor device according to an example disclosed in this specification, the interval in the second direction of the trench in the outer portion may be narrower than the interval in the second direction of the trench in the central portion.

[0020] In such a configuration, since the channel density in the outer portion is high, the channel resistance (that is, the on-resistance) can be reduced.

[0021] (Example 1) Figs. 1 to 4 show a semiconductor device 10 of Example 1. The semiconductor device 10 is a MOSFET (Metal - Oxide - Semiconductor Field - Effect Transistor). As shown in Fig. 1, the semiconductor device 10 has a semiconductor substrate 12. The semiconductor substrate 12 has an element region 62 and a peripheral region 64. In the semiconductor substrate 12 of the element region 62, a MOSFET structure is formed. The peripheral region 64 is arranged around the element region 62. Although not shown, in the semiconductor substrate 12 of the peripheral region 64, a peripheral breakdown voltage structure such as a guard ring is formed. The semiconductor substrate 12 is made of SiC (silicon carbide). However, the material of the semiconductor substrate 12 is not particularly limited, and for example, other semiconductor materials such as Si (silicon) and GaN (gallium nitride) may be used. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x - direction, a direction parallel to the semiconductor substrate 12 and perpendicular to the x - direction is referred to as the y - direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z - direction.

[0022] As shown in FIG. 1, a plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12 within the element region 62. Each trench 22 extends long along the y direction. Each trench 22 extends parallel to each other. Each trench 22 is arranged at intervals in the x direction. FIG. 2 is an enlarged view including the x-direction boundary between the element region 62 and the peripheral region 64 of FIG. 1. In FIGS. 1 and 2, illustration of the configuration (insulating film, electrode, etc.) on the upper surface 12a of the semiconductor substrate 12 is omitted. As shown in FIGS. 2 to 4, a gate insulating film 24 and a gate electrode 26 are disposed in each trench 22. The gate insulating film 24 covers the inner surface of each trench 22. The gate electrode 26 is disposed inside each trench 22. Each gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24.

[0023] As shown in FIGS. 3 and 4, the upper surface of each gate electrode 26 is covered by an interlayer insulating film 28. Also, in the peripheral region 64, substantially the entire upper surface 12a of the semiconductor substrate 12 is covered by an insulating film 65. An upper electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 at a portion where the interlayer insulating film 28 is not provided within the element region 62. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A lower electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in contact with substantially the entire lower surface 12b of the semiconductor substrate 12.

[0024] The element region 62 is provided with a plurality of source regions 30, a plurality of contact regions 31, a body region 32, a drift region 34, a drain region 35, a plurality of bottom regions 36, and a plurality of connection regions 38.

[0025] Each source region 30 is an n-type region. Each source region 30 is provided at a position exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 makes an ohmic contact with the upper electrode 70. Each source region 30 is in contact with the gate insulating film 24 in the trench 22 on the side surface of the trench 22.

[0026] Each contact region 31 is a p-type region. Each contact region 31 is provided at a position exposed on the upper surface 12a of the semiconductor substrate 12. Each contact region 31 is disposed at a position sandwiched between two source regions 30. Each contact region 31 is in ohmic contact with the upper electrode 70.

[0027] The body region 32 is a p-type region. The body region 32 has a lower p-type impurity concentration than the contact region 31. The body region 32 is in contact with the source region 30 and the contact region 31 from below. The body region 32 is in contact with the gate insulating film 24 in each trench 22 below the source region 30. The body region 32 is disposed across from the element region 62 into the peripheral region 64.

[0028] The drift region 34 is an n-type region. The drift region 34 is disposed below the body region 32. The drift region 34 is in contact with the body region 32 from below. The drift region 34 is in contact with the gate insulating film 24 in each trench 22 below the body region 32. The drift region 34 is separated from the source region 30 by the body region 32. The drift region 34 is disposed across from the element region 62 into the peripheral region 64.

[0029] The drain region 35 is an n-type region. The drain region 35 is disposed below the drift region 34. The drain region 35 has a higher n-type impurity concentration than the drift region 34. The drain region 35 is in contact with the drift region 34 from below. The drain region 35 is exposed on the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72 on the lower surface 12b of the semiconductor substrate 12. The drain region 35 is disposed across from the element region 62 into the peripheral region 64.

[0030] Each bottom region 36 is a p-type region. Each bottom region 36 extends in a direction (x direction) orthogonal to the trench 22. As shown in FIG. 2, the bottom regions 36 are arranged at intervals in the y direction. Each bottom region 36 is disposed below the trench 22 at a distance from the lower surface of the trench 22. The periphery of each bottom region 36 is surrounded by the drift region 34. Each bottom region 36 extends from the element region 62 to the peripheral region 64.

[0031] Each connection region 38 is a p-type region. As shown in FIG. 2, each connection region 38 extends in parallel with each trench 22 (that is, in the y direction). The connection regions 38 are arranged at intervals in a direction orthogonal to each trench 22. Each connection region 38 is disposed in the range between two trenches 22 when viewed from above. As shown in FIG. 3, each connection region 38 connects the body region 32 and the bottom region 36. The connection region 38 is also disposed in the peripheral region 64.

[0032] As described above, each bottom region 36 is connected to the body region 32 via each connection region 38. For this reason, each bottom region 36 is connected to the upper electrode 70 via the connection region 38, the body region 32, and the contact region 31. Therefore, the potential of each bottom region 36 is substantially equal to the potential of the upper electrode 70.

[0033] As shown in FIG. 1, the element region 62 has two outer portions 62a and a central portion 62b. The outer portions 62a are located at both ends of the element region 62 in the x direction. In FIGS. 2 to 4, only one end of the element region 62 in the x direction is illustrated, but the outer portion 62a is also located at the other end of the element region 62 in the x direction. The central portion 62b is disposed between the two outer portions 62a.

[0034] As shown in FIG. 3, in the central portion 62b, the connection regions 38 are provided in each of the ranges between the plurality of trenches 22. That is, in the central portion 62b, the connection regions 38 and the trenches 22 are alternately arranged along the x direction. On the other hand, in the outer portion 62a, the connection region 38 is not provided in the range between the two trenches 22. In the peripheral region 64, the connection regions 38 are provided at the same interval as in the central portion 62b. Therefore, the interval d1 between the connection regions 38 in the outer portion 62a is wider than the interval d2 between the connection regions 38 in the central portion 62b. Although not shown, the interval between the connection regions 38 is similarly widened in the other outer portion 62a. The interval between two adjacent trenches 22 is substantially equal in the outer portion 62a and the central portion 62b.

[0035] When the semiconductor device 10 is in use, a potential higher than that of the upper electrode 70 is applied to the lower electrode 72. When a voltage equal to or higher than the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in the range in contact with the gate insulating film 24, and the semiconductor device 10 is turned on. When the voltage applied to the gate electrode 26 is lowered below the gate threshold, the channel disappears and the semiconductor device 10 is turned off.

[0036] When the semiconductor device 10 is off, the potential of the lower electrode 72 is much higher than the potential of the upper electrode 70. In this state, the drift region 34 has a potential close to the lower electrode 72. Also, as described above, the bottom region 36 has a potential substantially equal to that of the upper electrode 70. Therefore, a high reverse voltage is applied to the pn junction at the interface between the drift region 34 and the bottom region 36. Accordingly, the depletion layer widely spreads from each bottom region 36 into the drift region 34. Thereby, the electric field concentration near the lower end of the trench 22 is suppressed, and the breakdown voltage of the semiconductor device 10 is ensured. Also, a reverse voltage is applied to the pn junction at the interface between the connection region 38 and the drift region 34. For this reason, the depletion layer also spreads from the connection region 38 into the drift region 34.

[0037] When the semiconductor device 10 is turned on, holes are supplied from the upper electrode 70 to each bottom region 36 via the contact region 31, the body region 32, and the connection region 38. As a result, the depletion layer that has spread from the connection region 38 and the bottom region 36 into the drift region 34 contracts. Until holes are supplied to the connection region 38 and the bottom region 36, the depletion layer spreads from the connection region 38 and the bottom region 36 into the drift region 34. Therefore, immediately after the semiconductor device 10 is turned on, the path of the main current is restricted by the depletion layer. However, in this embodiment, in the outer portion 62a of the element region 62, the interval d1 of the connection region 38 is widened. For this reason, in the outer portion 62a, a relatively wide range where the drift region 34 is not depleted exists, and even immediately after the semiconductor device 10 is turned on, a wide range of the drift region 34 (particularly, the drift region 34 located between the trenches 22) can be used as the path of the main current. Therefore, in the semiconductor device 10 of this embodiment, the on-resistance of the entire element region 62 can be reduced.

[0038] Here, inside the semiconductor substrate 12, a parasitic pn diode (hereinafter referred to as a body diode) is formed by the p-type contact region 31 and body region 32, and the n-type drift region 34 and drain region 35. In the operation of the semiconductor device 10, a potential higher than that of the lower electrode 72 may be applied to the upper electrode 70. When the upper electrode 70 becomes a higher potential (forward bias) than the lower electrode 72, the body diode is turned on. That is, holes flow into the drift region 34 from the upper electrode 70 via the contact region 31 and the body region 32.

[0039] Thereafter, when the lower electrode 72 switches to a higher potential (reverse bias) than the upper electrode 70, holes accumulated in the drift region 34 flow through the body region 32 and the contact region 31 to the upper electrode 70 in the process of turning off the body diode. That is, a recovery current flows. In the semiconductor device 10, a plurality of bottom regions 36 connected to the body region 32 via connection regions 38 are provided inside the drift region 34. Therefore, during reverse bias, holes accumulated in the drift region 34 easily flow from the drift region 34 into the bottom regions 36, and most of the holes flow through the bottom regions 36 and the connection regions 38 to the body region 32.

[0040] In this embodiment, the interval d2 between the connection regions 38 at the central portion 62b of the element region 62 is narrow. That is, at the central portion 62b, the connection regions 38 are densely arranged. Therefore, there are many paths for holes to flow from the bottom regions 36 to the body region 32, and the holes are quickly discharged to the upper electrode 70. Accordingly, the switching loss generated at the central portion 62b is small, and the temperature rise of the central portion 62b is suppressed. On the other hand, the interval d1 between the connection regions 38 at the outer portion 62a of the element region 62 is wide. Therefore, there are few paths for holes to flow from the bottom regions 36 to the body region 32. However, the outer portion 62a is adjacent to the peripheral region 64. Since there is no contact region 31 in the peripheral region 64, it is difficult for holes to accumulate in the drift region 34 of the peripheral region 64 during forward bias. Therefore, in the outer portion 62a, the density of holes accumulated in the drift region 34 during forward bias is lower than that at the central portion 62b. Accordingly, the recovery current in the outer portion 62a is small, and even though the interval d1 between the connection regions 38 in the outer portion 62a is wide, the density of the recovery current flowing through each connection region 38 does not become so high. Therefore, the switching loss generated in the outer portion 62a is small, and the temperature rise of the outer portion 62a is suppressed. Thus, in this embodiment, when the recovery current flows, the temperature rise in the entire element region 62 is suppressed, and the switching loss is suppressed.

[0041] Note that, as described above, when the semiconductor device 10 is turned off, a depletion layer spreads from the body region 32, the connection region 38, and the bottom region 36 to the drift region 34. As a result, substantially the entire drift region 34 is depleted. When a high voltage is applied to the lower electrode 72 with the semiconductor element 10 turned off, an avalanche current flows from the drift region 34 to the upper electrode 70 through the bottom region 36, the connection region 38, the body region 32, and the contact region 31. In the central portion 62b, since the interval of the connection regions 38 is narrow, the density of the avalanche current flowing through each connection region 38 becomes low. As a result, the temperature rise in the central portion 62b is suppressed. Also, in the outer portion 62a, since the interval of the connection regions 38 is wide, the density of the avalanche current flowing through each connection region 38 becomes high. However, since the outer portion 62a is adjacent to the outer peripheral portion 64, the outer portion 62a has high heat dissipation. Therefore, the temperature rise in the outer portion 62a is suppressed. Thus, when the avalanche current flows, the temperature rise of each of the central portion 62b and the outer portion 62a is suppressed. As described above, in this embodiment, when the avalanche current flows, the temperature rise in the entire element region 62 is suppressed. Therefore, the semiconductor device 10 has a high avalanche withstand voltage.

[0042] Also, during the operation of the semiconductor device 10, the semiconductor substrate 12 generates heat, but the outer portion 62a of the element region 62 allows heat to escape more easily than the central portion 62b. Also, the outer portion 62a is adjacent to the peripheral region 64 where the main current does not flow. For this reason, the outer portion 62a is less likely to heat up compared to the central portion 62b, and the temperature of the outer portion 62a is lower than the temperature of the central portion 62b. Therefore, even if the temperature rises in the outer portion 62a, the influence is small. As described above, in this semiconductor device 10, it is possible to suppress an increase in switching loss and a decrease in avalanche withstand voltage while reducing the on-resistance.

[0043] Also, in this embodiment, since the direction (x direction) in which the bottom region 36 extends and the direction (y direction) in which the connection region 38 extends intersect, for example, compared to a configuration in which the bottom region 36 and the connection region 38 extend in parallel, the bottom region 36 and the connection region 38 can be more reliably connected.

[0044] (Example 2) In the semiconductor device 100 of Example 2, the configuration of the connection region 38 is different from that of Example 1. In Example 2, the interval of the connection regions 38 in the outer portion 62a becomes wider toward the end of the element region 62. As shown in FIG. 5, in this embodiment, nine trenches 22 are arranged in the outer portion 62a. Also, four connection regions 38 are arranged in the outer portion 62a. In Example 2, the width of the outer portion 62a in the x direction is wider than that in Example 1. Hereinafter, for convenience, the connection regions 38 are described in order from the connection region 38 arranged most outward (that is, closest to the peripheral region 64) toward the central portion 62b as connection regions 38a, 38b, 38c, and 38d. As shown in FIG. 5, the interval d3 between the connection region 38a and the connection region 38b is wider than the interval d4 between the connection region 38b and the connection region 38c. The interval d4 is wider than the interval d5 between the connection region 38c and the connection region 38d. Also, the intervals d3, d4, and d5 are wider than the interval d6 of the connection regions 38 in the central portion 62b.

[0045] Four trenches 22 are arranged between the connection region 38a and the connection region 38b, three trenches 22 are arranged between the connection region 38b and the connection region 38c, and two trenches 22 are arranged between the connection region 38c and the connection region 38d. The interval between two adjacent trenches 22 is substantially equal in the outer portion 62a and the central portion 62b.

[0046] The amount of holes accumulated in the drift region 34 when a forward bias voltage is applied to the body diode decreases toward the end of the element region 62. In the semiconductor device 100 of Example 2, in the outer portion 62a, the interval of the connection regions 38 gradually becomes wider from the central portion 62b toward the peripheral region 64. In Example 2, since the connection regions 38 are arranged more sparsely than in Example 1, the on-resistance can be further reduced. Also, since the intervals d3 to d5 of the connection regions 38 are adjusted according to the distribution of the amount of holes accumulated in the drift region 34, the switching loss can be efficiently reduced.

[0047] (Example 3) In the semiconductor device 200 of Example 3, compared with Example 1, it is different in that a plurality of p-type connection auxiliary regions 39 are further provided in the outer portion 62a. As shown in FIGS. 6 and 7, each connection auxiliary region 39 is arranged in the range between two trenches 22 in the outer portion 62a. As shown in FIG. 6, the connection auxiliary regions 39 are arranged at intervals in the y direction. As shown in FIG. 7, each connection auxiliary region 39 connects the body region 32 and the bottom region 36. As shown in FIG. 8, the connection auxiliary region 39 is not arranged in the cross section where the bottom region 36 is not provided.

[0048] In Example 3, when a reverse bias voltage is applied to the body diode in the outer portion 62a, in addition to the connection region 38, holes flow from the bottom region 36 to the body region 32 through the connection auxiliary region 39. In Example 3, since holes can flow branched in more paths than in Example 1, the switching loss can be further reduced. Further, the connection auxiliary regions 39 are arranged at intervals in the y direction. Specifically, as shown in FIGS. 8 and 9, the connection auxiliary regions 39 are arranged only in the range directly above the bottom region 36. For this reason, in the state where the semiconductor device 200 is off, the depletion layer extending from the connection auxiliary region 39 to the drift region 34 does not spread over a wide range in the drift region 34. Therefore, even if the connection auxiliary region 39 exists, it is difficult to limit the path of the main current when the semiconductor device 200 is turned on. Further, the connection auxiliary region 39 is arranged only in the range directly above the bottom region 36 that does not function as a path of the main current when the semiconductor device 200 is turned on. Therefore, even if the connection auxiliary region 39 exists, the on-resistance hardly increases. As described above, in the semiconductor device 200 of Example 3, the switching loss can be further reduced while suppressing an increase in the on-resistance.

[0049] (Example 4) In the semiconductor device 300 of Example 4, the interval between the trenches 22 in the outer portion 62a is different from that in Example 1. As shown in FIG. 9, in Example 4, in the outer portion 62a, three trenches 22 are arranged in the range between the two connection regions 38. The interval D1 between the trenches 22 in the outer portion 62a is narrower than the interval D2 between the trenches 22 in the central portion 62b. As shown in FIG. 10, a source region 30, a contact region 31, a body region 32, and a drift region 34 are respectively provided in the semiconductor region between two adjacent trenches 22 in the outer portion 62a.

[0050] In Example 4, since the interval D1 between the trenches 22 in the outer portion 62a is narrow (that is, the trenches 22 are densely arranged), the channel density of the outer portion 62a is higher than that in Example 1. Therefore, in Example 4, the channel resistance (that is, the on-resistance) can be further reduced. In this embodiment as well, since the interval between the connection regions 38 in the outer portion 62a is wider than the interval between the connection regions 38 in the central portion 62b, it is difficult to limit the path of the main current in the outer portion 62a. For this reason, even if the interval D1 between the trenches 22 is narrowed in the outer portion 62a, the on-resistance caused by the presence of the connection regions 38 hardly increases.

[0051] As described above, the embodiments have been described in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. Hereinafter, modifications of the above-described examples will be described.

[0052] (Modification example) In each of the above-described embodiments, the connection region 38 was disposed in the range between the trenches 22. That is, the connection region 38 was disposed at an interval from the trenches 22. However, for example, as shown in FIG. 11, the connection region 38 may be disposed at a position in contact with the side surface of the trench 22. The connection region 38 may be in contact with the gate insulating film 24 in the trench 22 below the body region 32. The connection region 38 may extend in the y direction along the side surface of the trench 22. Also, in this modified example, the contact region 31 may be disposed at a position in contact with the side surface of the trench 22. The contact region 31 may be in contact with the gate insulating film 24 in the trench 22 on the side surface of the trench 22.

[0053] Also, in the above-described embodiment, the bottom region 36 extended in a direction orthogonal to the trench 22. However, as shown in FIG. 12, the bottom region 36 may extend parallel (y direction) to the trench 22. The bottom region 36 may extend along the bottom surface of the trench at an interval from the bottom surface of the trench 22. The bottom region 36 may be disposed at an interval in a direction orthogonal (x direction) to the trench 22.

[0054] The technical elements described in this specification or the drawings exhibit technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology exemplified in this specification or the drawings achieves a plurality of purposes simultaneously, and has technical utility by achieving one of those purposes itself.

Description of Reference Numerals

[0055] 10, 100, 200, 300: Semiconductor device 12: Semiconductor substrate 12a: Upper surface 12b: Lower surface 22: Trench 24: Gate insulating film 26: Gate electrode 30: Source region 31: Contact region 32: Body region 34: Drift region 35: Drain region 36: Bottom region 38: Connection region 39: Connection auxiliary region 62: Element region 62a: Outer part 62b: Central part 64: Peripheral region

Claims

1. A semiconductor substrate (12) having an element region (62) and a peripheral region (64) disposed around the element region, a plurality of trenches (22) provided on the upper surface (12a) of the semiconductor substrate, each extending in a first direction on the upper surface and arranged at intervals in a second direction orthogonal to the first direction on the upper surface, a gate insulating film (24) covering the inner surface of each trench, a gate electrode (26) disposed in each trench and insulated from the semiconductor substrate by the gate insulating film, comprising: wherein the element region includes an n-type source region (30) exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film in each trench, a p-type contact region (31) exposed on the upper surface of the semiconductor substrate, a p-type body region (32) in contact with the gate insulating film in each trench below the source region and in contact with the contact region, an n-type drift region (34) in contact with the gate insulating film in each trench below the body region and separated from the source region by the body region, a p-type bottom region (36) disposed at a lower portion of the trench at a distance from the bottom surface of the trench and surrounded by the drift region, a plurality of p-type connection regions (38) each connecting the body region and the bottom region, each extending in the first direction and arranged at intervals in the second direction, comprising: wherein the element region has an outer portion (62a) located at both ends of the element region in the second direction and a central portion (62b) disposed between the outer portions, and the interval in the second direction of the connection regions in the outer portion is wider than the interval in the second direction of the connection regions in the central portion. A semiconductor device (10, 100, 200, 300).

2. The semiconductor device according to claim 1, wherein the interval in the second direction of the connection regions in the outer portion becomes wider toward the end of the element region.

3. The semiconductor device according to claim 1 or 2, wherein the bottom region extends in the second direction and is arranged at intervals in the first direction.

4. The semiconductor device according to claim 3, further comprising a plurality of p-type connection auxiliary regions (39) in which the outer portions each connect the body region and the bottom region and are arranged at intervals in the first direction.

5. The semiconductor device according to any one of claims 1 to 4, wherein the interval in the second direction of the trench in the outer portion is narrower than the interval in the second direction of the trench in the central portion.

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