Semiconductor device

Abstract

To provide a semiconductor device which can be improved in withstanding voltage.SOLUTION: A semiconductor device comprises a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, a plurality of fifth semiconductor regions of the second conductivity type, a plurality of sixth semiconductor regions of the second conductivity type, and a second electrode. The first semiconductor region includes a first region and a second region. The fourth semiconductor region is provided between the first region and the gate electrode. The plurality of fifth semiconductor regions are located around the fourth semiconductor region along a first surface, and are separated from each other in a second direction from the first region toward the second region. The plurality of sixth semiconductor regions are located around the second semiconductor region along the first surface, and are separated from each other in the second direction. Each of the plurality of sixth semiconductor regions has an impurity concentration of the second conductivity type lower than that of each of the plurality of fifth semiconductor regions.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET) are used in applications such as power conversion. It is desirable that the breakdown voltage of the semiconductor device is high.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of improving the breakdown voltage.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, a plurality of fifth semiconductor regions of the second conductivity type, a plurality of sixth semiconductor regions of the second conductivity type, and a second electrode. The first semiconductor region is provided on the first electrode and includes a first region and a second region provided around the first region. The second semiconductor region is provided on the first region. The third semiconductor region is provided on a part of the second semiconductor region. The gate electrode faces the second semiconductor region via a gate insulating layer in a direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The fourth semiconductor region is provided between the first region and the gate electrode. The plurality of fifth semiconductor regions are located around the fourth semiconductor region along a first plane perpendicular to the first direction and are separated from each other in a second direction from the first region toward the second region. The plurality of sixth semiconductor regions are located around the second semiconductor region along the first plane and are separated from each other in the second direction. Each of the plurality of sixth semiconductor regions has a lower impurity concentration of the second conductivity type than each of the plurality of fifth semiconductor regions. The second electrode is provided on the second semiconductor region and the third semiconductor region.

Brief Description of the Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In the following description and drawings, n + , n, n - and p + , p, p - notations represent the relative levels of the respective impurity concentrations. That is, a notation with a “+” indicates that the impurity concentration is relatively higher than a notation without either “+” or “-”, and a notation with a “-” indicates that the impurity concentration is relatively lower than a notation without any of them. These notations represent the relative levels of the net impurity concentration after the p-type and n-type impurities compensate each other when both p-type and n-type impurities are included in each region. Regarding each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] (First Embodiment) FIG. 1 and FIG. 3 are plan views showing a semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along line A1 - A2 of FIGS. 1 and 3. FIG. 4 is a cross-sectional view taken along line B1 - B2 of FIGS. 1 and 3. In FIG. 3, n + -type source region 3, p + -type contact region 9b, gate electrode 10, insulating layer 15, and source electrode 22 are omitted. The semiconductor device according to the first embodiment is a MOSFET. As shown in FIGS. 1 to 4, the semiconductor device 100 according to the first embodiment includes an n - -type (first conductivity type) drift region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 (second semiconductor region), an n + -type source region 3 (third semiconductor region), a p + -type semiconductor region 4 (fourth semiconductor region), a p + -type semiconductor region 5 (an example of a fifth semiconductor region), a p - -type semiconductor region 6 (an example of a sixth semiconductor region), a p-type semiconductor region 7 (an example of a seventh semiconductor region), an n + -type drain region 9a, a p + -type contact region 9b, an n + -type semiconductor region 9c, a gate electrode 10, a drain electrode 21 (first electrode), and a source electrode 22 (second electrode).

[0009] For the description of the embodiment, an XYZ orthogonal coordinate system is used. The direction from the drain electrode 21 toward the n - -type drift region 1 is defined as the Z direction (first direction). One direction orthogonal to the Z direction is defined as the X direction. The direction orthogonal to both the X direction and the Z direction is defined as the Y direction. Also, here, the direction from the drain electrode 21 toward the n - -type drift region 1 is called "up", and the opposite direction is called "down". These directions are based on the relative positional relationship between the drain electrode 21 and the n - -type drift region 1 and are independent of the direction of gravity.

[0010] As shown in FIG. 1, a source electrode 22 is provided on the upper surface of the semiconductor device 100. The periphery of the source electrode 22 is covered by an insulating layer 15.

[0011] As shown in FIGS. 2 and 4, a drain electrode 21 is provided on the lower surface of the semiconductor device 100. n + The n-shaped drain region 9a is provided above the drain electrode 21 and is electrically connected to the drain electrode 21. n - The n-shaped drift region 1 is n + provided above the n-shaped drain region 9a. n - The n-shaped drift region 1 is n + electrically connected to the drain electrode 21 via the n-shaped drain region 9a.

[0012] As shown in FIGS. 1 to 4, n - the n-shaped drift region 1 includes a first region R1 and a second region R2. The second region R2 is provided around the first region R1 along the X-Y plane (the first plane). The first region R1 corresponds to the element region of the semiconductor device 100. The second region R2 corresponds to the termination region of the semiconductor device 100.

[0013] As shown in FIG. 2, the p-type base region 2 is provided above the first region R1. n + The n-shaped source region 3 and the p + -shaped contact region 9b are selectively provided above the p-type base region 2.

[0014] The gate electrode 10 faces the p-type base region 2 via the gate insulating layer 11 in the X direction. In the illustrated example, the gate electrode 10 further n - faces a part of the n-shaped drift region 1 and a part of the n + -shaped source region 3 via the gate insulating layer 11. p + The p-shaped semiconductor region 4 is provided between the n-shaped drift region 1 and the gate electrode 10 in the Z direction. p - The p-type impurity concentration of the p-shaped semiconductor region 4 is higher than that of the p-type base region 2. p + The p-shaped semiconductor region 4 is away from the p-type base region 2. + The p-shaped semiconductor region 4 is away from the p-type base region 2.

[0015] As shown in the illustration, n- The n-type drift region 1 may include portions 1a and 1b with different n-type impurity concentrations. Portion 1b is provided between portion 1a and the p-type base region 2 in the Z direction and is aligned with the gate electrode 10 in the X direction. The n-type impurity concentration of portion 1b is higher than that of portion 1a.

[0016] Portion 1b, n + type source region 3, p + type semiconductor region 4, p + type contact region 9b, and each of the gate electrodes 10 extends in the Y direction and is provided in plurality in the X direction. As shown in FIGS. 2 to 4, the p-type base region 2 is provided between the gate electrodes 10 and around the plurality of gate electrodes 10.

[0017] As shown in FIGS. 1 and 2, the source electrode 22 is provided on the first region R1 and is located on the plurality of n + type source regions 3 and the plurality of p + type contact regions 9b. The source electrode 22 is electrically connected to the plurality of n + type source regions 3 and the plurality of p + type contact regions 9b. The p-type base region 2 is electrically connected to the source electrode 22 through the p + type contact region 9b. The gate electrode 10 is electrically separated from the source electrode 22 by the insulating layer 15.

[0018] As shown in FIG. 4, the p + type semiconductor region 5 is provided in the second region R2. As shown in FIGS. 3 and 4, the p - type semiconductor region 6, n + type semiconductor region 9c is provided on the second region R2. The p - type semiconductor region 6 is located around the p-type base region 2 along the X-Y plane. The p-type impurity concentration of the p - type semiconductor region 6 is lower than the p-type impurity concentration of the p-type base region 2. p -A plurality of p-type semiconductor regions 6 are provided in the direction from the first region R1 to the second region R2 (radial direction: second direction). The radial direction is parallel to the X-Y plane. Each p - -type semiconductor regions 6 are separated from each other, and the distance between adjacent p - -type semiconductor regions 6 increases in the radial direction.

[0019] p + -type semiconductor regions 5 are located around a plurality of p + -type semiconductor regions 4 along the X-Y plane. The p + -type impurity concentration of the p-type semiconductor region 5 may be the same as or different from the p-type impurity concentration of the p-type semiconductor region 4. The p + -type impurity concentration of the p-type semiconductor region 5 is higher than the p-type impurity concentration of the p-type base region 2 and higher than the p + -type impurity concentration of the p-type semiconductor region 6. The p - -type semiconductor region 5 is provided in a plurality in the radial direction, similar to the p + -type semiconductor region 6. Each p - -type semiconductor region 5 is separated from each other, and the distance between adjacent p + -type semiconductor regions 5 increases in the radial direction. Also, a plurality of p + -type semiconductor regions 6 are separated from a plurality of p - -type semiconductor regions 5 in the Z direction. + The n

[0020] -type semiconductor region 9c is located around a plurality of p + -type semiconductor regions 6 along the X-Y plane. The n - -type semiconductor region 9c is separated from a plurality of p + -type semiconductor regions 6 and is provided along the outer periphery of the semiconductor device 100. The n - -type impurity concentration of the n-type semiconductor region 9c is higher than the n-type impurity concentration of the portion 1b. A part of the portion 1b, a plurality of p + -type semiconductor regions 6 and n - -type semiconductor region 9c are provided with an insulating layer 15 thereon. That is, on the second region R2, a part of the portion 1b, a plurality of p + -type semiconductor regions 6 and n - -type semiconductor region 9c are provided with an insulating layer 15 thereon. +The p-type semiconductor region 9c is covered by the insulating layer 15.

[0021] As shown in FIG. 4, among the plurality of p + -type semiconductor regions 4, the p + -type semiconductor region 4a located at the X-direction end may be in contact with the p-type base region 2. In this case, the electrode 10a surrounded by the p + -type semiconductor region 4a may function as a gate electrode, or may not function as a gate electrode (for example, a floating electrode). The electrode 10a may be electrically connected to the gate electrode 10, or may be electrically separated from the gate electrode 10. Among the plurality of p + -type semiconductor regions 5, the p + -type semiconductor region 5a closest to the first region R1 may be in contact with the p + -type semiconductor region 4a. In this case, the p + -type semiconductor region 5a is electrically connected to the source electrode 22 through the p + -type semiconductor region 4a and the p-type base region 2. Among the plurality of p - -type semiconductor regions 6, the p - -type semiconductor region 6a closest to the first region R1 may be in contact with the p-type base region 2, or may be separated from the p-type base region 2.

[0022] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the drain electrode 21 with respect to the source electrode 22, a voltage equal to or higher than the threshold value is applied to the gate electrode 10. Thereby, a channel (inversion layer) is formed in the p-type base region 2, and the semiconductor device 100 is turned on. Electrons flow from the source electrode 22 through the channel to the n - -type drift region 1 and move toward the drain electrode 21. Thereby, a current flows through the first region R1. When the voltage applied to the gate electrode 10 becomes lower than the threshold value, the channel in the p-type base region 2 disappears, and the semiconductor device 100 turns off.

[0023] An example of the material of each component of the semiconductor device 100 will be described. n - -type drift region 1, p-type base region 2, n+ p-type source region 3 + p-type semiconductor region 4 + p-type semiconductor region 5 - n-type semiconductor region 6 + p-type drain region 9a + n-type contact region 9b, and + n-type semiconductor region 9c includes a semiconductor material. As the semiconductor material, silicon carbide, silicon, gallium nitride, or gallium arsenide can be used. As the n-type impurity, arsenic, phosphorus, or antimony can be used. As the p-type impurity, boron can be used.

[0024] The gate electrode 10 includes a conductive material such as polysilicon. The gate electrode 10 may be doped with an n-type or p-type impurity. The gate insulating layer 11 and the insulating layer 15 include an electrical insulating material. For example, the gate insulating layer 11 and the insulating layer 15 include silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 21 and the source electrode 22 include a metal such as titanium, tungsten, or aluminum.

[0025] Explain the advantages of the first embodiment. In the semiconductor device 100, an n - p-type semiconductor region 4 is provided between the n-type drift region 1 and the gate electrode 10. + By providing the p-type semiconductor region 4, when the semiconductor device 100 is off, the electric field concentration near the lower end of the gate insulating layer 11 can be alleviated, and the breakdown of the gate insulating layer 11 can be suppressed. On the other hand, when the p-type semiconductor region 4 is provided, an electric field concentration occurs between the n-type drift region 1 and the p-type semiconductor region 4. In order to increase the breakdown voltage of the semiconductor device 100, it is preferable that the electric field concentration near the p-type semiconductor region 4 can also be alleviated. + + - + +

[0026] In particular, in the semiconductor device 100 in which each semiconductor region includes silicon carbide, the breakdown electric field is higher than the breakdown electric field of an insulating material such as silicon oxide. Therefore, p + ​​​​​If the p-type semiconductor region 4 is not provided, when a high voltage is applied to the semiconductor device 100 in the off state, an excessive voltage is applied to the gate insulating layer 11, and the gate insulating layer 11 may be broken down. Therefore, in the semiconductor device 100 using silicon carbide, it is more desirable to provide the p + -type semiconductor region 4.

[0027] In the semiconductor device 100 according to the first embodiment, p + -type semiconductor regions 5 are provided around the p + -type semiconductor region 4. By providing the p + -type semiconductor region 5 in the second region R2 which is the terminal region, the electric field distribution can be expanded toward the outer periphery of the semiconductor device 100, and the electric field concentration near the p + -type semiconductor region 4 can be alleviated. Also, around the p-type base region 2, by providing a plurality of p - -type semiconductor regions 6 on the second region R2, the electric field concentration at the outer periphery of the p-type base region 2 can also be alleviated. In particular, in the semiconductor device 100, the p-type impurity concentration of the p + -type semiconductor region 5 is higher than the p-type impurity concentration of the p - -type semiconductor region 6. By increasing the p-type impurity concentration of the p + -type semiconductor region 5, at the position where the p + -type semiconductor region 4 is provided, the electric field distribution can be further expanded toward the outer periphery of the semiconductor device 100. As a result, the electric field concentration can be further alleviated, and the breakdown voltage of the semiconductor device 100 can be further increased.

[0028] Also, the p + -type semiconductor region 5 is located inside the semiconductor layer instead of on the surface of the semiconductor layer, and is not completely depleted when the semiconductor device 100 is in the off state. Therefore, when the semiconductor device 100 is in the off state, electric field concentration occurs near the p + -type semiconductor region 5. In other words, electric field concentration occurs at a location away from the interface between the semiconductor region (p - -type semiconductor region 6 or portion 1b) and the insulating layer 15). At the interface between the semiconductor region and the insulating layer 15, there are trap levels for carriers. When electric field concentration occurs near this interface, carriers accelerated by the electric field may be trapped, which may affect the electric field distribution in the second region R2. p + By providing the p-type semiconductor region 5, the electric field concentration near the interface between the semiconductor region and the insulating layer 15 can be suppressed. A plurality of p - The electric field distribution expanded toward the outer periphery of the semiconductor device 100 by the p-type semiconductor regions 6 can be stabilized, and fluctuations in the breakdown voltage of the semiconductor device 100 can be suppressed.

[0029] (First Modified Example) FIG. 5 is a cross-sectional view showing a part of a semiconductor device according to a first modified example of the first embodiment. The semiconductor device 110 according to the first modified example is different from the semiconductor device 100 in that it further includes a p-type semiconductor region 7. As shown in FIG. 5, the p-type semiconductor region 7 is provided in the second region R2 and is located around the gate electrode 10 in the X-Y plane. The p-type semiconductor region 7 is p + located above the p-type semiconductor region 5 and p - located below the p-type semiconductor region 6. The p-type semiconductor region 7 is p + formed in a plurality in the X direction and the Y direction, similar to the p-type semiconductor region 5 and the p - type semiconductor region 6. Each p-type semiconductor region 7 is separated from each other.

[0030] The p-type impurity concentration of the p-type semiconductor region 7 is lower than the p-type impurity concentration of the p + type semiconductor region 5 and higher than the p-type impurity concentration of the p - type semiconductor region 6. The p-type impurity concentration of the p-type semiconductor region 7 may be the same as or different from the p-type impurity concentration of the p-type base region 2. Also, at least one of the plurality of p-type semiconductor regions 7 may be in contact with the p-type base region 2. Any one of the plurality of p-type semiconductor regions 7 may be in contact with any one or a plurality of the p + type semiconductor regions 5 or any one or a plurality of the p - type semiconductor regions 6.

[0031] According to the first modification example, by providing a plurality of p-type semiconductor regions 7, the depletion layer is more likely to spread in the Z direction on the outer periphery of the p-type base region 2. Compared with the semiconductor device 100, the electric field strength in the Z direction on the outer periphery of the p-type base region 2 can be further reduced, and the breakdown voltage of the semiconductor device 110 can be further increased.

[0032] FIGS. 6(a) and 6(b) are plan views showing a part of the semiconductor device according to the first modification example of the first embodiment. FIGS. 6(a) and 6(b) show the planar structure at the position where the p-type semiconductor region 7 is provided. As shown in FIG. 6(a), each of the plurality of p-type semiconductor regions 7 may be continuously provided around the plurality of gate electrodes 10. As shown in FIG. 6(b), a plurality of p-type semiconductor regions 7 may be arranged in the circumferential direction around the plurality of gate electrodes 10. Also, for the p + type semiconductor region 5, similarly, each of the plurality of p + type semiconductor regions 5 may be continuously provided around the plurality of gate electrodes 10. Around the plurality of gate electrodes 10, a plurality of p + type semiconductor regions 5 may be arranged in the circumferential direction.

[0033] In the case of the structure shown in FIG. 6(a), compared with the structure shown in FIG. 6(b), the electric field distribution in the second region R2 can be made more stable, and the breakdown voltage of the semiconductor device 110 can be stabilized. In the case of the structure shown in FIG. 6(b), by changing the density of the p-type semiconductor regions 7 according to the electric field strength in the second region R2, the length of the second region R2 in the radial direction can be made shorter compared with the structure shown in FIG. 6(a). For example, in the vicinity of the corner of the p-type base region 2 when viewed from the Z direction shown in FIG. 6(b), the electric field strength is more likely to be higher than in other regions. By increasing the density of the p-type semiconductor regions 7 in the vicinity of the corner compared with the density of the p-type semiconductor regions 7 in other regions, the increase in the length of the second region R2 can be suppressed while improving the breakdown voltage of the semiconductor device 110.

[0034] (Second Embodiment) FIG. 7 is a cross-sectional view showing a part of the semiconductor device according to the second embodiment. The semiconductor device 200 according to the second embodiment shown in FIG. 7, when compared with the semiconductor device 100, has a p - type semiconductor region 6 replaced by a p - type semiconductor region 6b (another example of the sixth semiconductor region). The p - type semiconductor region 6b is provided around the p-type base region 2 along the X-Y plane and is in contact with the p-type base region 2. The p - type semiconductor region 6b includes a first portion 6b1 and a second portion 6b2. The p-type impurity concentration of the first portion 6b1 is higher than that of the second portion 6b2. The first portion 6b1 and the second portion 6b2 are alternately provided in the radial direction.

[0035] The p-type impurity concentration of each of the first portion 6b1 and the second portion 6b2 is lower than the p-type impurity concentration of the p-type base region 2 and lower than the p-type impurity concentration of the p + type semiconductor region 5. Also, in the illustrated example, the width of each first portion 6b1 becomes narrower as it goes in the radial direction so that the p-type impurity concentration per unit area of the p - type semiconductor region 6b including the first portion 6b1 and the second portion 6b2 decreases toward the outer periphery of the semiconductor device 200. The "width" corresponds to the length in the radial direction.

[0036] p - If the p-type impurity concentration per unit area of the p-type semiconductor region 6b decreases toward the outer periphery of the semiconductor device 200, the width of the second portion 6b2 may become narrower toward the outer periphery of the semiconductor device 200.

[0037] In order to improve the breakdown voltage of the semiconductor device 200, it is effective to suppress an increase in the local electric field strength in the second region R2. The gentler the gradient of the p-type impurity concentration in the radial direction in the region around the p-type base region 2, the more the local electric field concentration can be alleviated and the electric field strength at the location where the electric field is concentrated can be reduced. In the semiconductor device 200, the width of the first portion 6b1 having a relatively high p-type impurity concentration decreases as it goes in the radial direction. By the decrease in the width of the first portion 6b1, p -The p-type impurity concentration per unit area of the p-type semiconductor region 6b decreases as it goes in the radial direction. By increasing the number of the first portions 6b1 and reducing the difference in width between adjacent first portions 6b1, the gradient of the p-type impurity concentration per unit area can be made even gentler. According to the second embodiment, an increase in the electric field strength in the second region R2 can be suppressed, and the breakdown voltage of the semiconductor device 200 can be improved.

[0038] Also, in order to vary the p-type impurity concentration per unit area, there is a method of making the p-type impurity concentrations of the respective first portions 6b1 different. However, in this method, it is necessary to perform the ion implantation process by the number of the first portions 6b1 having different p-type impurity concentrations. A plurality of first portions 6b1 having different widths can be formed by one ion implantation using a mask. The width of each first portion 6b1 can be controlled by adjusting the aperture width of the mask. Similarly, a plurality of second portions 6b2 can be formed by one ion implantation using a mask. By changing the width of each first portion 6b1 to adjust the p-type impurity concentration per unit area, a p-type semiconductor region 6b with a gentle gradient of impurity concentration can be formed more easily. - type semiconductor region 6b can be formed more easily.

[0039] (First modification example) FIG. 8 is a cross-sectional view showing a part of a semiconductor device according to a first modification example of the second embodiment. A semiconductor device 210 according to the second modification example shown in FIG. 8 includes a p-type semiconductor region 5b (another example of the fifth semiconductor region) instead of the plurality of p-type semiconductor regions 5 when compared with the semiconductor device 200. + type semiconductor region 5 - type semiconductor region 5b is provided around a plurality of p-type semiconductor regions 4 along the X-Y plane. - type semiconductor regions 4. + The p-type impurity concentration of the p-type semiconductor region 5b is lower than the p-type impurity concentration of the p-type semiconductor region 4. - type semiconductor region 4 + type semiconductor region 4.

[0040] p -The p-type semiconductor region 5b includes a plurality of portions 5b1 and 5b2 having different p-type impurity concentrations. Portion 5b2 is located around portion 5b1 along the X-Y plane. The p-type impurity concentration of portion 5b2 is lower than that of portion 5b1. The thickness of portion 5b2 is smaller than the thickness of portion 5b1. "Thickness" corresponds to the length in the Z direction. In the illustrated example, p - The p-type semiconductor region 5b includes two portions 5b1 and 5b2 having different p-type impurity concentrations and thicknesses. p - The p-type semiconductor region 5b may include more portions having different p-type impurity concentrations and thicknesses.

[0041] p + Even when a p - type semiconductor region 5b is provided instead of the p + type semiconductor region 5, at the position where the p + type semiconductor region 4 is provided, the electric field distribution can be expanded toward the outer periphery of the semiconductor device 210, and p

[0042] However, p + for further alleviating the electric field concentration near the p - type semiconductor region 4, a p + type semiconductor region 5 provided in the semiconductor device 100 or 110 is preferable compared to the p + type semiconductor region 5b. Also, as described above, by providing the p

[0043] (Third Embodiment) FIG. 9 is a cross-sectional view showing a part of a semiconductor device according to the third embodiment. In the semiconductor device 300 according to the third embodiment shown in FIG. 9, in the second region R2, a p - type semiconductor region 5b, a p - type semiconductor region 6c (another example of the sixth semiconductor region), and a p + type semiconductor region 7a (another example of the seventh semiconductor region) are provided.

[0044] The p-type semiconductor region 5b of the semiconductor device 300 - is provided around the p-type semiconductor region 5b of the semiconductor device 210 - similarly, along the X-Y plane, a plurality of p-type + semiconductor regions 4 are provided around. + The p-type semiconductor region 7a is located around the gate electrode 10 in the X-Y plane. + The p-type semiconductor region 7a + is located above the p-type semiconductor region 5. + The p-type impurity concentration of the p-type semiconductor region 7a is higher than that of the p-type base region 2 and - higher than the p-type impurity concentration of the p-type semiconductor region 5b. + A plurality of p-type semiconductor regions 7a are provided in the X direction and the Y direction. Each p-type + semiconductor region 7a is separated from each other.

[0045] A plurality of p-type + one or more of the semiconductor regions 7a may be in contact with the p-type - semiconductor region 5b or the p-type base region 2. A plurality of p-type + semiconductor regions 7a may be separated from the p-type - semiconductor region 5b and the p-type base region 2.

[0046] p-type - semiconductor region 6c is provided along the X-Y plane around the p-type base region 2 and is in contact with the p-type base region 2. - The p-type semiconductor region 6c is a plurality of p-type + is located above the semiconductor region 7a. - The p-type semiconductor region 6c is a plurality of p-type + may be in contact with one or more of the semiconductor regions 7a, or may be separated from the plurality of p-type semiconductor regions 7. - The p-type impurity concentration of the p-type semiconductor region 6c is lower than that of the p-type base region 2 and lower than the p-type impurity concentration of the p-type semiconductor region 7.

[0047] p-type -The p-type semiconductor region 6c includes a plurality of portions 6c1 and 6c2 having different p-type impurity concentrations from each other. The portion 6c2 is located around the portion 6c1 along the X-Y plane. The p-type impurity concentration of the portion 6c2 is lower than the p-type impurity concentration of the portion 6c1. The thickness of the portion 6c2 is smaller than the thickness of the portion 6c1. p - The p-type semiconductor region 6c may include more portions having different p-type impurity concentrations and thicknesses from each other than in the illustrated example.

[0048] In the semiconductor device 300, p - between the p-type semiconductor region 5b and the p - type semiconductor region 6c, a plurality of p + type semiconductor regions 7a having a higher p-type impurity concentration than these semiconductor regions are provided. p + By providing the p-type semiconductor regions 7a, in the second region R2, the depletion layer is likely to spread in the Z direction. The electric field strength in the Z direction in the second region R2 can be reduced, and the breakdown voltage of the semiconductor device 300 can be further increased.

[0049] (First Modified Example) FIG. 10 is a cross-sectional view showing a part of a semiconductor device according to a first modified example of the third embodiment. The semiconductor device 310 according to the first modified example shown in FIG. 10 includes a plurality of p - type semiconductor regions 5 instead of the p-type semiconductor region 5b when compared with the semiconductor device 300. p + In the semiconductor device 310, the specific structure of the p + type semiconductor region 5 can be applied to the specific structure of the p + type semiconductor region 5 in the semiconductor devices 100, 110, or 200.

[0050] p + The p-type impurity concentration of the p-type semiconductor region 7a may be the same as or different from the p-type impurity concentration of the p + type semiconductor region 5. One or more of the plurality of p + type semiconductor regions 7a may be in contact with one or more of the plurality of p + type semiconductor regions 5, or may be separated from the plurality of p + type semiconductor regions 5.

[0051] p - Instead of the p-type semiconductor region 5b, a plurality of p + When the p-type semiconductor regions 5 are provided, as described above, the electric field concentration near the interface between the semiconductor region and the insulating layer 15 can be suppressed, and the breakdown voltage of the semiconductor device 310 can be made more stable.

[0052] (Second Modified Example) FIG. 11 is a cross-sectional view showing a part of a semiconductor device according to a second modified example of the third embodiment. The semiconductor device 320 according to the second modified example shown in FIG. 11 includes, compared with the semiconductor device 300, a p - Instead of the p-type semiconductor region 6c, a p + type semiconductor region 6d (another example of the sixth semiconductor region).

[0053] p + The p-type semiconductor region 6d is located around the p-type base region 2 along the X-Y plane. The p + type impurity concentration of the p-type semiconductor region 6d is higher than the p-type impurity concentration of the p-type base region 2. The p + type impurity concentration of the p-type semiconductor region 6d is the p + type impurity concentration of the p-type semiconductor region 7a may be the same or different. The p + type semiconductor regions 6d are provided in plurality in the X direction and the Y direction. Each p + type semiconductor region 6d is separated from each other, and the interval between adjacent p + type semiconductor regions 6d becomes wider toward the radial direction.

[0054] Of the plurality of p + type semiconductor regions 6d, the p + type semiconductor region 6d closest to the first region R1 may be in contact with the p-type base region 2 or may be separated from the p-type base region 2. Of the plurality of p + type semiconductor regions 6d, one or more may be in contact with one or more of the plurality of p + type semiconductor regions 7a or may be separated from the plurality of p + type semiconductor regions 7a.

[0055] p + The p-type impurity concentration in the p-type semiconductor region 6d is higher than that in the p-type base region 2 and higher than that in the p-type semiconductor region 5b. For example, when the semiconductor device 320 is turned off, the p-type semiconductor region 6d does not completely deplete. Therefore, when the semiconductor device 320 is turned off, electric field concentration occurs near the bottom of the p-type semiconductor region 6d, making avalanche breakdown more likely to occur. By making avalanche breakdown more likely to occur at specific locations, it is possible to suppress avalanche breakdown from occurring at unintended locations and damaging the semiconductor device 320. - than the p-type impurity concentration in the p-type semiconductor region 5b. For example, + the p-type semiconductor region 6d does not completely deplete when the semiconductor device 320 is turned off. Therefore, when the semiconductor device 320 is turned off, + electric field concentration occurs near the bottom of the p-type semiconductor region 6d, making avalanche breakdown more likely to occur. By making avalanche breakdown more likely to occur at specific locations, it is possible to suppress avalanche breakdown from occurring at unintended locations and damaging the semiconductor device 320.

[0056] (Third Modified Example) FIG. 12 is a cross-sectional view showing a part of a semiconductor device according to a third modified example of the third embodiment. The semiconductor device 330 according to the third modified example shown in FIG. 12 includes a p - -type semiconductor region 6b instead of the p - -type semiconductor region 6c when compared with the semiconductor device 310. The specific structure of the p - -type semiconductor region 6b in the semiconductor device 330 can apply the specific structure of the p - -type semiconductor region 6b in the semiconductor device 200.

[0057] (Fourth Modified Example) FIG. 13 is a cross-sectional view showing a part of a semiconductor device according to a fourth modified example of the third embodiment. The semiconductor device 340 according to the fourth modified example shown in FIG. 13 further includes a p - -type pillar region 8 (eighth semiconductor region) when compared with the semiconductor device 300. The p - -type pillar region 8 is provided in the n - -type drift region 1 and is located below the p + -type semiconductor region 4 and the p - -type semiconductor region 5b. The p - -type pillar region 8 is in contact with the p + -type semiconductor region 4 or the p - -type semiconductor region 5b. The n - -type drift region 1 is p -The n-shaped pillar regions 8 are arranged in the X direction and - further include the n-shaped pillar region 1c. - The n-shaped pillar region 1c and the p - The n-shaped pillar regions 8 are alternately provided in the X direction. Each - n-shaped pillar region 1c and each p - The n-shaped pillar regions 8 extend in the Y direction along the gate electrode 10.

[0058] n - The n-shaped pillar region 1c and the p - By alternately providing the n-shaped pillar regions 1c and the p - n-shaped pillar regions 8 in the X direction, when the semiconductor device 340 is off, - a depletion layer can be expanded in the X direction from the pn junction between the n-shaped pillar region 1c and the p-shaped pillar region 8. Thereby, the breakdown voltage of the semiconductor device 340 can be increased.

[0059] Here, an example in which a plurality of p - n-shaped pillar regions 8 are further provided in the structure of the semiconductor device 300 has been described. Not limited to this example, a plurality of p - n-shaped pillar regions 8 may be further provided in any of the semiconductor devices 100, 110, 200, 210, or 310 to 330. In any semiconductor device, - by providing a plurality of p

[0060] As described above, some embodiments of the present invention have been illustrated. However, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope. Also, the above-described embodiments can be implemented in combination with each other.

Explanation of Reference Numerals

[0061] 1: n -Rectangular drift region, 1a, 1b: parts, 1c: n - Rectangular pillar region, 2: p-shaped base region, 3: n + Rectangular source region, 4, 4a: p + Rectangular semiconductor region, 5, 5a: p + Rectangular semiconductor region, 5b: p - Rectangular semiconductor region, 5b1, 5b2: parts, 6, 6a, 6b: p - Rectangular semiconductor region, 6b1: first part, 6b2: second part, 6c: p - Rectangular semiconductor region, 6c1, 6c2: parts, 6d: p + Rectangular semiconductor region, 7: p-type semiconductor region, 7a: p + Rectangular semiconductor region, 8: p - Rectangular pillar region, 9a: n + Rectangular drain region, 9b: p + Rectangular contact region, 9c: n + Rectangular semiconductor region, 10: gate electrode, 10a: electrode, 11: gate insulating layer, 15: insulating layer, 21: drain electrode, 22: source electrode, 100, 110, 200, 210, 300 - 340: semiconductor devices, R1: first region, R2: second region

Claims

1. a first electrode, a first semiconductor region of a first conductivity type provided on the first electrode and including a first region and a second region provided around the first region, a second semiconductor region of a second conductivity type provided on the first region, a third semiconductor region of a first conductivity type provided on a part of the second semiconductor region, a gate electrode facing the second semiconductor region via a gate insulating layer in a direction perpendicular to a first direction from the first electrode toward the first semiconductor region, a fourth semiconductor region of a second conductivity type provided between the first region and the gate electrode and in contact with the gate insulating layer, a plurality of fifth semiconductor regions of a second conductivity type provided in the second region, located around the fourth semiconductor region along a first plane perpendicular to the first direction, and separated from each other in a second direction from the first region toward the second region, a plurality of sixth semiconductor regions of a second conductivity type provided on the second region, located around the second semiconductor region along the first plane, separated from each other in the second direction, each having an impurity concentration of the second conductivity type lower than that of each of the plurality of fifth semiconductor regions, and separated from the plurality of fifth semiconductor regions in the first direction, a second electrode provided on the second semiconductor region and the third semiconductor region, a semiconductor device comprising the above.

2. The semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type of each of the plurality of sixth semiconductor regions is lower than the impurity concentration of the second conductivity type of the second semiconductor region.

3. A first electrode, a first semiconductor region of a first conductivity type provided on the first electrode and including a first region and a second region provided around the first region, a second semiconductor region of a second conductivity type provided on the first region, a third semiconductor region of a first conductivity type provided on a part of the second semiconductor region, a gate electrode facing the second semiconductor region via a gate insulating layer in a direction perpendicular to a first direction from the first electrode toward the first semiconductor region, a fourth semiconductor region of a second conductivity type provided between the first region and the gate electrode, a plurality of fifth semiconductor regions of a second conductivity type provided in the second region, located around the fourth semiconductor region along a first plane perpendicular to the first direction, and separated from each other in a second direction from the first region toward the second region, Provided above the second region, located around the second semiconductor region along the first surface, separated from each other in the second direction, and each having a second conductivity type impurity concentration lower than that of each of the plurality of fifth semiconductor regions, a plurality of sixth semiconductor regions of the second conductivity type, wherein the impurity concentration of each of the plurality of sixth semiconductor regions of the second conductivity type is lower than the impurity concentration of the second semiconductor region of the second conductivity type, the plurality of sixth semiconductor regions, A second electrode provided above the second semiconductor region and the third semiconductor region, A semiconductor device comprising the same.

4. Further comprising a plurality of seventh semiconductor regions of the second conductivity type located around the gate electrode along the first surface, The plurality of seventh semiconductor regions are located above the plurality of fifth semiconductor regions and below the plurality of sixth semiconductor regions, and the semiconductor device according to any one of claims 1 to 3.

5. A first electrode, A first semiconductor region of the first conductivity type provided above the first electrode and including a first region and a second region provided around the first region, A second semiconductor region of the second conductivity type provided above the first region, A third semiconductor region of the first conductivity type provided on a part of the second semiconductor region, A gate electrode facing the second semiconductor region through a gate insulating layer in a direction perpendicular to the first direction from the first electrode toward the first semiconductor region, A fourth semiconductor region of the second conductivity type provided between the first region and the gate electrode, A plurality of fifth semiconductor regions of the second conductivity type provided in the second region, located around the fourth semiconductor region along a first surface perpendicular to the first direction, and separated from each other in a second direction from the first region toward the second region, Provided above the second region, located around the second semiconductor region along the first surface, separated from each other in the second direction, and each having a second conductivity type impurity concentration lower than that of each of the plurality of fifth semiconductor regions, a plurality of sixth semiconductor regions of the second conductivity type, A plurality of seventh semiconductor regions of the second conductivity type located around the gate electrode along the first surface, above the plurality of fifth semiconductor regions and below the plurality of sixth semiconductor regions, A second electrode provided above the second semiconductor region and the third semiconductor region, A semiconductor device comprising the same.

6. The impurity concentration of the second conductivity type of each of the plurality of seventh semiconductor regions is lower than the impurity concentration of the second conductivity type of each of the plurality of fifth semiconductor regions and higher than the impurity concentration of the second conductivity type of each of the plurality of sixth semiconductor regions. The semiconductor device according to claim 4 or 5.

7. A first electrode, A first semiconductor region of a first conductivity type provided on the first electrode and including a first region and a second region provided around the first region, A second semiconductor region of a second conductivity type provided on the first region, A third semiconductor region of a first conductivity type provided on a part of the second semiconductor region, A gate electrode facing the second semiconductor region via a gate insulating layer in a direction perpendicular to a first direction from the first electrode toward the first semiconductor region, A fourth semiconductor region of a second conductivity type provided between the first region and the gate electrode, A fifth semiconductor region of a second conductivity type provided in the second region and located around the fourth semiconductor region along a first plane perpendicular to the first direction, A sixth semiconductor region of a second conductivity type provided on the second region, located around the second semiconductor region along the first plane, and including a first portion and a second portion alternately provided in a second direction from the first region toward the second region. The impurity concentration of the second conductivity type of the first portion is higher than the impurity concentration of the second conductivity type of the second portion, and the length of each of the plurality of first portions in the second direction decreases. A second electrode provided on the second semiconductor region and the third semiconductor region, A semiconductor device comprising the above.

8. Further comprising a plurality of seventh semiconductor regions of a second conductivity type located around the gate electrode along the first plane, The plurality of seventh semiconductor regions are separated from each other in the second direction, The plurality of seventh semiconductor regions are located above the fifth semiconductor region and below the sixth semiconductor region. The semiconductor device according to claim 7.

9. The impurity concentration of the second conductivity type of each of the plurality of seventh semiconductor regions is higher than the impurity concentration of the second conductivity type of the first portion and higher than the impurity concentration of the second conductivity type of the second portion. The semiconductor device according to claim 8.

10. A first electrode, A first semiconductor region of a first conductivity type provided on the first electrode and including a first region and a second region provided around the first region, A second semiconductor region of a second conductivity type provided on the first region, A third semiconductor region of a first conductivity type provided over a part of the second semiconductor region; A gate electrode facing the second semiconductor region via a gate insulating layer in a direction perpendicular to a first direction from the first electrode toward the first semiconductor region; A fourth semiconductor region of a second conductivity type provided between the first region and the gate electrode; A fifth semiconductor region of a second conductivity type provided in the second region and located around the fourth semiconductor region along a first plane perpendicular to the first direction; A sixth semiconductor region of a second conductivity type provided over the second region and located around the second semiconductor region along the first plane; A plurality of seventh semiconductor regions of a second conductivity type located around the gate electrode along the first plane, separated from each other in a second direction from the first region toward the second region, located above the fifth semiconductor region, located below the sixth semiconductor region, and having a higher impurity concentration of the second conductivity type than at least either of the fifth semiconductor region and the sixth semiconductor region; A second electrode provided over the second semiconductor region and the third semiconductor region; A semiconductor device comprising the above.

11. The semiconductor device according to claim 10, wherein an impurity concentration of the second conductivity type in the seventh semiconductor region is higher than an impurity concentration of the second conductivity type in each of the fifth semiconductor region and the sixth semiconductor region.

12. The semiconductor device according to any one of claims 1 to 11, further comprising a plurality of eighth semiconductor regions of a second conductivity type provided in the first semiconductor region and separated from each other in the perpendicular direction.

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