Semiconductor device and method of manufacturing the same

Abstract

To provide a novel semiconductor device and a manufacturing method for the same in view of a conventional problem which a semiconductor device faces, in which a special separation structure that can reduce a k-value and a parasitic capacitance of the entire device exists between a storage node contact and a storage node contact pad.SOLUTION: The present invention discloses a semiconductor structure. The semiconductor structure includes: a substrate including a first region and a second region; a gate structure disposed on a substrate structure in the second region; a side wall structure disposed on two side surfaces and an upper surface of the gate structure; a first dielectric layer disposed on the side wall structure; a second dielectric layer disposed on the first dielectric layer; a first insulating structure disposed in the second dielectric layer; and a second insulating structure penetrating the first insulating structure.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a contact isolation structure and a contact pad isolation structure and a method for manufacturing the same.

Background Art

[0002] Semiconductor devices are widely used in the electronics industry because of their characteristics such as small size, multifunctionality, and / or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that perform processing operations on logical data, and hybrid devices that have the functions of both memory devices and logic devices.

[0003] Some semiconductor devices may include a layer structure pattern stacked in the vertical direction and a contact plug or an interconnect structure that electrically connects the stacked patterns to each other. As semiconductor devices continue to be miniaturized and the integration density increases, the spacing between patterns and / or the spacing between a pattern and a contact plug also continues to decrease. Therefore, the parasitic capacitance between patterns and / or between a pattern and a contact plug increases, and the contact resistance between a pattern and an interconnect structure also increases accordingly, causing performance degradation of semiconductor devices such as a decrease in operating speed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In view of the above-described conventional problems faced by semiconductor devices, the present invention provides a novel semiconductor device and a method for manufacturing the same, in which a special isolation structure capable of reducing the k value and parasitic capacitance of the entire device exists between a storage node contact and a storage node contact pad.

Means for Solving the Problems

[0006] One aspect of the present invention is a semiconductor device including a substrate including a first region and a second region, a gate structure disposed on the substrate in the second region, sidewall structures disposed on two side surfaces and an upper surface of the gate structure, a first dielectric layer disposed on the sidewall structures, a second dielectric layer disposed on the first dielectric layer, a first insulating structure disposed in the second dielectric layer, and a second insulating structure penetrating the first insulating structure.

[0007] Another aspect of the present invention is a method for manufacturing a semiconductor structure, including supplying a substrate including a first region and a second region, forming a gate structure on the substrate in the second region, forming sidewall structures on two side surfaces and an upper surface of the gate structure, forming a first dielectric layer on the sidewall structures, forming a second dielectric layer on the first dielectric layer, forming a first insulating structure in the second dielectric layer, and forming a second insulating structure penetrating the first insulating structure.

[0008] These objects and other objects of the present invention will surely become clear to those skilled in the art after reading the following detailed description regarding preferred embodiments shown in various figures and drawings.

[0009] The accompanying drawings are included to provide a further understanding of the embodiments, are incorporated herein, and constitute a part of this specification. The drawings illustrate a part of the embodiments and are used together with the description to explain the principles. The following are shown in the drawings.

Brief Description of the Drawings

[0010]

Figure 1A

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Figure 5A

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Figure 7A

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Figure 12

Embodiments for Carrying Out the Invention

[0011] Next, in order to understand, implement, and realize the technical effects of the present disclosure, reference will be made in detail to exemplary embodiments of the present invention illustrated in the accompanying drawings. It can be understood that the following description is merely for illustration and does not limit the present disclosure. Various embodiments of the present disclosure and various features in non-contradictory embodiments can be combined and rearranged in various ways. Changes, equivalents, or improvements to the present disclosure are understandable to those skilled in the art and are intended to be included within the scope of the present disclosure without departing from the spirit and scope of the present disclosure.

[0012] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. The accompanying drawings form a part of this specification, and show specific embodiments in which the present invention can be implemented. These embodiments are described in sufficient detail so that those skilled in the art can implement the present invention. For simplicity and convenience, the scales and ratios of some parts in the drawings are intentionally reduced or exaggerated. Without departing from the scope of the present disclosure, the present invention can adopt other embodiments or make structural, logical, and electrical changes. FIGS. 1A to 7A are plan views showing a method of manufacturing a semiconductor device according to some embodiments, and FIGS. 1B to 7B are cross-sectional views taken along lines I-I', II-II', and III-III' of FIGS. 1A to 7A, respectively.

[0013] First, refer to FIGS. 1A and 1B. At the beginning of the process, a semiconductor substrate 100 is supplied as a setting base for the semiconductor structure of the present invention. The semiconductor substrate 100 may include an adjacent first region 100A (for example, a memory region 100A) and a second region 100B (for example, a peripheral region 100B). A plurality of memory cells may be formed in the memory region 100A, and peripheral transistors constituting a peripheral circuit may be formed in the peripheral region 100B. The semiconductor substrate 100 may be a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (SiGe) substrate. A device isolation pattern 102 may be formed on or in the semiconductor substrate 100 to define a cell active part CA in the memory region 100A and a peripheral active part PA in the peripheral region 100B. In one embodiment, each cell active part CA may be arranged in an island shape in a plan view and may correspond to a portion of the semiconductor substrate 100 surrounded by the device isolation pattern 102. The device isolation pattern 102 can be formed by shallow trench isolation (STI) technology, and the material of the device isolation pattern 102 may include an oxide (such as silicon oxide), a nitride (such as silicon nitride), and / or a nitrogen oxide (such as silicon oxynitride).

[0014] Refer further to FIGS. 1A and 1B. In one embodiment, the semiconductor substrate 100 includes a cell gate electrode GE (as a word line), and each cell active portion CA intersects a pair of cell gate electrodes GE. The cell gate electrode GE is embedded in the groove 104 of the semiconductor substrate 100, extends in the first direction D1, intersects the cell active portion CA of the memory region 100A, and the upper surface may be lower than the upper surface of the cell active portion CA on two side surfaces of the groove 104. A cell gate insulating layer 106 is provided between the cell gate electrode GE and the semiconductor substrate 100 to electrically insulate the cell gate electrode GE and the semiconductor substrate 100. The cell gate capping pattern 108 above each cell gate electrode GE fills the remainder of the groove 104 and is flush with the cell active portion CA.

[0015] In one embodiment, the cell gate capping pattern 108 is further used as a mask in the cell active portion CA to form the first and second source / drain regions SD1 and SD2. Each cell gate electrode GE and its adjacent first and second source / drain regions SD1 and SD2 may constitute a cell selection component. In other words, the cell selection component may be a field effect transistor.

[0016] Refer further to FIGS. 1A and 1B. In one embodiment, the insulating layer 110 may be formed over the cell active portion CA and the peripheral active portion PA. The conductive layer may be formed over the substrate 100 together with the insulating layer 110, and the portion thereof over the memory region 100A extends through the insulating layer 110 and is thereby connected to the first source / drain region SD1 respectively. Specifically, in one embodiment, the conductive layer may include a lower conductive layer 112, a contact plug 114, and an upper conductive layer 116. The lower conductive layer 112 may be formed over the entire surface of the semiconductor substrate 100 together with the insulating layer 110, and each contact plug 114 is connected to the first source / drain region SD1 respectively.

[0017] The upper conductive layer 116 may be formed on the lower conductive layer 112 and the contact plug 114. Additionally, the upper conductive layer 116 may further include a conductive barrier layer 116b disposed between the metal layer 116a and the lower conductive layer 112. The material of the conductive barrier layer 116b may be a metal nitride (such as titanium nitride, tantalum nitride, and / or tungsten nitride) or a transition metal (such as titanium or tantalum). In one embodiment, a hard mask layer 118 is formed on the upper conductive layer 116. The material of the hard mask layer 118 has an etching selectivity with respect to the conductive layers (i.e., the upper conductive layer 116, the lower conductive layer 112, and the contact plug 114), and is, for example, silicon nitride and / or silicon oxynitride. As shown in FIG. 1A, the patterns of the stacked structure such as the lower conductive layer 112, the upper conductive layer 116, and the hard mask layer 118 are formed on the memory region 100A and the peripheral region 100B. A peripheral gate pattern 118p of a peripheral transistor is formed in the peripheral region 100B, and a plate pattern 118c is formed in the memory region 100A. It can be seen that the cell gate electrode GE can extend beyond the plate pattern in the horizontal first direction D1 for connection to a subsequent peripheral transistor.

[0018] Further refer to FIGS. 1A and 1B. After the plate pattern 118c and the peripheral gate pattern 118p are formed, spacers 120 are formed on the sidewalls of the plate pattern 118c and the peripheral gate pattern 118p, and the material thereof may be silicon oxide, silicon nitride, and / or silicon oxynitride. The spacers 120 on the peripheral region 100B can be used to define the lightly doped drain (LDD) structure of the peripheral region and the extension structure of the source / drain regions. In one embodiment, an insulating liner 122 may be conformally formed on the structural topography of the semiconductor substrate 100. The insulating liner 122 may be formed of an insulating material having an etching selectivity with respect to the planarized interlayer insulating film 124 formed in a subsequent process. The insulating liner 122 in the peripheral region 100B is then used as an etch stop layer in the process of forming the peripheral contact holes.

[0019] Please refer to FIGS. 2A and 2B. After the insulating liner 122 is formed, an interlayer dielectric (ILD) 124 is formed over the entire surface of the semiconductor substrate 100. In this embodiment, the planarized interlayer dielectric 124 is flush with the hard mask layer 118 over the memory region 100A and the peripheral region 100B, and the insulating liner 122 that was initially present on the upper surface of the hard mask layer 118 is removed, exposing the hard mask layer 118. However, in other embodiments, as shown in FIG. 2C, the interlayer dielectric 124 may also cover the upper surface of the hard mask layer 118 (as shown in FIG. 12), and the insulating liner 122 present on the upper surface of the hard mask layer 118 may not be removed, but this is not limited thereto. In one embodiment, the material of the interlayer dielectric 124 may be silicon oxide, and the material of the insulating liner 122 may be silicon nitride and / or silicon oxynitride. Next, a capping layer 126 is formed on the same plane as the hard mask layer 118 and the interlayer dielectric 124. The capping layer 126 may be formed of an insulating material having an etching selectivity with respect to the interlayer dielectric, such as silicon nitride and / or silicon oxynitride.

[0020] Please further refer to FIGS. 2A and 2B. After the capping layer 126 is formed, a cell line mask pattern 128 is formed over the capping layer 126. In one embodiment, the cell line mask pattern 128 over the memory region 100A extends parallel to each other in the second direction D2, and thereby may intersect the plate pattern 118c. The cell line mask pattern 128 may be formed by a double patterning technique such that its width is smaller than the limit of the photolithography tool. The cell line mask pattern 128 formed using the double patterning method has a connection portion 128a that does not overlap the plate pattern 118c in the second direction D2. More specifically, as shown in FIG. 2A, the cell line mask pattern 128 may overlap the contact plugs 114 in the same row located at the center of all the cell active portions CA, but does not overlap the ends of all the cell active portions CA. The cell line mask pattern 128 is not formed in the peripheral region 100B.

[0021] Refer to FIGS. 3A and 3B. After the cell line mask pattern 128 is formed, a photolithography process is performed using the cell line mask pattern 128 as a mask, and the plate pattern 118c is patterned on the memory region 100A. On the other hand, the etching rate of the etching recipe may vary depending on the etching region, and the etching rate of the capping layer 126 with a large area (such as the capping layer 126 on the peripheral region 100B outside the cell line mask pattern 128) may be lower than the etching rate of the capping layer 126 with a small area (such as the capping layer 126 between the cell line mask patterns 128). Therefore, the capping layer 126 between the cell line mask patterns 128 and the hard mask layer 118 of the underlying plate pattern 118c may be etched continuously. Conversely, the capping layer 126 on the peripheral region 100B may be preserved. In addition, the capping layer 126 having a large area on the memory region 100A may be preserved. In other embodiments, optionally, an additional photoresist pattern may be formed at the edges of the memory region 100A and the peripheral region 100B to obtain the above-described effects. Thereafter, the etching is continuously performed with the patterned hard mask layer 118 and stopped at the insulating layer 110, whereby, as shown in FIG. 3A, the bit line pattern BL and the outermost bit line pattern BLe are formed, and the width of the outermost bit line pattern BLe in the first direction D1 is larger than that of the bit line pattern BL, and the outermost bit line pattern BLe can be used as a dummy bit line pattern to avoid defects caused by the microloading effect on the bit line pattern. The cell line mask pattern 128 may be removed after patterning the hard mask layer 118.

[0022] Further refer to FIGS. 3A and 3B. The bit line pattern BL extends in a second direction D2, is orthogonal to the cell gate electrode GE (as a word line), and the lower conductive layer 112 and the contact plugs 114 may be alternately and repeatedly arranged in the second direction D2. The contact plug 114 is connected to the corresponding first source / drain region SD1. The insulating layer 110 may be disposed between the lower conductive layer 112 and the semiconductor substrate 100. The bit line pattern BL further includes a stacked structure on the lower conductive layer 112 and the contact plugs 114, such as the upper conductive layer 116, the hard mask layer 118, and the capping layer 126. Thus, the plate pattern 118c on the memory region 100A is converted into a plurality of bit line patterns BL during this process, while the peripheral gate pattern 118p on the peripheral region 100B remains the same.

[0023] Please refer to FIGS. 4A and 4B. After the bit line pattern BL is formed, next, a conformal cell insulating liner 130 is formed over the entire surface topography of the semiconductor substrate 100, and a filling insulating layer 132 is formed over the cell insulating liner 130 and within the air gap between the bit line patterns BL and BLe. In one embodiment, the cell insulating liner 130 is conformally formed on the sidewalls of a stacked structure such as the capping layer 126, hard mask layer 118, upper conductive layer 116, lower conductive layer 112, and contact plug 114 over the memory region 100A and on the surface of the insulating layer 110. The filling insulating layer 132 fills the air gap between the bit line patterns BL and BLe and may extend parallel to each other in a second direction D2. The planarized filling insulating layer 132 may expose the capping layer 126, be flush with the upper surfaces of the capping layer 126 and the cell insulating liner 130, and the cell insulating liner 130 and the filling insulating layer 132 over the peripheral region 100B are removed. The cell insulating liner 130 may be formed of an insulating material having an etching selectivity with respect to the filling insulating layer 132, such as silicon nitride and / or silicon oxynitride, and may later function as an insulating layer between the storage node contacts and between the bit line pattern BL. The filling insulating layer 132 may be formed of silicon oxide and may define a storage node contact isolation structure together with the bit line pattern BL in a subsequent process. Note that in other embodiments, the cell insulating liner 130 may be in the form of a multi-layer structure or a spacer in order to provide better insulation and self-alignment effects.

[0024] Please refer to FIGS. 5A and 5B. After the cell insulating liner 130 and the filling insulating layer 132 are formed, a separation line mask pattern 134 is formed on the same plane of the semiconductor substrate 100. In one embodiment, the separation line mask pattern 134 on the memory region 100A may extend parallel to each other in a first direction D1, thereby intersecting the bit line patterns BL and BLe. Similar to the cell line mask pattern 128 of FIGS. 2A and 2B, since the cell line mask pattern 128 can be formed by a double patterning technique, its width can be smaller than the limit of the photolithography tool. Different from the cell line mask pattern 128, the separation line mask pattern 134 is a sacrificial pattern after removing the self-aligned spacer in the double patterning technique, and the removed self-aligned spacer pattern extends to the peripheral region 100B in the first direction as shown, forming a separation line pattern 136 that overlaps with the peripheral gate pattern 118p on the peripheral region B. More specifically, as shown in FIG. 5A, the separation line mask pattern 134 on the memory region 100A extends in a first direction D1 that alternately passes through the central contact plug 114 on different cell active parts CA and the two end positions of the second source / drain region SD2 (i.e., the storage node), and may partially overlap with the cell gate electrode GE. The separation line pattern 136 on the memory region 100A also extends in the first direction D1 that passes through the central contact plug 114 on different cell active parts CA and the position between the end second end source / drain regions SD2. In one embodiment, both the separation line mask pattern 134 and the separation line pattern 136 may extend to the peripheral region 100B and overlap with the peripheral gate pattern 118p on the peripheral region B, and the adjacent paired separation line patterns 136 may further be provided with connection end portions 136a on the peripheral region 100B. In one embodiment, the separation line pattern 136 may expose a part of the capping layer 126 and the filling insulating layer 132 on the memory region 100A, and the exposed region of the filling insulating layer 132 may define a storage node contact isolation structure to be formed later.The isolation line mask pattern 134 can be formed from an insulating material having an etching selectivity with respect to the filling insulating layer 132, such as silicon nitride and / or silicon oxynitride. In other embodiments, the isolation line mask pattern 134 may be directly formed by a photoresist.

[0025] Please refer to FIGS. 6A and 6B. After the isolation line mask pattern 134 and the isolation line pattern 136 are formed, the isolation line mask pattern 134 is used as a mask for a photolithography process to remove the exposed insulating layer 132 over the memory region 100A, thereby forming a contact separation structure trench 138 located between the bit line patterns BL and BLe. The cell regions covered by the isolation line mask pattern 134, such as the region traversed by the cutting line II-II', are not affected. In one embodiment, since the exposed insulating layer 132 only exists between the bit line patterns BL and BLe over the memory region 100A, the contact separation structure trench 138 can be formed only between the bit line patterns BL and BLe over the memory region 100A, and it should be noted that the contact separation structure trench 138 can expose the underlying insulating liner 130 that functions as an etch stop layer. The exposed surfaces of the other memory regions 100A and the peripheral region 100B are the capping layer 126, and this photolithography process may remove the exposed capping layer 126 to a certain thickness, whereby a part of the isolation line pattern 136 is transferred to the capping layer 126 to form an isolation line trench 140. The isolation line trench 140 can penetrate the peripheral region 100B in the first direction D1 and extend through the peripheral gate pattern 118p. The isolation line mask pattern 134 may be removed after the above-described photolithography process.

[0026] Please refer to FIGS. 7A and 7B. After the contact separation structure grooves 138 and the separation line grooves 140 are formed, an insulating material is filled into the contact separation structure grooves 138 and the separation line grooves 140, and a contact separation structure 142 (which may also be called a memory cell separation structure) is formed. In one embodiment, the contact separation structure 142 may include a lower half 142a of the contact separation structure groove 138 and an upper half 142b of the separation line groove 140. The contact separation structure 142 outside the memory region 100A has only the upper half 142b. The upper half 142b extends to the peripheral region 100B in the first direction D1, is located within the capping layer 126, overlaps with the peripheral gate pattern 118p, and connection ends 142c may be provided on the adjacent upper halves 142b in pairs on the peripheral region 100B. The lower half 142a of the contact separation structure 142 is located within the previously formed contact separation structure groove 138 and is arranged in an array. It can be seen that a plurality of upper halves 142b of the contact separation structure 142 may overlap with the peripheral gate pattern 118p. The flattened contact separation structure 142 and the capping layer 126 are flush. After the contact separation structure 142 is formed, an etching process is performed to remove the remaining insulating layer 132 on the memory region 100A, and storage node contact recesses 144 are formed in the memory region 100A. The etching process removes both the bottom cell insulation liner 130 and the insulating layer 110, so that the second source / drain region SD2 (i.e., the position of the storage node) of the underlying cell active portion CA and the device isolation pattern 102 are exposed. The other exposed surface is the region of the capping layer including the peripheral region 100B, and this region is not affected. In one embodiment, the contact separation structure 142 may be formed of an insulating material having an etching selectivity with respect to the filling insulating layer 132, such as silicon nitride and / or silicon oxynitride, and its upper half 142b and lower half 142a are composed of the same material layer.

[0027] In the following embodiments, with reference to FIGS. 8 to 11, the steps of forming a storage node contact in the semiconductor process of the present invention will be described. In the figures of the embodiments, the orientation of the peripheral gate pattern 118p on the peripheral region 100B is different from that of the previous embodiments, and its cross-section is a cross-section passing through the source / drain region SD3 of the peripheral device in order to clearly show the influence of this process step on the peripheral region.

[0028] Please refer to FIG. 8. After the insulating layer 132 is removed, a photolithography process is performed in the peripheral region 100B to form the contact hole 146. In one embodiment, the contact hole 146 extends continuously through the stacked structure of the capping layer 126, the interlayer insulating film 124, the cell insulating liner 130, and the insulating layer 110 on the peripheral region 100B and contacts the underlying third source / drain region SD3. In addition, a part of the above-described upper half 142b of the contact isolation structure 142 may be penetrated by the contact hole 146. Further, in one embodiment, this photolithography process may further etch the second source / drain region SD2 and the device isolation pattern 102 exposed from the storage node contact recess 144 on the storage region 100A, thereby causing the storage node contact recess 144 to be recessed and facilitating the formation of the embedded contact of the storage node, but it is not limited thereto.

[0029] Refer to FIG. 9. After the contact hole 146 is formed, the embedded contact 148 of the storage node is formed on the storage node contact recess 144 in the storage region 100A. The embedded contact 148 may contact the corresponding second source / drain SD2 on the storage region 100A. In this embodiment, the embedded contact 148 is not formed on the peripheral region 100B, which can be realized by forming a mask on the peripheral region 100B. The height of the embedded contact 148 is preferably lower than the upper surface of the hard mask layer 118, and its material may include epitaxial silicon, polysilicon, amorphous silicon, or the like. In other embodiments, the embedded contact 148 may not be formed, but is not limited thereto. Next, the barrier layer 152 and the conductive layer 154 are formed in the storage node contact recess 144 of the storage region 100A and the contact hole 146 of the peripheral region 100B. The barrier layer 152 may be conformally formed on the structural topography of the semiconductor substrate 100, and the conductive layer 154 fills the remaining storage node contact recess 144 and the contact hole 146 and covers the entire surface of the semiconductor substrate. In one embodiment, the barrier layer 152 on the storage region 100A may contact the embedded contact 148, and the barrier layer 152 on the peripheral region 100B directly contacts the third source / drain region SD3 in the peripheral active portion PA. The material of the barrier layer 152 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof, and the material of the conductive layer 154 may include tungsten (W), tungsten nitride (WN), titanium (Ti), nickel (Ni), cobalt (Co), aluminum (Al), or a combination thereof. To provide a better contact effect, a metal silicide layer 156 may be further formed between the barrier layer 152 and the embedded contact 148.

[0030] Please refer to FIG. 10. After the barrier layer 152 and the conductive layer 154 are formed, a photolithography process is performed, and the barrier layer 152 and the conductive layer 154 are patterned outside the storage node contact recess 144 and the contact hole 146, and the storage node contact 156 is formed. In one embodiment, the storage node contact 156 can be divided into a lower contact plug portion 156a and an upper contact pad portion 156b. The contact plug portion 156a is located in the storage node contact recess 144 described above, and the contact pad portion 156b is located in the upper half 142b of the contact isolation structure 142 and is located above the height of the upper surface of the capping layer 126. In one embodiment, a contact pad isolation groove 158 is formed between the patterned contact pad portions 156b. The contact pad isolation groove 158 can penetrate the capping layer 126 with a certain thickness and extend into the capping layer 126. For example, its bottom surface is lower than the height of the upper half 142b of the contact isolation structure 142, or extends deep into the interlayer insulating film 124 through the entire capping layer 126 (that is, as shown by the groove 158a, it is lower than the height of the bottom surface of the capping layer 126). The side walls of the contact pad isolation recess 158 may include the conductive layer 154, the barrier layer 152, the upper half 142b of the contact isolation structure 142, and / or the interlayer insulating film 124, and the barrier layer 152 does not exist on the surface of the contact pad isolation recess 158. In one embodiment, the contact pad isolation recess 158 generally overlaps the bit line pattern BL in the vertical direction. However, in other embodiments, the contact pad position 156b of the storage node contact 156 may be horizontally offset with respect to the contact plug position 156a, whereby the contact pad isolation recess 158 and the contact pad portion 156b partially overlap the underlying bit line pattern BL. Generally, the storage node contact 156 and the memory cell formed thereon are later arranged in an array on the substrate surface.In the present invention, the above-described patterning process used to form the storage node contact 156 on the memory region 100A can also be used to form the same recess and contact pad structure (the peripheral region may include a peripheral circuit pattern) on the peripheral region 100B. It should be noted that, similar to the contact hole 146 in FIG. 8, these recesses 158 may extend through a part of the upper half 142b of the contact isolation structure 142.

[0031] Please refer to FIG. 11. After the storage node contact 156 and the contact pad separation recess 158 are formed, a contact pad separation structure 160 is formed within the contact pad separation recess 158. In one embodiment, the contact pad separation structure 160 may include a first insulating layer 160a provided on the bottom and sidewalls of the contact pad separation structure 160, and a second insulating layer 160b provided on the upper portion of the contact pad separation structure 160 and covering the first insulating layer 160a. In one embodiment, the first insulating layer 160a may be conformally formed on the structural topography of the semiconductor substrate, and the second insulating layer 160b may fill the remaining contact pad separation groove 158. Additionally, when the width of the contact pad separation recess 158 is smaller, the second insulating layer 160b may not be required to fill the remaining contact pad separation recess 158. Instead, an air gap 160c can be defined within the contact pad separation structure 160 together with the first insulating layer 160a, but it is not limited thereto. In one embodiment, the air gap 160c can further improve the separation effect of the contact pad separation structure 160. The upper surface of the planarized contact pad separation structure 160 and the upper surface of the storage node contact 156 are preferably flush. Additionally, the contact pad separation structure 160 may extend into the capping layer 126, for example, with its bottom surface lower than the height of the upper half 142b of the contact separation structure 142, or may extend deeply into the interlayer insulating film 124 through the entire capping layer 126 (i.e., lower than the height of the bottom surface of the capping layer 126 as indicated by the recess 158a). The contact pad separation structure 160 may contact the contact separation structure 142, and its bottom surface is lower than the bottom surface of the contact separation structure 142. Generally, in one embodiment, the contact pad separation structures 160 are arranged in an array on the substrate surface. The material of the first insulating layer 160a is silicon nitride, and the material of the second insulating layer 160b is silicon carbonitride (SiCN).

[0032] Please refer to FIG. 12, which is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. In this embodiment, two adjacent peripheral gate patterns 118p are taken as an example. The contact 156 extends from a position between the two peripheral gate patterns 118p through layer structures such as the capping layer 126 and the interlayer insulating film 124 and is connected to a third source / drain region SD3 in the semiconductor substrate 100. The interlayer insulating film 124 may cover the upper surface and side walls of the peripheral gate pattern 118p, but is not limited thereto. The contact 156 may be further connected to an upper interconnect via the via 164. In the embodiment of FIG. 12, the contact pad isolation structure 160 may include a first insulating layer 162a on the bottom surface and side walls of the contact pad isolation structure 162 and a second insulating layer 162b conformally formed on the surfaces of the capping layer 126, the first insulating layer 162a, and the contact pad portion 156b. The bottom of the second insulating layer 162 may be lower than the bottoms of the first insulating layer 162a, the contact pad position 156b, and the upper half 142b of the contact isolation structure 142. In addition, as described above, when the width of the contact pad isolation recess is larger, the insulating layer may fill the space of the remaining contact pad isolation groove without forming an air gap. As a result, the contact pad isolation structure 162 may further include a third insulating layer 162c located on the second insulating layer 162b and filling the remaining recess space. In one embodiment, the bottom surface of the third insulating layer 162c of the contact pad isolation structure 162 may be lower (as 162c-1) than the bottom of the first insulating layer 162a, may be higher (as 162c-2) than the bottom of the first insulating layer 162a, or may be flush with the bottom of the first insulating layer 162a. In one embodiment, the materials of the first insulating layer 162a and the third insulating layer 162c may be silicon nitride, and the material of the second insulating layer 160b may be silicon carbonitride (SiCN).

[0033] Those skilled in the art will readily observe that numerous modifications and changes can be made to the devices and methods while maintaining the teachings of the present invention. Accordingly, the above disclosure should be construed as being limited only by the boundaries of the appended claims.

Description of Symbols

[0034] 100 Semiconductor substrate 100A First region, memory region 100B Second region, peripheral region 102 Device isolation pattern 104 Groove 106 Cell gate insulating layer 108 Cell gate capping pattern 110 Insulating layer 112 Lower conductive layer 114 Contact plug 116 Upper conductive layer 116a Metal layer 116b Conductive barrier layer 118 Hard mask layer 118c Plate pattern 118p Peripheral gate pattern 120 Spacer 122 Insulating liner 124 Interlayer insulating film 126 Capping layer 128 Cell line mask pattern 128a Connection part 130 Cell insulating liner 132 Filling insulating layer 134 Separation line mask pattern 136 Separation line pattern 136a Connection end 138 Contact separation structure groove 140 Separation line groove 142 Contact separation structure 142a Lower half of contact separation structure 142b Upper half of contact separation structure 142c Connection end 144 Storage node contact recess 146 Contact hole 148 Embedded contact 152 Barrier layer 154 Conductive layer 156 Storage node contact 156a Contact plug portion 156b Contact pad portion 158 Contact pad separation groove, contact pad separation recess 158a Groove, recess 160 Contact pad separation structure 160a First insulating layer 160b Second insulating layer 160c Air gap 162 Contact pad separation structure 162a First insulating layer 162b Second insulating layer 162c Third insulating layer 164 Via BL Bit line pattern BLe Outermost bit line pattern CA Cell active portion D1 First direction D2 Second direction GE Cell gate electrode PA Peripheral active portion SD1 First source / drain region SD1 SD2 Second source / drain region SD2 SD3 Third source / drain region SD3

Claims

1. A semiconductor structure, comprising: a substrate including a first region and a second region; a gate structure disposed on the substrate in the second region; sidewall structures disposed on two side surfaces and an upper surface of the gate structure; a first dielectric layer disposed on the sidewall structures; a second dielectric layer disposed on the first dielectric layer; a first insulating structure disposed within the second dielectric layer; a second insulating structure penetrating through the first insulating structure; a first contact structure including a lower portion of a contact plug and an upper portion of a conductive pad, wherein the contact plug penetrates through the first dielectric layer and the second dielectric layer, the conductive pad is disposed on the second dielectric layer and the first insulating structure, and the second insulating structure penetrates through the conductive pad.

2. The semiconductor structure according to claim 1, wherein a bottom surface of the second insulating structure is lower than a bottom surface of the first insulating structure.

3. The semiconductor structure according to claim 1, wherein a bottom surface of the second insulating structure is located within the first dielectric layer.

4. The semiconductor structure according to claim 1, wherein an upper surface of the first insulating structure is aligned with an upper surface of the second dielectric layer.

5. The semiconductor structure according to claim 1, wherein the second insulating structure includes a first insulating layer and a second insulating layer disposed on the first insulating layer, the first insulating layer contacts the second dielectric layer, sidewalls of the conductive pad, and sidewalls of the first insulating structure, and the second insulating layer contacts sidewalls of the first insulating layer.

6. The semiconductor structure according to claim 5, wherein the first insulating layer and the second insulating layer define an air gap of the second insulating structure.

7. The semiconductor structure according to claim 5, wherein the second insulating structure further includes a third insulating layer disposed on the second insulating layer, and the second insulating layer contacts an upper surface of the conductive pad.

8. The semiconductor structure according to claim 7, wherein a bottom surface of the second insulating layer is lower than a bottom surface of the first insulating layer, a bottom surface of the conductive pad, and a bottom surface of the first insulating structure.

9. The semiconductor structure according to claim 7, wherein a bottom of the third insulating layer is lower than a bottom of the first insulating layer.

10. The semiconductor structure according to claim 7, wherein a bottom of the third insulating layer is aligned with a bottom of the first insulating layer.

11. The semiconductor structure according to claim 7, wherein the bottom of the third insulating layer is higher than the bottom of the first insulating layer.

12. A plurality of bit lines disposed on the first region and extending in a first direction, A plurality of second contact structures disposed between the bit lines on the first region, the plurality of second contact structures being arranged in an array, A plurality of contact separation structures disposed between the bit lines and between the second contact structures on the first region, the plurality of contact separation structures being arranged in an array and the contact separation structures being formed of the same material layer as the first insulating structure, further comprising the semiconductor structure according to claim 1.

13. The semiconductor structure according to claim 12, wherein the first insulating structure extends in a second direction, and the second direction is orthogonal to the first direction.

14. A contact pad is formed on the second contact structure, the contact pad is separated by a contact pad separation structure, the contact pad separation structure is formed of the same material layer as the second insulating structure, and the upper surface of the contact pad, the upper surface of the contact pad separation structure, the upper surface of the second insulating structure, and the upper surface of the conductive pad are substantially flush, the semiconductor structure according to claim 12.

15. The semiconductor structure according to claim 13, wherein at least two adjacent first insulating structures have ends interconnected in the first direction.

16. A method of manufacturing a semiconductor structure, Supplying a substrate including a first region and a second region; Forming a gate structure on the substrate in the second region; Forming sidewall structures on two side surfaces and an upper surface of the gate structure; Forming a first dielectric layer on the sidewall structures; Forming a second dielectric layer on the first dielectric layer; Forming a first insulating structure in the second dielectric layer; Forming a second insulating structure penetrating the first insulating structure; A step of forming a first contact structure, wherein the first contact structure includes a lower portion of a contact plug and an upper portion of a conductive pad, the contact plug penetrates the first dielectric layer and the second dielectric layer, the conductive pad is disposed on the second dielectric layer and the first insulating structure, and the second insulating structure penetrates the conductive pad; and a method of manufacturing a semiconductor structure including the step of

17. The step of forming a first insulating structure in the second dielectric layer The method of manufacturing a semiconductor structure according to claim 16, further including a step of simultaneously forming a contact isolation structure in the first region.

18. The method of manufacturing a semiconductor structure according to claim 16, wherein the step of forming the second insulating structure simultaneously forms a contact pad isolation structure on the first region.

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