Monolithic Optical Transformer

Abstract

Provides a power efficient optical transformer device. Device architecture provides uniform current spreading minimizing efficiency droop. Quantum well design is optimized for both Light Emitting Diode (LED) and Photodiode (PD) operation. Low loss optical cavity allows efficient light transfer from the LED junction to the PD junction. The architecture provides low loss voltage up and down conversion and is compatible with production grade epitaxial growth and wafer fabrication processes.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to optoelectronic devices and methods for fabricating the same. More particularly, embodiments relate to devices and methods for integrating light emitting diodes (LEDs) and photodiodes (PDs) on a single monolithic semiconductor die. [Background technology]

[0002] When an LED is used as a photodiode, the process of photon absorption is opposite to the process of photon generation in the LED. By combining an LED with a photodiode, the LED's radiation can be detected by the photodiode, forming an optocoupler, a device widely used in the electronics industry and data communications. Summary of the Invention [Problem to be solved by the invention]

[0003] There is a continuing effort to improve the efficiency and power capabilities of optical coupling in these devices. Thus, there is a need for a monolithic LED / photodiode pair that allows light generation and detection within the same semiconductor device, such that optical losses associated with optical transitions between dielectric media, typically with different refractive indices, are minimized. Such a device would allow for an optocoupler with an overall quantum efficiency dominated by the internal quantum efficiency between the LED and the photodiode. Improved efficiency would allow for the transfer of greater amounts of power than current optocouplers, thus providing significantly broader functionality. [Means for solving the problem]

[0004] One or more embodiments relate to a monolithic optical device. In one or more embodiments, the monolithic optical device comprises: a light-emitting diode (LED) junction; a photodiode (PD) junction; a semi-insulating layer separating the light emitting diode (LED) junction and the photodiode (PD) junction; and The light emitting diode (LED) junction, the photodiode (PD) junction, and the semi-insulating layer are vertically stacked.

[0005] Another embodiment relates to a monolithic optical device. In one or more embodiments, the monolithic optical device comprises: a light-emitting diode (LED) junction; a photodiode (PD) junction; A tunnel junction and a contact shared by the light emitting diode (LED) junction and the photodiode (PD) junction; and The light emitting diode (LED) junction, the photodiode (PD) junction, and the tunnel junction are vertically stacked.

[0006] Another embodiment relates to a monolithic optical device. In one or more embodiments, the monolithic optical device comprises: a light-emitting diode (LED) junction; a first photodiode (PD) junction; a second photodiode (PD) junction; a tunnel junction separating the first photodiode (PD) junction and the second photodiode (PD) junction; a semi-insulating layer separating the light emitting diode (LED) junction and a first photodiode (PD) junction; and The light emitting diode (LED) junction, the first photodiode (PD) junction, the second photodiode (PD) junction, the tunnel junction, and the semi-insulating layer are vertically stacked.

[0007] Another embodiment relates to a monolithic optical device. In one or more embodiments, the monolithic optical device comprises: a junction segmented into a plurality of mesas on a common cathode, the junction having an n-type layer on the common cathode, an active region on the n-type layer, a p-type layer on the active region, and each of the plurality of mesas separated by a trench; an anode on the p-type layer of each of the plurality of mesas, the anode alternating between a photodiode (PD) anode and a light emitting diode (LED) anode; It has.

[0008] Yet another embodiment relates to a monolithic optical device. In one or more embodiments, the monolithic optical device comprises: a junction segmented into a plurality of mesas on a plurality of alternating photodiode (PD) anode regions and light emitting diode (LED) anode regions, the junction having a p-type layer on the plurality of alternating photodiode (PD) anode regions and light emitting diode (LED) anode regions, an active region on the p-type layer, an n-type layer on the active region, and each of the plurality of mesas separated by a trench; a cathode on the n-type layer of each of the plurality of mesas, the cathode alternating between a photodiode (PD) cathode and a light emitting diode (LED) cathode; It has.

[0009] Another embodiment of the present disclosure relates to a method for fabricating a monolithic optical device. In one or more embodiments, the method for fabricating the monolithic optical device includes forming a light emitting diode (LED) junction on a substrate, forming a semi-insulating layer on the light emitting diode (LED) junction, and forming a photodiode (PD) junction on the semi-insulating layer to form a vertically stacked monolithic optical device.

[0010] In order that the foregoing features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be provided by reference to embodiments. Some of the embodiments are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings merely illustrate typical embodiments of the present disclosure, and therefore the present disclosure should not be considered as limiting its scope. That is, the disclosure may admit of other equally effective embodiments. The embodiments described herein are shown by way of example and not by way of limitation to the figures of the accompanying drawings. In the drawings, like reference numerals represent like elements. [Brief explanation of the drawings]

[0011] [Figure 1] 1 illustrates a cross-section of an optical device according to one or more embodiments. [Figure 2] 1 illustrates a cross-section of an optical device according to one or more embodiments. [Figure 3] 1 illustrates a cross-section of an optical device according to one or more embodiments. [Figure 4] 1 illustrates a cross-section of an optical device according to one or more embodiments. [Figure 5] 1 illustrates a cross-section of an optical device according to one or more embodiments. [Figure 6] 1 illustrates a cross-section of an optical device according to one or more embodiments. [Figure 7] 1 illustrates a cross-section of an optical device according to one or more embodiments. [Figure 8] 1 illustrates a cross-section of an optical device according to one or more embodiments. [Figure 9] FIG. 10 is an energy band diagram of MQWs with distinct designs of QWs in the photodiode depletion region and QWs in the LED depletion region. [Figure 10] 1 illustrates a cross-section of an optical device according to one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0012] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of structure or process steps set forth in the following description, as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0013] In one or more embodiments, the term "substrate," as used herein, refers to a structure, intermediate, or final object having a surface or a portion of a surface on which a process acts. Also, references to a substrate in some embodiments refer to only a portion of a substrate, unless the context clearly indicates otherwise. Furthermore, references to deposition on a substrate in some embodiments include deposition on a bare substrate or deposition on a substrate having one or more films, features, or materials deposited or formed thereon.

[0014] In one or more embodiments, "substrate" refers to any substrate or material surface formed on a substrate on which film processing occurs during a manufacturing process. In exemplary embodiments, the substrate surface on which processing occurs includes materials such as silicon, silicon oxide, silicon-on-insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable material, such as, for example, metals, metal nitrides, III-nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials, depending on the application. The substrate may include, but is not limited to, a light-emitting diode (LED) device. In some embodiments, the substrate is exposed to a pre-treatment process, in which the substrate surface is polished, etched, reduced, oxidized, hydroxylated, annealed, UV-cured, e-beam-cured, and / or baked. In some embodiments, in addition to performing film treatments directly on the surface of the substrate itself, any disclosed film treatment steps are performed on underlying layers formed on the substrate, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, if a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer is the substrate surface.

[0015] The terms "wafer" and "substrate" are used interchangeably in this disclosure. Thus, as used herein, a wafer serves as a substrate for forming the LED devices described herein.

[0016] Electrical circuits can use power converters to increase or decrease voltage. For example, if a circuit uses 2.5 volts to operate a chip but the power supply provides 5 volts, the circuit can use a power converter to reduce the voltage by a factor of two. Because power is the product of voltage and current, a power converter can simultaneously change the voltage and current in a complementary manner. For example, a power converter that reduces the voltage by a factor of two can also increase the current by a factor of two.

[0017] Traditionally, power converters convert an input direct current (DC) signal to alternating current (AC) by inducing the AC signal through a first coil of wire and using magnetic induction to induce AC current in a second coil of wire placed in close proximity to the first coil of wire, and the AC current from the second coil of wire is rectified to produce an output DC electrical signal. Over the years, as circuits have become denser, electrical interference from these induction-based power converters has become a problem. Ripple in the voltage and / or current from the rectification process can also be a problem.

[0018] Optical-based power converters can overcome the drawbacks of inductive-based power converters. Optical-based power converters can generate light in response to an input electrical signal, absorb light, and generate an output electrical signal in response to the absorbed light. During operation, the light is entirely contained within the power converter, and the power converter can include only electrical signals (e.g., voltage and / or current) as its input and output signals.

[0019] Embodiments of the present invention relate to optical transformer devices with high power efficiency. In one or more embodiments, the device architecture provides uniform current spreading and minimizes efficiency degradation. In one or more embodiments, the quantum well design is optimized for both light-emitting diode (LED) and photodiode (PD) operation. A low-loss optical cavity allows efficient transmission of light from the LED junction to the PD junction. The architecture of one or more embodiments provides low-loss voltage up- and down-conversion and is compatible with production-grade epitaxial growth and wafer fabrication processes.

[0020] In the following description, numerous specific details are set forth, such as particular materials, chemical properties, and dimensions of elements, to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to one skilled in the art that one or more embodiments of the present disclosure may be practiced without these specific details. In other instances, LED manufacturing processes, techniques, materials, equipment, and the like have not been described in detail to avoid unnecessarily obscuring this description. Using the included description, one skilled in the art will be able to implement the appropriate functionality without undue experimentation.

[0021] While certain example embodiments of the present disclosure have been described and illustrated in the accompanying drawings, it is understood that such embodiments are merely illustrative and do not limit the disclosure, and that since modifications may occur to those skilled in the art, the disclosure is not limited to the specific configurations and arrangements shown and described.

[0022] In one or more embodiments, a vertical device architecture is provided, which includes a GaN-based epitaxial layer stack having an LED junction and a PD junction, capped with top and bottom reflectors, which may serve as contacts for the LED, the PD, or both. In one or more embodiments, the device has separate junctions for the LED and the PD, allowing for galvanic isolation by a semi-insulating GaN or AlGaN layer between the junctions. In other embodiments, the device uses the same junction for the LED and the PD, allowing for a simpler device design without complete galvanic isolation.

[0023] 1-8 illustrate cross-sectional views of a light emitting diode device according to one or more embodiments. Referring to FIG. 1, in one or more embodiments, separate junctions for the LED 102 and PD 114 are grown vertically in a single monolithic layer structure 100.

[0024] In one or more embodiments, the LED 102 and the PD 114 have semiconductor layers that include III-nitride materials, which in certain embodiments include epitaxial III-nitride materials. In some embodiments, the III-nitride materials include one or more of gallium (Ga), aluminum (Al), and indium (In). Thus, in some embodiments, the semiconductor layers of the LED 102 and the PD 114 include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), etc.

[0025] In one or more embodiments, the semiconductor layers of the LED 102 include a p-type layer 106, an active region 108, and an n-type layer 110. The active region 108 separates the p-type layer 106 from the n-type layer 110. In particular embodiments, the n-type layer 110 and the p-type layer 106 of the LED comprise n-doped and p-doped GaN. The semiconductor layers of the LED 102 (i.e., the p-type layer 106, the active region 108, and the n-type layer 110) are on the p-contact 104. The LED has a p-contact 104 and an n-contact 112.

[0026] In one or more embodiments, the semiconductor layers of the PD 114 include an n-type layer 118, an active region 120, and a p-type layer 122. The active region 120 separates the p-type layer 122 from the n-type layer 118. In particular embodiments, the n-type layer 118 and the p-type layer 122 of the PD 114 include n-doped and p-doped GaN. A p-contact 124 is on the semiconductor layers of the PD 114 (i.e., the p-type layer 122, the active region 120, and the n-type layer 118). The PD 114 includes a p-contact 124 and an n-contact 126.

[0027] In one or more embodiments, the layers of III-nitride materials forming the LEDs and PDs are epitaxially grown. In one or more embodiments, the substrate is placed in a metal organic vapor phase epitaxy (MOVPE) reactor for epitaxy of the LED and PD device layers, and the semiconductor layers are grown. In one or more embodiments, metal contact layers, dielectric mirrors, etc. are deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD).

[0028] Here, "sputter deposition" refers to the physical vapor deposition (PVD) of thin films by sputtering. In sputter deposition, materials, for example III-nitrides, are ejected onto a substrate from a source target. This technique is based on ion bombardment of the source material target. In ion bombardment, the gas phase is generated by a purely physical process, namely sputtering of the target material.

[0029] As used in some embodiments of this application, "atomic layer deposition" (ALD) or "cyclic deposition" refers to a gas-phase technique used to deposit thin films on a substrate surface. The ALD process involves exposing a surface of a substrate, or a portion of a substrate, to alternating precursors, i.e., two or more reactive compounds, to deposit layers of material on the substrate surface. When the substrate is exposed to alternating precursors, the precursors are introduced sequentially or simultaneously. The precursors are introduced into a reaction zone of a processing chamber, and the substrate, or a portion of the substrate, is exposed to the precursors separately.

[0030] As used herein, "chemical vapor deposition" refers to a process in which a film of material is deposited from the gas phase by decomposition of chemicals at the substrate surface. In CVD, the substrate surface is exposed to precursors and / or co-chemicals simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either a co-flow or when there is a significant overlap of precursor exposure.

[0031] As used in some embodiments, "plasma-enhanced atomic layer deposition (PEALD)" refers to a technique for depositing thin films on a substrate. In some examples of PEALD processes, materials may be formed from the same chemical precursors as in thermal ALD processes, but at higher deposition rates and lower temperatures. In PEALD processes, generally, reactant gases and reactant plasmas are sequentially introduced into a process chamber containing a substrate within the chamber. A first reactant gas is pulsed within the process chamber and adsorbed onto the substrate surface. A reactant plasma is then pulsed within the process chamber and reacts with the first reactant gas to form a deposition material, e.g., a thin film, on the substrate. As with thermal ALD processes, purge steps may be performed between each delivery of reactants.

[0032] As used in one or more embodiments, "plasma-enhanced chemical vapor deposition (PECVD)" refers to a technique for depositing thin films on a substrate. In a PECVD process, source materials in either gas or liquid phase, such as vapors of a gaseous or liquid III-nitride material entrained in a carrier gas, are introduced into a PECVD chamber. A plasma-initiating gas is also introduced into the chamber. When a plasma is generated in the chamber, excited radicals are formed. The excited radicals chemically bond to the surface of a substrate placed in the chamber, forming a desired film thereon.

[0033] In one or more embodiments, the semiconductor layers of the LED 102 and the PD 114 comprise a stack of undoped and doped III-nitride materials. The III-nitride materials may be doped with one or more of silicon (Si), oxygen (O), boron (B), phosphorus (P), germanium (Ge), manganese (Mn), or magnesium (Mg), depending on whether p-type or n-type III-nitride materials are required. In certain embodiments, the semiconductor layers of the LED 102 comprise an n-type layer 110, an active layer 108, and a p-type layer 106, and the semiconductor layers of the PD 114 comprise an n-type layer 118, an active layer 120, and a p-type layer 122.

[0034] In one or more embodiments, the semiconductor layers of the LED 102 and the PD 114 independently have a combined thickness in the range of about 1 μm to about 10 μm, including about 1 μm to about 9 μm, 1 μm to about 8 μm, 1 μm to about 7 μm, 1 μm to about 6 μm, 1 μm to about 5 μm, 1 μm to about 4 μm, 1 μm to about 3 μm, or a combined thickness in the range of 2 μm to about 10 μm, including about 2 μm to about 9 μm, 2 μm to about 8 μm, 2 μm to about 7 μm, 2 μm to about 6 μm, 2 μm to about 5 μm, 2 μm to about 4 μm, 2 μm to about 3 μm, or a combined thickness in the range of 3 μm to about 10 μm, including about 3 μm to about 10 μm, These include about 10 μm, 3 μm to about 9 μm, 3 μm to about 8 μm, 3 μm to about 7 μm, 3 μm to about 6 μm, 3 μm to about 5 μm, 3 μm to about 4 μm, 4 μm to about 10 μm, 4 μm to about 9 μm, 4 μm to about 8 μm, 4 μm to about 7 μm, 4 μm to about 6 μm, 4 μm to about 5 μm, 5 μm to about 10 μm, 5 μm to about 9 μm, 5 μm to about 8 μm, 5 μm to about 7 μm, 5 μm to about 6 μm, 6 μm to about 10 μm, 6 μm to about 9 μm, 6 μm to about 8 μm, 6 μm to about 7 μm, 7 μm to about 10 μm, 7 μm to about 9 μm, or 7 μm to about 8 μm.

[0035] In one or more embodiments, active region 108 is formed between n-type layer 110 and p-type layer 106 of LED 102, and active region 120 is formed between n-type layer 118 and p-type layer 122 of PD 114. Active region 108 and active region 120 may comprise any suitable material known to those of skill in the art. In one or more embodiments, active region 108 and active region 120 are independently composed of multiple quantum wells (MQWs) of III-nitride materials.

[0036] In one or more embodiments, light emitting diode (LED) 102 has p-contact 104 and n-contact 112, and photodiode (PD) has p-contact 124 and n-contact 126. In one or more embodiments, p-contact 104, n-contact 112, p-contact 124, and n-contact 126 independently comprise a metal selected from the group consisting of titanium (Ti), aluminum (Al), chromium (Cr), silver (Ag), gold (Ag), and alloys or multilayers thereof.

[0037] The junctions of the LED 102 and the PD 114 are separated by a semi-insulating layer 116. The semi-insulating layer 116 may comprise one or more of gallium nitride (GaN) or AlGaN. Similar to GaN power electronic structures, metal doping, such as iron (Fe) doping, may be used in the semi-insulating layer 116.

[0038] In one or more embodiments, a primary consideration in the design shown in FIG. 1 is the high resistivity of p-GaN, necessitating either a continuous contact layer or a dense array of contact vias to achieve good lateral current spreading. For high-power LEDs, this is typically achieved by growing the p-side of the LED on top and forming a contact thereon. For one or more embodiments of optical transformers with two separate junctions, this is more complicated because there are two p-type layers that need to be contacted. In the embodiment shown in FIG. 1, this is accomplished by growing the n-side of the first junction (LED 102) on top and the p-side of the second junction (PD 114) on top. The structure is then processed to deposit and etch the top p-contact 124 and deposit the respective n-contacts 112, 126. Finally, the die 100 is flipped onto a carrier (not shown), and the substrate is lifted off to access the bottom p-layer for the deposition of the second p-contact 104.

[0039] In one or more embodiments, the p-contacts 104, 124 are on the outer surface of the die 100, so that they both act as contacts and reflectors for the optical cavity. Silver is commonly used as the contact metal. Reflectivity may be further improved by using a dielectric mirror or DBR in front of the contacts, with a dense array of vias for electrical contact. N-contact materials with low ohmic resistance may include Al, Ag, and Ti alloys, as well as transparent conductive oxides such as ZnO.

[0040] 1 includes a light emitting diode (LED) junction 102, a photodiode (PD) junction 114, and a semi-insulating layer 116 separating the light emitting diode (LED) junction 102 and the photodiode (PD) junction 112. In one or more embodiments, the light emitting diode (LED) junction 102, the photodiode (PD) junction 114, and the semi-insulating layer 116 are vertically stacked. In some embodiments, the light emitting diode (LED) junction 102 includes an LED p-type layer 106 on an LED p-contact 104, an LED active region 108 on the LED p-type layer 106, an LED n-type layer 110 on the LED active region 108, and an LED n-contact 112 adjacent to the LED n-type layer. In one or more embodiments, the LED n-type layer 110 is in contact with a first side of the semi-insulating layer 116.

[0041] In one or more embodiments, the photodiode (PD) junction 114 of the monolithic optical device 100 includes a PD n-type layer 118 in contact with the second side of the semi-insulating layer 116, a PD active region 120 on the PD n-type layer 118, a PD p-type layer 122 on the PD active region 120, a PD p-contact 124 on the PD p-type layer 122, and a PD n-contact 126 adjacent to the PD n-type layer 118. In one or more embodiments, the PD n-contact 126 and the LED n-contact 112 are on opposite sides of the monolithic optical device 100.

[0042] A drawback of capping the device 100 shown in FIG. 1 with the top p-contact 124 and bottom p-contact 104 is the need to grow either the LED or the PD p-side down. LEDs are typically grown n-side down. Developing a process to efficiently fabricate p-side down structures is challenging. In addition to the challenge of efficiently growing p-side down LEDs, forming a good p-contact to p-type GaN after dry etching or laser lift-off is also challenging due to nonradiative recombination caused by the introduction of Mg into the active region, which results in a surface that converts to n-type GaN after these processes.

[0043] In the embodiment shown in FIG. 2, this problem is solved by growing both the LED 152 and the PD 164 n-side down and adding a tunnel junction and a second intermediate n-type layer to the p-side of the first device to enable efficient current spreading. In one or more embodiments, separate junctions for the LED 152 and the PD 164 are used, grown vertically in a single monolithic layer. In one or more embodiments, the LED 152 and the PD 164 have semiconductor layers comprising III-nitride materials. In some embodiments, the semiconductor layers of the LED 152 and the PD 164 include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), etc. In one or more embodiments, the semiconductor layers of the LED 152 include a p-type layer 156, an active region 158, and a first n-type layer 160. Referring to FIG. 2 , in one or more embodiments, a tunnel junction 180 is used, with the p-side of the first junction capped with a second n-type layer 182 to allow efficient current spreading. As used herein, the term “tunnel junction” refers to a structure in which, under reverse bias, electrons can tunnel from the valence band of the p-type layer to the conduction band of the n-type layer. As the electrons tunnel, holes are left behind in the p-type layer, and carriers are generated in both layers. Thus, in an electronic device such as a diode, a large current can flow through a tunnel junction under reverse bias because the leakage current that flows under reverse bias is small. The tunnel junction requires a specific alignment of the conduction and valence bands at the p / n tunnel junction, which is typically achieved in other material systems using extremely high doping (e.g., p++ / n++ junctions in the (Al)GaAs material system). III-nitride materials have an intrinsic polarization, which creates an electric field at heterointerfaces between different alloy compositions, and this polarization field can be used to achieve the band alignment necessary for tunneling.

[0044] In one or more embodiments, the active region 158 separates the p-type layer 156 from the first n-type layer 160. In particular embodiments, the first n-type layer 160, the second n-type layer 182, and the p-type layer 156 of the LED 152 comprise n-doped and p-doped GaN. The semiconductor layers of the LED 152 (i.e., the p-type layer 156, the active region 158, the first n-type layer 160, and the second n-type layer 182) are on the n-contact 162. The LED 152 has a p-contact 154 and an n-contact 162.

[0045] In one or more embodiments, the semiconductor layers of PD 164 include an n-type layer 168, an active region 170, and a p-type layer 172. The active region 170 separates the p-type layer 172 from the n-type layer 168. In particular embodiments, the n-type layer 168 and the p-type layer 172 of PD 164 include n-doped and p-doped GaN. A p-contact 174 is on the semiconductor layers of PD 164 (i.e., the p-type layer 172, the active region 170, and the n-type layer 168). PD 164 includes a p-contact 174 and an n-contact 176.

[0046] In one or more embodiments, active region 158 is formed between n-type layer 160 and p-type layer 156 of LED 152, and active region 170 is formed between n-type layer 168 and p-type layer 172 of PD 164. Active region 158 and active region 170 may comprise any suitable material known to those of skill in the art. In one or more embodiments, active region 158 and active region 170 are independently composed of multiple quantum wells (MQWs) of III-nitride materials.

[0047] In one or more embodiments, light emitting diode (LED) 152 has p-contact 154 and n-contact 162, and photodiode (PD) 164 has p-contact 174 and n-contact 176. In some embodiments, n-contact 162 of LED 152 is a reflective layer. In one or more embodiments, p-contact 154, n-contact 162, p-contact 174, and n-contact 176 independently comprise a metal selected from the group consisting of titanium (Ti), aluminum (Al), chromium (Cr), silver (Ag), gold (Ag), and alloys or multilayers thereof.

[0048] The junctions of the LED 152 and the PD 164 are separated by a semi-insulating layer 166. The semi-insulating layer 166 may comprise one or more of gallium nitride (GaN) or AlGaN. Similar to GaN power electronic structures, metal doping, for example, iron (Fe) doping, may be used in the semi-insulating layer 166.

[0049] 2 includes a light emitting diode (LED) junction 152, a photodiode (PD) junction 164, and a semi-insulating layer 166 separating the light emitting diode (LED) junction 152 and the photodiode (PD) junction 164. In one or more embodiments, the light emitting diode (LED) junction 152, the photodiode (PD) junction 164, and the semi-insulating layer 166 are vertically stacked. In some embodiments, the light emitting diode (LED) junction 152 includes an LED n-type layer 160 on an LED n-contact 162. In some embodiments, the LED n-contact 162 may be a reflective layer. In one or more embodiments, an LED active region 158 is on the LED n-type layer 160, an LED p-type layer 156 is on the LED active region 158, an LED tunnel junction 180 is on the LED p-type layer 156, a second LED n-type 182 is on the LED tunnel junction 180, and an LED p-contact 154 is adjacent to the second LED n-type layer 182. In one or more embodiments, the second LED n-type layer 182 is in contact with the first side of the semi-insulating layer 166.

[0050] In one or more embodiments, the photodiode (PD) junction 114 of the monolithic optical device 100 includes a PD n-type layer 118 in contact with the second side of the semi-insulating layer 116, a PD active region 120 on the PD n-type layer 118, a PD p-type layer 122 on the PD active region 120, a PD p-contact 124 on the PD p-type layer 122, and a PD n-contact 126 adjacent to the PD n-type layer 118. In one or more embodiments, the PD n-contact 126 and the LED n-contact 112 are on opposite sides of the monolithic optical device 100.

[0051] In one or more embodiments, the semi-insulating layer 166 in Figure 2 may be omitted, forming a shared contact arrangement as shown in Figure 3, where the shared contact 186 to the middle n-type layer 184 serves as both the n-contact for the PD 164 and the p-contact for the LED 152. The embodiment shown in Figure 3 does not provide galvanic isolation, but may be useful for voltage up-conversion or down-conversion when galvanic isolation is not required.

[0052] 2, in the device 150 of FIG. 3, the separate junctions of the LED 152 and the PD 164 are grown vertically in a single monolithic layer. In one or more embodiments, the LED 152 and the PD 164 have semiconductor layers comprising III-nitride materials. In some embodiments, the semiconductor layers of the LED 152 and the PD 164 comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), etc.

[0053] In one or more embodiments, the semiconductor layers of the LED 152 include a p-type layer 156, an active region 158, and a first n-type layer 160. Referring to Figure 3, in one or more embodiments, a tunnel junction 180 is used, where the p-side of the first junction is capped with a second intermediate n-type layer 184 to allow for efficient current spreading. In one or more embodiments, the second intermediate n-type layer 184 is shared by the LED 152 and the PD 164.

[0054] In one or more embodiments, the active region 158 separates the p-type layer 156 from the first n-type layer 160. In particular embodiments, the first n-type layer 160, the second intermediate n-type layer 184, and the p-type layer 156 of the LED 152 comprise n-doped and p-doped GaN. The semiconductor layers of the LED 152 (i.e., the p-type layer 156, the active region 158, and the first n-type layer 160) are on an n-contact 162. In one or more embodiments, the n-contact 162 may be a reflective layer. The LED 152 has a p-contact 154 and an n-contact 162.

[0055] In one or more embodiments, the semiconductor layers of PD 164 include an n-type layer 168, an active region 170, and a p-type layer 172. The active region 170 separates the p-type layer 172 from the n-type layer 168. In particular embodiments, the n-type layer 168 and the p-type layer 172 of PD 164 include n-doped and p-doped GaN. A p-contact 174 is on the semiconductor layers of PD 164 (i.e., the p-type layer 172, the active region 170, and the n-type layer 168). PD 164 includes a p-contact 174 and an n-contact 176.

[0056] In one or more embodiments, active region 158 is formed between n-type layer 160 and p-type layer 156 of LED 152, and active region 170 is formed between n-type layer 168 and p-type layer 172 of PD 164. Active region 158 and active region 170 may comprise any suitable material known to those of skill in the art. In one or more embodiments, active region 158 and active region 170 are each independently composed of multiple quantum wells (MQWs) of III-nitride materials.

[0057] In one or more embodiments, light emitting diode (LED) 152 has p-contact 154 and n-contact 162, and photodiode (PD) 164 has p-contact 174 and n-contact 176. In some embodiments, n-contact 162 of LED 152 is a reflective layer. In one or more embodiments, p-contact 154, n-contact 162, p-contact 174, and n-contact 176 independently comprise a metal selected from the group consisting of titanium (Ti), aluminum (Al), chromium (Cr), silver (Ag), gold (Ag), and alloys or multilayers thereof.

[0058] 3 has a light emitting diode (LED) junction 152, a photodiode (PD) junction 164, and a semi-insulating layer 166 separating the light emitting diode (LED) junction 152 and the photodiode (PD) junction 164. In one or more embodiments, the light emitting diode (LED) junction 152, the photodiode (PD) junction 164, and the semi-insulating layer 166 are vertically stacked.

[0059] In some embodiments, the light emitting diode (LED) junction 152 of the monolithic optical device 150 has an LED n-type layer 160 on an LED n-contact 162. In some embodiments, the LED n-contact 162 may be a reflective layer. In one or more embodiments, the LED active region 158 is on the LED n-type layer 160, the LED p-type layer 156 is on the LED active region 158, the LED tunnel junction 180 is on the LED p-type layer 156, and a second LED n-type junction 184 is on the LED tunnel junction 180, with the contact adjacent to the second LED n-type layer 184. In one or more embodiments, the contact 186 is shared by the light emitting diode (LED) junction 152 and the photodiode (PD) junction 164. In one or more embodiments, the contact 186 functions as the n-contact for the photodiode (PD) junction 164 and as the p-contact for the light emitting diode (LED) junction 152. In one or more embodiments, the p-type layer 156 of the LED contacts a first side of the tunnel junction 180 and the n-type layer 184 of the second LED contacts a second side of the tunnel junction 180 .

[0060] In one or more embodiments, the photodiode (PD) junction 164 of the monolithic optical device 150 has a PD active region 170 on a second LED n-type layer 184, a PD p-type layer 172 on the PD active region 170, a PD p-contact 174 on the PD p-type layer 172, and a contact adjacent to the LED n-type layer 186.

[0061] In one or more embodiments, several contact configurations may be used to optimize device characteristics or fabrication methods. The embodiment shown in Figures 1-3 relies on current spreading laterally through the n-GaN layer, which is fairly efficient at low current densities but can result in significant current crowding and resulting droop as the current density increases.

[0062] 4, n-vias 202, 204 are etched through the p-layer 208 into the respective n-layers 212, 216 to allow for more uniform current injection and extraction. This results in a flip-chip device in which the bottom p-contact 206 and n-contacts 224, 226 are directly interconnected to a submount (not shown) and the top p-contact 222 is wire-bonded.

[0063] 4, the separate junctions of LED 230 and PD 232 are grown vertically in a single monolithic layer. In one or more embodiments, LED 230 and PD 232 have semiconductor layers comprising III-nitride materials. In some embodiments, the semiconductor layers of LED 230 and PD 232 comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), etc.

[0064] In one or more embodiments, the semiconductor layers of the LED 230 include a p-type layer 208, an active region 210, and an n-type layer 212. In one or more embodiments, the active region 210 separates the p-type layer 208 from the n-type layer 212. In particular embodiments, the n-type layer 212 and the p-type layer 208 of the LED 230 include n-doped and p-doped GaN. The semiconductor layers of the LED 230 (i.e., the p-type layer 208, the active region 210, and the n-type layer 212) are on the p-contact 206. The LED 202 has a via 202 etched through the p-type layer 208 and into the n-type layer 212. The LED 202 has a p-contact 206 and n-contacts 224, 226. In one or more embodiments, the n-contacts 224, 226 are in electrical contact with the p-contact 206.

[0065] In one or more embodiments, the semiconductor layers of the PD 232 include an n-type layer 216, an active region 218, and a p-type layer 220. The active region 218 separates the p-type layer 220 from the n-type layer 216. In certain embodiments, the n-type layer 216 and the p-type layer 220 of the PD 232 include n-doped and p-doped GaN. A p-contact 222 is on the semiconductor layers of the PD 232 (i.e., the p-type layer 220, the active region 218, and the n-type layer 216). In one or more embodiments, the PD 232 includes a via 204 etched through the p-type layer 208 of the LED and into the n-type layer 216 of the PD 232. The PD 232 includes a p-contact 222 and n-contacts 224, 226. In one or more embodiments, the n-contacts 224, 226 are in electrical contact with the p-contact 206 of the LED 230.

[0066] In one or more embodiments, active region 210 is formed between n-type layer 212 and p-type layer 208 of LED 230, and active region 218 is formed between n-type layer 216 and p-type layer 220 of PD 232. Active region 210 and active region 218 may comprise any suitable material known to those of skill in the art. In one or more embodiments, active region 210 and active region 218 are each independently composed of multiple quantum wells (MQWs) of III-nitride materials.

[0067] In one or more embodiments, the light emitting diode (LED) 230 has a p-contact 206 and n-contacts 224, 226, and the photodiode (PD) 232 has a p-contact 222 and n-contacts 224, 226. In one or more embodiments, the p-contact 206, the n-contacts 224, 226, and the p-contact 222 independently comprise a metal selected from the group consisting of titanium (Ti), aluminum (Al), chromium (Cr), silver (Ag), gold (Ag), and alloys or multilayers thereof.

[0068] The junctions of the LED 230 and the PD 232 are separated by a semi-insulating layer 214. The semi-insulating layer 214 may comprise one or more of gallium nitride (GaN) or AlGaN. Similar to GaN power electronic structures, metal doping, for example, iron (Fe) doping, may be used in the semi-insulating layer 214.

[0069] 4 includes a light emitting diode (LED) junction 230, a photodiode (PD) junction 232, and a semi-insulating layer 214 separating the light emitting diode (LED) junction 230 and the photodiode (PD) junction 232. In one or more embodiments, the light emitting diode (LED) junction 230, the photodiode (PD) junction 232, and the semi-insulating layer 214 are vertically stacked. In some embodiments, the light emitting diode (LED) junction 230 includes an LED p-type layer 206 on the LED p-contact 204, an LED active region 210 on the LED p-type layer 208, and an LED n-type layer 212 on the LED active region 210. In one or more embodiments, the LED n-type layer 212 contacts a first side of the semi-insulating layer 214.

[0070] In one or more embodiments, the photodiode (PD) junction 232 of the monolithic optical device 200 of FIG. 4 includes a PD n-type layer 216 in contact with the second side of the semi-insulating layer 214, a PD active region 218 on the PD n-type layer 216, a PD p-type layer 220 on the PD active region 218, and a PD p-contact 222 on the PD p-type layer 220.

[0071] 4 has a first via 202 etched into the n-type layer 212 of the LED and a second via 204 etched into the n-type layer 216 of the PD. In one or more embodiments, at least one contact 224, 226 is in the first via 202 and at least one contact 224, 226 is in the second via.

[0072] In one or more embodiments, the bottom contact may be provided through a conductive substrate, eliminating the need to lift-off the device from the substrate for contact deposition. However, growth substrates generally do not have the high reflectivity required for efficient devices. Therefore, in one or more embodiments, this issue can be addressed by growing a conductive distributed Bragg reflector (DBR) 340 as part of the device structure, as shown in FIG. 5. The DBR 340 may be formed by III-nitride layers of different compositions or by a mesoporous structure.

[0073] 5, separate junctions for LED 332 and PD 334 are vertically grown in a single monolithic layer. In one or more embodiments, LED 332 and PD 334 have semiconductor layers comprising III-nitride materials. In some embodiments, the semiconductor layers of LED 332 and PD 334 comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), etc.

[0074] In one or more embodiments, the semiconductor layers of the LED 332 include a p-type layer 346, an active region 344, a first n-type layer 338, a second n-type layer 342, a third n-type layer 350, and a tunnel junction 348. In one or more embodiments, the active region 344 separates the p-type layer 346 from the second n-type layer 342. In certain embodiments, the p-type layer 346, the active region 344, the first n-type layer 338, the second n-type layer 342, and the third n-type layer 350 of the LED 332 include n-doped and p-doped GaN. The semiconductor layers of the LED 332 (i.e., the p-type layer 346, the active region 344, the first n-type layer 338, the second n-type layer 342, and the third n-type layer 350) are on the n-contact 336 or on a substrate. The LED 332 has a tunnel junction 340 between a first n-type layer 338 and a second n-type layer 342. The LED 332 has a p-contact 364 and an n-contact 336.

[0075] In one or more embodiments, the semiconductor layers of PD 334 include an n-type layer 354, an active region 358, and a p-type layer 360. The active region 358 separates the p-type layer 360 from the n-type layer 354. In particular embodiments, the n-type layer 354 and the p-type layer 360 of PD 334 include n-doped and p-doped GaN. A p-contact 362 is on the semiconductor layers of PD 334 (i.e., the p-type layer 360, the active region 358, and the n-type layer 354). In one or more embodiments, PD 334 includes a p-contact 362 and an n-contact 356.

[0076] In one or more embodiments, active region 344 is formed between second n-type layer 342 and p-type layer 346 of LED 332, and active region 358 is formed between n-type layer 354 and p-type layer 360 of PD 334. Active region 344 and active region 358 may comprise any suitable material known to those of skill in the art. In one or more embodiments, active region 344 and active region 358 are each independently composed of multiple quantum wells (MQWs) of III-nitride materials.

[0077] In one or more embodiments, light emitting diode (LED) 332 has p-contact 364 and n-contact 336, and photodiode (PD) 334 has p-contact 362 and n-contact 356. In one or more embodiments, p-contact 364, n-contacts 336, 356, and p-contact 362 independently comprise a metal selected from the group consisting of titanium (Ti), aluminum (Al), chromium (Cr), silver (Ag), gold (Ag), and alloys or multilayers thereof.

[0078] The junctions of the LED 332 and the PD 334 are separated by a semi-insulating layer 352. The semi-insulating layer 352 may comprise one or more of gallium nitride (GaN) or AlGaN. Similar to GaN power electronic structures, metal doping, for example, iron (Fe) doping, may be used in the semi-insulating layer 352.

[0079] 5 has a light emitting diode (LED) junction 332, a photodiode (PD) junction 334, and a semi-insulating layer 352 separating the light emitting diode (LED) junction 332 and the photodiode (PD) junction 334. In one or more embodiments, the light emitting diode (LED) junction 332, the photodiode (PD) junction 334, and the semi-insulating layer 352 are vertically stacked.

[0080] In some embodiments, the light emitting diode (LED) junction 332 has an LED n-type layer 338 on an LED n-contact 336. In some embodiments, the LED n-contact 336 may be a reflective layer. In one or more embodiments, an LED active region 344 is on the LED n-type layer 338, an LED p-type layer 346 is on the LED active region 344, an LED tunnel junction 348 is on the LED p-type layer 346, a second LED n-type layer 350 is on the LED tunnel junction 348, and an LED p-contact 364 is adjacent to the second LED n-type layer 350. In one or more embodiments, the second LED n-type layer 350 contacts a first side of the semi-insulating layer 352.

[0081] In one or more embodiments, the photodiode (PD) junction 334 of the monolithic optical device 330 has a PD n-type layer 354 in contact with the second side of the semi-insulating layer 352, a PD active region 358 on the PD n-type layer 354, a PD p-type layer 360 on the PD active region 358, a PD p-contact 362 on the PD p-type layer 360, and a PD n-contact 356 adjacent to the PD n-type layer 354. In one or more embodiments, the PD n-contact 356 and the LED n-contact 364 are on opposite sides of the monolithic optical device 330.

[0082] In one or more embodiments, a distributed Bragg reflector 340 and a third LED n-type layer 342 are disposed between the LED first n-type layer 338 and the LED active region 344 .

[0083] In one or more embodiments, voltage up or down conversion can be achieved in the PD or LED, respectively, by connecting multiple junctions in series, which can be done in two ways: at the epi level using tunnel junctions, or at the die level using die segmentation.

[0084] FIG. 6 shows an embodiment of voltage up-conversion with two PD junctions 414a, 414b (multiple quantum well structure) separated by a tunnel junction 430. In one or more embodiments, the device 400 of FIG. 6 provides an output voltage that is approximately twice the input voltage, with the exact voltage determined by the MQW design and the voltage drop across the tunnel junction. Higher output voltages can be achieved by stacking two or more PD junctions. Voltage down-conversion can be achieved by applying the same principle to the LED side.

[0085] 6, separate junctions for the LED 402 and the PD 414 are vertically grown in a single monolithic layer. In one or more embodiments, the LED 402 and the PD 414 have semiconductor layers comprising III-nitride materials. In some embodiments, the semiconductor layers of the LED 402 and the PD 414 comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), etc.

[0086] In one or more embodiments, the semiconductor layers of the LED 402 include a p-type layer 406, an active region 408, and an n-type layer 410. In one or more embodiments, the active region 408 separates the p-type layer 406 from the n-type layer 410. In particular embodiments, the p-type layer 406, the active region 408, and the n-type layer 410 of the LED 402 include n-doped and p-doped GaN. The semiconductor layers of the LED 402 (i.e., the p-type layer 406, the active region 408, and the n-type layer 410) are on a p-contact 404. The LED 402 includes a p-contact 404 and an n-contact 412.

[0087] In one or more embodiments, the semiconductor layers of the PD 414 include a first n-type layer 418, a first active region 420, a first p-type layer 432, a tunnel junction 430, a second n-type layer 434, a second active region 436, and a second p-type layer 422. The first active region 420 separates the first p-type layer 432 from the first n-type layer 418. The second active region 436 separates the second p-type layer 422 from the second n-type layer 434. In particular embodiments, the first n-type layer 418, the first active region 420, the first p-type layer 432, the second n-type layer 434, the second active region 432, and the second p-type layer 422 of the PD 414 include n-doped and p-doped GaN. A p-contact 424 is on the semiconductor layers of the PD 414. In one or more embodiments, the PD 414 has a p-contact 424 and an n-contact 426 .

[0088] In one or more embodiments, the active region 408 is formed between the n-type layer 410 and the p-type layer 406 of the LED 402, the first active region 420 is formed between the first n-type layer 418 and the first p-type layer 432 of the PD 414, and the second active region 436 is formed between the second n-type layer 432 and the second p-type layer 422 of the PD 414. The active regions 408, 420, and 436 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the active regions 408, 420, and 436 are each independently composed of multiple quantum wells (MQWs) of III-nitride materials.

[0089] In one or more embodiments, light emitting diode (LED) 402 has a p-contact 404 and an n-contact 412, and photodiode (PD) 414 has a p-contact 424 and an n-contact 426. In one or more embodiments, p-contact 404, n-contact 412, p-contact 424, and n-contact 426 independently comprise a metal selected from the group consisting of titanium (Ti), aluminum (Al), chromium (Cr), silver (Ag), gold (Ag), and alloys or multilayers thereof.

[0090] The junctions of the LED 402 and the PD 414 are separated by a semi-insulating layer 416. The semi-insulating layer 416 may comprise one or more of gallium nitride (GaN) or AlGaN. Similar to GaN power electronic structures, metal doping, for example, iron (Fe) doping, may be used in the semi-insulating layer 416.

[0091] In one or more embodiments, the monolithic optical device 400 has a light emitting diode (LED) junction 402, a first photodiode (PD) junction 414a, a second photodiode (PD) junction 414b, a tunnel junction 430 separating the first photodiode (PD) junction 414 and the second photodiode (PD) junction 414b, and a semi-insulating layer 416 separating the light emitting diode (LED) junction 402 and the first photodiode (PD) junction 414a.

[0092] In one or more embodiments, the light emitting diode (LED) junction 402, the first photodiode (PD) junction 414a, the second photodiode (PD) junction 414b, the tunnel junction 430, and the semi-insulating layer 416 are vertically stacked.

[0093] In one or more embodiments, the light emitting diode (LED) junction 401 of the monolithic optical device 400 shown in FIG. 6 has an LED p-type layer 406 on an LED p-type contact 404, an LED active region 408 on the LED p-type layer 406, an LED n-type layer 410 on the LED active region 408, and an LED n-contact 412 adjacent to the LED n-type layer 410, wherein the LED n-type layer 410 contacts a first side of the semi-insulating layer 416.

[0094] In one or more embodiments, the first photodiode (PD) junction 414 a of the monolithic optical device 400 includes a first PD n-type layer 418 in contact with the second side of the semi-insulating layer 416, a first PD active region 420 on the first PD n-type layer 418, a first PD p-type layer 432 on the first PD active region 420, and a PD n-contact 426 adjacent to the first PD n-type layer 418. In one or more embodiments, the second photodiode (PD) junction 414 b includes a second PD n-type layer 434 on the tunnel junction 430, a second PD active region 436 on the second PD n-type layer 434, a second PD p-type layer 422 on the second PD active region 436, and a PD p-contact 424 on the second PD p-type layer 422.

[0095] FIG. 7 shows an embodiment of voltage up conversion using die segmentation. The PD junction 514 is segmented into segments 530 by etching the active area 520. The segments are then connected in series by wafer-processed contacts, as shown schematically in FIG. 7. Such contact metallization designs are known from high-voltage LEDs. The voltage up conversion factor is approximately equal to the number of segments. Down conversion may be achieved by applying segmentation on the LED side.

[0096] 7, separate junctions for the LED 502 and the PD 514 are vertically grown in a single monolithic layer. In one or more embodiments, the LED 502 and the PD 514 have semiconductor layers comprising III-nitride materials. In some embodiments, the semiconductor layers of the LED 502 and the PD 514 comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN), etc.

[0097] In one or more embodiments, the semiconductor layers of the LED 502 include a p-type layer 506, an active region 508, and an n-type layer 510. In one or more embodiments, the active region 508 separates the p-type layer 506 from the n-type layer 510. In particular embodiments, the p-type layer 506, the active region 508, and the n-type layer 510 of the LED 502 include n-doped and p-doped GaN. The semiconductor layers of the LED 502 (i.e., the p-type layer 506, the active region 508, and the n-type layer 510) are on a p-contact 504. The LED 502 includes a p-contact 504 and an n-contact 512.

[0098] In one or more embodiments, the semiconductor layers of the PD 514 include an n-type layer 518, an active region 520, and a p-type layer 522. The active region 520 separates the p-type layer 522 from the n-type layer 518. In particular embodiments, the n-type layer 518, the active region 520, and the p-type layer 522 of the PD 514 include n-doped and p-doped GaN. A p-contact 536 is on the semiconductor layers of the PD 514. In one or more embodiments, the PD 514 includes a p-contact 536 and an n-contact 526.

[0099] In one or more embodiments, active region 508 is formed between n-type layer 510 and p-type layer 506 of LED 502, and active region 520 is formed between n-type layer 518 and p-type layer 522 of PD 514. Active regions 508, 520 may comprise any suitable material known to those skilled in the art. In one or more embodiments, active regions 508, 520 are each independently comprised of multiple quantum wells (MQWs) of III-nitride materials.

[0100] In one or more embodiments, light emitting diode (LED) 502 has a p-contact 504 and an n-contact 512, and photodiode (PD) 514 has a p-contact 536 and an n-contact 526. In one or more embodiments, p-contact 504, n-contact 512, p-contact 536, and n-contact 526 each independently comprise a metal selected from the group consisting of titanium (Ti), aluminum (Al), chromium (Cr), silver (Ag), gold (Ag), and alloys or multilayers thereof.

[0101] The junctions of the LED 502 and the PD 514 are separated by a semi-insulating layer 516. The semi-insulating layer 516 may comprise one or more of gallium nitride (GaN) or AlGaN. Similar to GaN power electronic structures, metal doping, for example, iron (Fe) doping, may be used in the semi-insulating layer 516.

[0102] 7 includes a light emitting diode (LED) junction 502, a photodiode (PD) junction 514, and a semi-insulating layer 516 separating the light emitting diode (LED) junction 502 and the photodiode (PD) junction 514. In one or more embodiments, the light emitting diode (LED) junction 502, the photodiode (PD) junction 514, and the semi-insulating layer 516 are vertically stacked. In some embodiments, the light emitting diode (LED) junction 502 includes an LED p-type layer 506 on an LED p-contact 510, an LED active region 508 on the LED p-type layer 506, an LED n-type layer 510 on the LED active region 508, and an LED n-contact 512 adjacent to the LED n-type layer. 504 In one or more embodiments, the LED n-type layer 510 contacts a first side of the semi-insulating layer 516.

[0103] As shown in FIG. 7, in one or more embodiments, the photodiode (PD) junction 514 of the monolithic optical device 500 is segmented into multiple photodiode (PD) mesas 530 separated by trenches 538 .

[0104] In one or more embodiments, each of the plurality of photodiode (PD) mesas 530 has a PD n-type layer 518 in contact with the second side of the semi-insulating layer 516, a PD active region 520 on the PD n-type layer 518, a PD p-type layer 522 on the PD active region 520, and a PD p-contact 536 on the PD p-type layer 522. In one or more embodiments, at least one contact 532, 534 is disposed in the trench 538. The at least one contact 532, 534 may be a conformal contact.

[0105] In another embodiment, the same junction (MQW structure) is used for both the LED and PD, as shown in Figure 8. In the device 600 of Figure 8, the n-side is used as a common cathode 602 and relies on the high resistivity of p-GaN 610 to form separate anodes 612, 614 for the PD and LED, respectively. In the embodiment shown in Figure 8, there is no galvanic isolation because the cathode 602 is shared, but voltage up- or down-conversion can be achieved by using a tunnel junction stack design, in which case additional junctions are etched away in the areas where the LED or PD anodes will be deposited.

[0106] 8 requires that light generated in the LED portion of the junction spread laterally to the PD portion of the junction. To minimize the number of internal reflections and optimize device efficiency, in one or more embodiments, the LED anode 614 and the PD anode 612 are densely interwined with one another. In one or more embodiments, the center-to-center spacing d between the LED anode 614 and the PD anode 612 may be less than 20 times, less than 10 times, or less than 5 times the thickness t of the device 600.

[0107] 8, a single MQW structure serves both the LED and PD functions, so the MQW design must consider both modes of operation. The MQW can be designed (by doping profile and structure) such that the active region structure 608 within the depletion region during operation differs between LED and PD operation, providing some ability to independently optimize LED and PD operation.

[0108] In one or more embodiments, the monolithic optical device 600 has a junction segmented into multiple mesas 616 on a common cathode 602. In one or more embodiments, the junction has an n-type layer 604 on the common cathode 602, an active region 608 on the n-type layer 604, and a p-type layer 610 on the active region 608. In one or more embodiments, each of the multiple mesas 616 is separated by a trench 620. In one or more embodiments, an anode 612, 614 is disposed on the p-type layer 610 of each of the multiple mesas 616. In one or more embodiments, the anodes 612, 614 are arranged alternately between photodiode (PD) anodes 612 and light emitting diode (LED) anodes 614.

[0109] In one or more embodiments, as shown in FIG. 8, the distance d between the light emitting diode (LED) anode 614 and the photodiode (PD) anode 612 of the monolithic optical device 60 is less than 20 times the thickness t of the monolithic optical device 600.

[0110] 9 shows an energy band diagram of MQWs with different designs for the QWs in the depletion region of a photodiode and the QWs in the depletion region of an LED. As shown in FIG. 9, in one or more embodiments, the quantum wells 706 in the PD depletion region 702 but outside the LED depletion region 704 have lower energy, which may facilitate photon absorption.

[0111] In one or more embodiments, the same junction (MQW structure) is used for both the LED and PD, as shown in Figure 10. The device 800 of Figure 10 uses a single multiple quantum well 804, allowing for bidirectional operation of the device 800. In one or more embodiments, the high resistivity of p-GaN 802 forms separate anodes 816, 818 for the PD and LED, respectively. Galvanic isolation in the embodiment shown in Figure 10 may be compromised. The n-type layer 806 forms separate cathodes 812, 814 for the PD and LED, respectively.

[0112] 10 requires that light generated at the LED portion of the junction spread laterally to the PD portion of the junction. To minimize the number of internal reflections and optimize device efficiency, in one or more embodiments, the LED anode 818 and the PD anode 816 are closely spaced relative to one another. In one or more embodiments, the center-to-center spacing d between the LED anode 818 and the PD anode 816 may be less than 20 times, less than 10 times, or less than 5 times the thickness of the device 600.

[0113] In designs such as that shown in Figure 10, where a single MQW structure serves both the LED and PD functions, the MQW design must account for both modes of operation. The MQWs can be designed (by doping profile and structure) such that the active region structure 804 within the operating depletion region differs between LED and PD operation, providing some ability for LED and PD operation to be independently optimized. For example, the PD depletion region may extend beyond the LED depletion region, and the QWs in the extending depletion region may have lower energy to aid in photon absorption in the PD.

[0114] 10 , in one or more embodiments, the monolithic optical device 800 has a junction segmented into multiple mesas 816 on multiple alternating photodiode (PD) anode 816 and light emitting diode (LED) anode regions 818. In one or more embodiments, the junction has a p-type layer 802 on the multiple alternating photodiode (PD) anode 816 and light emitting diode (LED) anode regions 818, an active region 804 on the p-type layer 802, and an n-type layer 806 on the active region 804. In one or more embodiments, each of the multiple mesas 816 is separated by a trench 820. In one or more embodiments, a cathode 812, 814 is disposed on the n-type layer 806 of each of the multiple mesas 816. The cathodes 812, 814 are disposed alternately between the photodiode (PD) cathodes 812 and the light emitting diode (LED) cathodes 814.

[0115] Additional embodiments may be formed by combining the aforementioned elements. Furthermore, while the junctions are described as LEDs and PDs, it should be understood that they are generally interchangeable, i.e., either the LED or PD structure can be grown first. Also, with suitable MQW designs, the device can operate bidirectionally, with either junction functioning as an LED or PD, depending on the external bias.

[0116] (Embodiment) Various embodiments are described below, and it is understood that the embodiments described below may be combined with all aspects and other embodiments in accordance with the scope of the present invention.

[0117] Embodiment (a) 1. A monolithic optical device comprising: a light-emitting diode (LED) junction; a first photodiode (PD) junction; a second photodiode (PD) junction; a tunnel junction separating the first photodiode (PD) junction and the second photodiode (PD) junction; a semi-insulating layer separating the light emitting diode (LED) junction and a first photodiode (PD) junction; and a light-emitting diode (LED) junction, a first photodiode (PD) junction, a second photodiode (PD) junction, a tunnel junction, and a semi-insulating layer, the light-emitting diode (LED) junction, a first photodiode (PD) junction, a second photodiode (PD) junction, the tunnel junction, and the semi-insulating layer being vertically stacked;

[0118] Embodiment (b) the light emitting diode (LED) junction includes an LED p-type layer on an LED p-contact, an LED active region on the LED p-type layer, an LED n-type layer on the LED active region, and an LED n-contact adjacent to the LED n-type layer; The monolithic optical device of embodiment (a), wherein the n-type layer of the LED contacts the first side of the semi-insulating layer.

[0119] Embodiment (c) the first photodiode (PD) junction includes a first PD n-type layer in contact with the second side of the semi-insulating layer, a first PD active region on the first PD n-type layer, a first PD p-type layer on the first PD active region, and a PD n-contact adjacent to the first PD n-type layer; The monolithic optical device of embodiments (a)-(b), wherein the second photodiode (PD) junction comprises a second PD n-type layer on the tunnel junction, a second PD active region on the second PD n-type layer, a second PD p-type layer on the second PD active region, and a PD p-contact on the second PD p-type layer.

[0120] Embodiment (d) A method of manufacturing the monolithic optical device of any one of embodiments (a) to (c), comprising the steps of: forming a light emitting diode (LED) junction on the substrate; forming a semi-insulating layer over the light emitting diode (LED) junction; forming a first photodiode (PD) junction on the semi-insulating layer; forming a tunnel junction on the first photodiode (PD) junction; forming a second photodiode (PD) junction on the tunnel junction to form a vertically stacked monolithic optical device; A method comprising:

[0121] Embodiment (e) The step of forming a light emitting diode (LED) junction includes: forming a p-type layer of an LED on a p-contact of the LED; forming an LED active region on the p-type layer of the LED; forming an n-type LED layer on the LED active region; forming an LED n-contact adjacent the LED n-type layer; and The method of embodiment (d), wherein the n-type layer of the LED contacts the first side of the semi-insulating layer.

[0122] Embodiment (f) The step of forming the first photodiode (PD) junction includes: forming a first PD n-type layer in contact with a second side of the semi-insulating layer; forming a first PD active region on the n-type layer of the first PD; forming a first PD p-type layer on the first PD active region; forming a PD n-contact adjacent the first PD n-type layer; The method of any one of embodiments (d) to (e), comprising:

[0123] Embodiment (g) The step of forming the second photodiode (PD) junction includes: forming an n-type layer of a second PD on the tunnel junction; forming a second PD active region on the n-type layer of the second PD; forming a p-type layer of a second PD on the second PD active region; forming a PD p-contact on the p-type layer of the second PD; The method of any one of embodiments (d) to (f), comprising:

[0124] Embodiment (h) 1. A monolithic optical device comprising: a junction segmented into multiple mesas on a common cathode; an anode on each of the plurality of mesas, the anode alternating between a photodiode (PD) anode and a light emitting diode (LED) anode; A monolithic optical device comprising:

[0125] Embodiment (i) The monolithic optical device of embodiment (h), wherein the junction comprises an n-type layer on a common cathode, an active region on the n-type layer, a p-type layer on the active region, and each of a plurality of mesas separated by trenches.

[0126] Embodiment (j) The monolithic optical device of any one of embodiments (h) to (i), wherein an anode is on the p-type layer of each of the plurality of mesas.

[0127] Embodiment (k) The monolithic optical device of any one of embodiments (h) to (j), wherein the distance between the light emitting diode (LED) anode and the photodiode (PD) anode is less than 20 times the thickness of the monolithic optical device.

[0128] Embodiment (l) A method for manufacturing a monolithic optical device according to any one of embodiments (h) to (k), comprising the steps of: The method comprises: forming a plurality of mesa segmented junctions on a common cathode; forming an anode on each of the plurality of mesas, alternating between a photodiode (PD) anode and a light emitting diode (LED) anode; A method comprising:

[0129] Embodiment (m) The step of forming the joint comprises: forming an n-type layer on the common cathode; forming an active region on the n-type layer; forming a p-type layer on the active region; and forming the plurality of mesas separated by trenches; 2. The method of claim 1, wherein

[0130] Embodiment (n) The method of any one of embodiments (1) to (m), wherein the anode is formed on the p-type layer of each of the mesas.

[0131] Embodiment (o) 1. A monolithic optical device comprising: a plurality of mesa-segmented junctions on a plurality of alternating photodiode (PD) anode regions and light emitting diode (LED) anode regions; a cathode on each of the plurality of mesas, the cathode alternating between the photodiode (PD) cathode and the light emitting diode (LED) cathode; A monolithic optical device comprising:

[0132] Embodiment (p) 10. The monolithic optical device of embodiment (o), wherein the junction includes a p-type layer on a plurality of alternating photodiode (PD) anode regions and light emitting diode (LED) anode regions, an active region on the p-type layer, an n-type layer on the active region, and each of the plurality of mesas separated by trenches.

[0133] Embodiment (q) The monolithic device of any one of embodiments (o) to (p), wherein the cathode is on the n-type layer of each of the mesas.

[0134] Embodiment (r) A method for manufacturing a monolithic optical device according to any one of embodiments (o) to (q), comprising the steps of: forming junctions on a plurality of alternating photodiode (PD) anode regions and light emitting diode (LED) anode regions, the junctions being segmented into a plurality of mesas; forming a cathode on each of the plurality of mesas, the cathodes alternating between photodiode (PD) cathodes and light emitting diode (LED) cathodes; A method comprising:

[0135] Embodiment(s) The step of forming the joint comprises: forming a p-type layer on a plurality of alternating photodiode (PD) anode regions and light emitting diode (LED) anode regions; forming an active region on the p-type layer; forming an n-type layer on the active region; forming the plurality of mesas separated by trenches; The method of embodiment (r), comprising:

[0136] Embodiment (t) The method of any one of embodiments (r) through (s), wherein the cathode is formed on the n-type layer of each of the mesas.

[0137] Embodiment (u) 1. A monolithic optical device comprising: a light-emitting diode (LED) junction; a photodiode (PD) junction; a semi-insulating layer separating the light emitting diode (LED) junction and the photodiode (PD) junction; and The light emitting diode (LED) junction, the photodiode (PD) junction, and the semi-insulating layer are vertically stacked in a monolithic optical device.

[0138] Embodiment (v) the light emitting diode (LED) junction includes an LED p-type layer on an LED p-contact, an LED active region on the LED p-type layer, an LED n-type layer on the LED active region, and an LED n-contact adjacent to the LED n-type layer; The monolithic optical device of embodiment (u), wherein the n-type layer of the LED contacts the first side of the semi-insulating layer.

[0139] Embodiment (w) the light emitting diode (LED) junction comprises an LED n-type layer on an LED n-contact, an LED active region on the LED n-type layer, an LED p-type layer on the LED active region, an LED tunnel junction on the LED p-type layer, a second LED n-type layer on the LED tunnel junction, and an LED p-contact adjacent to the second LED n-type layer; The monolithic optical device of embodiment (u), wherein the n-type layer of the second LED contacts the first side of the semi-insulating layer.

[0140] Embodiment (x) The monolithic optical device of any one of embodiments (u) to (w), wherein the photodiode (PD) junction includes a PD n-type layer in contact with the second side of the semi-insulating layer, a PD active region on the PD n-type layer, a PD p-type layer on the PD active region, a PD p-contact on the PD p-type layer, and a PD n-contact adjacent to the PD n-type layer.

[0141] Embodiment (y) The monolithic device of any one of embodiments (u) through (x), further comprising a distributed Bragg reflector and a third n-type layer of an LED on the first n-type layer of the LED.

[0142] Embodiment (z) the light emitting diode (LED) junction includes an LED p-type layer on an LED p-contact, an LED active region on the LED p-type layer, and an LED n-type layer on the LED active region; an n-type layer of the LED in contact with a first side of the semi-insulating layer; The monolithic optical device of embodiment (u), wherein the photodiode (PD) junction includes a PD n-type layer in contact with the second side of the semi-insulating layer, a PD active region on the PD n-type layer, a PD p-type layer on the PD active region, and a PD p-contact on the PD p-type layer.

[0143] Embodiment (aa) The monolithic optical device of any one of embodiments (u) to (z), further comprising a first via etched into the n-type layer of the LED and a second via etched into the n-type layer of the PD.

[0144] Embodiment (bb) The monolithic optical device of any one of embodiments (u) to (aa), further comprising at least one contact in the first via and at least one contact in the second via.

[0145] Embodiment (cc) The monolithic optical device of embodiment (v), wherein the photodiode (PD) junction is segmented into multiple photodiode (PD) mesas by trenches.

[0146] Embodiment (dd) The monolithic optical device of embodiment (cc), wherein each of the plurality of photodiode (PD) mesas has a PD n-type layer in contact with the second side of the semi-insulating layer, a PD active region on the PD n-type layer, a PD p-type layer on the PD active region, and a PD p-contact on the PD p-type layer.

[0147] Embodiment (ee) The monolithic optical device of any one of embodiments (cc) to (dd), further comprising a contact in the trench.

[0148] Embodiment (ff) 1. A monolithic optical device comprising: a light-emitting diode (LED) junction; a photodiode (PD) junction; A tunnel junction and a contact shared by the light emitting diode (LED) junction and the photodiode (PD) junction; and The light emitting diode (LED) junction, the photodiode (PD) junction, and the tunnel junction are vertically stacked in a monolithic optical device.

[0149] Embodiment (gg) the light emitting diode (LED) junction comprises an LED n-type layer on an LED n-contact, an LED active region on the LED n-type layer, an LED p-type layer on the LED active region, an LED tunnel junction on the LED p-type layer, and a second LED n-type layer on the LED tunnel junction; The monolithic optical device of embodiment (ff), wherein the contact is adjacent to an n-type layer of the second LED.

[0150] Embodiment (hh) the photodiode (PD) junction includes a PD active region on the second LED n-type layer, a PD p-type layer on the PD active region, and a PD p-contact on the PD p-type layer; The monolithic optical device of any one of embodiments (ff) to (gg), wherein the contact is adjacent to an n-type layer of the LED.

[0151] Embodiment (ii) 1. A method for manufacturing a monolithic optical device, comprising: forming a light emitting diode (LED) junction on the substrate; forming a semi-insulating layer over the light emitting diode (LED) junction; forming a photodiode (PD) junction on the semi-insulating layer to form a vertically stacked monolithic optical device; A method comprising:

[0152] Embodiment (jj) The step of forming a light emitting diode (LED) junction includes: forming a p-type layer of an LED on a p-contact of the LED; forming an LED active region on the p-type layer of the LED; forming an n-type LED layer on the LED active region; forming an LED n-contact adjacent the LED n-type layer; and The method of embodiment (ii), wherein an n-type layer of the LED contacts the first side of the semi-insulating layer.

[0153] Embodiment (kk) The step of forming a light emitting diode (LED) junction includes: forming an n-type layer of an LED on the n-contact of the LED; forming an LED active region on the n-type layer of the LED; forming a p-type layer of an LED on the LED active region; forming an LED tunnel junction on a p-type layer of the LED; forming an n-type layer of a second LED on the LED tunnel junction; forming a p-contact of an LED adjacent the n-type layer of the second LED; and The method of embodiment (ii), wherein the n-type layer of the second LED contacts the first side of the semi-insulating layer.

[0154] Embodiment (ll) The method of embodiment (ii), further comprising segmenting the photodiode (PD) junction into a plurality of photodiode (PD) mesas separated by trenches.

[0155] Embodiment (mm) The method of embodiment (ll) further comprising forming a contact in the trench.

[0156] Embodiment (nn) The step of forming a light emitting diode (LED) junction includes: forming a p-type layer of an LED on a p-contact of the LED; forming an LED active region on the p-type layer of the LED; forming an n-type LED layer on the LED active region, the n-type LED layer contacting a first side of the semi-insulating layer; and The step of forming a photodiode (PD) junction includes: forming an n-type layer of PD in contact with a second side of the semi-insulating layer; forming a PD active region on the PD n-type layer; forming a p-type layer of a PD on the PD active region; forming a PD p-contact on the PD p-type layer; The method of embodiment (ii), comprising:

[0157] Embodiment (oo) The method of any one of embodiments (ii) through (nn), further comprising etching a first via in an n-type layer of the LED and a second via in an n-type layer of the PD.

[0158] In the context of describing the materials and methods discussed herein (particularly in the context of the claims), the use of the terms "a," "an," "the," and similar references are understood to encompass both the singular and the plural unless otherwise indicated or clearly contradicted by context. The recitation of ranges of values herein is merely intended to serve as a shorthand method for referring individually to each separate value falling within that range, unless otherwise indicated, and each separate value is incorporated herein as if individually set forth in the application. All methods described herein can be performed in any suitable order unless otherwise indicated in the application or clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "etc.") provided herein is intended merely to further clarify the materials and methods and does not limit the scope unless otherwise specified. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the disclosed materials and methods.

[0159] Throughout this application, references to terms such as "first," "second," "third," etc. may be used to describe various elements, and these elements should not be limited by these terms. These terms may be used to distinguish one element from another.

[0160] Throughout this application, a reference to a layer, region, or substrate being "on" or extending "on" another element means that it is directly on or extends directly onto the other element, or that intervening elements may be present. When an element is referred to as being "on" or extending "directly onto" another element, there may be no intervening elements present. Furthermore, when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element and / or may be connected or coupled to the other element via one or more intervening elements. When an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements between the element and the other element. It is understood that these terms are intended to encompass different orientations of elements in addition to any orientation depicted in the figures.

[0161] Relative terms such as "bottom," "upper," "top," "lower," "horizontal," or "vertical" may be used to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It is understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0162] References throughout this application to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of phrases such as "in one or more embodiments," "a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this application do not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0163] Although the present disclosure has been illustrated with reference to particular embodiments, it is understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Therefore, it is intended that the present disclosure cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A monolithic optical device comprising: a light-emitting diode (LED) junction; a photodiode (PD) junction; a semi-insulating layer separating the light emitting diode (LED) junction and the photodiode (PD) junction; and the light emitting diode (LED) junction, the photodiode (PD) junction, and the semi-insulating layer are vertically stacked; the light emitting diode (LED) junction includes an LED p-type layer on an LED p-contact, an LED active region on the LED p-type layer, and an LED n-type layer on the LED active region; an n-type layer of the LED in contact with a first side of the semi-insulating layer; the photodiode (PD) junction includes a PD n-type layer in contact with the second side of the semi-insulating layer, a PD active region on the PD n-type layer, a PD p-type layer on the PD active region, and a PD p-contact on the PD p-type layer; The monolithic optical device further includes a first via extending from the LED p-contact through the LED p-type layer and the LED active region to the LED n-type layer, and a second via extending from the LED p-contact through the LED junction and the semi-insulating layer to the PD n-type layer.

2. 10. The monolithic optical device of claim 1, wherein the light emitting diode (LED) junction comprises an n-contact of the LED adjacent an n-type layer of the LED.

3. 10. The monolithic optical device of claim 1, wherein the photodiode (PD) junction comprises a PD n-contact adjacent to an n-type layer of the PD.

4. The monolithic optical device of claim 1 , further comprising at least one contact in the first via and at least one contact in the second via.

5. 10. The monolithic optical device of claim 1, wherein the photodiode (PD) junction is segmented into multiple photodiode (PD) mesas by trenches.

6. 6. The monolithic optical device of claim 5, wherein each of the plurality of photodiode (PD) mesas includes a PD n-type layer in contact with the second side of the semi-insulating layer, a PD active region on the PD n-type layer, a PD p-type layer on the PD active region, and a PD p-contact on the PD p-type layer.

7. 1. A monolithic optical device comprising: a light-emitting diode (LED) junction; a photodiode (PD) junction; A tunnel junction and a contact shared by the light emitting diode (LED) junction and the photodiode (PD) junction; and the light emitting diode (LED) junction, the photodiode (PD) junction, and the tunnel junction are vertically stacked; the light emitting diode (LED) junction comprises an LED n-type layer on an LED n-contact, an LED active region on the LED n-type layer, an LED p-type layer on the LED active region, an LED tunnel junction on the LED p-type layer, and a second LED n-type layer on the LED tunnel junction; the contact is adjacent to the n-type layer of the second LED; the photodiode (PD) junction includes a PD active region on an n-type layer of the second LED, a PD p-type layer on the PD active region, and a PD p-contact on the PD p-type layer.

8. 1. A monolithic optical device comprising: a junction segmented into a plurality of mesas on a common cathode, the junction having an n-type layer on the common cathode, an active region on the n-type layer, a p-type layer on the active region, and each of the plurality of mesas separated by a trench; an anode on the p-type layer of each of the plurality of mesas, the anode alternating between a photodiode (PD) anode and a light emitting diode (LED) anode; and The trench extends to the n-type layer but not to the common cathode.

9. 9. The monolithic optical device of claim 8, wherein the distance between the light emitting diode (LED) anode and the photodiode (PD) anode is less than 20 times the thickness of the monolithic optical device.

10. 1. A monolithic optical device comprising: a junction segmented into a plurality of mesas on a plurality of alternating photodiode (PD) anode regions and light emitting diode (LED) anode regions, the junction having a p-type layer on the plurality of alternating photodiode (PD) anode regions and light emitting diode (LED) anode regions, an active region on the p-type layer, an n-type layer on the active region, and each of the plurality of mesas separated by a trench; a cathode on the n-type layer of each of the plurality of mesas, the cathode alternating between a photodiode (PD) cathode and a light emitting diode (LED) cathode; and The monolithic optical device, wherein the trench does not penetrate the p-type layer, and the p-type layer is shared by a photodiode (PD) and a light-emitting diode (LED).

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