Transistors and semiconductor devices

Abstract

A transistor comprises a wide-band-gap semiconductor layer, a gate electrode, a gate pad, and a gate runner. The gate electrode extends to a region in which the gate pad is positioned, and a region in which the gate runner is positioned. The gate pad is connected to the gate electrode. The gate runner is connected to the gate electrode. The gate electrode includes: a first region connected to the gate pad; a second region connected to the gate runner; and a third region and fourth region between the first region and the second region and disposed in mutually differing positions in a first direction. In a cross-section perpendicular to the first direction, the cross-sectional area of the gate electrode in the fourth region is less than the cross-sectional area of the gate electrode in the third region.

Description

[Technical Field]

[0001] The present disclosure relates to transistors and semiconductor devices.

[0002] This application claims priority from Japanese Application No. 2020-60648, filed on March 30, 2020, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0003] BACKGROUND ART A semiconductor device including a plurality of transistor cells is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2015 / 080162 Summary of the Invention

[0005] A transistor according to the present disclosure includes a wide bandgap semiconductor layer including a plurality of transistor cells each having a channel region; a gate insulating film disposed on the wide bandgap semiconductor layer; a gate electrode disposed in a region facing the channel region across the gate insulating film; an interlayer insulating film covering the wide bandgap semiconductor layer, the gate insulating film, and the gate electrode; a gate pad formed of a conductor and disposed on the interlayer insulating film; and a gate runner formed of a conductor and disposed on the interlayer insulating film at a position separate from the gate pad. The gate electrode extends, as viewed in the thickness direction of the wide bandgap semiconductor layer, from a region facing the channel region to a region where the gate pad is located and a region where the gate runner is located. The interlayer insulating film includes a first opening disposed in the region where the gate pad is located and penetrating the interlayer insulating film in the thickness direction, and a second opening disposed in the region where the gate runner is located and penetrating the interlayer insulating film in the thickness direction. The gate pad is connected to the gate electrode by filling the first opening. The gate runner is connected to the gate electrode by filling the second opening. The gate electrode includes a first region connected to the gate pad, a second region connected to the gate runner, and a third region and a fourth region located between the first and second regions and at different positions in a first direction indicated by the direction from the first region to the second region. In a cross section perpendicular to the first direction, the cross-sectional area of the gate electrode in the fourth region is smaller than the cross-sectional area of the gate electrode in the third region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view showing a transistor according to the first embodiment. [Figure 2] FIG. 2 is an enlarged cross-sectional view of a portion of the transistor shown in FIG. [Figure 3] 3 is an enlarged cross-sectional view of the region enclosed by the dashed line in FIG. 1, taken along line III-III in FIG. [Figure 4] 4 is an enlarged cross-sectional view of the region enclosed by the dashed line in FIG. 1, taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the gate electrode in the third region taken along line VV in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the gate electrode in the fourth region taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a part of a gate electrode included in a transistor according to the second embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view of the fourth region taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a part of a semiconductor device including a transistor according to the third embodiment. [Figure 10] FIG. 10 is a schematic plan view showing a part of the semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] [Problem to be solved by this disclosure] The semiconductor device disclosed in Patent Document 1 employs a configuration including an internal resistor made of p-type polysilicon inside the semiconductor chip in order to reduce noise generation during switching operations. In the semiconductor device disclosed in Patent Document 1, the internal resistor is disposed between a gate pad, which is a control pad, and a gate finger connected to a gate electrode, which is a control electrode, and electrically connects the gate finger and the gate pad. The gate electrode and the internal resistor are disposed physically separated from each other.

[0008] In such a configuration, the gate electrode and the built-in resistor must be located apart within the semiconductor device, and an area for the built-in resistor must be secured. As a result, the area occupied by the gate pad increases in the thickness direction of the semiconductor layer, making it difficult to miniaturize the device. In addition, it is also necessary to reduce the effects of surge voltages during switching operations.

[0009] Therefore, one object is to provide a transistor that can reduce the influence of surge voltage and can be easily miniaturized.

[0010] [Effects of this disclosure] The above transistor can reduce the influence of surge voltages and can be easily miniaturized.

[0011] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be described. A transistor according to the present disclosure includes a wide bandgap semiconductor layer including a plurality of transistor cells each having a channel region; a gate insulating film disposed on the wide bandgap semiconductor layer; a gate electrode disposed in a region facing the channel region across the gate insulating film; an interlayer insulating film covering the wide bandgap semiconductor layer, the gate insulating film, and the gate electrode; a gate pad formed of a conductor and disposed on the interlayer insulating film; and a gate runner formed of a conductor and disposed on the interlayer insulating film at a position separate from the gate pad. The gate electrode extends, as viewed in the thickness direction of the wide bandgap semiconductor layer, from a region facing the channel region to a region where the gate pad is located and a region where the gate runner is located. The interlayer insulating film includes a first opening disposed in the region where the gate pad is located and penetrating the interlayer insulating film in the thickness direction, and a second opening disposed in the region where the gate runner is located and penetrating the interlayer insulating film in the thickness direction. The gate pad is connected to the gate electrode by filling the first opening. The gate runner is connected to the gate electrode by filling the second opening. The gate electrode includes a first region connected to the gate pad, a second region connected to the gate runner, and a third region and a fourth region located between the first and second regions and at different positions in a first direction indicated by the direction from the first region to the second region. In a cross section perpendicular to the first direction, the cross-sectional area of the gate electrode in the fourth region is smaller than the cross-sectional area of the gate electrode in the third region.

[0012] In the transistor, the gate pad is connected to the gate electrode by filling the first opening, and the gate runner is connected to the gate electrode by filling the second opening. The gate electrode in the transistor includes a first region connected to the gate pad, a second region connected to the gate runner, and a third and fourth region located between the first and second regions and at different positions in a first direction, which is the direction from the first region to the second region. In a cross section perpendicular to the first direction, the cross-sectional area of the gate electrode in the fourth region is smaller than that of the gate electrode in the third region. This allows the fourth region to function as the transistor's internal resistance. This allows the internal resistance in the fourth region to be adjusted, reducing the effects of surge voltages. This is also effective in suppressing ringing. Furthermore, because the fourth region functioning as the internal resistance is not separated from the gate electrode but is integrated with it, the area occupied by the gate pad can be reduced. This allows the transistor to reduce the effects of surge voltages and facilitates miniaturization. The wide band gap semiconductor layer refers to a semiconductor layer made of a material whose band gap is wider than that of silicon.

[0013] In the above transistor, the gate electrode in the fourth region may have a through hole penetrating in a thickness direction of the wide band gap semiconductor layer, whereby the cross-sectional area of the gate electrode in the fourth region can be easily reduced by the through hole included in the gate electrode in the fourth region.

[0014] In the above transistor, the thickness of the gate electrode in the fourth region may be smaller than the thickness of the gate electrode in the third region, which allows the thicknesses of the gate electrode in the fourth region and the gate electrode in the third region to be adjusted, thereby easily reducing the cross-sectional area of the fourth region.

[0015] In the above transistor, the wide bandgap semiconductor layer may be a SiC semiconductor layer, an AlN semiconductor layer, a GaN semiconductor layer, or a gallium oxide (Ga2O3) semiconductor layer. Such a wide bandgap semiconductor layer is capable of passing a large current while ensuring a high breakdown voltage, and is therefore suitable for use in the above transistor.

[0016] In the above transistor, the gate electrode may be made of polysilicon. The resistance of polysilicon can be easily controlled by adjusting the concentration of the impurities implanted. Therefore, by doing so, it is easy to achieve the desired internal resistance.

[0017] In the transistor, the impurity concentration of the gate electrode may be constant. This facilitates the fabrication of the transistor. Here, a constant impurity concentration means, for example, that the impurity concentration is within a range of ±20% or less of a target center value.

[0018] The semiconductor device according to the present disclosure includes an insulating substrate having a circuit pattern and the above-described transistor disposed on the circuit pattern. Because the semiconductor device includes a fourth region in which the transistor functions as an internal resistor, it is not necessary to provide a separate gate resistor in the circuit outside the transistor. This simplifies the manufacturing process.

[0019] [Details of the embodiments of the present disclosure] Next, an embodiment of a transistor according to the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated.

[0020] (Embodiment 1) A transistor according to a first embodiment of the present disclosure will be described. FIG. 1 is a schematic plan view illustrating a transistor according to the first embodiment. FIG. 2 is an enlarged cross-sectional view of a portion of the transistor illustrated in FIG. 1. FIG. 3 is an enlarged cross-sectional view of the region surrounded by the dashed line in FIG. 1, taken along line III-III in FIG. 2. FIG. 4 is an enlarged cross-sectional view of the region surrounded by the dashed line in FIG. 1, taken along line IV-IV in FIG. 2. In FIG. 2, the thickness direction of the wide bandgap semiconductor layer is indicated by arrow Z. Positions P1, P2, P3, and P4 in FIG. 1 correspond to positions P1, P2, P3, and P4 in FIGS. 2 to 4. Note that, for ease of understanding, FIGS. 3 and 4 illustrate enlarged schematic views of portions of the transistor cell. In addition, arrows W1 and W2 are illustrated in FIGS. 1, 3, and 4 to clearly indicate the directions. In this embodiment, arrows W1 and W2 are perpendicular to each other. In Figure 2, the direction of the arrow indicated by +W2 indicates the direction from position P1 to position P2, the direction of the arrow indicated by -W1 indicates the direction from position P2 to position P3, and the direction of the arrow indicated by -W2 indicates the direction from position P3 to position P4.

[0021] 1 to 4, a transistor 11a according to the first embodiment is, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), specifically a vertical MOSFET. The transistor 11a includes a drain electrode 12, a SiC substrate 13, a wide bandgap semiconductor layer 14, a gate insulating film 15, a gate electrode 16, an interlayer insulating film 17, a gate pad 18, a gate runner 19, and a source pad 20. The transistor 11a according to the present embodiment employs a trench gate structure. A trench 36 is formed in the wide bandgap semiconductor layer 14 in a region where the gate electrode 16 is disposed. The trench 36 is composed of wall surfaces extending in the thickness direction of the wide bandgap semiconductor layer 14.

[0022] The wide bandgap semiconductor layer 14 is disposed on the SiC substrate 13. In this embodiment, the wide bandgap semiconductor layer 14 is a SiC semiconductor layer. The wide bandgap semiconductor layer 14 includes a plurality of transistor cells 22 each having a channel region 21. In this embodiment, the channel region 21 extends in the thickness direction of the wide bandgap semiconductor layer 14.

[0023] The drain electrode 12 is disposed on the SiC substrate 13 on the side opposite to the side on which the wide band gap semiconductor layer 14 is disposed. The drain electrode 12 is made of a conductor.

[0024] The gate insulating film 15 is disposed on the wide band gap semiconductor layer 14. The material of the gate insulating film 15 is, for example, SiO2.

[0025] The gate electrode 16 is disposed in a region facing the channel region 21 across the gate insulating film 15. The gate insulating film 15 is made of, for example, polysilicon. The impurity concentration of the gate electrode 16 is constant.

[0026] Interlayer insulating film 17 is disposed so as to cover wide bandgap semiconductor layer 14, gate insulating film 15, and gate electrode 16. The material of interlayer insulating film 17 is, for example, SiO2. The thickness direction of interlayer insulating film 17 is indicated by arrow Z in Figure 2. That is, the thickness direction of wide bandgap semiconductor layer 14 and the thickness direction of interlayer insulating film 17 are the same.

[0027] The gate pad 18 is disposed on the interlayer insulating film 17. When viewed in the thickness direction of the wide band gap semiconductor layer 14, the outer shape of the gate pad 18 is rectangular. The gate pad 18 is made of a conductor. Note that in FIGS. 2 to 4, a boundary 52 of the gate pad 18 on the side where the gate runner 19 is located is illustrated.

[0028] The gate runner 19 is disposed on the interlayer insulating film 17 at a position separated from the gate pad 18. The gate runner 19 is made of a conductor. 2 to 4 show a boundary 53 of the gate runner 19 on the side where the gate pad 18 is located and a boundary 54 on the outer edge side opposite the side where the gate pad 18 is located.

[0029] The source pad 20 is disposed on the interlayer insulating film 17 at a position separated from the gate pad 18 and the gate runner 19. The source pads 20 are disposed side by side in the direction indicated by the arrow W1. The source pad 20 is made of a conductor. The gate runners 19 described above are disposed on the outer periphery of the source pad 20 with a gap therebetween, with some exceptions. Note that FIG. 2 illustrates a boundary 55 of the source pad 20 on the side where the gate runners 19 are located.

[0030] The gate pad 18, the gate runner 19, and the source pad 20 are made of, for example, copper or aluminum.

[0031] The wide band gap semiconductor layer 14 is disposed on the SiC substrate 13 side. - The drift region 23 and the p + The transistor cell 22 of the wide band gap semiconductor layer 14 includes a contact region 24. - Body region 25 and n + A source region 26 and p + The contact region 27 is formed by, for example, ion implantation. - The body region 25 includes the channel region 21 .

[0032] In the transistor 11a, a voltage is applied to the gate electrode 16 to generate an electric field in the channel region 21, and the n-channel MOSFET 22 is connected from the source pad 20 to the n-channel MOSFET 22. + Source region 26, p - Body region 25, n -The current passing through the drift region 23 and through the SiC substrate 13 to the drain electrode 12 is controlled.

[0033] The gate electrode 16 extends from a region 37 facing the channel region 21 to a region where the gate pad 18 is located and a region where the gate runner 19 is located, as viewed in the thickness direction of the wide bandgap semiconductor layer 14. Specifically, the gate electrode 16 extends to a boundary 51, which is the edge of the region where the gate pad 18 is located. The gate electrode 16 also extends to a boundary 55, which is the edge on the outer edge side of the region where the gate runner 19 is located. The interlayer insulating film 17 includes a first opening 28, which is disposed in the region where the gate pad 18 is located and penetrates the interlayer insulating film 17 in the thickness direction, and a second opening 29, which is disposed in the region where the gate runner 19 is located and penetrates the interlayer insulating film 17 in the thickness direction. The gate pad 18 is connected to the gate electrode 16 by filling the first opening 28. The gate runner 19 is connected to the gate electrode 16 by filling the second opening 29. The interlayer insulating film 17 has a p + The interlayer insulating film 17 includes a third opening 30 that is disposed in a region where the contact region 27 is located and that penetrates the interlayer insulating film 17 in the thickness direction. The source pad 20 fills the third opening 30.

[0034] Here, the gate electrode 16 includes a first region 31 connected to the gate pad 18, a second region 32 connected to the gate runner 19, and a third region 33 and a fourth region 34 that are located between the first region 31 and the second region 32 and are arranged at different positions in a first direction (direction indicated by arrow D1) that is the direction from the first region 31 to the second region 32. In a cross section perpendicular to the first direction, the cross-sectional area of the gate electrode 16 in the fourth region 34 is smaller than the cross-sectional area of the gate electrode 16 in the third region 33. In this embodiment, the thickness T1 of the gate electrode 16 in the third region 33 is the same as the thickness T1 of the gate electrode 16 in the fourth region 34.

[0035] 5 is a schematic cross-sectional view of the gate electrode 16 in the third region 33 taken along line VV in FIG. 3. FIG. 6 is a schematic cross-sectional view of the gate electrode 16 in the fourth region 34 taken along line VI-VI in FIG. 3. In FIG. 3, the direction from the first region 31 toward the second region 32 is indicated by arrow D1. The direction indicated by arrow D1 is the same as the direction indicated by arrow W2. FIGS. 5 and 6 are cross sections perpendicular to the first direction.

[0036] 3 to 6, in this embodiment, the gate electrode 16 in the fourth region 34 has a through hole 35 penetrating in the thickness direction of the wide band gap semiconductor layer 14. The wall surfaces of the through hole 35 appear to have a rectangular shape when viewed in the thickness direction of the wide band gap semiconductor layer 14. A plurality of through holes 35 are formed. The plurality of through holes 35 are arranged at intervals in a direction perpendicular to the direction indicated by arrow D1. In this embodiment, five through holes 35 are formed. The cross-sectional area of the gate electrode 16 in the fourth region 34 is smaller than the cross-sectional area of the gate electrode 16 in the third region 33 by the area occupied by the through hole 35.

[0037] In the transistor 11a, the gate pad 18 is connected to the gate electrode 16 by filling the first opening 28, and the gate runner 19 is connected to the gate electrode 16 by filling the second opening 29. In the transistor 11a, the gate electrode 16 includes a first region 31 connected to the gate pad 18, a second region 32 connected to the gate runner 19, and a third region 33 and a fourth region 34 located between the first region 31 and the second region 32 and at different positions in a first direction, which is the direction from the first region 31 to the second region 32. In a cross section perpendicular to the first direction, the cross-sectional area of the gate electrode 16 in the fourth region 34 is smaller than the cross-sectional area of the gate electrode 16 in the third region 33. This allows the fourth region 34 to function as an internal resistance of the transistor 11a. This allows the internal resistance in the fourth region 34 to be adjusted, thereby reducing the effects of surge voltages due to voltage jumps. This is also effective in suppressing ringing. Furthermore, the fourth region 34, which functions as an internal resistor, is not separated from the gate electrode 16 but is integrated with the gate electrode 16, thereby reducing the area occupied by the gate pad 18. Therefore, the transistor 11a can be less affected by surge voltages and can be easily miniaturized.

[0038] Briefly, the transistor 11a in the first embodiment is manufactured as follows. First, a SiC substrate 13 is prepared, and a wide band gap semiconductor layer 14 is formed on one surface of the SiC substrate 13. Then, doping is performed by ion implantation in the region where the transistor cell 22 is to be disposed, and p - Body region 25, n + Source region 26 and p +A contact region 27 is formed. Next, a trench 36 is formed, followed by the sequential formation of a gate insulating film 15 and a gate electrode 16 made of polysilicon. At this time, the gate electrode 16 is formed, as viewed in the thickness direction of the wide bandgap semiconductor layer 14, up to the region where the gate pad 18 and the gate runner 19 are located. A through-hole 35 is then formed in a position corresponding to the fourth region of the gate electrode 16, and an interlayer insulating film 17 is then formed to cover the wide bandgap semiconductor layer 14, the gate insulating film 15, and the gate electrode 16. After that, a first opening 28, a second opening 29, and a third opening 30 are formed, and a source electrode capable of ohmic contact and a drain electrode are formed on the other surface of the SiC substrate 13. Next, the gate pad 18, the gate runner 19, and the source pad 20 are formed in predetermined locations. In this manner, the transistor 11a is manufactured.

[0039] In this embodiment, the gate electrode 16 in the fourth region 34 has a through hole 35 that penetrates in the thickness direction of the wide band gap semiconductor layer 14. Therefore, in the transistor 11a, the cross-sectional area of the fourth region 34 can be easily reduced by the through hole 35 included in the gate electrode 16 in the fourth region 34.

[0040] In this embodiment, the wide band gap semiconductor layer 14 is a SiC semiconductor layer, and therefore the transistor 11a is capable of passing a large current while ensuring a high breakdown voltage.

[0041] In this embodiment, the gate electrode 16 is made of polysilicon. The resistance of polysilicon can be easily controlled by adjusting the concentration of implanted impurities. Therefore, the transistor 11a can be easily configured to have a desired internal resistance.

[0042] In the transistor 11a, the impurity concentration of the gate electrode 16 is constant, which makes the transistor 11a easy to manufacture.

[0043] In the above embodiment, the wall surfaces of the through holes 35 have a rectangular shape when viewed in the thickness direction of the wide band gap semiconductor layer 14, but the shape is not limited thereto, and the wall surfaces of the through holes 35 may have a square shape, a round shape, or an elliptical shape. Furthermore, the plurality of through holes 35 may have a combination of a plurality of different shapes. Also, the number of through holes 35 may be one.

[0044] In the above embodiment, trench 36 has walls extending vertically, i.e., in the thickness direction of wide band gap semiconductor layer 14. However, this is not limiting, and the walls of trench 36 may be inclined with respect to the thickness direction of wide band gap semiconductor layer 14 so that the area of the opening side increases. Specifically, trench 36 may be configured so that the opening area decreases toward SiC substrate 13 when viewed in the thickness direction of wide band gap semiconductor layer 14, for example.

[0045] (Embodiment 2) Next, another embodiment, embodiment 2, will be described. Fig. 7 is a schematic cross-sectional view showing a part of a gate electrode included in a transistor in embodiment 2. Fig. 8 is a schematic cross-sectional view taken along line VIII-VIII in Fig. 7. The transistor in embodiment 2 differs from embodiment 1 in that no through-hole is formed in the gate electrode in the fourth region and the thickness of the gate electrode in the fourth region is thinner than that of the gate electrode in the third region.

[0046] 7 and 8, in gate electrode 41 included in transistor 11b according to the second embodiment, step 42 is formed between gate electrode 41 in third region 43 and gate electrode 41 in fourth region 44, and thickness T2 of gate electrode 41 in fourth region 44 is smaller than thickness T3 of gate electrode 41 in third region 43. Transistor 11b is a transistor in which the cross-sectional area of gate electrode 41 in fourth region 44 can be easily reduced by adjusting thickness T2 of gate electrode 41 in fourth region 44 and thickness T3 of gate electrode 41 in third region 43.

[0047] (Embodiment 3) Next, a third embodiment, which is yet another embodiment, will be described. Figure 9 is a schematic cross-sectional view showing a part of a transistor in the third embodiment. The transistor in the third embodiment differs from the first embodiment in that it employs a planar gate structure.

[0048] 9, a transistor 11c according to the third embodiment includes a drain electrode 12, a SiC substrate 13, a wide bandgap semiconductor layer 14, a gate insulating film 15, a gate electrode 16, an interlayer insulating film 17, a gate pad 18, a gate runner 19, and a source pad 20. The transistor 11c according to the third embodiment has a planar gate structure. Unlike the transistor 11a according to the first embodiment, the channel region 21 extends along a plane perpendicular to the thickness direction of the wide bandgap semiconductor layer 14.

[0049] The transistor 11c having such a configuration can also reduce the influence of surge voltages and facilitates miniaturization.

[0050] (Fourth embodiment) Next, a fourth embodiment, which is yet another embodiment, will be described. Fig. 10 is a schematic plan view of a semiconductor device including a transistor according to the first embodiment, as viewed in the thickness direction of a substrate.

[0051] 10, a semiconductor device 61 includes an insulating substrate 63 disposed on a heat sink and having a circuit pattern 64, the above-described transistor 11a, a transistor 11d having a configuration similar to that of the transistor 11a, a Schottky barrier diode 65c, a plurality of terminals 67a, 67b, and 67c, a plurality of wires 68a, 68b, 68c, 68d, 68e, 68f, 68g, and 68h, and a case 66. Note that in the transistors 11a and 11d, the gate runner 19 is not shown, and the gate pad 18 and the source pad 20 are simply shown.

[0052] The case 66 is made of, for example, insulating resin. In this embodiment, the case 66 has a rectangular cylindrical shape with a longer length in the X direction than in the Y direction. The case 66 includes a first wall portion 69a, a second wall portion 69b, a third wall portion 69c, and a fourth wall portion 69d. The first wall portion 69a and the second wall portion 69b are arranged opposite each other in the X direction. The third wall portion 69c and the fourth wall portion 69d are arranged opposite each other in the Y direction. The case 66 is attached to a heat sink with, for example, an adhesive. Note that the Z direction in FIGS. 1 to 9 is a direction perpendicular to the X direction and the Y direction in FIG. 10.

[0053] The insulating substrate 63 is disposed within a region surrounded by the first wall portion 69a to the fourth wall portion 69d. The insulating substrate 63 is made of, for example, ceramic.

[0054] The circuit pattern 64 is disposed in contact with one surface of the insulating substrate 63 in the thickness direction of the insulating substrate 63. The circuit pattern 64 is composed of a plurality of circuit boards. In this embodiment, the circuit pattern 64 specifically includes a first circuit board 64a, a second circuit board 64b, a third circuit board 64c, and a fourth circuit board 64d. In this embodiment, the circuit pattern 64 is so-called copper wiring.

[0055] Transistors 11a and 11d are each connected to a third circuit board 64c. Schottky barrier diode 65c is connected to a fourth circuit board 64d.

[0056] In the Schottky barrier diode 65c, a cathode electrode is arranged on the surface facing the fourth circuit board 64d, and an anode electrode is arranged on the surface of the insulating substrate 63 opposite the facing surface in the thickness direction.

[0057] The transistor 11a has a drain electrode disposed on the surface facing the third circuit plate 64c. The transistor 11a includes a source pad 20 and a gate pad .

[0058] The terminals 67a to 67c are made of metal. In this embodiment, the terminals 67a to 67c are each formed by bending a flat metal member, for example. In the semiconductor device 61, electrical connection with the outside is ensured by using the terminals 67a to 67c. The three terminals 67a to 67c are each attached to the case 66. Specifically, the terminals 67a and 67b are attached to a first wall portion 69a of the case 66 with an interval in the Y direction. The terminal 67c is attached to a second wall portion 69b.

[0059] Terminal 67a and first circuit plate 64a are electrically connected by wire 68a. Terminal 67b and second circuit plate 64b are electrically connected by wire 68b. Gate pad 18 of transistor 11d and first circuit plate 64a are electrically connected by wire 68c. Source pad 20 of transistor 11d and second circuit plate 64b are electrically connected by wire 68d. A drain electrode located on the surface opposite to the side on which gate pad 18 and source pad 20 of transistor 11d are arranged is electrically connected to third circuit plate 64c. Gate pad 18 of transistor 11a and first circuit plate 64a are electrically connected by wire 68e. Source pad 20 of transistor 11a and second circuit plate 64b are electrically connected by wire 68f. A drain electrode located on the surface opposite to the side on which gate pad 18 and source pad 20 of transistor 11a are arranged is electrically connected to third circuit plate 64c. The third circuit plate 64c and the fourth circuit plate 64d are connected by a wire 68g. The cathode electrode of the Schottky barrier diode 65c and the fourth circuit plate 64d are electrically connected. The anode electrode of the Schottky barrier diode 65c and the terminal 67c are electrically connected by a wire 68h. The wires 68a to 68h are joined to the respective components such as the transistor 11a by, for example, ultrasonic bonding.

[0060] In the semiconductor device 61 having such a configuration, since the transistors 11a and 11d include the fourth region 34 that functions as an internal resistor, there is no need to provide a separate member corresponding to a gate resistor in the circuit outside the transistor 11a, thereby simplifying the manufacturing process.

[0061] (Other embodiments) In the above embodiment, the wide band gap semiconductor layer 14 is a SiC semiconductor layer, but is not limited thereto, and the wide band gap semiconductor layer 14 may be a SiC semiconductor layer, an AlN semiconductor layer, a GaN semiconductor layer, or a gallium oxide (Ga2O3) semiconductor layer. Such a wide band gap semiconductor layer 14 is capable of passing a large current while ensuring a high breakdown voltage, and is therefore suitable for use in the above transistor.

[0062] Furthermore, in the above-described embodiments, the transistors are MOSFETs, but the present invention is not limited to this. The transistors may be, for example, IGBTs (Insulated Gate Bipolar Transistors), that is, insulated gate bipolar transistors.

[0063] It should be understood that the embodiments disclosed herein are illustrative in all respects and are not limiting in any respect. The scope of the present disclosure is defined not by the above description but by the scope of the claims, and it is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0064] 11a, 11b, 11c, 11d transistors 12 Drain electrode 13 SiC substrate 14 Wide band gap semiconductor layer 15 Gate insulating film 16,41 Gate electrode 17 Interlayer insulating film 18 Gate Pad 19 Gate Runner 20 Saucepad 21 Channel Region 22 transistor cells 23n - Drift Region 24,27 pages + Contact Area 25 p - Body region 26n + Source Region 28 First Opening 29 Second Opening 30 Third Opening 31 First area 32 Second area 33,43 Third area 34,44 4th area 35 through holes 36 Trench 37,38,39 area 42 steps 51,52,53,54,55 boundary 61 Semiconductor devices 63 Insulating substrate 64 Circuit Pattern 64a 1st circuit board 64b 2nd circuit board 64c 3rd circuit board 64d 4th circuit board 65c Schottky barrier diode 66 cases 67a,67b,67c terminal 68a, 68b, 68c, 68d, 68e, 68f, 68g, 68h Wire 69a First wall 69b Second wall 69c 3rd wall 69d Fourth wall D1, W1, W2, X, Y, Z arrows P1,P2,P3,P4 position T1, T2, T3 thickness

Claims

1. a wide bandgap semiconductor layer including a plurality of transistor cells each having a channel region; a gate insulating film disposed on the wide band gap semiconductor layer; a gate electrode disposed in a region facing the channel region with the gate insulating film interposed therebetween; an interlayer insulating film covering the wide band gap semiconductor layer, the gate insulating film, and the gate electrode; a gate pad made of a conductor and disposed on the interlayer insulating film; a gate runner made of a conductor, the gate runner being disposed on the interlayer insulating film and spaced apart from the gate pad; the gate electrode extends from a region facing the channel region to a region where the gate pad is located and a region where the gate runner is located, as viewed in a thickness direction of the wide band gap semiconductor layer; the interlayer insulating film includes a first opening disposed in a region where the gate pad is located and penetrating the interlayer insulating film in a thickness direction, and a second opening disposed in a region where the gate runner is located and penetrating the interlayer insulating film in a thickness direction, the gate pad is connected to the gate electrode by filling the first opening; the gate runner is connected to the gate electrode by filling the second opening; The gate electrode is a first region connected to the gate pad; a second region connected to the gate runner; a third region and a fourth region that are disposed between the first region and the second region and at different positions in a first direction that is a direction from the first region toward the second region, In a cross section perpendicular to the first direction, a cross-sectional area of the gate electrode in the fourth region is smaller than a cross-sectional area of the gate electrode in the third region; the gate electrode in the fourth region has a through hole penetrating in a thickness direction of the wide band gap semiconductor layer, A transistor, wherein the fourth region is disposed between two of the third regions in the first direction.

2. A step is formed between the gate electrode in the third region and the gate electrode in the fourth region, The transistor of claim 1 , wherein a thickness of the gate electrode in the fourth region is less than a thickness of the gate electrode in the third region.

3. 3. The transistor according to claim 1, wherein the wide bandgap semiconductor layer is a SiC semiconductor layer, an AlN semiconductor layer, a GaN semiconductor layer, or a gallium oxide semiconductor layer.

4. 4. The transistor according to claim 1, wherein the gate electrode is made of polysilicon.

5. 5. The transistor according to claim 1, wherein the concentration of impurities in the gate electrode is constant.

6. an insulating substrate having a circuit pattern; The transistor according to claim 1 , which is disposed on the circuit pattern.

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