Semiconductor Devices

Abstract

Provided is a semiconductor device that comprises: a base region of a second conductivity type that is disposed between a drift region and an upper surface of a semiconductor substrate; a first lifetime region that is disposed in a drift region further on a lower-surface side of the semiconductor substrate than the base region; and a second lifetime region that is disposed so as to be sandwiched by the first lifetime region in a first direction that is parallel to the upper surface of the semiconductor substrate and has a longer carrier lifetime than the first lifetime region. The width of the second lifetime region in the first direction is at least 0.2 times the thickness of the first lifetime region in a second direction that is perpendicular to the upper surface of the semiconductor substrate.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, in a semiconductor device including a free wheel diode (FWD) or the like, a technique for adjusting carrier lifetime by forming lattice defects in a semiconductor substrate is known (see, for example, Patent Documents 1 and 2). Patent Document 1: JP 2020-31155 A Patent Document 2: JP 2020-120121 A Problem to be Solved

[0003] In semiconductor devices, it is preferable to suppress snapback.

[0004] To solve the above problems, a first aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and a first conductivity type drift region provided therein. Any of the above semiconductor devices may include a diode section provided in the semiconductor substrate. In any of the above semiconductor devices, the diode section may have a second conductivity type base region provided between the drift region and the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the diode section may have a first lifetime region disposed in the drift region closer to the lower surface of the semiconductor substrate than the base region. In any of the above semiconductor devices, the diode section may have a second lifetime region disposed between the first lifetime regions in a first direction parallel to the upper surface of the semiconductor substrate, the second lifetime region having a longer carrier lifetime than the first lifetime region. In any of the above semiconductor devices, the width of the second lifetime region in the first direction may be greater than the width W (μm) expressed by equation (1). W=0.21×T1+3.3 (1) Here, T1 is the thickness of the first lifetime region in a second direction perpendicular to the top surface.

[0005] In any of the above semiconductor devices, the second lifetime region may have a width in the first direction of 7 μm or more.

[0006] In any of the above semiconductor devices, the width of the second lifetime region in the first direction may be 12 μm or less.

[0007] In any of the above semiconductor devices, the diode section may have one or more second lifetime regions, and a sum of widths of the one or more second lifetime regions in the first direction may be 0.1 times or less the width of the diode section in the first direction.

[0008] Any of the above semiconductor devices may include a transistor section provided on the semiconductor substrate and arranged alongside the diode section in the first direction.

[0009] In any of the above semiconductor devices, the diode section and the transistor section may have a plurality of trench sections arranged at intervals in the first direction.

[0010] Any of the above semiconductor devices may include a transistor section provided on the semiconductor substrate and arranged alongside the diode section in a third direction that is parallel to the top surface of the semiconductor substrate and perpendicular to the first direction.

[0011] In any of the above semiconductor devices, the diode section and the transistor section may have a plurality of trench sections arranged at intervals in the third direction.

[0012] In any of the above semiconductor devices, at least a portion of the trench portion of the diode portion may be arranged above the first lifetime region, and the distance between the second lifetime region and the transistor portion in the first direction may be greater than or equal to the distance between the lower end of the trench portion and the first lifetime region in the second direction.

[0013] In any of the above semiconductor devices, the diode section may have two or more of the second lifetime regions arranged at intervals in the first direction.

[0014] In any of the above semiconductor devices, the second lifetime region may also be sandwiched between the first lifetime regions in a third direction that is parallel to the top surface of the semiconductor substrate and perpendicular to the first direction.

[0015] In any of the above semiconductor devices, the width of the second lifetime region in the third direction may be 0.2 times or more the thickness of the first lifetime region in the second direction.

[0016] In any of the above semiconductor devices, the width of the second lifetime region in the first direction may be 3% or more of the diffusion length of electrons in the semiconductor substrate.

[0017] In any of the above semiconductor devices, the thickness of the first lifetime region in the second direction may be 100 μm or less.

[0018] In any of the above semiconductor devices, the width of the second lifetime region in the first direction may be 0.2 times or more the thickness of the first lifetime region in a second direction perpendicular to the top surface of the semiconductor substrate.

[0019] In any of the above semiconductor devices, the first lifetime region may contain hydrogen.In any of the above semiconductor devices, the first lifetime region may contain helium.

[0020] In any of the above semiconductor devices, the first lifetime region may be provided in the diode section and the transistor section. In the transistor section of any of the above semiconductor devices, a ratio of an area of the second lifetime region 200 surrounded by the first lifetime region to an area of the first lifetime region 204 may be smaller than a ratio of an area of the second lifetime region 200 surrounded by the first lifetime region to an area of the first lifetime region in the diode section.

[0021] In any of the above semiconductor devices, the first lifetime region may be provided in the diode section and the transistor section. In any of the above semiconductor devices, the second lifetime region may be provided within the first lifetime region of the diode section. In any of the above semiconductor devices, the second lifetime region may not be provided within the first lifetime region of the transistor section.

[0022] In any of the semiconductor devices described above, each of the plurality of trench portions may extend in a direction greater than 0 degrees and less than 90 degrees with respect to the first direction on the upper surface of the semiconductor substrate.

[0023] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged view of an area D in FIG. [Figure 3] FIG. 3 is a diagram showing an example of an ee cross section in FIG. 2. [Figure 4] FIG. 10 is a diagram showing an example of VI characteristics when the diode section 80 according to the comparative example is in forward conduction. [Figure 5]2 is a diagram showing an example of the arrangement of a first lifetime region 204 and a second lifetime region 200 in a diode section 80. FIG. [Figure 6] FIG. 2 is an enlarged cross-sectional view of the vicinity of the second lifetime region 200. [Figure 7] 7 is a diagram showing an example of distribution of carrier lifetime, vacancy density, and helium chemical concentration in the ff line of FIG. 6. FIG. [Figure 8] 7A and 7B are diagrams showing examples of distributions of carrier lifetime, vacancy density, and helium chemical concentration in the gg line of FIG. 6. [Figure 9] 7 is a diagram showing an example of distribution of carrier lifetime, vacancy density, and helium chemical concentration in the hh line of FIG. 6. FIG. [Figure 10] 10 is another example of an enlarged cross-sectional view of the vicinity of the second lifetime region 200. FIG. [Figure 11A] FIG. 10 shows distribution diagrams of the net doping concentration (A), hydrogen chemical concentration (B), lattice defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along line hh in the semiconductor device 100 according to the embodiment. [Figure 11B] 10 is another example of an enlarged cross-sectional view of the vicinity of the second lifetime region 200. FIG. [Figure 11C] 11B shows distribution diagrams of the net doping concentration (A), hydrogen chemical concentration (B), lattice defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along line hh in the semiconductor device 100 according to the embodiment. [Figure 11D] 10 is another example of an enlarged cross-sectional view of the vicinity of the second lifetime region 200. FIG. [Figure 12] 10 is a diagram showing an example of VI characteristics when the diode section 80 is in forward conduction. FIG. [Figure 13] 10 is a diagram showing the trade-off characteristics between the forward voltage Vf and the reverse recovery loss Err in the diode section 80. FIG. [Figure 14] 10 is a diagram showing the relationship between the width W1 of the second lifetime region 200 and the amount of snapback (amount of SB). FIG. [Figure 15] FIG. 10 is a diagram showing whether snapback occurs when the thickness T1 of the first lifetime region 204 and the width W1 of the second lifetime region 200 are changed. [Figure 16A] 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 in the diode section 80. FIG. [Figure 16B] 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 in the diode section 80. FIG. [Figure 16C] 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 in the diode section 80. FIG. [Figure 17] FIG. 10 is a diagram showing whether or not snapback occurs when the number of second lifetime regions 200 included in one diode section 80 and the width W1 of each second lifetime region 200 are changed. [Figure 18] 10 is a diagram showing an example of the arrangement of a first lifetime region 204 and a second lifetime region 200 on the XY plane. FIG. [Figure 19] FIG. 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. [Figure 20] FIG. 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. [Figure 21] FIG. 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. [Figure 22A] FIG. 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. [Figure 22B] FIG. 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. [Figure 23A] FIG. 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. [Figure 23B]FIG. 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. [Figure 24] FIG. 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. [Figure 25] FIG. 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. [Figure 26] FIG. 10 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. DETAILED DESCRIPTION OF THE INVENTION

[0025] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0026] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0027] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0028] In this specification, orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0029] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0030] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0031] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0032] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any point is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0033] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons. In this specification, a VOH defect may be referred to as a hydrogen donor.

[0034] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors due to dopants that are uniformly contained in the ingot that is the base of the semiconductor substrate when it is manufactured. In this example, the bulk donors are elements other than hydrogen. The dopants of the bulk donors include, but are not limited to, phosphorus, antimony, arsenic, selenium, or sulfur. In this example, the bulk donor is phosphorus. The bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), or the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 The higher the oxygen concentration, the easier it is to generate hydrogen donors. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, and may be between 90% and 100% of that chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 10 / cm 3 That's it, 5 x 10 12 / cm 3The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 11 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 12 / cm 3 The concentrations in the present invention may be values at room temperature, for example, values at 300 K (Kelvin) (approximately 26.9° C.).

[0035] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is used in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system used in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0036] As used herein, chemical concentration refers to the atomic density of an impurity measured regardless of its electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance (CV) measurement. The carrier concentration measured by spreading resistance (SR) measurement may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as the value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is significantly greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0037] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. When the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. 3 , or / cm 3 This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atom notation may be omitted.

[0038] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0039] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method may be lower than the chemical concentration of the element that represents the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which act as donors in silicon semiconductors, or the acceptor concentration of boron, which acts as an acceptor, is approximately 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the chemical concentration of hydrogen.

[0040] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0041] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of edges 162 facing each other in a top view. In FIG. 1, the X-axis and Y-axis are parallel to either edge 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0042] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region where a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is not shown in FIG. 1. The active portion 160 is, in top view, a region where a main current flows between the upper and lower surfaces of the semiconductor substrate 10 in the depth direction. and The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0043] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). The active section 160 may further be provided with a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0044] In FIG. 1, the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0045] The diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 in which the diode section 80 is extended in the Y-axis direction to a gate wiring (described later) may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0046] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, the gate structure having an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0047] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 162. The vicinity of the edge 162 refers to the region between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0048] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is indicated by diagonal hatching.

[0049] The gate wiring in this example has a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. In a top view, the region surrounded by the well region may be the active portion 160.

[0050] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0051] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, it is possible to reduce variations in wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0052] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active section 160. The peripheral gate wiring 130 and the active side gate wiring 131 are arranged above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0053] The active-side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active-side gate wiring 131 extends in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 that sandwich the active section 160, crossing the active section 160 at approximately the center in the Y-axis direction. When the active section 160 is divided by the active-side gate wiring 131, the transistor sections 70 and the diode sections 80 may be arranged alternately in the X-axis direction in each divided region.

[0054] The semiconductor device 100 may include a temperature sensing section (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detecting section (not shown) that simulates the operation of a transistor section provided in the active section 160.

[0055] In the present example, semiconductor device 100 includes an edge termination structure 90 between active section 160 and edge 162 when viewed from above. Edge termination structure 90 in the present example is disposed between peripheral gate wiring 130 and edge 162. Edge termination structure 90 alleviates electric field concentration on the top surface side of semiconductor substrate 10. Edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding active section 160.

[0056] 2 is an enlarged view of region D in FIG. 1. Region D is a region including a transistor section 70, a diode section 80, and an active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of a semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0057] An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is not shown in Fig. 2. In this example, contact holes 54 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with diagonal lines.

[0058] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0059] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0060] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the area where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. Furthermore, the contact hole may have a plug formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0061] The well region 11 is provided so as to overlap with the active-side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the active-side gate wiring 131. In this example, the well region 11 is provided away from the end of the contact hole 54 in the Y-axis direction toward the active-side gate wiring 131. The well region 11 is a region of a second conductivity type having a doping concentration higher than that of the base region 14. In this example, the base region 14 is P- type, and the well region 11 is P+ type.

[0062] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0063] The gate trench portion 40 in this example may have two straight line portions 39 (parts of the trench that are linear along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0064] At least a part of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0065] In the transistor section 70, the dummy trench section 30 is Two adjacent It is provided between the straight portions 39. Two adjacent One or more dummy trench portions 30 may be provided between the straight line portions 39. The dummy trench portion 30 may have a straight line shape extending in the extension direction, and may have a straight line portion 29 and an end portion 31, similar to the gate trench portion 40. The semiconductor device 100 shown in FIG. 2 includes both a straight line dummy trench portion 30 without an end portion 31 and a dummy trench portion 30 with an end portion 31.

[0066] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0067] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the mesa portion simply referred to as a mesa portion refers to both the mesa portion 60 and the mesa portion 61.

[0068] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active-side gate wiring 131 is referred to as the base region 14-e. While FIG. 2 shows the base region 14-e at one end of each mesa portion in the extension direction, a base region 14-e is also provided at the other end of each mesa portion. Each mesa portion may be provided with at least one of a first-conductivity-type emitter region 12 and a second-conductivity-type contact region 15 in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0069] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0070] The contact regions 15 and the emitter regions 12 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0071] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0072] The mesa portion 61 of the diode portion 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, a contact region 15 may be provided in contact with each of the base regions 14-e. In the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, a base region 14 may be provided. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15.

[0073] A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched between the base regions 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in regions corresponding to the base region 14-e and the well region 11. The contact hole 54 may be arranged in the center of the arrangement direction (X-axis direction) of the mesa portions 60.

[0074] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0075] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0076] Fig. 3 is a diagram showing an example of an ee cross section in Fig. 2. The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0077] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact hole 54 described with reference to FIG. 2.

[0078] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and contacts the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0079] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0080] In the mesa portion 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region may be provided in the mesa portion 60. The accumulation region is disposed between the base region 14 and the drift region 18. The accumulation region is an N+ type region having a higher doping concentration than the drift region 18. By providing a high-concentration accumulation region between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. An accumulation region may also be provided in each mesa portion 61 of the diode section 80.

[0081] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0082] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0083] A P-type base region 14 is provided in the mesa portion 61 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. The base region 14 of the diode portion 80 may be referred to as an anode region 14.

[0084] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. The doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0085] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as the chemical concentration peaks of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0086] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0087] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as the donor and acceptor in each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0088] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the top surface 21 of the semiconductor substrate 10. Each trench extends from the top surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed after the doped regions are formed. The trenches penetrating the doped regions also include trenches formed after the trenches are formed.

[0089] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. The diode section 80 is provided with the dummy trench section 30, but is not provided with the gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0090] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and on the inner side of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0091] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0092] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0093] In this example, the gate trench 40 and the dummy trench 30 are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may have a downwardly convex curved shape (a curved shape in cross section). In this specification, the depth position of the lower end of the gate trench 40 is defined as Zt.

[0094] The semiconductor device 100 of this example includes a first lifetime region 204 for adjusting the carrier lifetime. The first lifetime region 204 of this example is a region where the lifetime of charge carriers is locally short. The charge carriers are electrons or holes. Charge carriers may be simply referred to as carriers. The first lifetime region 204 may be a region in the depth direction of the semiconductor substrate 10 where the carrier lifetime exhibits a minimum value.

[0095] The first lifetime region 204 is disposed on the upper surface 21 side of the semiconductor substrate 10. The first lifetime region 204 is provided in the diode section 80. The first lifetime region 204 may also be provided in a part of the transistor section 70. In the example of FIG. 3 , the first lifetime region 204 is provided in a region of the transistor section 70 that contacts the diode section 80.

[0096] By injecting charged particles such as helium into the semiconductor substrate 10, lattice defects 202 are formed near the injection position. In FIG. 3, the lattice defects 202 at the injection position of the charged particles are schematically indicated by an x. In regions where many lattice defects 202 remain, carriers are captured by the lattice defects 202, shortening the carrier lifetime. By adjusting the carrier lifetime, it is possible to adjust the characteristics of the diode section 80, such as the turn-off time and reverse recovery loss. By injecting charged particles such as helium into the semiconductor substrate 10, lattice defects 210 such as vacancies are formed near the injection position. The lattice defects 202 generate recombination centers. The lattice defects 202 may be primarily vacancies, such as monovacancies (V) and divacancies (VV), or may be dislocations, interstitial atoms, transition metals, or the like. For example, atoms adjacent to the vacancies have dangling bonds. In a broad sense, lattice defects 202 may include donors and acceptors, but in this specification, lattice defects 202 mainly composed of vacancies may be referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, lattice defects 202 may be referred to simply as recombination centers or lifetime killers, as they are recombination centers that contribute to carrier recombination. The lifetime killers may be formed by implanting helium ions into the semiconductor substrate 10. In this case, the helium chemical concentration may be used as the density of the lattice defects 202. In this example, the helium chemical concentration may be used as the density of the lattice defects 202.

[0097] On the other hand, if the diode section 80 is provided with the first lifetime region 204, holes injected from the anode region 14 and electrons injected from the cathode region 82 decrease in the first lifetime region 204 during forward conduction of the diode section 80. This makes it difficult for the potential difference at the PN junction between the anode region 14 and the drift region 18 to become smaller than the built-in potential, which may cause snapback of the forward voltage in the low current operation region. In particular, if the first lifetime region 204 is provided over the entire diode section 80 in the X-axis direction, it becomes difficult for the hole density and electron density to increase in the region on the top surface 21 side of the diode section 80, making snapback more likely to occur.

[0098] FIG. 4 is a diagram showing an example of VI characteristics during forward conduction of a diode section 80 according to a comparative example. The diode section 80 of this example has a first lifetime region 204 extending over the entire X-axis direction. FIG. 4 shows the relationship between the forward current If of the diode section 80 and the anode-cathode voltage Vak. FIG. 4 also shows VI characteristics for multiple examples in which the carrier lifetime in the first lifetime region 204 is varied. The carrier lifetime in the first lifetime region 204 can be adjusted by the dose of charged particles, such as helium, implanted into the semiconductor substrate 10. The greater the dose of charged particles, such as helium, the greater the density of lattice defects formed in the semiconductor substrate 10, resulting in a shorter carrier lifetime.

[0099] When the first lifetime region 204 is provided over the entire diode section 80, shortening the carrier lifetime of the first lifetime region 204 may result in snapback in the VI characteristics, as shown in FIG. 4. Snapback is a phenomenon in which, as shown in FIG. 4, current increase is suppressed in the low-current operating region during forward conduction until the voltage Vak reaches a predetermined value, and then the current suddenly increases once the voltage Vak exceeds the predetermined value. In the low-current operating region, the majority carrier density (electron density in this example) must be increased to ensure that the potential difference across the PN junction exceeds the built-in potential. To provide the electron density required to exceed the built-in potential, the shorter the carrier lifetime, the higher the anode-cathode voltage Vak required. When the potential difference across the PN junction exceeds the built-in potential, minority carrier injection begins, increasing the forward current and decreasing the resistance of the diode section 80. This reduces the anode-cathode voltage Vak, causing conductivity modulation and resulting in snapback in the VI characteristics.

[0100] The VI waveform in the large current operating region is approximated by a straight line 85. In this specification, the difference (V2-V1) between the voltage V1 at which the current If=0 on the straight line 85 and the peak voltage V2 at snapback may be referred to as the snapback amount (SB amount). In the semiconductor device 100, snapback is suppressed by adjusting the arrangement of the first lifetime region 204 in the diode section 80.

[0101] 5 is a diagram showing an example of the arrangement of the first lifetime region 204 and the second lifetime region 200 in the diode section 80. FIG. 5 shows an XZ cross section passing through a part of the diode section 80 and a part of the transistor section 70. In FIG. 5, the interlayer insulating film 38, the emitter electrode 52, the collector electrode 24, and the like arranged above and below the semiconductor substrate 10 are omitted. In FIG. 5, the lattice defects 202 are omitted, and the hatching of the dummy conductive portion 34 and the gate conductive portion 44 is omitted.

[0102] The diode section 80 of this example has a first lifetime region 204 and a second lifetime region 200 in a region on the upper surface 21 side of the semiconductor substrate 10. The first lifetime region 204 is arranged in the drift region 18, which is closer to the lower surface 23 of the semiconductor substrate 10 than the base region 14. The first lifetime region 204 may be arranged below the lower end of the dummy trench portion 30. The diode section 80 may be provided with a plurality of first lifetime regions 204 that are arranged apart from each other in the X-axis direction. The width of one first lifetime region 204 in the X-axis direction may be larger than the width of one mesa portion sandwiched between two trench portions.

[0103] The second lifetime region 200 is disposed between the first lifetime regions 204 in a first direction (X-axis direction in this example) parallel to the upper surface 21 of the semiconductor substrate 10. The first lifetime region 204 and the second lifetime region 200 are provided at the same position in the depth direction (Z-axis direction) of the semiconductor substrate 10.

[0104] The second lifetime region 200 is a region having a longer carrier lifetime than the first lifetime region 204. In this example, the carrier lifetime of the second lifetime region 200 may be the same as the carrier lifetime of the drift region 18. In other words, the second lifetime region 200 may be the remaining drift region 18 without the first lifetime region 204 being formed. In another example, the carrier lifetime of the second lifetime region 200 may be shorter than the carrier lifetime of the drift region 18.

[0105] The second lifetime region 200 has a lower lattice defect density than the first lifetime region 204. The lattice defect density of the second lifetime region 200 may be the same as or higher than the lattice defect density of the drift region 18. The concentration of impurities such as helium in the second lifetime region 200 may be lower than the concentration of impurities such as helium in the first lifetime region 204. The concentration of impurities such as helium in the second lifetime region 200 may be the same as or higher than the impurity concentration of the drift region 18. The impurities in the impurity concentration in this example may be impurities that cause lattice defects that reduce the carrier lifetime. For example, the impurities may be atoms other than atoms in the semiconductor substrate 10 or may be interstitial atoms between atoms in the semiconductor substrate 10. The impurities may be n-type or p-type dopants, impurities that do not contribute to the conductivity type (e.g., helium, argon), or metal atoms (platinum, gold, etc.). Alternatively, the lattice defects that reduce the carrier lifetime may be vacancies or interstitials that do not contain impurities.

[0106] The second lifetime region 200 has a longer carrier lifetime than the first lifetime region 204, allowing electrons or holes to pass through it more easily. By providing the second lifetime region 200 in the diode section 80 as in this example, electrons injected from the cathode region 82 and holes injected from the anode region 14 can pass through the second lifetime region 200 during forward conduction of the diode section 80. Electrons that pass through the second lifetime region 200 diffuse in the XY plane and spread above the first lifetime region 204. Holes that pass through the second lifetime region 200 diffuse in the XY plane and spread below the first lifetime region 204. This improves the electron and hole densities in the regions closer to the upper surface 21 and the lower surface 23 than the first lifetime region 204 during forward conduction of the diode section 80, particularly during low-current operation. As a result, conductivity modulation can be generated without increasing the anode-cathode voltage Vak, thereby suppressing snapback. In this example, one second lifetime region 200 is provided for one diode section 80. The second lifetime region 200 may be disposed at the center of the diode section 80 in the X-axis direction.

[0107] FIG. 6 is an enlarged cross-sectional view of the vicinity of the second lifetime region 200. The width of the second lifetime region 200 in a first direction (the X-axis direction in this example) is defined as W1. The thickness of the first lifetime region 204 in a second direction (the Z-axis direction in this example) perpendicular to the upper surface 21 of the semiconductor substrate 10 is defined as T1. The width W1 of the second lifetime region 200 is at least 0.2 times the thickness of the first lifetime region 204. If the width W1 of the second lifetime region 200 is too small, electrons or holes passing through the second lifetime region 200 are more likely to be captured by the lattice defects 202 in the first lifetime regions 204 on both sides. The lattice defects 202 capturing electrons or holes may have a trap level. Furthermore, if the thickness T1 of the first lifetime region 204 is large, electrons or holes passing through the second lifetime region 200 are more likely to be captured by the lattice defects 202 in the first lifetime region 204. In contrast, by setting the width W1 of one second lifetime region 200 to be 0.2 times or more the thickness of the first lifetime region 204, it is possible to ensure the amount of electrons and holes passing through the second lifetime region 200. The width W1 may be 0.25 times or more, 0.3 times or more, 0.4 times or more, 0.5 times or more, 1 time or more, or 2 times or more the thickness T1.

[0108] However, if the second lifetime region 200 is made too large, the reverse recovery time of the diode section 80 becomes longer, and the reverse recovery charge and reverse recovery loss increase. In the diode section 80, the total width of the second lifetime region 200 in the X-axis direction is preferably smaller than the total width of the first lifetime region 204. The total width of the second lifetime region 200 in the diode section 80 in the X-axis direction may be 10% or less, or may be 5% or less, of the width of the diode section 80 in the X-axis direction.

[0109] One diode section 80 may have one second lifetime region 200 or multiple second lifetime regions 200 spaced apart in the X-axis direction. The width W1 of each second lifetime region 200 may be 7 μm or more. Increasing the width W1 of the second lifetime region 200 can prevent electrons or holes from being captured by lattice defects 202 in the first lifetime regions 204 on either side when the electrons or holes pass through the second lifetime region 200. The width W1 may be 8 μm or more, or 9 μm or more. The width W1 may be 12 μm or less. If the width W1 is too large, the turn-off time of the diode section 80 increases, and reverse recovery loss also increases. The width W1 may be 11 μm or less, or 10 μm or less.

[0110] The spacing between trench portions (dummy trench portions 30 in this example) in the X-axis direction is defined as W2. The spacing between trench portions may be the spacing between the centers of the trench portions in the X-axis direction. The width W1 of the second lifetime region 200 may be larger than the spacing W2 between the trench portions. In other words, the width W1 of the second lifetime region 200 may be larger than the mesa width of a mesa portion sandwiched between two adjacent trench portions in the X-axis direction. The width W1 may be 1.2 times or more, 1.5 times or more, or even 2 times or more the spacing W2. The width W1 may be 10 times or less, 5 times or less, or 3 times or less the spacing W2.

[0111] FIG. 7 shows an example of the distribution of carrier lifetime, vacancy density, and helium chemical concentration along the ff line in FIG. 6. The ff line is a straight line parallel to the X-axis direction and passing through two first lifetime regions 204 and one second lifetime region 200. The carrier lifetime in the first lifetime region 204 is denoted as τ1, and the carrier lifetime in the second lifetime region 200 is denoted as τ2. The minimum value of the carrier lifetime in the first lifetime region 204 may be used as the carrier lifetime τ1. The maximum value of the carrier lifetime in the second lifetime region 200 may be used as the carrier lifetime τ2. The carrier lifetime τ2 may be the same as or smaller than the carrier lifetime in the drift region 18. The value at the center of the drift region 18 in the depth direction may be used as the carrier lifetime in the drift region 18, or an average value may be used.

[0112] The position where the carrier lifetime becomes τa is defined as the boundary position between the first lifetime region 204 and the second lifetime region 200. τa is a value greater than or equal to τ1 and less than or equal to τ2. τa may be equal to either τ1 or τ2, or may be a value obtained by multiplying either τ1 or τ2 by a predetermined coefficient. τa may be a value slightly greater than τ1, the average value of τ1 and τ2, or another value. The position where the carrier lifetime becomes greater than τ1 may be defined as the boundary position between the first lifetime region 204 and the second lifetime region 200. The carrier lifetime τ2 of the second lifetime region 200 may be 10 times or more, 100 times or more, or 1000 times or more the carrier lifetime τ1 of the first lifetime region 204. For example, the carrier lifetime τ1 is 100 ns or less, and the carrier lifetime τ2 is 1 μs or more. τ1 may be 10 ns or less, and τ2 may be 10 μs or more.

[0113] The vacancy density in the first lifetime region 204 is defined as V1, and the vacancy density in the second lifetime region 200 is defined as V2. The maximum vacancy density in the first lifetime region 204 may be used as the vacancy density V1. The minimum vacancy density in the second lifetime region 200 may be used as the vacancy density V2. The vacancy density V2 may be the same as or larger than the vacancy density in the drift region 18. The vacancy density in the drift region 18 may be the value at the center in the depth direction of the drift region 18, or an average value may be used.

[0114] The position where the vacancy density becomes Va may be determined as the boundary position between the first lifetime region 204 and the second lifetime region 200. Va is a value greater than or equal to V2 and less than or equal to V1. Va may be the same as either V1 or V2, or may be a value obtained by multiplying either V1 or V2 by a predetermined coefficient. Va may be a value slightly smaller than V1, may be the average value of V1 and V2, or may be some other value. The position where the vacancy density becomes smaller than V1 may be determined as the boundary position between the first lifetime region 204 and the second lifetime region 200.

[0115] The helium chemical concentration in the first lifetime region 204 is designated as H1, and the helium chemical concentration in the second lifetime region 200 is designated as H2. The maximum value of the helium chemical concentration in the first lifetime region 204 may be used as the helium chemical concentration H1. The minimum value of the helium chemical concentration in the second lifetime region 200 may be used as the helium chemical concentration H2. The helium chemical concentration H2 may be the same as or greater than the helium chemical concentration in the drift region 18. The helium chemical concentration in the drift region 18 may be the value at the center in the depth direction of the drift region 18, or an average value may be used.

[0116] The position where the helium chemical concentration becomes Ha may be determined as the boundary position between the first lifetime region 204 and the second lifetime region 200. Ha is a value greater than or equal to H2 and less than or equal to H1. Ha may be equal to either H1 or H2, or may be a value obtained by multiplying either H1 or H2 by a predetermined coefficient. Ha may be a value slightly smaller than H1, the average value of H1 and H2, or another value. The position where the helium chemical concentration becomes smaller than H1 may be determined as the boundary position between the first lifetime region 204 and the second lifetime region 200. When lattice defects are formed by implanting charged particles other than helium, the boundary position between the first lifetime region 204 and the second lifetime region 200 may be determined based on the chemical concentration of the charged particles.

[0117] Figure 8 shows an example of the distribution of carrier lifetime, vacancy density, and helium chemical concentration at the g-g line in Figure 6. The g-g line is a straight line that crosses the first lifetime region 204 in the Z-axis direction. In this example, the first lifetime region 204 is sandwiched between drift regions 18 in the Z-axis direction. In this example, the drift region 18 has a carrier lifetime of τ2, a vacancy density of V2, and a helium chemical concentration of H2.

[0118] The position where the carrier lifetime is τa may be set as the boundary position between the first lifetime region 204 and the drift region 18. The carrier lifetime τa is the same as in the example explained in FIG. 7. smaller than τ2 The position where the vacancy density becomes Va may be determined as the boundary position between the first lifetime region 204 and the drift region 18. The position where the vacancy density becomes Va may be determined as the boundary position between the first lifetime region 204 and the drift region 18. The vacancy density Va is the same as in the example described in FIG. 7. Larger than V2 The position where the helium chemical concentration becomes Ha may be taken as the boundary position between the first lifetime region 204 and the drift region 18. The position where the helium chemical concentration becomes Ha may be taken as the boundary position between the first lifetime region 204 and the drift region 18. The helium chemical concentration Ha is the same as in the example described in FIG. 7. Larger than H2The position where the first lifetime region 204 is reached is called the first lifetime region 204. Drift Region 18 The carrier lifetime distribution in the first lifetime region 204 may be a distribution that decreases Gaussianly from τ2. The vacancy density distribution in the first lifetime region 204 may be a distribution that increases Gaussianly from V2. The helium chemical concentration distribution in the first lifetime region 204 may be a distribution that increases Gaussianly from H2.

[0119] FIG. 9 is a diagram showing an example of the distribution of the carrier lifetime, vacancy density, and helium chemical concentration along the hh line in FIG. 6. The hh line is Second Lifetime Region 200 The second lifetime region 200 of this example is sandwiched between the drift regions 18 in the Z-axis direction.

[0120] In this example, Second Lifetime Region 200 and the carrier lifetime of the drift region 18 is τ, the vacancy density is V, and the helium chemical concentration is H. In another example, Second Lifetime Region 200 The carrier lifetime of the GaN layer may be shorter than the carrier lifetime of the drift region 18, as shown by the dashed line in FIG. Second Lifetime Region 200 The vacancy density in the first region may be higher than the vacancy density in the drift region 18, as shown by the dashed line in FIG. Second Lifetime Region 200 The helium chemical concentration in the second lifetime region 200 may be higher than the helium chemical concentration in the drift region 18, as shown by the dashed line in Figure 9. The carrier lifetime distribution in the second lifetime region 200 may be a distribution that Gaussianly decreases from τ. The vacancy density distribution in the second lifetime region 200 may be a distribution that Gaussianly increases from V. The helium chemical concentration distribution in the second lifetime region 200 may be a distribution that Gaussianly increases from H.

[0121] 10 is another example of an enlarged cross-sectional view of the vicinity of the second lifetime region 200. In this example, the first lifetime region 204 is formed by implanting hydrogen ions into the semiconductor substrate 10. When the hydrogen ions are implanted, lattice defects 202 are formed in the passage region through which the hydrogen ions have passed. The hydrogen ions may be implanted from the upper surface 21 of the semiconductor substrate 10. The first lifetime region 204 may be formed up to the upper surface 21 of the semiconductor substrate 10. The structure other than the first lifetime region 204 is the same as any of the embodiments described herein.

[0122] When the first lifetime region 204 is formed up to the upper surface 21 of the semiconductor substrate 10, the thickness T1 is the distance from the lower end of the first lifetime region 204 to the upper surface 21. As described herein, the width W1 of the second lifetime region 200 may be determined according to the thickness T1. The distance in the depth direction from the depth position of the density peak of the lattice defects 202 to the lower end of the first lifetime region 204 is defined as T1'. The thickness T1 of the first lifetime region 204 may be 2×T1'.

[0123] FIG. 11A shows distribution diagrams of the net doping concentration (A), hydrogen chemical concentration (B), lattice defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along line hh in the semiconductor device 100 according to the embodiment shown in FIG. 10. The horizontal axis in each distribution diagram indicates the position in the depth direction. In this example, hydrogen ions are implanted from the upper surface 21 to a depth position Ps to form the first lifetime region 204. The buffer region 20 also has multiple doping concentration peaks. In FIG. 11A, the doping concentration peaks are located at depth positions Pb1 to Pb4 in ascending order from the lower surface 23. At a depth position Kb, a lower-side lifetime region 19 is provided, which is formed by irradiating charged particles such as helium.

[0124] The distribution diagram (A) shows the net doping concentration distribution of electrically activated donors and acceptors. In this example, the concentration N pIn FIG. 11A, the region where the peak is provided is designated as a high-concentration region 26. The doping concentration in a portion of the region on the lower surface 23 side from the position Ps is designated as a doping concentration N0. The doping concentration N0 may be a bulk donor concentration. The bulk donor of the semiconductor substrate 10 may be phosphorus, antimony, or arsenic, and may further include a bulk acceptor (boron, aluminum, indium, etc.) to an extent that does not exceed the bulk donor concentration.

[0125] In distribution diagram (A), an N-type region having a doping concentration higher than that of drift region 18 is defined as N+ type. The doping concentration of at least a portion of drift region 18 between positions Ps and Pb4 may be lower than the doping concentration of drift region 18 on the upper surface 21 side of position Ps. Hydrogen ions implanted from the upper surface 21 of semiconductor substrate 10 pass through drift region 18 on the upper surface 21 side. Therefore, the doping concentration of drift region 18 may be higher than the doping concentration N0 of semiconductor substrate 10 due to remaining hydrogen donors. The average doping concentration of drift region 18 on the upper surface 21 side may be three times or less the doping concentration N0 of semiconductor substrate 10.

[0126] Hydrogen ions are implanted into positions Pb4, Pb3, Pb2, and Pb1 from the lower surface 23 of the semiconductor substrate 10. Therefore, the doping concentration in the region on the lower surface 23 side of position Pb4 may be higher than the doping concentration N0 of the semiconductor substrate 10 as a whole. That is, the doping concentration (donor concentration in this example) of the drift region 18 in the region sandwiched in the depth direction between two hydrogen donor peaks (the hydrogen donor peaks at positions Ps and Pb4 in this example) is the lowest. The doping concentration (donor concentration in this example) in the region sandwiched between these two hydrogen donor peaks is the doping concentration N0 of the semiconductor substrate 10, and the doping concentration distribution may be substantially flat. A doping concentration distribution being substantially flat may be defined as when the difference between the maximum and minimum doping concentrations in a region of a predetermined proportion to the distance between positions Ps and Pb4 is 50% or less of the average doping concentration in that region. The predetermined ratio may be any value in the range of 50% to 80% of the distance between positions Ps and Pb4. Due to the hydrogen donors, the doping concentration from position Ps to the upper surface 21 and from position Pb4 to the lower surface 23 may be higher than the doping concentration N0 of the semiconductor substrate 10. In this example, the cathode region 82 is formed by implanting phosphorus and diffusing or electrically activating it.

[0127] 11A, an N+ type accumulation region 16 may be provided between the anode region 14 and the drift region 18. In each mesa portion, the accumulation region 16 may be provided continuously from one to the other of two trench portions adjacent to each other in the X-axis direction.

[0128] The distribution diagram (B) shows the chemical concentration of implanted hydrogen (hydrogen chemical concentration). Each peak of the hydrogen chemical concentration has a base on the main surface side where the hydrogen ions are implanted. In this example, the hydrogen chemical concentration peak at position Ps has a base S on the top surface 21 side. That is, the hydrogen chemical concentration distribution in this example gradually and monotonically decreases on the top surface 21 side from the first position Ps to the top surface 21. The base S may be provided across the drift region 18 and the anode region 14.

[0129] The hydrogen chemical concentration distribution in this example has a base where the change in concentration distribution is steeper from position Ps to the lower surface 23 side than base S. That is, the hydrogen chemical concentration distribution exhibits an asymmetric distribution on the upper surface 21 side and the lower surface 23 side of position Ps.

[0130] Furthermore, the hydrogen chemical concentration peaks at positions Pb4, Pb3, Pb2, and Pb1 each have a base S' on the lower surface 23 side. The hydrogen chemical concentration peaks at positions Pb4, Pb3, Pb2, and Pb1 each have a base on the upper surface 21 side where the change in concentration distribution is steeper than base S'. That is, the hydrogen chemical concentration peaks at positions Pb4, Pb3, Pb2, and Pb1 each have a base S' on the upper surface 21 side where the change in concentration distribution is steeper than base S'. its location The distribution is asymmetric on the upper surface 21 side and the lower surface 23 side.

[0131] The hydrogen chemical concentration may be minimum between the position closest to the lower surface 23 among the positions where hydrogen ions are implanted from the upper surface 21 (position Ps in this example) and the position closest to the upper surface 21 among the positions where hydrogen ions are implanted from the lower surface 23 (position Pb4 in this example). The position where the hydrogen chemical concentration is minimum is the position where the sum of the distribution of hydrogen implanted at position Ps and the distribution of hydrogen implanted at position Pb4 is minimum. Alternatively, the position where the hydrogen chemical concentration is minimum may be sandwiched between two hydrogen donor peaks (positions Ps and Pb4 in this example) and in a region of a substantially flat doping concentration distribution where the doping concentration indicates the doping concentration N0 of the semiconductor substrate 10. Alternatively, the position where the hydrogen chemical concentration is minimum may be on the upper surface 21.

[0132] The distribution diagram (C) shows the lattice defect density after implanting hydrogen ions into the semiconductor substrate 10 and then annealing under predetermined conditions. The position Z0 is the position where the net doping concentration of the high concentration region 26 is approximately equal to the doping concentration N0 of the semiconductor substrate 10 on the lower surface 23 side of the position Ps. On the lower surface 23 side of the position Z0, the lattice defect density may be a sufficiently small value Nr0. The lattice defect density being a sufficiently small value Nr0 means that the lattice defect density has a value low enough that the carrier lifetime is not shorter than τ0, which will be described below. As an example, let the concentration of vacancies or divacancies be Nr0, and let Nr0 be 1×10 at a temperature of 300 K. 12 atoms / cm 3 or smaller, 1×10 11 atoms / cm 3 May be less than 1 x 10 10 atoms / cm 3 At the position J0 of the pn junction between the anode region 14 and the drift region 18 or the accumulation region 16, the lattice defect density may be higher than Nr0.

[0133] Lattice defects are formed in the vicinity of position Ps and in the passage region from the upper surface 21 to position Ps due to the passage of hydrogen ions. This allows the formation of a first lifetime region 204. However, since lattice defects are terminated by hydrogen in the vicinity of position Ps, the distribution of lattice defect density and the distribution of hydrogen chemical concentration have different shapes. For example, the peak position Ps of the hydrogen chemical concentration does not coincide with the peak position Ks of the lattice defect density. In this example, the peak position Ks of the lattice defect density is located closer to the upper surface 21 of the semiconductor substrate 10 than the peak position Ps of the hydrogen chemical concentration. The lattice defect density may decrease monotonically on the upper surface 21 side of position Ks. The lattice defect density may decrease more steeply and monotonically on the lower surface 23 side of position Ks than on the upper surface 21 side.

[0134] Near the peak position Ps of the hydrogen chemical concentration, a large amount of hydrogen terminates dangling bonds such as vacancies and divacancies. Therefore, the lattice defect density near the peak position Ps of the hydrogen chemical concentration is much smaller than the lattice defect density at the peak position Ks of the lattice defect density. In this specification, the width of the distribution showing a concentration greater than 1% of the peak concentration is referred to as the 1% full width or FW1%M. The vicinity of the peak position Ps may refer to the region within the 1% full width range centered on the peak position Ps. The peak position Ks of the lattice defect density may be located at a position shallower than the 1% full width range centered on the peak position Ps.

[0135] However, the distance D between the peak position Ks of the lattice defect density and the peak position Ps of the hydrogen chemical concentration is determined depending on the distance hydrogen diffuses within the semiconductor substrate 10 due to annealing. The distance D may be 40 μm or less, 20 μm or less, or 10 μm or less. The distance D may be 1 μm or more, 3 μm or more, or 5 μm or more. The distance D may be greater than or equal to the 1% full width of the hydrogen chemical concentration. The distance D may be greater than or equal to the 1% full width of the net doping concentration at the position Ps. In this case, the 1% full width of the net doping concentration is the width of the peak at 0.01 Np. The value range of the distance D may be a combination of any of the upper and lower limits described above. For example, the lattice defect density distribution can be observed by measuring the density distribution of vacancies and divacancies using positron annihilation spectroscopy.

[0136] The depth position from the upper surface 21 toward the lower surface 23 where the lattice defect density first coincides with Nr0 is defined as Z1. The first lifetime region 204 may be provided from the upper surface 21 to position Z1. As described in FIG. 10, the thickness from the upper surface 21 to position Z1 may be defined as T1. In another example, twice the distance T' from position Ks to position Z1 may be used as the thickness T1. The first lifetime region 204 in this example includes a hydrogen donor.

[0137] A lattice defect density peak (lower surface-side lifetime region 19) may be located between the lower surface 23 and position Pb4. In this example, the lattice defect density peak (lower surface-side lifetime region 19) is located at position Kb between positions Pb2 and Pb1. The lattice defect density peak at position Kb mainly contains lattice defects formed when helium ions are implanted from the lower surface 23 between positions Pb2 and Pb1. In this example, no lattice defect density peak is located on the lower surface 23 side of position Pb4 other than at position Kb.

[0138] For example, hydrogen ions are implanted at positions Pb4, Pb3, Pb2, and Pb1, and the semiconductor substrate 10 is annealed under first conditions. This results in peaks of the hydrogen chemical concentration distribution at positions Pb4, Pb3, Pb2, and Pb1. Thereafter, hydrogen ions are implanted at position Ps, and helium ions are implanted between positions Pb2 and Pb1, and the semiconductor substrate 10 is annealed under second conditions. The second conditions have an annealing temperature lower than that of the first conditions. Most of the lattice defects caused by the implantation of hydrogen ions at positions Pb4, Pb3, Pb2, and Pb1 are terminated by annealing at a relatively high temperature. In contrast, the lattice defects caused by the implantation of hydrogen ions at position Ps are terminated by annealing at a relatively low temperature. On the other hand, since a large amount of hydrogen is also present near position Pb1, the lattice defects generated by implanting helium ions between positions Pb2 and Pb1 are also terminated near position Pb1, and the lattice defect density has a peak between positions Pb2 and Pb1.

[0139] In this example, the peak of the hydrogen chemical concentration at the position Ps is not provided with other peaks of the hydrogen chemical concentration on the side where the hydrogen ions are implanted (on the upper surface 21 side in this example). positionThe peak of the hydrogen chemical concentration at Pb2 is located on the side where helium ions are implanted (the side of the lower surface 23 in this example), and another hydrogen chemical concentration peak (position Pb1) is located on that side. The integral value of the lattice defect density on the upper surface 21 side of position Ps may be greater than the integral value of the lattice defect density on the lower surface 23 side of position Pb2. The lattice defect density at position Kb may be the helium chemical concentration.

[0140] The distribution diagram (D) shows the carrier lifetime distribution after annealing under predetermined conditions after implanting hydrogen ions into the semiconductor substrate 10. The carrier lifetime distribution is a function of the lattice defect density. minutes The vertical axis of the fabric is inverted. For example, the position where the carrier lifetime is at its minimum is lattice This coincides with the center peak position Ks of the defect density. In a region within the range of FW1%M centered on the peak position Ps of the hydrogen chemical concentration, the carrier lifetime of the semiconductor device 100 may be a maximum value τ0. The maximum value τ0 may be the carrier lifetime in the drift region 18 on the lower surface 23 side of the peak position Ps of the hydrogen chemical concentration. In a region within the range of FW1%M centered on each of the peak positions Ps, Pb4, Pb3, Pb2, and Pb1 of the hydrogen chemical concentration, the carrier lifetime of the semiconductor device 100 may be a maximum value τ0.

[0141] The carrier lifetime may be a sufficiently large value τ0 on the lower surface 23 side of position Z0. A sufficiently large carrier lifetime τ0 may be the carrier lifetime when lifetime killers or defects mainly consisting of vacancies or divacancies are not intentionally introduced into the semiconductor substrate 10. At a temperature of 300 K, τ0 may be 10 μs or more, or may be 30 μs or more. As an example, τ0 is 10 μs. At position J0 of the pn junction between the anode region 14 and the drift region 18 or the accumulation region 16, the carrier lifetime may be shorter than τ0.

[0142] The distribution diagram (E) shows the distribution of carrier mobility after implanting hydrogen ions into the semiconductor substrate 10 and then annealing under predetermined conditions. On the lower surface 23 side of the position Z0, the carrier mobility may be the mobility μ0 in the case of an ideal crystal structure. For example, in the case of silicon at a temperature of 300 K, the mobility μ0 is 1360 cm 2 / (Vs), hole is 495cm 2 / (Vs). At the position J0 of the pn junction between the anode region 14 and the drift region 18 or the accumulation region 16, the carrier mobility may be smaller than μ0.

[0143] The position where the carrier mobility is at its minimum may coincide with the center peak position Ks of the lattice defect density. The position where the carrier mobility is at its minimum may coincide with the center peak position Kb of the lattice defect density. In the region within the range FW1%M centered on each of the peak positions Ps, Pb4, Pb3, Pb2, and Pb1 of the hydrogen chemical concentration, the carrier mobility of the semiconductor device 100 may be at its maximum value μ0.

[0144] The distribution diagram (F) shows the distribution of carrier concentration after implanting hydrogen ions into the semiconductor substrate 10 and then annealing under predetermined conditions. The carrier concentration can be measured by, for example, spreading resistance measurement (SR measurement). In the SR measurement, spreading resistance is converted into resistivity, and the carrier concentration is calculated from the resistivity. The resistivity is expressed as ρ (Ω·cm) and the mobility is expressed as μ (cm 2 / (V s)), the elementary charge q (C), and the carrier concentration N ( / cm 3 ), then N=1 / (μqρ).

[0145] In the SR measurement method, the carrier mobility is calculated based on the ideal crystalline state of the semiconductor substrate 10. However, if damage to the semiconductor substrate 10 occurs due to ion implantation, the crystalline state of the semiconductor substrate 10 is disrupted, resulting in a disordered state, resulting in a reduced mobility. Ideally, the reduced mobility should be used as the mobility in the SR measurement, but it is difficult to measure the reduced mobility value. For this reason, the ideal value is used for the mobility in the SR measurement shown in the example of distribution diagram (F). This results in a larger denominator for the carrier concentration equation described above, resulting in a reduced mobility. In other words, in distribution diagram (F), the measured carrier concentration is generally reduced in the region through which hydrogen ions have passed (the region from the bottom of the anode region 14 of the semiconductor substrate 10 to the high-concentration region 26). However, in the high-concentration region 26 near the hydrogen ion range Ps, the hydrogen chemical concentration is high, which alleviates the disordered state due to the hydrogen termination effect, bringing the mobility closer to the crystalline state. Furthermore, hydrogen donors are also formed. Therefore, the carrier concentration is higher than the carrier concentration N0 of the semiconductor substrate 10.

[0146] In the region through which the hydrogen ions have passed (the region from the lower end of the anode region 14 of the semiconductor substrate 10 to the vicinity of the position Ps), the measured carrier concentration is generally lower. However, in the region on the lower surface 23 side of the position Pb4, the hydrogen chemical concentration is generally higher, and therefore the carrier concentration is higher than the substrate concentration N0.

[0147] In the semiconductor device 100 of this example, the lattice defect density after annealing decreases around the peak position Ps of the hydrogen chemical concentration, and therefore the carrier lifetime near the peak position Ps of the hydrogen chemical concentration increases and becomes approximately τ0.

[0148] As an example, the hydrogen chemical concentration at the peak position Pb1 is the highest in the entire semiconductor substrate 10. The maximum value of the hydrogen chemical concentration at the peak position Pb1 is 1×10 15 atoms / cm 3If the value is 1 or more, the concentration of hydrogen diffusing to the upper surface 21 side increases. At this time, hydrogen diffuses up to the position Ps. As a result, the dangling bond due to the vacancy or divacancy at the position Ps is position In addition to the hydrogen injected into Ps at the maximum concentration, position It is also terminated by hydrogen that has moved by diffusion from the position of Pb1. This ensures that the lattice defect density near the peak of the doping concentration distribution at position Ps is Nr0, and the carrier lifetime at position Ps can be τ0.

[0149] FIG. 11B is another example of an enlarged cross-sectional view of the vicinity of the second lifetime region 200. This example differs from the example of FIG. 10 in that hydrogen ions are implanted from the lower surface 23 toward the upper surface 21 (e.g., near the lower end of the trench portion or the upper surface 21) to form the first lifetime region 204. The distance T1 from the lower surface 23 to the end of the first lifetime region 204 on the upper surface 21 side may be greater than half the thickness of the semiconductor substrate 10 in the Z-axis direction. The distance T1 in this example corresponds to the thickness of the first lifetime region 204. As in the example of FIG. 10, the depth distance from the depth position of the density peak of the lattice defects 202 to the upper end of the first lifetime region 204 is defined as T1'. The thickness T1 of the first lifetime region 204 may be 2×T1'.

[0150] FIG. 11C shows the distributions of the net doping concentration (A), hydrogen chemical concentration (B), lattice defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along the line hh in the semiconductor device 100 according to the embodiment shown in FIG. 11B. Figure 11C , at least one of the doping concentration and the carrier concentration on the buffer region 20 side of the drift region 18 may be higher than the bulk donor concentration. The buffer region 20 side of the drift region 18 refers to the side closer to the buffer region 20 than the center of the drift region 18 in the depth direction. In the example of FIG. 11C , a region in the drift region 18 where at least one of the doping concentration and the carrier concentration is higher than the bulk donor concentration is provided at a position in contact with the buffer region 20.

[0151] FIG. 11D is another example of an enlarged cross-sectional view of the vicinity of the second lifetime region 200. This example differs from the examples of FIGS. 10 and 11B in that the first lifetime region 204 is formed over the entire area from the upper surface 21 to the lower surface 23. The first lifetime region 204 in this example may be formed by implanting hydrogen ions or helium from the upper surface 21 and passing through the lower surface 23, or by implanting hydrogen ions or helium from the lower surface 23 and passing through the upper surface 21. The first lifetime region 204 in this example may be formed by irradiating with an electron beam. The thickness T1 of the first lifetime region 204 in this example is the same as the thickness of the semiconductor substrate 10. As an example, T1 may be the width of a region where the density of lattice defects 202 is equal to or greater than a predetermined value. The predetermined value of the density of lattice defects 202 is 1×10 14 / cm 3 The predetermined value of the density of lattice defects 202 may be set as the value of the doping concentration of the drift region 18. As another example, T1 may be the width of the region where the carrier concentration measured by SR measurement is lower than the doping concentration of the drift region 18. The doping concentration of the drift region 18 may be the bulk donor concentration, the difference between the bulk donor concentration and the bulk acceptor concentration, the sum of the bulk donor concentration and the hydrogen donor concentration, or the sum of the difference between the bulk donor concentration and the bulk acceptor concentration and the hydrogen donor concentration.

[0152] FIG. 12 is a diagram showing an example of a VI characteristic when the diode section 80 is in forward conduction. A characteristic 250 shown in FIG. 12 is the same as the characteristic of the comparative example shown in FIG. 4. In the comparative example, the second lifetime region 200 is not provided. A characteristic 251 shown in FIG. 12 is a characteristic of an example in which one second lifetime region 200 is provided in one diode section 80, as described with reference to FIGS. 5 to 9. In the example of characteristic 251, the width W1 of the second lifetime region 200 is 8 μm, the thickness T1 of the first lifetime region 204 is 30 μm, and the ratio W1 / T1 is about 0.27. Characteristic 250-1 and characteristic 25 1The carrier lifetimes in the first lifetime region 204 are the same, and the characteristics 250-2 and 250-1 are the same. 1 The carrier lifetimes in the first lifetime region 204 are the same, and the characteristics 250-3 and 250-2 are the same. 1 -3 have the same carrier lifetime in the first lifetime region 204. As shown in Fig. 12, by providing the second lifetime region 200, snapback can be suppressed even if the carrier lifetime in the first lifetime region 204 is shortened. This makes it possible to reduce the reverse recovery loss of the diode section 80 while suppressing snapback.

[0153] Fig. 13 is a diagram showing the trade-off characteristics between the forward voltage Vf and the reverse recovery loss Err in the diode section 80. The plots indicated by circles in Fig. 13 are characteristics when one second lifetime region 200 is provided in one diode section 80, as described in Figs. 5 to 9. The plots indicated by squares in Fig. 13 are characteristics when no second lifetime region 200 is provided. In the example indicated by a solid square, snapback occurs.

[0154] 13, even when the second lifetime region 200 is provided, the same trade-off characteristics can be obtained as compared to when the second lifetime region 200 is not provided. Furthermore, even in regions with short carrier lifetimes, the occurrence of snapback can be suppressed by providing the second lifetime region 200.

[0155] FIG. 14 is a diagram showing the relationship between the width W1 of the second lifetime region 200 and the amount of snapback (SB amount). In this example, as described in FIGS. 5 to 9, one second lifetime region 200 is provided in one diode section 80. In this example, the thickness T1 of the first lifetime region 204 is 30 μm. It can be seen that the amount of snapback decreases by increasing the width W1 of the second lifetime region 200. In particular, when the width W1 of the second lifetime region 200 exceeds 7 μm, the amount of snapback decreases significantly, and when the width W1 is 11 μm or more, the amount of snapback becomes zero.

[0156] The width W1 of the second lifetime region 200 may be 7 μm or more. The width W1 may be 8 μm or more, 10 μm or more, or even 11 μm or more. The ratio W1 / T1 of the width W1 of the second lifetime region 200 to the thickness T1 of the first lifetime region 204 may be 0.23 or more, 0.27 or more, 0.33 or more, or 0.37 or more. Also, Second Lifetime Region 200 The width W1 may be 12 μm or less, and the ratio W1 / T1 may be 0.4 or less.

[0157] Fig. 15 is a diagram showing whether snapback occurs when the thickness T1 of the first lifetime region 204 and the width W1 of the second lifetime region 200 are changed. The circle plots in Fig. 15 indicate boundary cases where snapback does not occur. In regions 220, 222, and 224 where the width W1 is larger (or the thickness T1 is smaller) than the boundary cases, snapback does not occur.

[0158] However, in region 222, the thickness T1 of the first lifetime region 204 is large, which weakens the IE effect and results in an excessively high forward voltage Vf. In region 224, the thickness T1 of the first lifetime region 204 is small, which strengthens the IE effect even in the low current operating region and results in an excessively low forward voltage Vf. For this reason, it is preferable to set the thickness T1 of the first lifetime region 204 and the width W1 of the second lifetime region 200 within the range of region 220. Region 220 is a region where width W1 is larger than the width W (μm) defined by line 230. Line 230 is given by equation (1). W=0.21×T1+3.3 (1)

[0159] As described above, if the thickness T1 of the first lifetime region 204 is too large, the IE effect will be weak. The thickness T1 may be less than the thickness of the drift region 18 in the depth direction (Z-axis direction). The thickness T1 may also be 100 μm or less, 60 μm or less, or 40 μm or less. The thickness T1 is greater than 0. However, if the thickness T1 is too small, the IE effect will be strong even in the low current operating region, and the forward voltage Vf will become too low. The thickness T1 may be 10 μm or more, 15 μm or more, or 20 μm or more.

[0160] 16A is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 in the diode section 80. Other than the arrangement of the first lifetime region 204 and the second lifetime region 200, it is the same as any of the embodiments described in FIGS.

[0161] The semiconductor device 100 of this example includes two or more second lifetime regions 200 in one diode section 80. The second lifetime regions 200 are arranged at intervals in a first direction (the X-axis direction in this example). A first lifetime region 204 is arranged between the two second lifetime regions 200. The width W1 of each second lifetime region 200 may be the same as the width W1 described with reference to FIGS. 1 to 15. By providing two or more second lifetime regions 200, the electron density above the first lifetime region 204 can be made uniform. Electrons can be distributed among the multiple second lifetime regions 200 and pass through.

[0162] 1 to 16A, the sum of the widths W1 in the first direction (the X-axis direction in this example) of one or more second lifetime regions 200 included in one diode section 80 may be 0.1 times or less the width WD in the first direction of one diode section 80. If the sum of the widths W1 becomes too large, the turn-off time of the diode section 80 will be longer and the reverse recovery loss will increase. The sum of the widths W1 may be 0.05 times or less the width WD. The sum of the widths W1 may be 0.001 times or more the width WD, and is preferably 0.01 times or more.

[0163] The diode section 80 has a plurality of trenches (dummy trenches 30 in this example) disposed above the first lifetime region 204. A distance D2 between the second lifetime region 200 and the transistor section 70 in the first direction (the X-axis direction in this example) may be equal to or greater than a distance D1 between a lower end of a trench (the dummy trench 30 in this example) and the first lifetime region 204 in the second direction (the Z-axis direction in this example). The trench may be the dummy trench 30 closest to the transistor section 70 among the plurality of dummy trenches 30 in the diode section 80. The end of the transistor section 70 in the X-axis direction is the boundary between the collector region 22 and the cathode region 82. Ensuring the distance D2 can prevent electrons injected from the cathode region 82 from spreading to the transistor section 70 and reduce their leakage to the emitter electrode 52 through an n-type channel formed in the base region 14 of the transistor section 70. The distance D2 may be 1.5 times or more, or may be twice or more, the distance D1.

[0164] Two or more second lifetime regions 200 may be arranged at equal intervals in the first direction. In another example, the interval W3 between the second lifetime regions 200 may be smaller than the distance D2. This configuration also allows the distance D2 to be increased. In this example, the interval W3 between the second lifetime regions 200 is the width of the first lifetime region 204 in the first direction. Any one of the second lifetime regions 200 may be disposed in the center of the diode section 80 in the first direction. This allows electrons or holes to be injected symmetrically with respect to the center of the diode section 80, resulting in a substantially uniform distribution of carrier concentration in the diode section 80.

[0165] FIG. 16B illustrates another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 in the diode section 80. This example differs from the example of FIG. 16A in that the first lifetime region 204 and the second lifetime region 200 are formed on the lower surface 23 side. The first lifetime region 204 and the second lifetime region 200 may be formed inside the buffer region 20, in both the buffer region 20 and the cathode region 82, or in both the buffer region 20 and the collector region 22. As in the example of FIG. 11B, the depth distance from the depth position of the density peak of lattice defects 202 to the upper end of the first lifetime region 204 is defined as T1'. The thickness T1 of the first lifetime region 204 may be 2×T1'. This allows electrons or holes to be uniformly injected in the first direction, suppressing snapback.

[0166] FIG. 16C illustrates another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 in the diode section 80. This example differs from the example of FIG. 16B in that the first lifetime region 204 and the second lifetime region 200 are formed on the lower surface 23 side of the drift region 18. The distance T1 from the lower surface 23 to the upper end of the first lifetime region 204 may be smaller than half the thickness of the semiconductor substrate 10 in the Z-axis direction. When the first lifetime region 204 is formed by implanting hydrogen ions or the like from the lower surface 23, the distance T1 corresponds to the thickness of the first lifetime region 204. As in the example of FIG. 11B, the depth distance from the depth position of the density peak of lattice defects 202 to the upper end of the first lifetime region 204 is defined as T1'. The thickness T1 of the first lifetime region 204 may be 2×T1'.

[0167] FIG. 17 is a diagram showing whether snapback occurs when the number of second lifetime regions 200 included in one diode section 80 and the width W1 of each second lifetime region 200 are changed. The circle plots in FIG. 17 indicate boundary examples where snapback does not occur. Snapback does not occur in regions 240 with a width W1 larger than the boundary examples. When multiple second lifetime regions 200 are provided, the multiple second lifetime regions 200 are arranged at equal intervals in the first direction. In this example, the thickness T1 of the first lifetime region 204 is 30 μm.

[0168] Increasing the number of second lifetime regions 200 (the number of regions on the horizontal axis in FIG. 17) tends to suppress snapback even if the width W1 of the second lifetime regions 200 is reduced. However, even if the number of second lifetime regions 200 is increased beyond four, the width W1 of the second lifetime regions 200 required to prevent snapback does not become smaller.

[0169] The width W1 of one second lifetime region 200 may be 8 μm or more. The width W1 may be 0.27 times or more the thickness T1 of the first lifetime region 204. Even when only one second lifetime region 200 is provided in one diode section 80, a width W1 of approximately 12 μm can suppress snapback. The width W1 may be 12 μm or less. The width W1 may be 0.4 times or less the thickness T1 of the first lifetime region 204.

[0170] 18 is a diagram showing an example of the arrangement of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the first lifetime region 204 and the second lifetime region 200 are stripe-shaped and are parallel to the upper surface 21 of the semiconductor substrate 10, with their elongated sides extending in a third direction (the Y-axis direction in this example) perpendicular to the first direction (the X-axis direction in this example). The first lifetime region 204 and the second lifetime region 200 may have the same length as the cathode region 82 in the Y-axis direction, or may be longer than the cathode region 82.

[0171] In this example, the diode section 80 and the transistor section 70 are arranged side by side in the first direction (X-axis direction). As shown in FIG. 2 and other figures, the trench sections (gate trench section 40 and dummy trench section 30) are arranged at intervals in the first direction (X-axis direction). In this example, the longitudinal direction of the first lifetime region 204 and the second lifetime region 200 is the same as the longitudinal direction of the trench section. The longitudinal direction of the first lifetime region 204 and the second lifetime region 200 is the same as the longitudinal direction of the diode section 80 (or cathode region 82).

[0172] 19 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. In this example, the Y-axis direction is the first direction, and the X-axis direction is the third direction. That is, the first lifetime region 204 and the second lifetime region 200 of this example are arranged side by side in the Y-axis direction. The first lifetime region 204 and the second lifetime region 200 of this example are in a stripe shape with their longitudinal axes in the X-axis direction (third direction). The first lifetime region 204 and the second lifetime region 200 may have the same length as the diode section 80 in the X-axis direction, or may be longer than the diode section 80.

[0173] In this example, the diode section 80 and the transistor section 70 are arranged side by side in the third direction (X-axis direction). Furthermore, the trench sections (gate trench section 40 and dummy trench section 30) are arranged at intervals in the third direction (X-axis direction). In this example, the longitudinal direction of the first lifetime region 204 and the second lifetime region 200 is perpendicular to the longitudinal direction of the trench section. Furthermore, the longitudinal direction of the first lifetime region 204 and the second lifetime region 200 is perpendicular to the longitudinal direction of the diode section 80 (or the cathode region 82). Even with this arrangement, it is possible to reduce the reverse recovery loss of the diode section 80 while suppressing snapback.

[0174] 20 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 in the XY plane. The second lifetime region 200 in this example is parallel to the upper surface 21 of the semiconductor substrate 10 and is also sandwiched between the first lifetime regions 204 in a third direction (the Y-axis direction in this example) perpendicular to the first direction (the X-axis direction in this example).

[0175] As an example, a plurality of first lifetime regions 204 may be discretely arranged in both the X-axis direction and the Y-axis direction. In the example of Fig. 20, the first lifetime regions 204, each rectangular in top view, are discretely arranged along both the X-axis direction and the Y-axis direction. The second lifetime regions 200 in this example have a lattice shape in top view, where a portion extending in the X-axis direction intersects with a portion extending in the Y-axis direction.

[0176] In another example, a plurality of second lifetime regions 200 may be discretely arranged in both the X-axis direction and the Y-axis direction. For example, second lifetime regions 200 having a rectangular shape in a top view may be discretely arranged along both the X-axis direction and the Y-axis direction.

[0177] In this example, the width of the second lifetime region 200 in the Y-axis direction is defined as W2. The width W2 may satisfy the same conditions as the width W1 described with reference to FIGS. 1 to 19. For example, the width W2 is 0.2 times or more the thickness T1 of the first lifetime region 204. However, the widths W2 and W1 do not have to be the same. The widths W1 and W2 may be different values within the range of the conditions of the width W1 described with reference to FIGS. 1 to 19. Even with this configuration, it is possible to reduce the reverse recovery loss of the diode section 80 while suppressing snapback.

[0178] 21 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 in the XY plane. The first lifetime region 204 of this example is parallel to the upper surface 21 of the semiconductor substrate 10. of It is sandwiched between second lifetime regions 200 in both the first direction (X-axis direction in this example) and the third direction (Y-axis direction in this example).

[0179] As an example, a plurality of second lifetime regions 200 may be discretely arranged in both the X-axis direction and the Y-axis direction. In the example of FIG. 21 , rectangular second lifetime regions 200 are discretely arranged along both the X-axis direction and the Y-axis direction in a top view. The first lifetime regions 204 in this example have a lattice shape in which portions extending in the X-axis direction and portions extending in the Y-axis direction intersect in a top view. Even with this configuration, it is possible to reduce the reverse recovery loss of the diode section 80 while suppressing snapback.

[0180] The second lifetime region 200 may be disposed within the first lifetime region 204 of the diode section 80. The second lifetime region 200 may or may not be disposed within the first lifetime region 204 of the transistor section 70. Disposing the second lifetime region 200 within the first lifetime region 204 means that the second lifetime region 200 is surrounded by the first lifetime region 204 in a top view. In the transistor section 70, the ratio of the area S2_t of the second lifetime region 200 surrounded by the first lifetime region 204 to the area S1_t of the first lifetime region 204 is defined as S2_t / S1_t. In the diode section 80, the ratio of the area S2_d of the second lifetime region 200 surrounded by the first lifetime region 204 to the area S1_d of the first lifetime region 204 is defined as S2_d / S1_d. The ratio S2_t / S1_t may be smaller than the ratio S2_d / S1_d. The ratio S2_t / S1_t may be 50% or less, 20% or less, or 10% or less of the ratio S2_d / S1_d. The area S2_t may be 0. When the body diode of the transistor section 70 is conducting, a relatively large number of carriers are injected, but the lifetime of these carriers can be shortened by reducing the size of the second lifetime region 200 inside the first lifetime region 204 of the transistor section 70 or by not providing such a region.

[0181] 22A is a diagram showing another example of the arrangement of the first lifetime regions 204 and the second lifetime regions 200 on the XY plane. This example differs from the example in FIG. 21 in the arrangement of the multiple second lifetime regions 200. The other structures are similar to the example in FIG. 21.

[0182] 21, the plurality of second lifetime regions 200 are arranged side by side in the X-axis direction and the Y-axis direction. In the example of Fig. 22A, the plurality of second lifetime regions 200 are arranged side by side along two directions different from both the X-axis and the Y-axis. Even with this configuration, it is possible to reduce the reverse recovery loss of the diode section 80 while suppressing snapback.

[0183] The second lifetime region 200 may be disposed inside the first lifetime region 204 of the diode section 80. The second lifetime region 200 may or may not be disposed inside the first lifetime region 204 of the transistor section 70. Even with this configuration, it is possible to reduce the reverse recovery loss of the diode section 80 while suppressing snapback.

[0184] 22B is a diagram showing another example of the arrangement of the first lifetime regions 204 and the second lifetime regions 200 on the XY plane. This example differs from the example of FIG. 22A in the arrangement of the multiple second lifetime regions 200. The arrangement of the multiple second lifetime regions 200 does not have to be symmetrical, and may be random.

[0185] 23A is a diagram showing another example of the arrangement of the first lifetime regions 204 and the second lifetime regions 200 on the XY plane. This example differs from the example in FIG. 20 in the arrangement of the multiple first lifetime regions 204. The other structures are similar to the example in FIG. 20.

[0186] 20, the plurality of first lifetime regions 204 are arranged side by side in the X-axis direction and the Y-axis direction. In the example of Fig. 23A, the plurality of first lifetime regions 204 are arranged side by side along two directions different from both the X-axis and the Y-axis. Even with this configuration, it is possible to reduce the reverse recovery loss of the diode section 80 while suppressing snapback.

[0187] In this example, the second lifetime region 200 has a lattice shape in which a portion extending in the X-axis direction and a portion extending in the Y-axis direction intersect when viewed from above. The widths W1 and W2 of the second lifetime region 200 may be the width in a direction perpendicular to the extension direction of the second lifetime region 200. In this example, the width in the X-axis direction of the second lifetime region 200 extending in the Y-axis direction is W1, and the width in the Y-axis direction of the second lifetime region 200 extending in the X-axis direction is W2.

[0188] Figure 23B is a diagram showing another example of the arrangement of the first lifetime regions 204 and the second lifetime regions 200 on the XY plane. This example differs from the example of Figure 23A in the arrangement of the multiple first lifetime regions 204. The arrangement of the multiple first lifetime regions 204 does not have to be symmetrical, and may be random.

[0189] 24 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the extension direction of the first lifetime region 204 and the second lifetime region 200 is different from both the X-axis direction and the Y-axis direction. The other structures are similar to any of the embodiments described herein.

[0190] In this example, the first lifetime regions 204 and the second lifetime regions 200 are alternately arranged along a first direction perpendicular to the extension direction of each lifetime region. The first direction in this example is different from both the X-axis direction and the Y-axis direction. The trench portions of the transistor section 70 and the diode section 80 are provided extending in the Y-axis direction (i.e., having a longitudinal direction). Therefore, each of the multiple trench portions extends in a direction greater than 0 degrees and less than 90 degrees with respect to the first direction on the upper surface 21 of the semiconductor substrate 10. The angle may be 15 degrees or more, 30 degrees or more, or 45 degrees or more. The angle may be 75 degrees or less, 60 degrees or less, or 45 degrees or less. This configuration also reduces the reverse recovery loss of the diode section 80 while suppressing snapback.

[0191] 25 is a diagram showing another example of the arrangement of the first lifetime regions 204 and the second lifetime regions 200 on the XY plane. In this example, the annular first lifetime regions 204 and the annular second lifetime regions 200 are arranged alternately in a concentric pattern. In this example, the width in the X-axis direction of the second lifetime region 200 extending in the Y-axis direction is set to W1, and the width in the Y-axis direction of the second lifetime region 200 extending in the X-axis direction is set to W2.

[0192] The second lifetime region 200 may be disposed inside the first lifetime region 204 of the diode section 80. The second lifetime region 200 may or may not be disposed inside the first lifetime region 204 of the transistor section 70. Even with this configuration, it is possible to reduce the reverse recovery loss of the diode section 80 while suppressing snapback.

[0193] 26 is a diagram showing another example of the arrangement of the first lifetime region 204 and the second lifetime region 200 on the XY plane. In this example, the Y-axis direction is the first direction, and the X-axis direction is the third direction. That is, the first lifetime region 204 and the second lifetime region 200 in this example are arranged side by side in the Y-axis direction.

[0194] In this example, the first lifetime region 204 and the second lifetime region 200 have stripe-shaped portions extending in the X-axis direction (third direction). In this example, both ends of the first lifetime region 204 in the X-axis direction are located in the transistor section 70. In this example, both ends of the second lifetime region 200 in the X-axis direction are located in the diode section 80 or at the boundary between the diode section 80 and the transistor section 70. Even with this arrangement, it is possible to reduce the reverse recovery loss of the diode section 80 while suppressing snapback.

[0195] In each example described with reference to FIGS. 1 to 26 , the widths W1 and W2 of the second lifetime region 200 may be 3% or more of the carrier diffusion length in the semiconductor substrate 10. The carrier diffusion length in the semiconductor substrate 10 may be, for example, the carrier diffusion length in a region not subjected to lifetime control. The region not subjected to lifetime control may be, for example, a drift region 18 that is neither the first lifetime region 204 nor the second lifetime region 200. The carrier diffusion length may be the electron diffusion length, the hole diffusion length, or the ambipolar diffusion length. As described above, when electrons pass through the second lifetime region 200, they may bind to lattice defects 202 in the first lifetime regions 204 on both sides. By setting the widths W1 and W2 of the second lifetime region 200 to a predetermined ratio or more of the electron diffusion length, it is possible to prevent electrons from binding to the lattice defects 202.

[0196] Electron diffusion length L n is given by equation (2). L n =(D n τ n ) 0.5 ···(2) However, D n is the electron diffusion coefficient (cm 2 / s), and τ n is the electron lifetime (s). Diffusion coefficient D n is given by equation (3). Dn =(k B Tμ n ) / q ···(3) However, k B is the Boltzmann constant (1.38×10 -23 (J / K)), T is temperature (K), and μ n is the electron mobility (cm 2 / Vs), and q is the elementary charge (1.60×10 -19 (C)). The diffusion length of the hole, L p is given by equation (4). L p =(D p τ p ) 0.5 ···(4) However, D p is the diffusion coefficient of holes (cm 2 / s), and τ p is the electron lifetime (s). Diffusion coefficient D p is given by equation (5). D p =(k B Tμ p ) / q ···(5) however μ p is the hole mobility (cm) in the semiconductor substrate 10 2 / Vs). The ambipolar diffusion length is given by equation (6). L a =(D a τ HL ) 0.5 ···(6) However, D a is the ambipolar diffusion coefficient (cm 2 / s) and D a =2D n D p / (D n +D p ) is τ HL is the high injection level lifetime (s), and τ HL =τ n +τ p is. When the semiconductor substrate 10 is a silicon substrate and the temperature T is −40° C., τ nis 1 x 10 -5 (s) and μ n is 2600 (cm 2 / Vs) and D n is 52.25 (cm 2 / s) and L n When the semiconductor substrate 10 is a silicon substrate and the temperature T is −40° C., τ p is 1 x 10 -5 (s) and μ p is 860 (cm 2 / Vs) and D p is 17.36 (cm 2 / s) and L p When the semiconductor substrate 10 is a silicon substrate and the temperature T is −40° C., τ HL is 2 x 10 -5 (s) and D a is 26.06 (cm 2 / s) and L a may be 228.3 (μm). The width W1 and the width W2 of the second lifetime region 200 may be 3% or more of the diffusion length of carriers in the semiconductor substrate 10, or may be 4% or more.

[0197] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0198] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0199] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 19 lower surface lifetime region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 26 high concentration region, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, 41 tip portion, 42 gate insulating film, 44 gate Conductive portion, 52...emitter electrode, 54...contact hole, 60, 61...mesa portion, 70...transistor portion, 80...diode portion, 81...extension region, 82...cathode region, 85...line, 90...edge termination structure portion, 100...semiconductor device, 130...periphery gate wiring, 131...active side gate wiring, 160...active portion, 162...edge, 164...gate pad, 200...second lifetime region, 202...lattice defects, 204...first lifetime region, 220, 222, 224...region, 230...line, 240...region, 250...characteristics, 251...characteristics

Claims

1. a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; a diode portion provided on the semiconductor substrate; Equipped with The diode section a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a first lifetime region disposed in the drift region closer to the lower surface of the semiconductor substrate than the base region; a second lifetime region that is sandwiched between the first lifetime regions in a first direction parallel to the top surface of the semiconductor substrate and has a longer carrier lifetime than the first lifetime region; and The width of the second lifetime region in the first direction is greater than the width W (μm) expressed by formula (1). W=0.21×T1+3.3...(1) where T1 is the thickness (μm) of the first lifetime region in a second direction perpendicular to the top surface. Semiconductor device.

2. The width of the second lifetime region in the first direction is 7 μm or more. The semiconductor device according to claim 1 .

3. The width of the second lifetime region in the first direction is 12 μm or less. The semiconductor device according to claim 1 .

4. the diode portion has one or more second lifetime regions, The sum of the widths of the one or more second lifetime regions in the first direction is 0.1 times or less the width of the diode portion in the first direction. The semiconductor device according to claim 1 .

5. a transistor section provided on the semiconductor substrate and arranged alongside the diode section in the first direction; The semiconductor device according to claim 1 .

6. The diode section and the transistor section each have a plurality of trench sections spaced apart in the first direction. The semiconductor device according to claim 5 .

7. a transistor section provided on the semiconductor substrate and arranged alongside the diode section in a third direction that is parallel to the top surface of the semiconductor substrate and perpendicular to the first direction; The semiconductor device according to claim 1 .

8. The diode section and the transistor section each have a plurality of trench sections spaced apart in the third direction. The semiconductor device according to claim 7 .

9. at least a portion of the trench portion of the diode portion is disposed above the first lifetime region; The distance between the second lifetime region and the transistor portion in the first direction is equal to or greater than the distance between the bottom end of the trench portion and the first lifetime region in the second direction. The semiconductor device according to claim 6.

10. The diode portion has two or more second lifetime regions spaced apart in the first direction. The semiconductor device according to claim 1 .

11. The second lifetime region is also sandwiched between the first lifetime regions in a third direction that is parallel to the top surface of the semiconductor substrate and perpendicular to the first direction. The semiconductor device according to claim 1 .

12. The width of the second lifetime region in the third direction is 0.2 times or more the thickness of the first lifetime region in the second direction. The semiconductor device according to claim 11.

13. The width of the second lifetime region in the first direction is 3% or more of the diffusion length of charge carriers in the semiconductor substrate. The semiconductor device according to claim 1 .

14. The thickness of the first lifetime region in the second direction is less than the thickness of the drift region in the second direction. The semiconductor device according to claim 1 .

15. The width of the second lifetime region in the first direction is 0.2 times or more the thickness of the first lifetime region in a second direction perpendicular to the top surface of the semiconductor substrate. The semiconductor device according to claim 1 .

16. The width of the first lifetime region is larger than the width of the mesa portion sandwiched between the adjacent trench portions. The semiconductor device according to claim 6.

17. The first lifetime region includes hydrogen. The semiconductor device according to claim 1 .

18. The first lifetime region includes helium. The semiconductor device according to claim 1 .

19. the first lifetime region is provided in the diode portion and the transistor portion, In the transistor section, the ratio of the area of the second lifetime region surrounded by the first lifetime region to the area of the first lifetime region is smaller than the ratio of the area of the second lifetime region surrounded by the first lifetime region to the area of the first lifetime region in the diode section. The semiconductor device according to claim 5 .

20. the second lifetime region is provided within the first lifetime region of the diode portion, The second lifetime region is not provided inside the first lifetime region of the transistor portion. The semiconductor device according to claim 5 .

21. The semiconductor substrate has, on its upper surface, a plurality of trench portions extending in a direction greater than 0 degrees and less than 90 degrees with respect to the first direction. The semiconductor device according to claim 1 .

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