Semiconductor light emitting element, vehicle lamp, and method for manufacturing semiconductor light emitting element

Abstract

To provide a semiconductor light-emitting element, a vehicle lamp fitting, and a method of manufacturing the semiconductor light-emitting element capable of increasing an amount of light emitted from a top face by a simple configuration.SOLUTION: A semiconductor light-emitting element comprises: a growth substrate (11); a plurality of columnar semiconductor layers (13, 14, 15) formed on the growth substrate (11); and an embedded layer (16) that covers the plurality of columnar semiconductor layers (13, 14, 15). In each of the plurality of columnar semiconductor layers (13, 14, 15), an n-type nanowire layer (13) is formed at the center, and an active layer (14) is formed at an outer periphery from the n-type nanowire layer (13), and a p-type semiconductor layer (15) is formed at an outer periphery from the active layer (14). A cavity (17) is provided inside the embedded layer (16) above the growth substrate (11) between the columnar semiconductor layers (13, 14, 15).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor light-emitting element, a vehicle lamp, and a method for manufacturing the semiconductor light-emitting element, and more particularly to a semiconductor light-emitting element having a structure in which a plurality of columnar semiconductor layers are buried in a burying layer, a vehicle lamp, and a method for manufacturing the semiconductor light-emitting element. [Background technology]

[0002] Semiconductor light-emitting devices emit light through the recombination of holes and electrons in an active layer. Conventionally, a flat sheet-like well layer has been used as the active layer. In recent years, active layers with three-dimensional structures, such as columnar structures, have been studied. For example, such semiconductor light-emitting devices have a configuration in which an active layer is formed around an n-type columnar semiconductor layer, a p-type semiconductor layer is formed around the active layer, and a buried layer is further formed around the active layer.

[0003] On the other hand, a common issue for semiconductor light-emitting devices is the need to improve the extraction efficiency of light emitted from the active layer. Furthermore, while the light emitted from a semiconductor light-emitting device can be extracted from the top, side, bottom, etc., in many cases, light is extracted from the top for face-up mounting. In other words, there are cases where an improvement in the light extraction efficiency from the top of a semiconductor light-emitting device is required.

[0004] For example, Patent Document 1 is known as a conventional technique for improving the light extraction efficiency from the top surface of a semiconductor light-emitting device using a columnar semiconductor layer. The semiconductor light-emitting device according to Patent Document 1 includes a plurality of columnar semiconductors, each of which is hexagonal, and a light extraction surface having a plurality of convex portions, with the pitch interval between the columnar semiconductors and the pitch interval between the convex portions being different. Patent Document 1 claims that this configuration can improve the light extraction efficiency of a semiconductor light-emitting device having an active layer with a three-dimensional microstructure. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-077817 Summary of the Invention [Problem to be solved by the invention]

[0006] Incidentally, the columnar semiconductor layer described above is also called a nanowire, and semiconductor light-emitting devices using nanowires (e.g., LEDs (Light Emitting Diodes)) have attracted attention because they can suppress the decrease in power efficiency in high current regions. As an example, a semiconductor light-emitting device using nanowires has a configuration in which an active layer and a p-type GaN layer are grown around a hexagonal columnar n-type GaN nanowire.

[0007] In other words, while conventional semiconductor light-emitting devices with flat active layers have a two-dimensional structure, semiconductor light-emitting devices using nanowires have a three-dimensional structure. Therefore, semiconductor light-emitting devices using nanowires are characterized by the fact that a large amount of light is emitted laterally. In this case, the light emitted laterally is affected by light scattering and light absorption by the surrounding nanowires, limiting the light extraction efficiency. On the other hand, if it is desired to extract light primarily from the top surface of a semiconductor light-emitting device, a means (optical path conversion means) is required to convert the light emitted laterally to the top surface.

[0008] For example, it is conceivable to provide a reflecting mirror outside the semiconductor light-emitting element, for example, inside a package that houses the semiconductor light-emitting element, as the light path conversion means. However, this method has the problem of making the package that houses the semiconductor light-emitting element complex. Another conceivable method is to incorporate a light path conversion means having a mirror surface inside the semiconductor light-emitting element during the manufacturing process of the semiconductor light-emitting element. However, this method generally has the problem of making the manufacturing process of the semiconductor light-emitting element complex. In this regard, Patent Document 1 does not refer to a light path conversion means that converts light emitted in a lateral direction into a light that is emitted upward.

[0009] Therefore, the present invention has been made in consideration of the above-mentioned conventional problems, and aims to provide a semiconductor light-emitting element, a vehicle lamp, and a method for manufacturing a semiconductor light-emitting element that can increase the amount of light emitted from the top surface with a simple configuration. [Means for solving the problem]

[0010] In order to solve the above problems, the present invention provides a semiconductor light emitting device including a growth substrate, a plurality of pillar-shaped semiconductor layers formed on the growth substrate, and a light emitting element including: Side and top surfaces of and a buried layer covering the pillar-shaped semiconductor layers, wherein each of the pillar-shaped semiconductor layers has an n-type nanowire layer formed at the center, an active layer formed on an outer periphery of the n-type nanowire layer, and a p-type semiconductor layer formed on an outer periphery of the active layer, and the buried layer is a semiconductor layer; The aforementioned a void within the buried layer above a growth substrate; The gap has a plurality of voids located between the plurality of pillar-shaped semiconductor layers and connection portions that connect the plurality of voids to each other. It is characterized by:

[0011] In such a semiconductor light-emitting device of the present invention, a void is formed inside the buried layer between the columnar semiconductor layers, and light generated from the active layer and traveling laterally is reflected or scattered by the void, thereby making it possible to increase the amount of light emitted from the top surface.

[0012] In one aspect of the present invention, the growth substrate is a GaN substrate, and the buried layer is a GaN layer.

[0015] In one aspect of the present invention, an aspect ratio defined by the height of the pillar-shaped semiconductor layer and the interval between the pillar-shaped semiconductor layers is is greater than or equal to 0.5 .

[0016] In order to solve the above problems, the vehicle lamp of the present invention uses the above semiconductor light emitting element.

[0017] In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor light-emitting device, comprising: a masking step of forming a mask layer having a plurality of openings on a growth substrate; a growth step of forming pillar-shaped semiconductor layers in each of the plurality of openings by using selective growth; and a method for manufacturing a semiconductor light-emitting device, comprising: Side and top surfaces of and a burying step of growing a burying layer on the growth substrate so as to cover the buried layer, the buried layer being a semiconductor layer, the growing step including a step of forming an n-type nanowire layer, a step of forming an active layer outside the n-type nanowire layer, and a step of forming a p-type semiconductor layer outside the active layer, On the inner mask layer Including a step of forming voids The voids have a plurality of voids located between the plurality of pillar-shaped semiconductor layers and connection portions that connect the plurality of voids to each other. A method for manufacturing a semiconductor light-emitting device.

[0018] In one aspect of the present invention, an aspect ratio defined by the height of the pillar-shaped semiconductor layer and the interval between the pillar-shaped semiconductor layers is 0.5 or more It is set. [Effects of the Invention]

[0019] The present invention can provide a semiconductor light emitting element, a vehicle lamp, and a method for manufacturing a semiconductor light emitting element that can increase the amount of light emitted from the top surface with a simple configuration. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1A is a cross-sectional view of a semiconductor light emitting element according to a first embodiment, and FIG. 1B is a diagram illustrating the operation thereof. [Figure 2] 1A and 1B are cross-sectional views showing a method for manufacturing a semiconductor light-emitting element according to a first embodiment, in which (a) shows a mask formation process, (b) shows a nanowire growth process, (c) shows an active layer and p-type semiconductor layer growth process, (d) shows a void formation process, (e) shows a trench etching process and activation process, and (f) shows an electrode formation process. [Figure 3] 1A is a diagram illustrating the positions where voids are formed, and FIG. 1B is a diagram illustrating voids due to connection portions, in a semiconductor light emitting device according to an embodiment. [Figure 4]3 is a diagram showing an SEM photograph of voids formed in the semiconductor light emitting device according to the first embodiment. FIG. [Figure 5] 10A and 10B are diagrams showing a method for manufacturing a semiconductor light-emitting element according to a second embodiment, in which (a) shows a diagram in which the growth substrate is tilted and the ITO target is thrown from a predetermined direction, (b) shows a diagram in which the ITO target is thrown from a direction different from the predetermined direction, and (c) shows a diagram in which the growth substrate is held horizontal and the ITO target is thrown. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor light emitting device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be assigned the same reference numerals, and redundant explanations will be omitted where appropriate. In the embodiment described below, a semiconductor light emitting device will be described that is intended to be applied to a face-up type semiconductor light emitting device, and that aims to increase the amount of light emitted from the top surface. Such a semiconductor light emitting device is used, for example, in a vehicle lamp. (First embodiment)

[0022] A semiconductor light-emitting device 10 according to this embodiment will be described with reference to FIGS. 1 to 4. FIG. 1(a) is a cross-sectional view showing the semiconductor light-emitting device 10 according to the first embodiment. As shown in FIG. 1(a), the semiconductor light-emitting device 10 includes a growth substrate 11, a mask 12, a nanowire layer 13, an active layer 14, a p-type semiconductor layer 15, a buried layer 16, a void 17 (air gap), a mesa groove 18, a cathode electrode 20, and an anode electrode 21. The nanowire layer 13, the active layer 14, and the p-type semiconductor layer 15 are selectively grown in a direction perpendicular to the growth substrate 11 to form a columnar shape, constituting the columnar semiconductor layer of this embodiment.

[0023] 1(a), a mesa groove 18 (mesa structure) is formed by removing the buried layer 16 from the surface to the growth substrate 11 in a portion of the semiconductor light emitting device 10, and the surface of the growth substrate 11 is exposed and a cathode electrode 20 is formed thereon. An anode electrode 21 is also formed on the buried layer 16. Here, the mesa structure refers to a structure in which a groove is formed through the semiconductor layers so as to surround a predetermined region, thereby exposing a cross section of the stacked structure of each semiconductor layer from the side.

[0024] The growth substrate 11 is a substantially flat plate-shaped member made of a material that allows crystal growth of a semiconductor material, and a mask 12 is formed on the main surface side. A portion of the growth substrate 11 is exposed, and a cathode electrode 20 is formed on the exposed portion. When the semiconductor light-emitting element 10 is made of a nitride-based semiconductor, a GaN substrate is preferably used as the growth substrate 11. To achieve laser oscillation, a c-plane GaN substrate, which allows cavity planes to be easily formed by cleavage, may be used. Alternatively, a heterogeneous substrate, such as a c-plane sapphire substrate or a Si substrate made of a material different from the semiconductor material grown on the growth substrate 11, on which multiple semiconductor layers, such as a buffer layer and an underlayer, are grown may be used.

[0025] The buffer layer is formed between the single crystal substrate and the underlayer to reduce the lattice mismatch between them. When a c-plane sapphire substrate is used as the single crystal substrate, it is preferable to use GaN for the buffer layer, but AlN or AlGaN may also be used.

[0026] The underlayer is a single-crystal semiconductor layer formed on the growth substrate 11 or buffer layer, and is preferably composed of multiple layers, with undoped GaN formed to a thickness of several μm and an n-type semiconductor layer such as an n-type contact layer formed thereon. The n-type contact layer is a semiconductor layer doped with n-type impurities, for example, Si-doped n-type Al 0.05 Ga 0.95 N is one example.

[0027] The mask 12 is a layer made of a dielectric material formed on the surface of the growth substrate 11 or the underlayer. The material for the mask 12 is selected from those from which semiconductor crystal growth is difficult, and suitable materials include SiO2, SiNx, and Al2O3. The mask 12 has a plurality of openings (described later) formed therein, allowing a semiconductor layer to grow from the surface of the growth substrate 11 or the underlayer that is partially exposed through the openings.

[0028] The nanowire layer 13 is a columnar semiconductor layer selectively grown (crystal grown) on the growth substrate 11 or base layer exposed through the openings in the mask 12, and is formed as a substantially columnar semiconductor layer standing vertically relative to the main surface of the growth substrate 11. Such a nanowire layer 13 can be obtained by setting appropriate growth conditions according to the semiconductor material and performing selective growth that grows a specific crystal plane orientation. In the example shown in Figure 1(a), multiple openings are formed two-dimensionally and periodically in the mask 12, and therefore the nanowire layer 13 is also formed two-dimensionally and periodically on the growth substrate 11.

[0029] The nanowire layer 13 is made of, for example, GaN doped with n-type impurities. When GaN is used as the nanowire layer 13, the nanowire layer 13 selectively grown on the growth substrate 11 has a roughly hexagonal prism shape with six m-planes formed as facets. In FIG. 1, the nanowire layer 13 appears to grow only in the region where the opening is formed, but in reality, crystal growth proceeds on the mask 12 due to lateral growth, resulting in the formation of an enlarged hexagonal prism around the opening. For example, if the opening is formed as a circle with a diameter of approximately 150 nm, the nanowire layer 13 can be formed as a hexagonal prism with a height of approximately 1.0 to 2.0 μm, with a base that is a hexagon inscribed in a circle with a diameter of approximately 200 nm. However, the size of the nanowire layer 13 is not limited to this and may be, for example, approximately 0.2 to 1.0 μm wide and approximately 0.5 to 2.5 μm high. The spacing (distance) between the nanowire layers 13 may also be approximately 0.2 to 1.8 μm.

[0030] Although this embodiment shows an example in which GaN is used for the nanowire layer 13, when the In composition of the active layer 14 is increased to lengthen the emission wavelength, GaInN may be used for the nanowire layer 13 to reduce misfit dislocations due to lattice mismatch. Similarly, when shortening the wavelength of the semiconductor light emitting element 10, it is also possible to use AlGaN for the nanowire layer 13, or to change the well layer and barrier layer of the active layer 14 to AlGaN with different compositions.

[0031] The active layer 14 is a semiconductor layer grown along the nanowire layer 13 and on the outer periphery thereof. For example, it may be a multi-quantum well active layer formed by stacking five periods of 5-nm-thick GaInN quantum well layers and 10-nm-thick GaN barrier layers. While a multi-quantum well active layer is used here, it may also have a single quantum well structure or a bulk active layer. Because the active layer 14 is formed on the side and top surfaces of the nanowire layer 13, a sufficient area can be secured. The higher the proportion of In incorporated into the active layer 14, the longer the emission wavelength of the semiconductor light-emitting device 10. By setting the In composition ratio to 0.10 or greater, the emission wavelength can be increased to 480 nm or greater. Furthermore, by setting the In composition ratio to 0.12 or greater, the emission wavelength can be increased to 500 nm or greater. Furthermore, because the side surfaces of the nanowire layer 13 are formed from m-planes, the active layer 14 formed on the side surfaces is also a nonpolar m-plane, improving droop characteristics.

[0032] The p-type semiconductor layer 15 is a semiconductor layer grown along the active layer 14 and on the outer periphery of the active layer 14, and is made of, for example, GaN doped with p-type impurities. Because the p-type semiconductor layer 15 is formed on the side and top surfaces of the active layer 14, a double heterostructure is formed by the n-type nanowire layer 13, the active layer 14, and the p-type semiconductor layer 15, which can effectively confine carriers in the active layer 14 and improve the probability of radiative recombination.

[0033] The buried layer 16 is a semiconductor layer grown outside the p-type semiconductor layer 15 and is made of GaN in this embodiment. The buried layer 16 covers the side and top surfaces of the p-type semiconductor layer 15, extending down to the growth substrate 11 or the underlying layer. While FIG. 1 shows an example in which the buried layer 16 is made of a single layer, it may have a multi-layer structure as long as the semiconductor layer is buried from the surface of the growth substrate 11 to the top surface of the columnar semiconductor layer. The buried layer 16 also functions to fix and protect the thin nanowire layer 13. As will be described later, various materials are conceivable for the buried layer 16. However, because a material with a band gap smaller than that of the material constituting the active layer 14 absorbs light emitted from the active layer 14, it is necessary to select a material with a band gap larger than that of the material constituting the active layer 14.

[0034] The mesa groove 18 is a groove formed penetrating each semiconductor layer from the upper surface of the burying layer 16 to the growth substrate 11 or the underlayer, and constitutes a mesa structure by dividing the light-emitting region of the semiconductor light-emitting element 10. The outer periphery of the burying layer 16 is exposed from the side surface of the mesa groove 18. Here, "the burying layer 16 being exposed on the side surface of the mesa structure" means that the outer periphery of the burying layer extends to the side surface of the mesa structure when the mesa groove 18 is formed, and also includes cases where a passivation film or other structure is formed within the mesa groove 18 in a later process. Element isolation grooves are further formed in the mesa groove 18 to individually separate the semiconductor light-emitting elements 10.

[0035] The cathode electrode 20 is an electrode formed in an exposed region of the growth substrate 11 or the underlayer, and is composed of a laminated structure of a metal material that makes ohmic contact with the exposed semiconductor layer and a pad electrode. The anode electrode 21 is an electrode formed on a portion of the buried layer 16, and is composed of a laminated structure of a metal material that makes ohmic contact with the outermost surface of the buried layer 16 and a pad electrode. Although not shown in FIG. 1(a), a known structure may be applied, such as covering the surface of the semiconductor light-emitting element 10 with a passivation film, if necessary. Alternatively, a transparent electrode in which the anode electrode 21 is extended over the entire buried layer 16 may be formed.

[0036] The voids 17 are spaces intentionally formed inside the embedding layer 16, and constitute the optical path conversion means according to this embodiment. Air is enclosed inside the voids 17, for example, but this is not limiting and other gases, such as inert gases such as nitrogen, may also be enclosed. The size of the voids is, for example, approximately 0.05 to 0.4 μm in width and approximately 0.3 to 0.7 μm in height.

[0037] The voids 17 according to this embodiment are formed by controlling the aspect ratio of the space between the plurality of columnar semiconductor layers, i.e., (height of the columnar semiconductor layer) / (spacing between the columnar semiconductor layers), which is defined by the height h of the columnar semiconductor layer and the spacing d between the columnar semiconductor layers as shown in FIG. 1(b). Generally, when filling an opening in a substrate with a predetermined substance using sputtering or the like, if the aspect ratio of the opening is large, the substance may accumulate near the opening after a certain amount of sputtering, narrowing the opening and ultimately forming a void at the bottom of the opening. In the semiconductor light emitting device 10 according to this embodiment, this phenomenon is utilized to intentionally form the voids 17 within the buried layer 16.

[0038] The function of the voids 17 in the semiconductor light-emitting device 10 according to this embodiment will be described with reference to FIG. 1(b). As described above, the semiconductor light-emitting device 10 is designed to extract light emitted in the active layer 14 from the top surface as emitted light L. That is, most of the light emitted in the active layer 14 travels in a direction parallel to the growth substrate 11 (hereinafter sometimes referred to as the "lateral direction"). On the other hand, the interface between the voids 17 and the buried layer 16 is a mirror or rough surface, and light traveling from the active layer 14 to the voids 17 via the buried layer 16 is reflected or scattered. Therefore, in the semiconductor light-emitting device 10, light traveling in the lateral direction from the active layer 14 is reflected or scattered by the voids 17, thereby changing its optical path toward the upper surface. For example, regarding light reflected by the voids 17, as shown in FIG. 1(b), light traveling in the lateral direction from the active layer 14 is reflected by the voids 17 and travels toward the upper surface as reflected light Lr. That is, the voids 17 function as optical path conversion sections that convert the lateral optical path of light generated in the active layer 14 into an optical path toward the top surface. In this case, the higher the refractive index of the material of the buried layer 16, the greater the difference in refractive index with the interior of the voids 17, and the narrower the critical angle, resulting in a higher reflection effect. Due to the above-mentioned actions, the semiconductor light emitting element 10 can increase the amount of light emitted from the top surface with a simple configuration.

[0039] Figure 2 is a cross-sectional view showing a manufacturing method of the semiconductor light-emitting element 10, where Figure 2(a) shows a mask formation process, Figure 2(b) shows a nanowire growth process, Figure 2(c) shows an active layer and p-type semiconductor layer growth process, Figure 2(d) shows a void formation process, Figure 2(e) shows a groove etching process and activation process, and Figure 2(f) shows an electrode formation process.

[0040] First, in the mask formation process shown in FIG. 2(a), a SiO2 mask 12 with a thickness of approximately 30 nm is deposited on a growth substrate 11 made of n-type GaN by sputtering, and an opening 12a with a diameter of approximately 150 nm is formed using a fine pattern formation method such as nanoimprinting lithography. When a heterogeneous substrate such as sapphire is used as the growth substrate 11, a buffer layer, an underlayer, and an n-type semiconductor layer may be formed on the sapphire substrate, and the surface of the n-type semiconductor layer may be used as the surface of the growth substrate 11. The buffer layer is grown under the following conditions: source gases include TMA (TriMethyl Aluminum), TMG (TriMethyl Gallium), and ammonia; a growth temperature of 1100°C; a V / III ratio of 1000; and a pressure of 10 hPa using hydrogen as the carrier gas. The growth conditions for the underlayer and n-type semiconductor layer are, for example, a growth temperature of 1050°C; a V / III ratio of 1000; and a pressure of 500 hPa using hydrogen as the carrier gas.

[0041] 2(b), a nanowire layer 13 made of GaN is grown on the growth substrate 11 exposed from the opening 12a by selective growth using the MOCVD method. The growth conditions for the nanowire layer 13 are, for example, TMG and ammonia as source gases, a growth temperature of 1050°C, a V / III ratio of 10, hydrogen as carrier gas, and a pressure of 100 hPa.

[0042] 2(c), the active layer and p-type semiconductor layer growth process begins by using MOCVD to grow the active layer 14, which consists of five periods of 5-nm-thick GaInN quantum well layers and 10-nm-thick GaN barrier layers, on the side and top surfaces of the nanowire layer 13. The growth conditions for the active layer 14 are, for example, a growth temperature of 800°C, a V / III ratio of 3000, a pressure of 1000 hPa using nitrogen as the carrier gas, and TMG, TMI (TriMethylIndium), and ammonia as the source gases.

[0043] Thereafter, a p-type semiconductor layer 15 made of GaN doped with p-type impurities is grown. The growth conditions for the p-type semiconductor layer 15 are, for example, a growth temperature of 950°C, a V / III ratio of 1000, a pressure of 300 hPa using hydrogen as a carrier gas, and TMG, Cp2Mg (bisCycropentadienylMagnesium), and ammonia as source gases.

[0044] 2(d), a GaN buried layer 16 is grown to fill the outer periphery and top surface of the columnar semiconductor layer consisting of the nanowire layer 13, active layer 14, and p-type semiconductor layer 15. The growth conditions for the buried layer 16 are, for example, a growth temperature of 950°C, a V / III ratio of 1000, a pressure of 300 hPa using hydrogen as the carrier gas, and TMG, Cp2Mg (bisCycropentadienylMagnesium), and ammonia as source gases. To thicken the buried layer 16, the growth conditions for the buried layer 16 are preferably conditions that promote c-plane growth, which is vertical growth.

[0045] The buried layer 16 is grown on the mask 12 provided between the pillar-shaped semiconductor layers, and in this embodiment, as described above, the aspect ratio = (height of the pillar-shaped semiconductor layer) / (spacing between the pillar-shaped semiconductor layers) is controlled to intentionally generate voids (air gaps) below the pillar-shaped semiconductor layers. This is because the high aspect ratio of the pillar-shaped semiconductor layers makes it easier for the raw material to grow as a crystal above the pillar-shaped semiconductor layers during growth of the buried layer 16, and the amount of raw material that reaches the base of the buried layer close to the growth substrate 11 is reduced.

[0046] As described above, the height of the nanowire layer 13 is about 0.5 to 2.5 μm, and the distance between the nanowire layers 13 is about 0.2 to 1.8 μm. Therefore, taking these dimensions into consideration, in this embodiment, the aspect ratio = (height of the pillar-shaped semiconductor layer) / (distance between the pillar-shaped semiconductor layers) is set to 0.5 or more, more preferably in the range of 3 to 5.

[0047] A more detailed example of the growth conditions for the buried layer 16 is as follows. Specifically, the buried layer 16 is preferably grown using TMG, silane, and ammonia as source gases at a low temperature and a low V / III ratio to promote lateral m-plane growth in the initial stage. An example of a low temperature and a low V / III ratio is a temperature of 800°C or less, a V / III ratio of 100 or less, and a pressure of 200 hPa using hydrogen as a carrier gas. After the lateral growth of the buried layer 16 fills the lower portion of the columnar semiconductor layer except for the voids 17 on the mask 12, it is preferably grown at a high temperature and a high V / III ratio to promote vertical c-plane growth. An example of a high temperature and a high V / III ratio is a temperature of 1000°C or more, a V / III ratio of 2000 or more, and a pressure of 500 hPa using hydrogen as a carrier gas.

[0048] In this embodiment, voids are basically generated by controlling the aspect ratio = (height of the pillar-shaped semiconductor layer) / (spacing between the pillar-shaped semiconductor layers), but the growth conditions of the buried layer 16 may be appropriately changed to make it easier for voids to be generated.

[0049] 2(e), a mesa groove 18 is selectively formed by dry etching, extending from the top surface of the buried layer 16 down to the growth substrate 11. After the mesa groove 18 is formed, an activation process is carried out to remove hydrogen from the buried layer 16 that has reached the side surface of the mesa structure and is exposed, thereby performing an activation process. The activation process is not limited to any particular method, but one example is heat treatment (annealing) at 600°C in an air atmosphere. Although annealing in an air atmosphere is shown here, any heat treatment may be performed in an atmosphere free of atomic hydrogen that can activate buried layer 16.

[0050] 2(f), a cathode electrode 20 is formed on the surface of the growth substrate 11, and an anode electrode 21 is formed on the buried layer 16. If necessary, annealing after electrode formation, formation of a passivation film, and element division are performed to obtain the semiconductor light-emitting element 10.

[0051] In the semiconductor light-emitting device 10 of this embodiment, when a voltage is applied between the cathode electrode 20 and the anode electrode 21, a current flows through the buried layer 16, the p-type semiconductor layer 15, the active layer 14, the nanowire layer 13, and the growth substrate 11 in that order, and light is generated by radiative recombination in the active layer 14. The light emitted from the active layer 14 is extracted to the outside of the semiconductor light-emitting device 10. In this case, in the semiconductor light-emitting device 10 of this embodiment, the amount of light extracted from the top surface of the semiconductor light-emitting device 10 is increased due to the action of the voids 17 described above.

[0052] Furthermore, because the side surfaces of the nanowire layer 13 are m-planes formed by selective growth, the active layer 14 and p-type semiconductor layer 15 formed on the outer periphery of the nanowire layer 13 are also in contact with each other at the m-plane. The m-plane is a nonpolar plane and does not generate polarization, so the light emission efficiency of the active layer 14 is high, and since all the side surfaces of the hexagonal prism are m-planes, the light emission efficiency of the semiconductor light emitting element 10 can be improved. Furthermore, because the film thickness of the active layer 14 can be increased, the volume of the active layer 14 can be increased by approximately 3 to 10 times that of conventional semiconductor light emitting elements, reducing the injected carrier density and significantly reducing efficiency droop.

[0053] Next, the voids 17 according to this embodiment will be described in more detail with reference to FIG. 3. FIGS. 3(a) and 3(b) are diagrams showing the shape of the voids 17 formed in the semiconductor light emitting device 10 in a plan view. As described above, the voids 17 according to this embodiment may be formed in five locations between the columnar semiconductor layers (nanowire layers 13 are shown in FIG. 3) arranged at the vertices of a square, as shown in FIG. 3(a). However, it is not necessary for the voids 17 to be formed in all five locations shown in FIG. 3(a), and there may be portions lacking the voids 17, as shown by the missing portions 17a.

[0054] Furthermore, the void 17 according to this embodiment may be an air gap in which two voids 17 are connected and integrated by a connecting portion 17b as shown in FIG. 3(b).

[0055] The arrangement of the pillar-shaped semiconductor layers is not limited to the vertices of a rectangle as in this embodiment, but may be the vertices of other polygons such as triangles. In this case, too, there is a possibility that voids 17 may be formed between the pillar-shaped semiconductor layers.

[0056] 4 shows a photograph taken with a scanning electron microscope (SEM) of voids 17 that have actually occurred in the semiconductor light emitting device 10 according to this embodiment. As shown in FIG. 4, it can be seen that voids 17 have occurred between the nanowire layers 13. (Second embodiment)

[0057] This embodiment will be described with reference to Figure 5. In this embodiment, the embedded layer 16 in the semiconductor light emitting device 10 according to the first embodiment is replaced with an ITO (Indium Tin Oxide) film. Therefore, since the configuration of the semiconductor light emitting device is the same as that shown in Figures 1 and 2 except for the embedded layer 16, Figures 1 and 2 will be referred to as necessary, and illustration of the semiconductor light emitting device will be omitted. Furthermore, the same components as those in the first embodiment will be assigned the same reference numerals, and detailed description thereof will be omitted.

[0058] Since the main function of the buried layer 16 of the semiconductor light emitting element 10 is to form a current path toward the p-type semiconductor layer 15, an ITO film, which is also used for transparent electrodes, can be used as a substitute for the buried layer 16. The ITO film may be formed by a sputtering method. For example, an RF magnetron sputtering device using ITO as a target may be used to spray ITO and deposit it in a target area.

[0059] 5 is a diagram showing the void formation process according to this embodiment, which corresponds to the void formation process shown in FIG. 2(d). In this embodiment, the relative angle between the ITO target T and the growth substrate 11 is changed, and film formation is performed in multiple steps. While FIG. 5 illustrates an example in which the angle of the growth substrate 11 is changed relative to the target T flying in the vertical direction, it is also possible to make the growth substrate 11 horizontal and deviate the angle of the flying direction of the target T from the vertical.

[0060] As shown in Fig. 5(a), the growth substrate 11 is tilted at a predetermined angle, and the first film formation is performed. Because the flying direction of the target T is not perpendicular to the main surface of the growth substrate 11, the ITO film 19a is deposited unevenly with respect to the pillar-shaped semiconductor layer. In other words, the ITO film 19a is deposited mainly on a specific surface of the pillar-shaped semiconductor layer.

[0061] Next, as shown in FIG. 5(b), the growth substrate 11 is tilted in a direction different from that shown in FIG. 5(a) and a second film formation is performed. The tilt angle may be the same as that used in the first film formation, or it may be different. In this film formation, an ITO film 19b is deposited on a surface of the columnar semiconductor layer different from that shown in FIG. 5(a). The ITO film 19a and the ITO film 19b overlap between the columnar semiconductor layers, forming a gap 17c. The gap 17c is an internal gap in the ITO film formed on the mask 12.

[0062] Next, as shown in FIG. 5(c), the growth substrate 11 is set horizontally, and the angle between the target T and the main surface of the growth substrate 11 is set perpendicular, and a third film formation is performed. This film formation forms an ITO film 19c that buries the ITO films 19a and 19b. This film formation determines the shape of the gap 19c, and finally forms the void 17.

[0063] In the present embodiment, the number of times of film formation by sputtering, which is performed by changing the relative angle between the target T and the growth substrate 11, is two has been described as an example, but the number of times is not limited to two and may be three or more, or may be one in consideration of the above-mentioned aspect ratio. Because the columnar semiconductor layer of the semiconductor light emitting element according to this embodiment has a hexagonal shape in a plan view, if the number of times of film formation is three or six, voids 17 with a more regular shape are formed.

[0064] As described above, the semiconductor light emitting device according to this embodiment also makes it possible to increase the amount of light emitted from the upper surface with a simple configuration. (Third embodiment)

[0065] A semiconductor light emitting device 50 according to this embodiment will be described with reference to Fig. 6. In this embodiment, the embedded layer 16 in the first embodiment is replaced with an insulating material. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0066] In the semiconductor light emitting device 50 according to this embodiment, by providing a separate current path from the anode electrode 21 to the p-type semiconductor layer 15, it is possible to use a dielectric material such as SiO2 or a transparent resin such as silicone resin instead of the buried layer 16. However, the material of the buried layer used in this embodiment is not limited to these, and other insulators that are transparent to the light emitted from the active layer 14 may also be used.

[0067] 6 shows a semiconductor light emitting device 50 that uses a SiO2 layer 22 as a buried layer. As shown in FIG. 6, the semiconductor light emitting device 50 includes a p-type semiconductor layer 15a, a SiO2 layer 22, and an ITO film .

[0068] The p-type semiconductor layer 15a includes a contact layer for making ohmic contact with an electrode material in an upper surface region of the p-type semiconductor layer 15, and is formed so that a part of the upper surface side protrudes from the SiO2 layer 22. The contact layer may be formed not only in the upper surface region of the p-type semiconductor layer, but also on the entire outer surface of the p-type semiconductor layer.

[0069] The SiO2 layer 22 is formed around the pillar-shaped semiconductor layer by, for example, a chemical vapor deposition (CVD) method, and has the function of mainly protecting the pillar-shaped semiconductor layer. In this embodiment, by setting the above aspect ratio, voids 17 are formed during the deposition process of the SiO2 layer 22.

[0070] Furthermore, when forming an SiO2 layer by sputtering, similar to the second embodiment described above, sputtering may be performed multiple times while shifting the angle between the target direction and the main surface of the growth substrate 11 from perpendicular to form the film.

[0071] The ITO film 23 is formed on the SiO2 layer 22 so as to be in contact with the contact layer of the p-type semiconductor layer 15a, and the anode electrode 21 is disposed on the ITO film 23. Note that the ITO film 23 is an example of a transparent electrode, and other transparent electrode materials may also be used.

[0072] In the semiconductor light-emitting device according to this embodiment, current flows through the anode electrode 21, ITO film 23, contact layer of p-type semiconductor layer 15a, p-type semiconductor layer, active layer 14, nanowire layer 13, and growth substrate 11 in that order, and light is emitted in active layer 14. A portion of the light generated in active layer 14 has its optical path changed by voids 17 toward the upper surface.

[0073] The semiconductor light emitting device 50 described above also makes it possible to increase the amount of light emitted from the upper surface with a simple configuration.

[0074] The semiconductor light-emitting device of this embodiment may have a configuration in which the SiO layer 22 is replaced with a silicone resin. In this case, the silicone resin film may be formed by a spin coating method. When forming the silicone resin film using the spin coating method, the generation of voids 17 may be controlled by controlling the rotation speed of the growth substrate 11, the supply rate of the silicone resin, and the like, in addition to controlling the aspect ratio. (Fourth embodiment)

[0075] In this embodiment, the buried layer 16 in the first embodiment is a p-type semiconductor layer. The above embodiments have been described with reference to an example in which a p-type semiconductor layer 15 is formed along the active layer 14 on the outside of the active layer 14, and a buried layer 16 is formed on the growth substrate 11 in contact with the p-type semiconductor layer 15. However, a semiconductor light-emitting device can also be formed with a nanowire layer 13, an active layer 14 formed along the nanowire layer 13 on the outside of the nanowire layer 13, and a p-type semiconductor layer is formed on the growth substrate 11 in contact with the active layer 14. The p-type semiconductor layer is formed, for example, from p-type GaN. In this case, an anode electrode 21 is disposed on the top surface of the p-type semiconductor layer. In this embodiment, the nanowire layer 13 and the active layer 14 form a columnar semiconductor layer.

[0076] In the semiconductor light emitting device according to this embodiment, voids 17 are formed between the columnar semiconductor layers inside the p-type semiconductor layer. In the manufacturing method according to this embodiment (particularly, the method for forming the voids 17), the aspect ratio is controlled in the same manner as in the first embodiment in which the buried layer 16 made of GaN is formed.

[0077] In the semiconductor light emitting device according to this embodiment, a current flows through the anode electrode 21, the p-type semiconductor layer (buried layer), the active layer 14, the nanowire layer 13, and the growth substrate 11 in that order, and light is emitted in the active layer 14. A portion of the light generated in the active layer 14 has its optical path changed by the voids 17 toward the upper surface.

[0078] As described above, the semiconductor light emitting device according to this embodiment also makes it possible to increase the amount of light emitted from the upper surface with a simple configuration.

[0079] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. [Explanation of symbols]

[0080] 10, 50...Semiconductor light emitting element 11...Growth substrate 12...Mask 12a...Opening 13...Nanowire layer 14…Active layer 15, 15a...p-type semiconductor layer 16...Buried layer 17...Void 17a...Defective part 17b...Connection 17c...Gap 18...Mesa groove 19, 19a, 19b, 19c...ITO film 20...Cathode electrode 21...Anode electrode 22...SiO2 layer 23...ITO film L…Outgoing light Lr…Reflected light

Claims

1. A semiconductor light emitting device comprising: a growth substrate; a plurality of pillar-shaped semiconductor layers formed on the growth substrate; and a buried layer covering side surfaces and top surfaces of the plurality of pillar-shaped semiconductor layers, each of the plurality of pillar-shaped semiconductor layers has an n-type nanowire layer formed at the center, an active layer formed on an outer periphery of the n-type nanowire layer, and a p-type semiconductor layer formed on an outer periphery of the active layer; the buried layer is a semiconductor layer, a void within the buried layer above the growth substrate; The gap has a plurality of voids located between the plurality of pillar-shaped semiconductor layers and a connection portion connecting the plurality of voids to each other. Semiconductor light emitting element.

2. The semiconductor light emitting device according to claim 1 , the growth substrate is a GaN substrate; The buried layer is a GaN layer. Semiconductor light emitting element.

3. 3. The semiconductor light emitting device according to claim 1, The aspect ratio defined by the height of the pillar-shaped semiconductor layer and the spacing between the pillar-shaped semiconductor layers is 0.5 or more. Semiconductor light emitting element.

4. A vehicle lamp using the semiconductor light emitting element according to any one of claims 1 to 3.

5. a masking step of forming a mask layer having a plurality of openings on a growth substrate; a growing step of forming pillar-shaped semiconductor layers in each of the plurality of openings by using selective growth; and a burying step of growing a burying layer on the growth substrate so as to cover side surfaces and top surfaces of the plurality of pillar-shaped semiconductor layers, the buried layer is a semiconductor layer, The growing step includes a step of forming an n-type nanowire layer, a step of forming an active layer outside the n-type nanowire layer, and a step of forming a p-type semiconductor layer outside the active layer. Including, the embedding step includes forming a void on the mask layer inside the embedding layer; The method for manufacturing a semiconductor light-emitting element, wherein the gap has a plurality of voids located between a plurality of the columnar semiconductor layers and connection portions connecting the plurality of voids to each other.

6. 6. The method for manufacturing a semiconductor light-emitting device according to claim 5, A method for manufacturing a semiconductor light emitting device, wherein an aspect ratio defined by the height of the pillar-shaped semiconductor layer and the spacing between the pillar-shaped semiconductor layers is set to 0.5 or more.

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