signal processing device

Abstract

To provide a signal processing device for which the wiring area can be reduced.SOLUTION: The signal processing device includes a plurality of pixel signal processing units lined up in a first direction and in a second direction, each acquiring a digital signal having a plurality of bits on the basis of an output of the corresponding avalanche photodiode and a signal line group including signal lines that are arranged in association with the plurality of pixel signal processing units lined up in the first direction and output in common a plurality of signals corresponding to a plurality of bits of different digits on each of the digital signals held in each of the plurality of pixel signal processing units lined up in the first direction.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a signal processing device. [Background technology]

[0002] Patent Document 1 discloses an information processing device including a counter that counts the number of pulse signals generated in response to the incidence of photons. The counter disclosed in Patent Document 1 is a binary counter that can acquire a digital signal containing multiple bits. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-150377 Summary of the Invention [Problem to be solved by the invention]

[0004] There are cases where it is required to reduce the area for arranging wiring for outputting digital signals. However, Patent Document 1 does not consider the output of digital signals to circuits subsequent to the counter.

[0005] An object of the present invention is to provide a signal processing device that can reduce the wiring area. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a signal line group including: a plurality of pixel signal processing units arranged to be aligned in a first direction and a second direction, each of which acquires a digital signal having a plurality of bits based on an output from a corresponding avalanche photodiode; and a signal line group arranged corresponding to the plurality of pixel signal processing units arranged in the first direction, the signal line group including signal lines through which a plurality of signals corresponding to a plurality of bits of different digits of the digital signal held in each of the plurality of pixel signal processing units arranged in the first direction are commonly output.the digital signal includes four consecutive bits, namely, a first bit, a second bit, a third bit, and a fourth bit, in this order; the signal line group includes a first signal line through which a signal corresponding to the first bit and a signal corresponding to the fourth bit are commonly output, and a second signal line through which a signal corresponding to the second bit and a signal corresponding to the third bit are commonly output; A signal processing device is provided. According to one aspect of the present invention, there is provided a signal processing device comprising: a plurality of pixel signal processing units arranged in a first direction and a second direction, each of which acquires a digital signal having a plurality of bits based on the output from a corresponding avalanche photodiode; a signal line group arranged in correspondence with the plurality of pixel signal processing units arranged in the first direction, including signal lines to which a plurality of signals corresponding to different digits of a plurality of bits of the digital signal held in each of the plurality of pixel signal processing units arranged in the first direction are commonly output; and a dummy circuit that outputs a dummy signal to one signal line of the signal line group. [Effects of the Invention]

[0007] According to the present invention, a signal processing device capable of reducing the wiring area is provided. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram illustrating the overall configuration of a photoelectric conversion device according to a first embodiment. [Figure 2] 2 is a schematic block diagram showing an example of the configuration of a sensor substrate according to the first embodiment. FIG. [Figure 3A] 1 is a schematic block diagram showing an example of the configuration of a circuit board according to a first embodiment. [Figure 3B] FIG. 4 is a schematic block diagram showing another configuration example of the circuit board according to the first embodiment. [Figure 4] 2 is a schematic block diagram showing an example of the configuration of one pixel of a photoelectric conversion unit and a pixel signal processing unit according to the first embodiment. FIG. [Figure 5] 3A to 3C are diagrams illustrating the operation of the avalanche photodiode according to the first embodiment. [Figure 6] FIG. 3 is a timing chart showing the operation of the pixel signal processing unit according to the first embodiment. [Figure 7] FIG. 10 is a schematic block diagram showing an example of the configuration of one pixel of a photoelectric conversion unit and a pixel signal processing unit according to a second embodiment. [Figure 8] FIG. 10 is a schematic diagram showing the connection relationship between a counter circuit and a pixel output circuit according to the second embodiment. [Figure 9] FIG. 10 is a plan view schematically showing the layout of a pixel signal processing unit according to a second embodiment. [Figure 10] FIG. 10 is a timing chart showing the operation of a pixel signal processing unit according to the second embodiment. [Figure 11] FIG. 11 is a schematic block diagram showing an example of the configuration of one pixel of a photoelectric conversion unit and a pixel signal processing unit according to a third embodiment. [Figure 12] FIG. 11 is a plan view schematically showing the layout of a pixel signal processing unit according to a third embodiment. [Figure 13] FIG. 11 is a timing chart showing the operation of a pixel signal processing unit according to the third embodiment. [Figure 14] FIG. 10 is a schematic block diagram showing an example of the configuration of a photoelectric conversion unit and a pixel signal processing unit for one pixel according to a fourth embodiment. [Figure 15] FIG. 10 is a circuit diagram illustrating a configuration example of an open-drain buffer circuit according to a fourth embodiment. [Figure 16] FIG. 10 is a plan view schematically showing the layout of an open-drain buffer circuit according to a fourth embodiment. [Figure 17] FIG. 13 is a schematic block diagram showing an example of the configuration of a photoelectric conversion unit and a pixel signal processing unit for two pixels according to a fifth embodiment. [Figure 18] FIG. 13 is a schematic block diagram showing an example of the configuration of a photoelectric conversion unit and a pixel signal processing unit for two pixels according to a sixth embodiment. [Figure 19] FIG. 13 is a schematic block diagram showing an example of the configuration of one pixel of a photoelectric conversion unit and a pixel signal processing unit according to the seventh embodiment. [Figure 20] FIG. 13 is a timing chart showing the operation of a pixel signal processing unit according to the seventh embodiment. [Figure 21] FIG. 13 is a block diagram of a light detection system according to an eighth embodiment. [Figure 22] FIG. 13 is a block diagram of a light detection system according to a ninth embodiment. [Figure 23] FIG. 19 is a schematic diagram of an endoscopic surgery system according to a tenth embodiment. [Figure 24] FIG. 22 is a schematic diagram of a light detection system according to an eleventh embodiment. [Figure 25] FIG. 22 is a schematic diagram of a moving body according to an eleventh embodiment. [Figure 26] 22 is a flowchart showing the operation of the light detection system according to the eleventh embodiment. [Figure 27] FIG. 23 is a diagram showing a specific example of an electronic device according to a twelfth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. The same or corresponding elements in multiple drawings are designated by the same reference numerals, and their descriptions may be omitted or simplified.

[0010] [First embodiment] FIG. 1 is a schematic diagram showing the overall configuration of a photoelectric conversion device 100 according to this embodiment. The photoelectric conversion device 100 may be, for example, a solid-state imaging device, a focus detection device, a distance measurement device, a time-of-flight (TOF) camera, or the like. The photoelectric conversion device 100 includes a sensor substrate 11 (first substrate) and a circuit substrate 21 (second substrate) stacked on top of each other. The sensor substrate 11 and the circuit substrate 21 are electrically connected to each other. The sensor substrate 11 includes a pixel region 12 in which a plurality of pixels 101 are arranged in a plurality of rows and a plurality of columns. The circuit substrate 21 includes a first circuit region 22 in which a plurality of pixel signal processing units 103 are arranged in a plurality of rows and a plurality of columns, and a second circuit region 23 arranged on the periphery of the first circuit region 22. The second circuit region 23 may include a circuit for controlling the plurality of pixel signal processing units 103, etc. The sensor substrate 11 has a light incident surface (first surface) that receives incident light and a connection surface (second surface) that faces the light incident surface. The sensor substrate 11 is connected to the circuit board 21 on the connection surface side. In other words, the photoelectric conversion device 100 is a so-called backside illuminated type.

[0011] In this specification, "plan view" refers to a view from a direction perpendicular to the light incident surface. Furthermore, a cross section refers to a surface in a direction perpendicular to the light incident surface of the sensor substrate 11. Note that the light incident surface may be rough when viewed microscopically, and in such cases, the plan view is defined based on the light incident surface when viewed macroscopically. Furthermore, in this specification, the depth direction is the direction from the light incident surface toward the connection surface.

[0012] In the following description, the sensor substrate 11 and the circuit board 21 are described as being diced chips, but the sensor substrate 11 and the circuit board 21 are not limited to being chips. For example, the sensor substrate 11 and the circuit board 21 may be wafers. Furthermore, if the sensor substrate 11 and the circuit board 21 are diced chips, the photoelectric conversion device 100 may be manufactured by stacking them in a wafer state and then dicing them, or by stacking them after dicing.

[0013] FIG. 2 is a schematic block diagram showing an example configuration of the sensor substrate 11. A plurality of pixels 101 are arranged in a plurality of rows and a plurality of columns in the pixel region 12. Each of the plurality of pixels 101 has a photoelectric conversion unit 102 including an avalanche photodiode (hereinafter referred to as an APD) as a photoelectric conversion element. If the photoelectric conversion device 100 is an imaging device, the plurality of pixels 101 may be elements that generate image signals by photoelectric conversion. However, if the photoelectric conversion device 100 is a distance measuring device using technology such as TOF, the pixels 101 may be elements that measure the time and amount of light that arrives. In other words, the use of the plurality of pixels 101 is not limited to image acquisition.

[0014] The conductivity type of the charge pairs generated in an APD that are used as signal charges is called the first conductivity type. The first conductivity type refers to a conductivity type in which charges of the same polarity as the signal charges serve as majority carriers. The conductivity type opposite the first conductivity type is called the second conductivity type. In the following, we will explain an example in which the signal charges are electrons, the first conductivity type is N-type, and the second conductivity type is P-type. However, the signal charges may also be holes, the first conductivity type is P-type, and the second conductivity type is N-type.

[0015] 3A is a schematic block diagram showing an example configuration of a circuit board 21. The circuit board 21 has a first circuit area 22 in which a plurality of pixel signal processing units 103 are arranged in a plurality of rows and a plurality of columns. In the following description, the plurality of pixel signal processing units 103 are assumed to be arranged in m+1 rows from the 0th row to the mth row and in n+1 columns from the 0th column to the nth column, but the number of rows and columns is not particularly limited. In this specification, the direction in which a plurality of pixel signal processing units 103 arranged in the same row are arranged (the horizontal direction in FIG. 3A) may be referred to as a first direction, and the direction in which a plurality of pixel signal processing units 103 arranged in the same column are arranged (the vertical direction in FIG. 3A) may be referred to as a second direction.

[0016] Also arranged on the circuit board 21 are a vertical scanning circuit 110, a horizontal scanning circuit 111, a readout circuit 112, pixel output signal lines 113, an output circuit 114, a control signal generation unit 115, and drive lines 214, 215. The multiple photoelectric conversion units 102 shown in Fig. 2 and the multiple pixel signal processing units 103 shown in Fig. 3A are electrically connected to each other via connection wiring provided for each pixel 101.

[0017] The control signal generation unit 115 is a control circuit that generates control signals for driving the vertical scanning circuit 110, the horizontal scanning circuit 111, and the readout circuit 112, and supplies these signals to each of these units. In this way, the control signal generation unit 115 controls the drive timing of each unit, etc.

[0018] The vertical scanning circuit 110 supplies a control signal to each of the plurality of pixel signal processing units 103 based on the control signal supplied from the control signal generation unit 115. As shown in FIG. 3A, the vertical scanning circuit 110 supplies control signals pRES and pVSEL to each pixel signal processing unit 103 for each row via two drive lines 214 provided for each row in the first circuit area 22. Note that in FIG. 3A and other figures, an argument may be added after the name of the control signal, and this argument indicates the corresponding row or column number. The vertical scanning circuit 110 may include logic circuits such as a shift register and an address decoder. In this way, the vertical scanning circuit 110 selects a row from which the pixel signal processing unit 103 outputs a signal.

[0019] The signal output from the photoelectric conversion unit 102 of the pixel 101 is processed in the pixel signal processing unit 103. The pixel signal processing unit 103 counts the number of pulses output from the APD included in the photoelectric conversion unit 102 to acquire and hold a digital signal having multiple bits.

[0020] The horizontal scanning circuit 111 supplies a control signal to each of the plurality of pixel signal processing units 103 based on the control signal supplied from the control signal generation unit 115. As shown in FIG. 3A, the horizontal scanning circuit 111 supplies a control signal pHSEL to each pixel signal processing unit 103 for each column via a drive line 215 provided for each column of the first circuit area 22. In this manner, the horizontal scanning circuit 111 selects a column from which a signal is to be output from the pixel signal processing unit 103. Note that there may be multiple drive lines 215 for each column. In this embodiment, as will be described later, two drive lines 215 are provided for each column.

[0021] The pixel output signal lines 113 are arranged to correspond to each row of the multiple pixel signal processing units 103. That is, the pixel output signal line 113 of one row is shared by the multiple pixel signal processing units 103 of the corresponding row. The multiple pixel signal processing units 103 of a column selected by the horizontal scanning circuit 111 output a signal POUT to the corresponding pixel output signal line 113. The signal POUT output to the pixel output signal line 113 is read out to the readout circuit 112. The readout circuit 112 outputs the signal POUT to a storage unit or a signal processing unit external to the photoelectric conversion device 100 via the output circuit 114 based on a control signal supplied from the control signal generation unit 115. The pixel output signal line 113 corresponding to one row may be a signal line group including multiple signal lines.

[0022] It is not necessary for one pixel signal processing unit 103 to be provided for each pixel 101. For example, one pixel signal processing unit 103 may be shared by multiple pixels 101. In this case, the pixel signal processing unit 103 provides a signal processing function to each pixel 101 by sequentially processing the signals output from each photoelectric conversion unit 102.

[0023] 2 and 3A, a first circuit region 22 having a plurality of pixel signal processing units 103 arranged therein is arranged in a region overlapping the pixel region 12 in a plan view. A vertical scanning circuit 110, a horizontal scanning circuit 111, a readout circuit 112, an output circuit 114, and a control signal generation unit 115 are arranged between an end of the sensor substrate 11 and an end of the pixel region 12 so as to overlap the first circuit region 22 in a plan view. In other words, the sensor substrate 11 has the pixel region 12 and a non-pixel region arranged on the periphery of the pixel region 12. A second circuit region 23 having the vertical scanning circuit 110, the horizontal scanning circuit 111, the readout circuit 112, the output circuit 114, and the control signal generation unit 115 arranged therein is arranged in a region of the circuit substrate 21 overlapping the non-pixel region in a plan view.

[0024] FIG. 3B is a schematic block diagram showing another example of the configuration of the circuit board 21. The configuration of FIG. 3B is a partial modification of the configuration of FIG. 3A. The differences between FIG. 3A and FIG. 3B will be described below. In FIG. 3A, pixel output signal lines 113 are arranged to correspond to each row of the multiple pixel signal processing units 103. In contrast, in FIG. 3B, signal lines 116 are arranged to correspond to each column of the multiple pixel signal processing units 103. The signal line 116 includes multiple wirings and has at least the function of outputting a signal POUT to the readout circuit 112 and the function of supplying a control signal pHSEL to the pixel signal processing unit 103. In other words, the signal line 116 combines the function of the pixel output signal line 113 in FIG. 3A and the function of the drive line 215. The configuration of other parts in FIG. 3B is the same as in FIG. 3A, so description thereof will be omitted.

[0025] The configuration of Fig. 3B can also operate in the same manner as the configuration of Fig. 3A, except that the direction of signal readout is different. In the following explanation, the configuration of circuit board 21 is assumed to be that shown in Fig. 3A, but by appropriately changing the explanation, it can also be applied to the configuration of Fig. 3B.

[0026] Fig. 4 is a schematic block diagram showing an example of the configuration of one pixel of the photoelectric conversion unit 102 and pixel signal processing unit 103 according to this embodiment. Fig. 4 schematically shows a more specific example of the configuration, including the connection relationship between the photoelectric conversion unit 102 arranged on the sensor substrate 11 and the pixel signal processing unit 103 arranged on the circuit board 21. Note that in Fig. 4, the two drive lines 214 in Fig. 3A are shown as drive lines 214a and 214b, and the two drive lines 215 are shown as drive lines 215a and 215b.

[0027] The photoelectric conversion unit 102 has an APD 201. The pixel signal processing unit 103 has a quenching element 202, a waveform shaping unit 210, a counter circuit 211, and a pixel output circuit 212. The counter circuit 211 has a first memory 211a and a second memory 211b. The pixel output circuit 212 has a first output circuit 212a and a second output circuit 212b. It is sufficient that the pixel signal processing unit 103 has at least one of the waveform shaping unit 210, the counter circuit 211, and the pixel output circuit 212.

[0028] The APD 201 generates charge pairs according to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD 201. A cathode of the APD 201 is connected to a first terminal of the quench element 202 and an input terminal of the waveform shaping unit 210. A voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to a second terminal of the quench element 202. As a result, a reverse bias voltage is supplied to the anode and cathode of the APD 201 such that the APD 201 performs avalanche multiplication. When charges are generated by incident light in the APD 201 to which the reverse bias voltage is supplied, the charges undergo avalanche multiplication, generating an avalanche current.

[0029] The APD 201 can operate in either Geiger mode or linear mode when a reverse bias voltage is supplied to it. The Geiger mode is a mode in which the APD operates with a potential difference between the anode and cathode greater than the breakdown voltage, while the linear mode is a mode in which the APD operates with a potential difference between the anode and cathode close to or less than the breakdown voltage.

[0030] An APD operated in Geiger mode is called a SPAD (Single Photon Avalanche Diode). In this case, for example, the voltage VL (first voltage) is −30 V and the voltage VH (second voltage) is 1 V. The APD 201 may be operated in either linear mode or Geiger mode. A SPAD is preferable because the potential difference is larger than that of a linear mode APD, making the avalanche multiplication effect more pronounced.

[0031] The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication. The quench element 202 suppresses the voltage supplied to the APD 201 to suppress avalanche multiplication (quench operation). The quench element 202 also returns the voltage supplied to the APD 201 to voltage VH by passing a current corresponding to the voltage drop caused by the quench operation (recharge operation). The quench element 202 may be, for example, a resistive element.

[0032] The waveform shaping unit 210 is a circuit that shapes the potential change of the cathode of the APD 201 obtained when a photon is detected and outputs a pulse. For example, an inverter circuit is used as the waveform shaping unit 210. While Fig. 4 shows an example in which one inverter is used as the waveform shaping unit 210, the waveform shaping unit 210 may be a circuit in which multiple inverters are connected in series, or may be any other circuit that has a waveform shaping effect.

[0033] The counter circuit 211 counts the number of pulses output from the waveform shaping unit 210 and holds a digital signal indicating the count value. A first memory 211a and a second memory 211b of the counter circuit 211 hold a first bit and a second bit of the digital signal, respectively. The counter circuit 211 resets the values held in the first memory 211a and the second memory 211b when a control signal pRES is supplied via the drive line 214a.

[0034] A control signal pVSEL is supplied to the pixel output circuit 212 from the vertical scanning circuit 110 shown in FIG. 3A via a drive line 214b shown in FIG. 4. Control signals pHSEL0 and pHSEL1 are also supplied to the pixel output circuit 212 from the horizontal scanning circuit 111 shown in FIG. 3A via a plurality of drive lines 215a and 215b shown in FIG. 4. The control signal pHSEL in FIG. 3A includes both the control signals pHSEL0 and pHSEL1. These control signals in FIG. 4 switch between electrical connection and disconnection between the counter circuit 211 and the pixel output signal line 113. The pixel output circuit 212 includes, for example, a buffer circuit for reading values stored in the first memory 211a and the second memory 211b and outputting a signal corresponding to the stored values.

[0035] The first output circuit 212a of the pixel output circuit 212 is configured to read out the first bit value held in the first memory 211a based on the control signal pHSEL0, and output it to the pixel output signal line 113. The second output circuit 212b of the pixel output circuit 212 is configured to read out the second bit value held in the second memory 211b based on the control signal pHSEL1, and output it to the pixel output signal line 113. In other words, the pixel output signal line 113 is a common signal line that transmits the first bit and second bit signals.

[0036] 4, the pixel output circuit 212 switches between electrical connection and disconnection between the counter circuit 211 and the pixel output signal line 113, but the method for controlling the signal output to the pixel output signal line 113 is not limited to this. For example, a switch such as a transistor may be disposed at a node between the quench element 202 and the APD 201, or between the photoelectric conversion unit 102 and the pixel signal processing unit 103, and the like, to switch between electrical connection and disconnection, thereby controlling the signal output to the pixel output signal line 113. Alternatively, the signal output to the pixel output signal line 113 may be controlled by changing the value of the voltage VH or voltage VL supplied to the photoelectric conversion unit 102 using a switch such as a transistor.

[0037] FIG. 4 shows an example configuration using a counter circuit 211. However, instead of the counter circuit 211, a time-to-digital converter (hereinafter referred to as TDC) and a memory may be used to acquire the timing for detecting a pulse. In this case, the generation timing of the pulse output from the waveform shaping unit 210 is converted into a digital signal by the TDC. In this case, a control signal pREF (reference signal) may be supplied to the TDC from the vertical scanning circuit 110 in FIG. 3A via a drive line. The TDC acquires, as a digital signal, a signal indicating the relative time of the input timing of the pulse with reference to the control signal pREF.

[0038] 5(a), 5(b), and 5(c) are diagrams illustrating the operation of the APD 201 according to this embodiment. FIG. 5(a) is a diagram illustrating the APD 201, the quench element 202, and the waveform shaping unit 210 extracted from FIG. 4. As shown in FIG. 5(a), the connection node between the APD 201, the quench element 202, and the input terminals of the waveform shaping unit 210 is referred to as node A. Also, as shown in FIG. 5(a), the node at the output terminal of the waveform shaping unit 210 is referred to as node B.

[0039] FIG. 5(b) is a graph showing the time change in the potential of node A in FIG. 5(a). FIG. 5(c) is a graph showing the time change in the potential of node B in FIG. 5(a). From time t0 to time t1, a voltage of VH-VL is applied to the APD 201. When a photon is incident on the APD 201 at time t1, avalanche multiplication occurs in the APD 201. As a result, an avalanche current flows through the quench element 202, and the potential of node A drops. Thereafter, the voltage drop increases further, and the voltage applied to the APD 201 gradually decreases. Then, at time t2, avalanche multiplication in the APD 201 stops. As a result, the potential of node A does not drop below a certain value. Then, from time t2 to time t3, a current flows to node A from the node at voltage VH to compensate for the voltage drop, and at time t3, node A settles to its original potential.

[0040] In the above process, the potential of node B becomes high during the period when the potential of node A is lower than a certain threshold. In this way, the waveform of the drop in potential of node A caused by the incidence of a photon is shaped by waveform shaping section 210 and output as a pulse to node B.

[0041] 6 is a timing diagram showing the operation of the pixel signal processing unit 103 according to this embodiment. Fig. 6 shows the relationship between the levels of the control signals pVSEL, pHSEL0, and pHSEL1 and the signal POUT on the pixel output signal line 113. In Fig. 6, only the kth and k+1th rows are shown for the control signal pVESL and signal POUT, and only the 0th and nth columns are shown for the control signals pHSEL0 and pHSEL1, but the same is true for the other rows and columns. The kth row can be any row from the 0th to the m-1th row.

[0042] At time t1, the control signal pVSEL[k] goes high, enabling the pixel output circuit 212 in the k-th row, thereby selecting the pixel signal processing unit 103 in the k-th row.

[0043] From time t2 to time t3, the control signal pHSEL0[0] goes high, causing the first output circuit 212a in the kth row and 0th column to read the first bit value P01 stored in the first memory 211a and output it to the pixel output signal line 113 in the kth row.

[0044] From time t4 to time t5, the control signal pHSEL1[0] goes high, causing the second output circuit 212b in the kth row and 0th column to read the second bit value P02 stored in the second memory 211b and output it to the pixel output signal line 113 in the kth row.

[0045] The period from time t1 to time t2 and the period from time t3 to time t4 may include a pixel output signal line reset period in which a reset operation of the potential of the pixel output signal line 113 is performed. This reset operation is an operation in which a predetermined potential is applied to the pixel output signal line 113 from an external potential supply line before the value of each bit is read out, thereby resetting the potential of the pixel output signal line 113. Resetting the pixel output signal line 113 to a predetermined potential before a signal is output from the pixel output circuit 212 to the pixel output signal line 113 reduces the influence of external noise or the level of a signal that was previously output to the pixel output signal line 113. This may stabilize the output of a signal from the pixel output circuit 212 to the pixel output signal line 113.

[0046] Furthermore, the length of the pixel output signal line reset period between time t1 and time t2 may be different from the length of the pixel output signal line reset period between time t3 and time t4. For example, assume that the first bit value P01 is required to be output in a more stable state than the second bit value P02. In this case, it is desirable that the pixel output signal line reset period included in the period between time t1 and time t2 be set longer than the pixel output signal line reset period included in the period between time t3 and time t4. This can make the output of the first bit value P01 from the first output circuit 212a to the pixel output signal line 113 more stable.

[0047] In this way, a signal is output from the pixel signal processing unit 103 in the kth row and 0th column to the pixel output signal line 113. At this time, the first bit value P01 and the second bit value P02 are selectively read out, and therefore they are not simultaneously read out to one pixel output signal line 113. Furthermore, by outputting the first bit value P01 and the second bit value P02 to one pixel output signal line 113 at different timings, the pixel output signal line 113 can be shared by multiple bits. By combining the first bit value P01 and the second bit value P02, it is possible to obtain the value of a digital signal corresponding to the pixel signal processing unit 103 in the kth row and 0th column. Similar reading is performed sequentially for the 1st to n-1th columns.

[0048] From time t6 to time t7, the control signal pHSEL0[n] goes high, causing the first output circuit 212a in the kth row and nth column to read the first bit value Pn1 stored in the first memory 211a and output it to the pixel output signal line 113 in the kth row.

[0049] From time t8 to time t9, the control signal pHSEL1[n] goes high, causing the second output circuit 212b in the kth row and nth column to read out the second bit value Pn2 stored in the second memory 211b and output it to the pixel output signal line 113 in the kth row.

[0050] The pixel output signal line reset period may be included in the period before time t6 and the period between time t7 and time t8. Furthermore, the lengths of these pixel output signal line reset periods may be different from each other.

[0051] In this manner, signals are output from the pixel signal processing unit 103 in the kth row and nth column to the pixel output signal line 113. At time t10, the control signal pVSEL[k] goes low, disabling the pixel output circuit 212 in the kth row. This deselects the pixel signal processing unit 103 in the kth row. Readout from the pixel signal processing unit 103 in the kth row is performed in the manner described above from time t1 to time t10.

[0052] Next, from time t11 to time t20, reading is performed from the (k+1)th row pixel signal processing unit 103. This operation is generally similar to the operation of the kth row from time t1 to time t10, and therefore description thereof will be omitted.

[0053] As described above, in this embodiment, the first bit signal and the second bit signal of the digital signals held in the pixel signal processing unit 103 are output in common to one pixel output signal line 113. This makes it possible to reduce the number of pixel output signal lines 113 compared to the case where an individual pixel output signal line is provided for each bit, and reduces the area required for wiring the pixel output signal lines 113. Therefore, this embodiment provides a signal processing device that can reduce the wiring area.

[0054] Furthermore, by utilizing the area gained by reducing the number of wires of the pixel output signal line 113 to expand the width of the wires and the space between the wires, it is possible to adjust the wire resistance and the inter-wire capacitance and reduce the time constant of the pixel output signal line 113. Therefore, by optimizing the line-and-space design of the pixel output signal line 113 while applying the configuration of this embodiment, it may be possible to reduce the output delay in some cases.

[0055] [Second embodiment] In the photoelectric conversion device 100 of this embodiment, the counter circuit 211 and pixel output circuit 212 are compatible with 4-bit digital signals. Descriptions of elements common to the first embodiment may be omitted or simplified.

[0056] FIG. 7 is a schematic block diagram showing an example of the configuration of one pixel of the photoelectric conversion unit 102 and the pixel signal processing unit 103 according to this embodiment. The counter circuit 211 of this embodiment further includes a third memory 211c and a fourth memory 211d in addition to the configuration shown in FIG. 4. The first to fourth bits held in the first to fourth memories 211a to 211d, respectively, are four consecutive bits in this order. Furthermore, the pixel signal processing unit 103 of this embodiment further includes a third output circuit 212c and a fourth output circuit 212d in addition to the configuration shown in FIG. 4. Furthermore, in this embodiment, a pixel output signal line 113a (first signal line) connected to the first output circuit 212a and the fourth output circuit 212d, and a pixel output signal line 113b (second signal line) connected to the second output circuit 212b and the third output circuit 212c are provided.

[0057] The first output circuit 212a is configured to read out the first bit value held in the first memory 211a based on the control signal pHSEL0 and output it to the pixel output signal line 113a. The fourth output circuit 212d is configured to read out the fourth bit value held in the fourth memory 211d based on the control signal pHSEL1 and output it to the pixel output signal line 113a. In other words, the pixel output signal line 113a is a common signal line that transmits the first and fourth bit signals.

[0058] The second output circuit 212b is configured to read out the second bit value held in the second memory 211b based on the control signal pHSEL0 and output it to the pixel output signal line 113b. The third output circuit 212c is configured to read out the third bit value held in the third memory 211c based on the control signal pHSEL1 and output it to the pixel output signal line 113b. In other words, the pixel output signal line 113b is a common signal line that transmits the second and third bit signals.

[0059] FIG. 8 is a schematic diagram showing the connection relationship between the counter circuit 211 and the pixel output circuit 212 according to this embodiment. FIG. 8 schematically shows the arrangement of each memory and each input circuit, and the connection relationship of the wiring in the first wiring layer and the second wiring layer that connects them to each other. In the counter circuit 211, each memory corresponding to the first to fourth bits has an input terminal CK and an output terminal Q. In the pixel output circuit 212, each output circuit corresponding to the first to fourth bits has an input terminal IN and an output terminal OUT. In FIG. 8, the reference symbols for the input terminal CK, the output terminal Q, the input terminal IN, and the output terminal OUT are assigned numbers indicating the corresponding bits, such as "CK1."

[0060] 8, the first memory 211a and the second memory 211b are arranged adjacent to each other in the second direction (vertical direction), and the second memory 211b and the third memory 211c are arranged adjacent to each other in the first direction (horizontal direction). The third memory 211c and the fourth memory 211d are arranged adjacent to each other in the second direction, and the fourth memory 211d and the first memory 211a are arranged adjacent to each other in the first direction. By arranging the multiple memories in a unicursal pattern according to the bit order in this way, the length of the wiring for carrying between bits, etc. can be minimized, thereby improving wiring efficiency.

[0061] 8, the first output circuit 212a and the second output circuit 212b are adjacently arranged in the second direction, and the second output circuit 212b and the third output circuit 212c are adjacently arranged in the first direction. The third output circuit 212c and the fourth output circuit 212d are adjacently arranged in the second direction, and the fourth output circuit 212d and the first output circuit 212a are adjacently arranged in the first direction. In this way, the arrangement order of each memory and each output circuit is in a parallel shift relationship. In other words, the positional relationship of each memory in a planar view is the same as the positional relationship of each output circuit in a planar view. By arranging them in this way, a layout is realized in which the wiring between the output of the memory and the input of the output circuit does not cross, thereby improving wiring efficiency.

[0062] The output terminal of the waveform shaping unit 210 is connected to the input terminal CK1 of the first memory 211a by wiring on the first wiring layer. The output terminal Q1 of the first memory 211a is connected to the input terminal CK2 of the second memory 211b by wiring on the first wiring layer and to the input terminal IN1 of the first output circuit 212a by wiring on the second wiring layer. The output terminal Q2 of the second memory 211b is connected to the input terminal CK3 of the third memory 211c by wiring on the second wiring layer and to the input terminal IN2 of the second output circuit 212b by wiring on the second wiring layer. The output terminal Q3 of the third memory 211c is connected to the input terminal CK4 of the fourth memory 211d by wiring on the first wiring layer and to the input terminal IN3 of the third output circuit 212c by wiring on the second wiring layer. The output terminal Q4 of the fourth memory 211d is connected to the input terminal IN4 of the fourth output circuit 212d by wiring on the second wiring layer.

[0063] The output terminal OUT1 of the first output circuit 212a and the output terminal OUT4 of the fourth output circuit 212d are connected to each other by wiring on the second wiring layer. The output terminal OUT2 of the second output circuit 212b and the output terminal OUT3 of the third output circuit 212c are connected to each other by wiring on the second wiring layer.

[0064] Fig. 9 is a plan view schematically showing the layout of the pixel signal processing unit 103 according to this embodiment. Fig. 9 schematically shows the arrangement of each memory and each input circuit, the connection relationships of the wiring in the first wiring layer and the second wiring layer that connect them to each other, the positions of the plugs, etc. Explanations of parts with the same connection relationships as in Fig. 8 will be omitted or simplified.

[0065] 9 schematically shows the quench element 202 and the waveform shaping unit 210 in addition to the counter circuit 211 and pixel output circuit 212 shown in FIG. 8. A voltage VH is supplied to a second terminal 301 of the quench element 202. A first terminal 302 of the quench element 202 is connected to an input terminal 303 of the waveform shaping unit 210 by a wire in the first wiring layer. An output terminal 304 of the waveform shaping unit 210 is connected to an input terminal CK1 of the first memory 211a by a wire in the first wiring layer.

[0066] The reset terminal 305 of the first memory 211a is connected to a drive line 214a provided on the second wiring layer via the first wiring layer. The other memories are similarly connected to the drive line 214a.

[0067] The vertical selection terminal 306 of the first output circuit 212a is connected to a drive line 214b provided on the second wiring layer via the first wiring layer. The other output circuits are similarly connected to the drive line 214b.

[0068] The horizontal selection terminals 307 of the first output circuit 212a and the second output circuit 212b are connected to a drive line 215a provided on the first wiring layer, and the horizontal selection terminals 307 of the third output circuit 212c and the fourth output circuit 212d are connected to a drive line 215b provided on the first wiring layer.

[0069] The output terminal OUT1 of the first output circuit 212a and the output terminal OUT4 of the fourth output circuit 212d are commonly connected to a pixel output signal line 113a provided on the third wiring layer. The output terminal OUT2 of the second output circuit 212b and the output terminal OUT3 of the third output circuit 212c are commonly connected to a pixel output signal line 113b provided on the third wiring layer.

[0070] Fig. 10 is a timing diagram showing the operation of the pixel signal processing unit 103 according to this embodiment, illustrating the relationship between the levels of the control signals pVSEL, pHSEL0, and pHSEL1, the signal POUT0 on the pixel output signal line 113a, and the signal POUT1 on the pixel output signal line 113b.

[0071] At time t1, the control signal pVSEL[k] goes high, enabling the pixel output circuit 212 in the k-th row, thereby selecting the pixel signal processing unit 103 in the k-th row.

[0072] From time t2 to time t3, the control signal pHSEL0[0] goes high. As a result, the first output circuit 212a in the kth row and 0th column reads out the first bit value P01 held in the first memory 211a and outputs it to the kth row pixel output signal line 113a. In addition, the second output circuit 212b in the kth row and 0th column reads out the second bit value P02 held in the second memory 211b and outputs it to the kth row pixel output signal line 113b.

[0073] From time t4 to time t5, the control signal pHSEL1[0] goes high. As a result, the third output circuit 212c in the kth row and 0th column reads out the third bit value P03 stored in the third memory 211c and outputs it to the kth row pixel output signal line 113b. In addition, the fourth output circuit 212d in the kth row and 0th column reads out the fourth bit value P04 stored in the fourth memory 211d and outputs it to the kth row pixel output signal line 113a.

[0074] In this way, signals are output from the pixel signal processing unit 103 in the kth row and 0th column to the pixel output signal lines 113a and 113b. By outputting the first bit value P01 and the fourth bit value P04 to one pixel output signal line 113a at different times, it is possible to share the pixel output signal line 113a for multiple bits. Furthermore, by outputting the second bit value P02 and the third bit value P03 to one pixel output signal line 113b at different times, it is possible to share the pixel output signal line 113b for multiple bits. Note that the processing in the subsequent periods is generally similar to that described above, and therefore will not be described here.

[0075] As described above, in this embodiment, the first-bit signal and the fourth-bit signal of the digital signals held in the pixel signal processing unit 103 are output in common to one pixel output signal line 113a. Furthermore, the second-bit signal and the third-bit signal are output in common to one pixel output signal line 113b. This allows the number of pixel output signal lines 113a and 113b to be reduced compared to when individual pixel output signal lines are provided for each bit, thereby reducing the area required for wiring the pixel output signal lines 113a and 113b. Furthermore, in this embodiment, multiple memories and multiple output circuits can be arranged in a unicursal pattern, thereby improving wiring efficiency. Therefore, this embodiment provides a signal processing device that can reduce the wiring area.

[0076] [Third embodiment] In the photoelectric conversion device 100 of this embodiment, the counter circuit 211 supports a 3-bit digital signal, and the pixel output circuit 212 has a dummy circuit. Descriptions of elements common to the first and second embodiments may be omitted or simplified.

[0077] FIG. 11 is a schematic block diagram showing an example of the configuration of one pixel of the photoelectric conversion unit 102 and the pixel signal processing unit 103 according to this embodiment. The counter circuit 211 of this embodiment further includes a third memory 211c in addition to the configuration shown in FIG. 4. The pixel signal processing unit 103 of this embodiment further includes a third output circuit 212c and a dummy circuit 212e in addition to the configuration shown in FIG. 4. The dummy circuit 212e is a circuit that outputs a dummy signal having a fixed value. In this embodiment, a pixel output signal line 113a connected to the first output circuit 212a and the dummy circuit 212e, and a pixel output signal line 113b connected to the second output circuit 212b and the third output circuit 212c are also provided.

[0078] The first output circuit 212a is configured to read the value of the first bit stored in the first memory 211a based on the control signal pHSEL0 and output the value to the pixel output signal line 113a. The dummy circuit 212e is configured to output a dummy signal to the pixel output signal line 113a based on the control signal pHSEL1. That is, the pixel output signal line 113a is a common signal line that transmits the first bit and the dummy signal.

[0079] 12 is a plan view schematically showing the layout of the pixel signal processing unit 103 according to this embodiment. Descriptions of the same parts as in FIG. 9 will be omitted or simplified.

[0080] 12 differs from FIG. 9 in that the fourth memory 211d and the wiring connected thereto are not provided, and that a dummy circuit 212e is provided instead of the fourth output circuit 212d. The dummy circuit 212e does not have an input terminal equivalent to the input terminal IN4 of the fourth output circuit 212d, and outputs a dummy signal having a fixed value from the output terminal OUT4. The output terminal OUT1 of the first output circuit 212a and the output terminal OUT4 of the dummy circuit 212e are commonly connected to a pixel output signal line 113a provided in the third wiring layer.

[0081] 13 is a timing chart showing the operation of the pixel signal processing unit 103 according to this embodiment. Descriptions of operations similar to those in FIG. 10 will be omitted or simplified.

[0082] FIG. 13 differs from FIG. 10 in that a dummy signal is output during a period, such as from time t4 to time t5. From time t4 to time t5, the control signal pHSEL1[0] goes high. This causes the third output circuit 212c in the kth row and 0th column to read the third bit value P03 stored in the third memory 211c and output it to the kth row pixel output signal line 113b. The dummy circuit 212e in the kth row and 0th column outputs the dummy signal D0 to the kth row pixel output signal line 113a. By outputting the first bit value P01 and the dummy signal D0 to the same pixel output signal line 113a at different timings, the first bit value P01 and the dummy signal D0 can share the pixel output signal line 113a. Note that the processing during other periods is generally similar to that described above, and therefore will not be described here.

[0083] The fixed value of the dummy signal output by the dummy circuit 212e may be low or high. However, this fixed value may be the same level as the level given to the memory holding the value of the bit output next to the dummy signal when the memory is reset by the control signal pRES. For example, in this embodiment, focusing on the kth row, the value of the bit output next to the dummy signal D0 is P11, which is the value of the bit held in the first memory 211a in the kth row and first column of the pixel signal processing unit 103. For example, if the value of the bit held in the first memory 211a when the first memory 211a is reset by inputting the control signal pRES to the first memory 211a is low, the value of the dummy signal D0 is low.

[0084] The effect of setting the fixed value output by the dummy circuit 212e in this manner will now be described. When signals are sequentially output via the same pixel output signal line 113a, the level of the previously output signal may cause an incorrect signal level to be output to the pixel output signal line 113a. For example, assume that the dummy signal D0 output to the pixel output signal line 113a is high and the bit value stored in the first memory 211a inside the pixel signal processing unit 103 for the kth row and first column is low. In this case, in FIG. 13, the bit value P11 output after the dummy signal D0 should actually be low. However, the bit value P11 may become high due to the influence of the previously output high-level dummy signal D0. Such an error in the bit value significantly affects image quality under conditions with a low S / N ratio, particularly under conditions where there is no incident light. This condition of no incident light can also be rephrased as a condition where no pulses are output from the APD 201. Therefore, if the level of the dummy signal D0 is set so that the dummy signal D0 and the bit value P11 output subsequently are the same level under conditions where there is no incident light, an error in the bit value under conditions where there is no incident light is less likely to occur. For example, under conditions where there is no incident light, the bit value P11 is the same level as that given when the first memory 211a in the kth row and first column inside the pixel signal processing unit 103 is reset by the control signal pRES. To achieve the above-mentioned effect, it is desirable that the fixed value of the dummy signal D0 be the same level as the bit value P11 output subsequently.

[0085] As described above, in this embodiment, the first bit signal and the dummy signal among the digital signals held in the pixel signal processing unit 103 are commonly output to one pixel output signal line 113a. The reason for providing the dummy circuit 212e that outputs the dummy signal will be explained. When the number of bits of the digital signal is an odd number, such as three, one of the pixel output signal lines carries fewer signals than the other pixel output signal lines, which can result in a blank period during which no signal flows. During the blank period, the potential becomes unstable, which makes it necessary to process a digital value containing unstable bits in a subsequent signal processing stage, potentially complicating signal processing. In contrast, in this embodiment, a dummy signal having a fixed value is output during this blank period, which makes the bit value during the blank period constant, thereby simplifying signal processing. As a result, this embodiment provides a photoelectric conversion device 100 that, in addition to the effects of the first or second embodiment, also facilitates signal processing when the bit value of the digital signal is odd.

[0086] [Fourth embodiment] In the photoelectric conversion device 100 of this embodiment, similarly to the second embodiment, the counter circuit 211 and the pixel output circuit 212 support 4-bit digital signals, and an open-drain buffer circuit is used in the pixel output circuit 212. Descriptions of elements common to any of the first to third embodiments may be omitted or simplified.

[0087] 14 is a schematic block diagram showing an example configuration of one pixel of the photoelectric conversion unit 102 and pixel signal processing unit 103 according to this embodiment. The first memory 211a of this embodiment outputs a first output signal Q1 and a second output signal QB1, which is an inverted signal of the first output signal Q1, to the first output circuit 212a. Similarly, the second memory 211b, the third memory 211c, and the fourth memory 211d are configured to output the first output signals Q2, Q3, and Q4 and their inverted signals, second output signals QB2, QB3, and QB4, respectively.

[0088] The pixel signal processing unit 103 of this embodiment also includes a selection circuit 212f. The selection circuit 212f receives a control signal pHSEL0 from a drive line 215a, a control signal pHSEL1 from a drive line 215b, and a control signal pVSEL from a drive line 214b. The selection circuit 212f generates control signals SEL0 and SEL1 based on these control signals pHSEL0, pHSEL1, and pVSEL. The control signal SEL0 is input to the first output circuit 212a and the second output circuit 212b to enable or disable these circuits. The control signal SEL1 is input to the third output circuit 212c and the fourth output circuit 212d to enable or disable these circuits.

[0089] In this embodiment, pixel output signal lines 113c, 113d, 113e, and 113f are provided. The first output circuit 212a and the fourth output circuit 212d output first output signals Q1 and Q4 to the pixel output signal line 113c and output second output signals QB1 and QB4 to the pixel output signal line 113d. The second output circuit 212b and the third output circuit 212c output first output signals Q2 and Q3 to the pixel output signal line 113e and output second output signals QB2 and QB3 to the pixel output signal line 113f. The signals output to the pixel output signal lines 113c, 113d, 113e, and 113f are referred to as signals POUTP0, POUTN0, POUTP1, and POUTN1, respectively.

[0090] The first output circuit 212a, the second output circuit 212b, the third output circuit 212c, and the fourth output circuit 212d of this embodiment are configured by open-drain buffer circuits. Fig. 15 is a circuit diagram showing an example configuration of an open-drain buffer circuit according to this embodiment. Fig. 15 shows an example of the open-drain buffer circuits that configure the first output circuit 212a and the fourth output circuit 212d.

[0091] 15 includes transistors M1, M2, M3, and M4 that constitute the first output circuit 212a, and transistors M5, M6, M7, and M8 that constitute the fourth output circuit 212d. These transistors are n-type MOS transistors.

[0092] The drains of transistors M1 and M7 are commonly connected to each other and connected to a pixel output signal line 113d. The drains of transistors M3 and M5 are commonly connected to each other and connected to a pixel output signal line 113c. The source of transistor M1 is connected to the drain of transistor M2. The source of transistor M3 is connected to the drain of transistor M4. The source of transistor M5 is connected to the drain of transistor M6. The source of transistor M7 is connected to the drain of transistor M8. The sources of transistors M2, M4, M6, and M8 are commonly connected to each other and connected to a ground wiring.

[0093] A control signal SEL0 is input to the gates of transistors M1 and M3 via signal line 215c. A control signal SEL1 is input to the gates of transistors M5 and M7 via signal line 215d. A first output signal Q1 is input to the gate of transistor M4 via signal line 217. A second output signal QB1 is input to the gate of transistor M2 via signal line 218. A first output signal Q4 is input to the gate of transistor M6 via signal line 219. A second output signal QB4 is input to the gate of transistor M8 via signal line 220.

[0094] Fig. 16 is a plan view schematically showing the layout of the open-drain buffer circuit according to this embodiment. Fig. 16 shows the arrangement of an active region 310 in which transistors M1 to M8 are formed, the arrangement of signal lines 215c, 215d, and 217 to 220 which are gate wirings, the arrangement of pixel output signal lines 113c and 113d, and the arrangement of a ground wiring 311. The ground wiring 311 is arranged in a first wiring layer, and the pixel output signal lines 113c and 113d are arranged in a second wiring layer.

[0095] 16, the active region 310 is shared by the transistors M1 to M8. The ground wiring 311 is shared by the transistors M2, M4, M6, and M8. Although only the first output circuit 212a and the fourth output circuit 212d are shown in FIGS. 15 and 16, the same circuit configuration and layout can be applied to the second output circuit 212b and the third output circuit 212c.

[0096] In this embodiment, an open-drain buffer circuit is used, which allows signals with a small voltage difference to be amplified and read out at high speed. The configuration of this embodiment is particularly effective when there are a large number of pixels and high-speed readout is required. Furthermore, in this embodiment, the active region 310 and the ground wiring 311 are shared, improving the area efficiency of the layout.

[0097] In this embodiment, a signal processing device capable of reducing the wiring area is provided, similar to the first or second embodiment. Furthermore, according to this embodiment, at least one of the effects of increasing the read speed and improving the area efficiency of the layout can be achieved.

[0098] [Fifth embodiment] The photoelectric conversion device 100 of this embodiment has a pixel output signal line 113 shared by signal processing units of two adjacent rows. Descriptions of elements common to the first embodiment may be omitted or simplified.

[0099] FIG. 17 is a schematic block diagram showing an example configuration of two pixels, including a photoelectric conversion unit 102 and pixel signal processing units 103a and 103b, according to this embodiment. FIG. 17 shows the pixel signal processing unit 103a arranged in the kth row and the pixel signal processing unit 103b arranged in the k+1th row. As shown in FIG. 17, both the pixel signal processing unit 103a and the pixel signal processing unit 103b are configured to output signals to the pixel output signal line 113 in the kth row. This allows the number of pixel output signal lines 113 to be reduced. Therefore, this embodiment provides a signal processing device that can further reduce the wiring area compared to the configuration of the first embodiment.

[0100] [Sixth embodiment] The photoelectric conversion device 100 of this embodiment has a pixel output circuit 212 and a pixel output signal line 113 shared by pixel signal processing units in two adjacent rows. Descriptions of elements common to the first and fifth embodiments may be omitted or simplified.

[0101] FIG. 18 is a schematic block diagram showing an example configuration of two pixels, including a photoelectric conversion unit 102 and pixel signal processing units 103a and 103b, according to this embodiment. FIG. 18 shows the pixel signal processing unit 103a arranged in the kth row and the pixel signal processing unit 103b arranged in the k+1th row. In this embodiment, a pixel output circuit 212 is arranged outside the pixel signal processing units 103a and 103b and is shared by the pixel signal processing units 103a and 103b. The pixel output circuit 212 is connected to the pixel output signal line 113 in the kth row. Therefore, as shown in FIG. 18, both the pixel signal processing unit 103a and the pixel signal processing unit 103b are configured to output signals to the pixel output signal line 113 in the kth row. This reduces the number of pixel output signal lines 113. Furthermore, the area required for the pixel output circuit 212 can also be reduced. Therefore, this embodiment provides a signal processing device that can further reduce the area of wiring or elements compared to the configuration of the first embodiment.

[0102] Although the present embodiment describes an example in which the pixel output circuit 212 is shared by two pixel signal processing units 103a and 103b arranged across two rows, the pixel output circuit 212 may also be shared by two pixel signal processing units arranged across two columns. This also has the effect of reducing the area required for the pixel output circuit 212.

[0103] [Seventh embodiment] In the photoelectric conversion device 100 of this embodiment, the counter circuit 211 supports a 3-bit digital signal, and the pixel output circuit 212 has a dummy circuit. Descriptions of elements common to the first to sixth embodiments may be omitted or simplified.

[0104] 19 is a schematic block diagram showing an example of the configuration of one pixel of the photoelectric conversion unit 102 and pixel signal processing unit 103 according to this embodiment. The pixel signal processing unit 103 of this embodiment differs from the configuration in FIG. 11 in that the third output circuit 212c and the dummy circuit 212e are connected to the pixel output signal line 113a, and the first output circuit 212a and the second output circuit 212b are connected to the pixel output signal line 113b.

[0105] The dummy circuit 212e is configured to output a dummy signal to the pixel output signal line 113a based on a control signal pHSEL0. The third output circuit 212c is configured to read out the value of the third bit held in the third memory 211c based on a control signal pHSEL1, and output the value to the pixel output signal line 113a. In other words, the pixel output signal line 113a is a common signal line that transmits the third bit and the dummy signal.

[0106] The second output circuit 212b is configured to read out the second bit value held in the second memory 211b based on the control signal pHSEL0 and output it to the pixel output signal line 113b. The first output circuit 212a is configured to read out the first bit value held in the first memory 211a based on the control signal pHSEL1 and output it to the pixel output signal line 113b. In other words, the pixel output signal line 113b is a common signal line that transmits the second bit and the first bit.

[0107] 20 is a timing chart showing the operation of the pixel signal processing unit 103 according to this embodiment. Descriptions of operations similar to those in FIG. 13 will be omitted or simplified.

[0108] FIG. 20 differs from FIG. 13 in that the third bit and the dummy signal are output in common to the pixel output signal line 113a, and the first bit and the second bit are output in common to the pixel output signal line 113b. That is, from time t2 to time t3, the control signal pHSEL0[0] goes high. As a result, the dummy circuit 212e in the kth row and 0th column outputs the dummy signal D0 to the kth row pixel output signal line 113a. In addition, the second output circuit 212b in the kth row and 0th column reads the value P02 of the second bit stored in the second memory 211b and outputs it to the kth row pixel output signal line 113b. Thereafter, from time t4 to time t5, the control signal pHSEL1[0] goes high. As a result, the third output circuit 212c in the kth row and 0th column reads out the third bit value P03 held in the third memory 211c and outputs it to the kth row pixel output signal line 113a. Similarly, the first output circuit 212a in the kth row and 0th column reads out the first bit value P01 held in the first memory 211a and outputs it to the kth row pixel output signal line 113b. By outputting the third bit value P03 and the dummy signal D0 to one pixel output signal line 113a at different timings, the third bit value P03 and the dummy signal D0 can share the pixel output signal line 113a.

[0109] As described above, in this embodiment, the third bit signal and the dummy signal among the digital signals held in the pixel signal processing unit 103 are commonly output to one pixel output signal line 113a. The effect of commonly outputting the third bit signal and the dummy signal to one pixel output signal line will be described below. When a signal is output via the pixel output signal line 113a, the bit value may be inverted from the level that should be output due to external noise or the like received by the pixel output signal line 113a. Such inversion of the bit value has a significant impact on image quality under conditions with a low S / N ratio, particularly under conditions with little incident light. Furthermore, when signals are sequentially output via the same pixel output signal line 113a, the output value of a certain bit may be affected by the value of the bit output immediately before.

[0110] Therefore, as described in the third embodiment, a method of reading out a dummy signal before reading out the value of a bit for which it is desired to prevent inversion due to noise or the like is considered. For example, if the counter circuit 211 is a binary counter, no pulse is output from the output terminal of the waveform shaping unit 210 when there is no incident light. Therefore, the third bit signal, the second bit signal, and the first bit signal all become the state when the third memory 211c, the second memory 211b, and the first memory 211a are reset by the control signal pRES, for example, at a low level.

[0111] In this state, consider a case where any one of the first to third bits is erroneously inverted from low to high due to the influence of noise. If the first bit, which is the least significant bit, is inverted, the value originally held by the counter circuit 211 (first digital signal) is 0 in decimal, while the output value (second digital signal) is an erroneous value of 1 in decimal. Similarly, if the second bit is inverted, the output value (second digital signal) is 2 in decimal, and if the third bit, which is the most significant bit, is inverted, the output value (second digital signal) is 4 in decimal. Thus, when the value of any one bit is inverted, the impact is greatest when the third bit, which is the most significant bit, is inverted.

[0112] Therefore, in this embodiment, a signal of the third bit, which is the most significant bit, and a low-level dummy signal are output in common to one pixel output signal line 113a. Because the low-level dummy signal is read out before the signal of the third bit is read out, even if the pixel output signal line 113a is subjected to external noise or the like, the third bit is unlikely to be inverted from low level to high level. As a result, this embodiment provides a photoelectric conversion device 100 that can reduce the influence of noise when there is little incident light, in addition to the effects of the first to third embodiments.

[0113] [Eighth embodiment] An optical detection system according to an eighth embodiment of the present invention will be described with reference to Fig. 21. Fig. 21 is a block diagram of the optical detection system according to this embodiment. The optical detection system according to this embodiment is an imaging system that acquires an image based on incident light.

[0114] The photoelectric conversion device in the above-described embodiment can be applied to various imaging systems. Examples of imaging systems include digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and surveillance cameras. Fig. 21 shows a block diagram of a digital still camera as an example of an imaging system.

[0115] The imaging system 7 shown in Fig. 21 includes a barrier 706, a lens 702, an aperture 704, an imaging device 70, a signal processing unit 708, a timing generating unit 720, an overall control and calculation unit 718, a memory unit 710, a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. The barrier 706 protects the lens, and the lens 702 forms an optical image of a subject on the imaging device 70. The aperture 704 varies the amount of light that passes through the lens 702. The imaging device 70 is configured like the photoelectric conversion device of the above-mentioned embodiment, and converts the optical image formed by the lens 702 into image data. The signal processing unit 708 performs various processes such as correction and data compression on the imaging data output from the imaging device 70.

[0116] The timing generating unit 720 outputs various timing signals to the imaging device 70 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, and the recording medium 714 is a removable recording medium such as a semiconductor memory for recording or reading image data. The external I / F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the imaging system 7, and the imaging system 7 only needs to have at least the imaging device 70 and the signal processing unit 708 for processing image signals output from the imaging device 70.

[0117] In this embodiment, the imaging device 70 and the signal processing unit 708 may be formed on the same semiconductor substrate, or the imaging device 70 and the signal processing unit 708 may be formed on separate semiconductor substrates.

[0118] Furthermore, each pixel of the image capture device 70 may include a first photoelectric conversion unit and a second photoelectric conversion unit. The signal processing unit 708 processes a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and can acquire information about the distance from the image capture device 70 to the subject.

[0119] [Ninth embodiment] Fig. 22 is a block diagram of a light detection system according to this embodiment, more specifically, a range image sensor using the photoelectric conversion device described in the above embodiment.

[0120] 22, the range image sensor 401 includes an optical system 402, a photoelectric conversion device 403, an image processing circuit 404, a monitor 405, and a memory 406. The range image sensor 401 receives light (modulated light, pulsed light) emitted from a light source device 411 toward a subject and reflected by the surface of the subject. The range image sensor 401 can obtain a range image according to the distance to the subject, based on the time between light emission and light reception.

[0121] The optical system 402 includes one or more lenses, guides image light (incident light) from a subject to the photoelectric conversion device 403 , and forms an image on the light receiving surface (sensor section) of the photoelectric conversion device 403 .

[0122] The photoelectric conversion devices of the above-described embodiments can be applied as the photoelectric conversion device 403. The photoelectric conversion device 403 supplies the image processing circuit 404 with a distance signal indicating the distance determined from the light reception signal.

[0123] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 403. The distance image (image data) obtained by the image processing can be displayed on a monitor 405 and stored (recorded) in a memory 406.

[0124] The range image sensor 401 configured in this manner can acquire an accurate range image by applying the above-described photoelectric conversion device.

[0125] [Tenth embodiment] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system, which is an example of an optical detection system.

[0126] Fig. 23 is a schematic diagram of the endoscopic surgery system according to this embodiment. Fig. 23 shows a state in which an operator (doctor) 1131 is performing surgery on a patient 1132 on a patient bed 1133 using an endoscopic surgery system 1103. As shown in the figure, the endoscopic surgery system 1103 includes an endoscope 1100, a surgical tool 1110, an arm 1121, and a cart 1134 on which various devices for endoscopic surgery are mounted.

[0127] The endoscope 1100 includes a lens barrel 1101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 1132, and a camera head 1102 connected to the base end of the lens barrel 1101. Although Fig. 23 shows the endoscope 1100 configured as a so-called rigid scope having a rigid lens barrel 1101, the endoscope 1100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0128] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 1101. A light source device 1203 is connected to the endoscope 1100. Light generated by the light source device 1203 is guided to the tip of the lens barrel 1101 by a light guide extending inside the lens barrel 1101, and is irradiated via the objective lens towards an observation target inside the body cavity of the patient 1132. Note that the endoscope 1100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0129] An optical system and a photoelectric conversion device are provided inside the camera head 1102, and light reflected from an observation object (observation light) is focused onto the photoelectric conversion device by the optical system. The observation light is photoelectrically converted by the photoelectric conversion device to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observation image. The photoelectric conversion device may be any of the photoelectric conversion devices described in the above-described embodiments. The image signal is transmitted to a camera control unit (CCU) 1135 as RAW data.

[0130] The CCU 1135 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 1100 and the display device 1136. Furthermore, the CCU 1135 receives an image signal from the camera head 1102, and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0131] Under the control of the CCU 1135 , the display device 1136 displays an image based on the image signal that has been subjected to image processing by the CCU 1135 .

[0132] The light source device 1203 includes a light source such as an LED (Light Emitting Diode), and supplies the endoscope 1100 with irradiation light when photographing an operation site or the like.

[0133] The input device 1137 is an input interface for the endoscopic surgery system 1103. A user can input various information and instructions to the endoscopic surgery system 1103 via the input device 1137.

[0134] The treatment tool control device 1138 controls the driving of the energy treatment tool 1112 for cauterizing tissue, incising, sealing blood vessels, or the like.

[0135] The light source device 1203 can supply illumination light to the endoscope 1100 when photographing the surgical site, and can be, for example, a white light source such as an LED, a laser light source, or a combination of these. When the white light source is configured by combining RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision. This makes it possible to adjust the white balance of the captured image in the light source device 1203. In this case, laser light from each of the RGB laser light sources can be irradiated onto the observation object in a time-division manner, and the drive of the image sensor of the camera head 1102 can be controlled in synchronization with the irradiation timing. This makes it possible to capture images corresponding to each RGB in a time-division manner. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0136] Furthermore, the driving of the light source device 1203 may be controlled so that the intensity of light output from the light source device 1203 is changed at predetermined time intervals. By controlling the driving of the image sensor of the camera head 1102 in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0137] Furthermore, the light source device 1203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation can utilize, for example, the wavelength dependence of light absorption in body tissue. Specifically, by irradiating light with a narrower band than the light (i.e., white light) used in normal observation, a specific tissue, such as blood vessels on the surface of the mucosa, can be photographed with high contrast. Alternatively, special light observation may involve fluorescence observation, in which an image is obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto a body tissue and observing the fluorescence from the body tissue, or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 1203 can be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0138] [Eleventh embodiment] The light detection system and moving body of this embodiment will be described with reference to Figures 24, 25 and 26. In this embodiment, an in-vehicle camera will be shown as an example of the light detection system.

[0139] FIG. 24 is a schematic diagram of a photodetection system according to this embodiment, illustrating an example of a vehicle system and a photodetection system mounted on the vehicle system. The photodetection system 1301 includes a photoelectric conversion device 1302, an image preprocessing unit 1315, an integrated circuit 1303, and an optical system 1314. The optical system 1314 forms an optical image of a subject on the photoelectric conversion device 1302. The photoelectric conversion device 1302 converts the optical image of the subject formed by the optical system 1314 into an electrical signal. The photoelectric conversion device 1302 is any one of the photoelectric conversion devices according to the above-described embodiments. The image preprocessing unit 1315 performs predetermined signal processing on the signal output from the photoelectric conversion device 1302. The function of the image preprocessing unit 1315 may be incorporated into the photoelectric conversion device 1302. The light detection system 1301 is provided with at least two sets of an optical system 1314 , a photoelectric conversion device 1302 and an image pre-processing unit 1315 , and the output from each set of image pre-processing units 1315 is input to the integrated circuit 1303 .

[0140] The integrated circuit 1303 is an integrated circuit for use in an imaging system, and includes an image processing unit 1304 including a storage medium 1305, an optical distance measurement unit 1306, a parallax calculation unit 1307, an object recognition unit 1308, and an abnormality detection unit 1309. The image processing unit 1304 performs image processing such as development and defect correction on the output signal of the image pre-processing unit 1315. The storage medium 1305 temporarily stores the captured image and stores the defect positions of the captured pixels. The optical distance measurement unit 1306 focuses or measures the distance to the subject. The parallax calculation unit 1307 calculates distance measurement information from multiple image data acquired by multiple photoelectric conversion devices 1302. The object recognition unit 1308 recognizes subjects such as cars, roads, signs, and people. If the abnormality detection unit 1309 detects an abnormality in the photoelectric conversion device 1302, it notifies the main control unit 1313 of the abnormality.

[0141] The integrated circuit 1303 may be realized by dedicated hardware, a software module, or a combination thereof. It may also be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like, or a combination thereof.

[0142] The main control unit 1313 supervises and controls the operations of the light detection system 1301, the vehicle sensor 1310, the control unit 1320, etc. Instead of having the main control unit 1313, the light detection system 1301, the vehicle sensor 1310, and the control unit 1320 may each have a communication interface and send and receive control signals via a communication network according to, for example, the CAN standard.

[0143] The integrated circuit 1303 has a function of receiving a control signal from the main control unit 1313 or transmitting a control signal or a set value to the photoelectric conversion device 1302 by its own control unit.

[0144] The optical detection system 1301 is connected to a vehicle sensor 1310 and can detect the vehicle's driving conditions, such as vehicle speed, yaw rate, and steering angle, as well as the conditions of the environment outside the vehicle and other vehicles and obstacles. The vehicle sensor 1310 also serves as a distance information acquisition unit that acquires distance information to an object. The optical detection system 1301 is also connected to a driving assistance control unit 1311 that performs various driving assistance functions, such as automatic steering, automatic cruising, and collision prevention functions. In particular, the collision determination function determines whether or not a collision with another vehicle or obstacle has occurred based on the detection results of the optical detection system 1301 and the vehicle sensor 1310. This allows for avoidance control when a collision is predicted, and activation of safety devices in the event of a collision.

[0145] The light detection system 1301 is also connected to an alarm device 1312 that issues an alarm to the driver based on the determination result of the collision determination unit. For example, if the collision determination unit determines that there is a high possibility of a collision, the main control unit 1313 performs vehicle control such as applying the brakes, releasing the accelerator, and suppressing engine output, thereby avoiding the collision or mitigating damage. The alarm device 1312 issues an alarm to the user by issuing an alarm such as a sound, displaying alarm information on the display screen of a car navigation system or an instrument panel, applying vibration to the seat belt or steering wheel, etc.

[0146] The light detection system 1301 in this embodiment can capture images of the surroundings of the vehicle, for example, the front or rear. Figures 25(a), 25(b), and 25(c) are schematic diagrams of a moving object in this embodiment, showing a configuration in which the light detection system 1301 captures an image of the area in front of the vehicle.

[0147] The two photoelectric conversion devices 1302 are disposed in front of the vehicle 1300. Specifically, it is preferable that the center line of the vehicle 1300 relative to its forward / backward direction or its outer shape (for example, its width) be regarded as an axis of symmetry, and that the two photoelectric conversion devices 1302 be disposed symmetrically about the axis of symmetry. This makes it possible to effectively obtain distance information between the vehicle 1300 and an object to be photographed and to determine the possibility of a collision. It is also preferable that the photoelectric conversion devices 1302 be disposed in a position that does not obstruct the driver's field of vision when the driver visually checks the situation outside the vehicle 1300 from the driver's seat. It is preferable that the warning device 1312 be disposed in a position that is easily within the driver's field of vision.

[0148] Next, a fault detection operation of the photoelectric conversion device 1302 in the photodetection system 1301 will be described with reference to Fig. 26. Fig. 26 is a flowchart showing the operation of the photodetection system in this embodiment. The fault detection operation of the photoelectric conversion device 1302 can be performed in accordance with steps S1410 to S1480 shown in Fig. 26.

[0149] In step S1410, startup settings are made for the photoelectric conversion device 1302. That is, setting information for the operation of the photoelectric conversion device 1302 is transmitted from outside the photodetection system 1301 (for example, from the main control unit 1313) or from inside the photodetection system 1301, and the photoelectric conversion device 1302 starts imaging operations and fault detection operations.

[0150] Next, in step S1420, the photoelectric conversion device 1302 acquires pixel signals from the valid pixels. Furthermore, in step S1430, the photoelectric conversion device 1302 acquires output values from failure detection pixels provided for failure detection. These failure detection pixels include photoelectric conversion elements, just like the valid pixels. A predetermined voltage is written to these photoelectric conversion elements. The failure detection pixels output signals corresponding to the voltage written to these photoelectric conversion elements. Note that steps S1420 and S1430 may be executed in reverse order.

[0151] Next, in step S1440, the photodetection system 1301 determines whether the expected output value of the fault detection pixel matches the actual output value from the fault detection pixel. If the result of the determination in step S1440 indicates that the expected output value and the actual output value match, the photodetection system 1301 proceeds to processing in step S1450, determines that the imaging operation is being performed normally, and proceeds to processing in step S1460. In step S1460, the photodetection system 1301 transmits the pixel signals of the scanning row to the storage medium 1305 for temporary storage. Thereafter, the photodetection system 1301 returns to processing in step S1420 and continues the fault detection operation. On the other hand, if the result of the determination in step S1440 indicates that the expected output value and the actual output value do not match, the photodetection system 1301 proceeds to processing in step S1470. In step S1470, the light detection system 1301 determines that there is an abnormality in the imaging operation, and issues an alarm to the main control unit 1313 or the alarm device 1312. The alarm device 1312 displays on the display unit that an abnormality has been detected. Thereafter, in step S1480, the light detection system 1301 stops the photoelectric conversion device 1302, and ends the operation of the light detection system 1301.

[0152] In this embodiment, the flowchart is looped for each line, but the flowchart may be looped for each set of lines, or the fault detection operation may be performed for each frame. The issuance of the alarm in step S1470 may be notified to the outside of the vehicle via a wireless network.

[0153] Furthermore, although the present embodiment has been described as a control for preventing collisions with other vehicles, the present invention is also applicable to control for automatic driving by following other vehicles, control for automatic driving so as not to deviate from a lane, and the like. Furthermore, the light detection system 1301 is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention is not limited to moving bodies, but can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0154] The photoelectric conversion device of the present invention may further be configured to be capable of acquiring various types of information such as distance information.

[0155] [Twelfth embodiment] FIG. 27(a) is a diagram showing a specific example of an electronic device according to this embodiment, illustrating glasses 1600 (smart glasses). The glasses 1600 are provided with a photoelectric conversion device 1602 according to any of the above-described embodiments. That is, the glasses 1600 are an example of a light detection system to which the photoelectric conversion device 1602 according to any of the above-described embodiments can be applied. A display device including a light-emitting device such as an OLED or LED may be provided on the rear side of the lens 1601. The number of photoelectric conversion devices 1602 may be one or more. Furthermore, multiple types of photoelectric conversion devices may be combined. The arrangement position of the photoelectric conversion device 1602 is not limited to that shown in FIG. 27(a).

[0156] The glasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the photoelectric conversion device 1602 and the display device described above. The control device 1603 also controls the operations of the photoelectric conversion device 1602 and the display device. The lens 1601 is formed with an optical system for focusing light onto the photoelectric conversion device 1602.

[0157] FIG. 27(b) shows glasses 1610 (smart glasses) according to one application example. The glasses 1610 include a control device 1612, which is equipped with a photoelectric conversion device corresponding to the photoelectric conversion device 1602 and a display device. A lens 1611 includes a photoelectric conversion device within the control device 1612 and an optical system for projecting light emitted from the display device, and an image is projected onto the lens 1611. The control device 1612 functions as a power source for supplying power to the photoelectric conversion device and the display device, and controls the operation of the photoelectric conversion device and the display device. The control device 1612 may also include a gaze detection unit for detecting the gaze of the wearer. Infrared light may be used for gaze detection. The infrared light emitter emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit having a light receiving element detects the emitted infrared light reflected from the eyeball, thereby obtaining an image of the eyeball. By providing a reduction means for reducing the amount of light from the infrared light emitting section to the display section in a plan view, degradation of image quality is reduced.

[0158] The control device 1612 detects the user's line of sight with respect to the displayed image from the captured image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using the captured image of the eyeball. As an example, a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea can be used.

[0159] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0160] The display device of this embodiment may have a photoelectric conversion device having a light receiving element, and may control the image displayed on the display device based on information on the user's line of sight from the photoelectric conversion device.

[0161] Specifically, the display device determines a first field of view area where the user gazes and a second field of view area other than the first field of view area based on the line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device or by an external control device. In the display area of the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than that of the first field of view area.

[0162] The display area may also include a first display area and a second display area different from the first display area. A high-priority area may be determined from the first display area and the second display area based on line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device or by an external control device. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0163] Note that AI (Artificial Intelligence) may be used in determining the first field of view area and the area with high priority. The AI may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from the image of the eyeball, using as training data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI program may be provided in either the display device or the photoelectric conversion device, or in an external device. If the external device has the AI program, it may be transmitted to the display device from a server or the like via communication.

[0164] When display control is performed based on visual recognition detection, this embodiment can be preferably applied to smart glasses that further include a photoelectric conversion device that captures an image of the outside world. The smart glasses can display captured external information in real time.

[0165] [Other embodiments] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also an embodiment of the present invention.

[0166] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0167] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0168] 100 Photoelectric conversion device 102 Photoelectric conversion unit 103 Pixel signal processing unit 113 Pixel output signal line 201 Avalanche photodiode 211 Counter Circuit 211a First Memory 211b Second Memory 212 pixel output circuit 212a First output circuit 212b Second output circuit

Claims

1. a plurality of pixel signal processing units arranged in a first direction and a second direction, each of which acquires a digital signal having a plurality of bits based on an output from a corresponding avalanche photodiode; a signal line group including a signal line that is arranged corresponding to the plurality of pixel signal processing units arranged in the first direction, and that commonly outputs a plurality of signals that respectively correspond to a plurality of bits of different digits of the digital signal held in each of the plurality of pixel signal processing units arranged in the first direction; Equipped with the digital signal includes four consecutive bits, a first bit, a second bit, a third bit, and a fourth bit, in this order; the signal line group includes a first signal line through which a signal corresponding to the first bit and a signal corresponding to the fourth bit are commonly output, and a second signal line through which a signal corresponding to the second bit and a signal corresponding to the third bit are commonly output. A signal processing device comprising:

2. A plurality of pixel signal processing units arranged in a first direction and a second direction, each of which acquires a digital signal having a plurality of bits based on an output from a corresponding avalanche photodiode; a signal line group including a signal line that is arranged corresponding to the plurality of pixel signal processing units arranged in the first direction, and that commonly outputs a plurality of signals that respectively correspond to a plurality of bits of different digits of the digital signal held in each of the plurality of pixel signal processing units arranged in the first direction; a dummy circuit that outputs a dummy signal to one of the signal lines; A signal processing device comprising:

3. each of the plurality of pixel signal processing units includes a counter circuit that acquires the digital signal by counting the number of pulses output from a corresponding avalanche photodiode; 3. The signal processing device according to claim 1 or 2.

4. each of the plurality of pixel signal processing units further includes an output circuit that reads out the value of each of the plurality of bits from the counter circuit and outputs the value to the signal line; 4. The signal processing device according to claim 3.

5. the output circuit selectively reads out any one of the values of the plurality of bits and outputs it to the signal line; 5. The signal processing device according to claim 4.

6. the output circuit outputs the plurality of signals corresponding to the plurality of bits to the signal line at timings different from each other; 6. The signal processing device according to claim 4, wherein:

7. during a period in which each of the plurality of signals corresponding to the plurality of bits is output from the output circuit to the signal line, a reset operation is performed by applying a predetermined potential to the signal line between a time when a signal corresponding to one bit of the plurality of bits is output and a time when a signal corresponding to another bit of the plurality of bits is output; 7. The signal processing device according to claim 6.

8. the output circuit is an open-drain buffer circuit including a plurality of transistors; 8. The signal processing device according to claim 4, wherein:

9. the plurality of transistors are formed in a common active region; 9. The signal processing device according to claim 8.

10. The plurality of transistors are connected to a common ground wiring.

10. The signal processing device according to claim 8 or 9.

11. each of the plurality of pixel signal processing units includes a counter circuit that acquires the digital signal by counting the number of pulses output from a corresponding avalanche photodiode; the counter circuit includes a first memory that holds the first bit, a second memory that holds the second bit, a third memory that holds the third bit, and a fourth memory that holds the fourth bit; the first memory and the second memory are arranged adjacent to each other in the second direction, the second memory and the third memory are arranged adjacent to each other in the first direction, the third memory and the fourth memory are arranged adjacent to each other in the second direction, the fourth memory and the first memory are arranged adjacent to each other in the first direction; 2. The signal processing device according to claim 1.

12. further comprising a first output circuit that reads out the first bit, a second output circuit that reads out the second bit, a third output circuit that reads out the third bit, and a fourth output circuit that reads out the fourth bit from the counter circuit; the first output circuit and the second output circuit are arranged adjacent to each other in the second direction, the second output circuit and the third output circuit are arranged adjacent to each other in the first direction, the third output circuit and the fourth output circuit are arranged adjacent to each other in the second direction, the fourth output circuit and the first output circuit are disposed adjacent to each other in the first direction; 12. The signal processing device according to claim 11.

13. a positional relationship among the first memory, the second memory, the third memory, and the fourth memory in a plan view is the same as a positional relationship among the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit in the plan view; 13. The signal processing device according to claim 12.

14. the number of bits included in the digital signal is odd, the signal line group includes a signal line through which a signal corresponding to one bit of the digital signal and the dummy signal are commonly output; 3. The signal processing device according to claim 2.

15. a value of the dummy signal is the same as a value of a bit output next to the dummy signal when no pulse is output from the avalanche photodiode; 15. The signal processing device according to claim 2 or 14.

16. a bit outputted next to the dummy signal onto a signal line through which a signal corresponding to one bit of the digital signal and the dummy signal are commonly outputted, the bit being such that the difference between a first digital signal held by a counter circuit when no pulse is outputted from the avalanche photodiode and a second digital signal in which any one bit of the first digital signal is inverted is the largest; 16. A signal processing device according to claim 2, 14 or 15.

17. the signal line group includes a signal line through which a plurality of signals based on two pixel signal processing units adjacent to each other in the second direction are commonly output.

17. A signal processing device according to any one of claims 1 to 16.

18. each of the plurality of pixel signal processing units includes a counter circuit that acquires the digital signal by counting the number of pulses output from a corresponding avalanche photodiode; a common output circuit that reads and outputs the values of the plurality of bits from the counter circuits of the two pixel signal processing units adjacent to each other in the first direction or the second direction, 18. A signal processing device according to any one of claims 1 to 17.

19. a plurality of avalanche photodiodes; a signal processing device according to any one of claims 1 to 18, which processes signals output from each of the plurality of avalanche photodiodes; A photoelectric conversion device comprising:

20. the plurality of avalanche photodiodes are disposed on a first substrate; the signal processing device is disposed on a second substrate stacked on the first substrate; 20. The photoelectric conversion device according to claim 19.

21. The photoelectric conversion device according to claim 19 or 20; a signal processing unit that processes a signal output from the photoelectric conversion device; An optical detection system comprising:

22. A mobile object, The photoelectric conversion device according to claim 19 or 20; a distance information acquisition unit that acquires distance information to an object from a signal output from the photoelectric conversion device; a control unit that controls the moving object based on the distance information; A moving object comprising:

Images