Grain size control of superconducting materials in thin films for Josephson junctions

Abstract

The superconducting circuit includes a Josephson junction device including a lower superconducting material layer formed on a substrate and a junction layer formed on the lower superconducting material layer. The superconducting circuit also includes an upper superconducting material layer formed on the junction layer. At least the lower superconducting material layer includes crystal grains having a size larger than the size of the Josephson junctions of the Josephson junction device.

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION The presently claimed embodiments of the present invention relate to methods for controlling the grain size of superconducting material for Josephson junctions and Josephson junction circuits having superconducting material. [Background technology]

[0002] Quantum circuits containing Josephson junctions have many applications. Quantum computing circuits use qubits, which can include Josephson junctions. Josephson junctions are often formed as a stack of a bottom superconducting material layer (e.g., an aluminum superconducting layer), a thin oxide, and a top superconducting material layer (e.g., an aluminum layer), with the stack formed on a substrate such as silicon. The grain size of the thin film of superconducting material layer, such as the aluminum layer, is a significant fraction of the size of the Josephson junction. As a result, the junction may contain varying amounts of aluminum grains. As a result, the ratio of grain boundary (GB) area to superconducting aluminum (Al) grain area can change when moving between junctions, leading to material-based inhomogeneities in Josephson junction characteristics.

[0003] Furthermore, oxidation of the aluminum surface during Josephson junction fabrication occurs at different rates at different surfaces or grain boundaries, and permeates differently through different GB orientations. If the superconducting (aluminum) grain size in the superconducting material layer is similar in size compared to the size of the Josephson junction, the number of grains and grain boundary area may vary from junction to junction if oxidation is differential, causing material-based variations in Josephson junction characteristics.

[0004] It would therefore be desirable to overcome these and other problems of the prior art, for example, by controlling the grain size of the superconducting material layer. Summary of the Invention

[0005] One aspect of the present invention is to provide a superconducting circuit including a Josephson junction device including a lower superconducting material layer formed on a substrate, a bonding layer formed on the lower superconducting material layer, and an upper superconducting material layer formed on the bonding layer, wherein at least the lower superconducting material layer includes crystal grains having a size larger than the size of the Josephson junctions of the Josephson junction device.

[0006] In one embodiment, the lower superconducting material layer is formed of single crystal grains. In one embodiment, the lower superconducting material layer is epitaxial with the substrate. In one embodiment, the epitaxial lower superconducting material is formed of aluminum. In one embodiment, the aluminum is oriented such that its (110) plane is parallel to the substrate. In one embodiment, the grains of the lower superconducting material layer are formed by increasing the size of the grains by annealing. In one embodiment, the substrate comprises at least one of silicon (Si) and sapphire.

[0007] Another aspect of the present invention is to provide a superconducting circuit including a Josephson junction device including a superconducting alloy layer and a junction layer formed on the superconducting alloy layer, wherein the superconducting alloy layer has an average grain size of less than about 20 nm, which is smaller than the width and length of the Josephson junction of the Josephson junction device.

[0008] In one embodiment, the superconducting alloy layer is an aluminum alloy layer. In one embodiment, the aluminum alloy layer has an average grain size of less than 10 nm. In one embodiment, the superconducting alloy layer is amorphous. In one embodiment, the aluminum alloy includes aluminum and at least one element selected from the group consisting of Si, Mg, V, Nb, Ta, La, Zr, Hf, Ti, Zn, In, and Sn. In one embodiment, the concentration of aluminum in the aluminum alloy is in the range of about 66% to about 97%.

[0009] A further aspect of the present invention is to provide a method of forming a Josephson junction device, the method including forming a layer of superconducting material on a substrate and annealing the layer of superconducting material such that the layer of superconducting material has a single grain across the width and length of a Josephson junction of the Josephson junction device.

[0010] In one embodiment, the superconducting material layer is an aluminum layer. In one embodiment, the single crystal grain is epitaxially aligned with the substrate. In one embodiment, the substrate comprises at least one of Si and sapphire. In one embodiment, the annealing is performed at a temperature range of about 200°C to about 570°C, preferentially about 400°C to about 570°C.

[0011] Another aspect of the present invention provides a method for forming a Josephson junction of a Josephson junction device, the method including forming a superconducting alloy layer of the Josephson junction device on a substrate, the superconducting alloy layer having an average grain size of less than about 20 nm, which is smaller than the width and length of the Josephson junction.

[0012] In one embodiment, the superconducting alloy layer is an aluminum alloy layer. In one embodiment, the average grain size is less than 10 nm. In one embodiment, the superconducting alloy layer is amorphous. In one embodiment, the aluminum alloy layer is amorphous. In one embodiment, the aluminum alloy layer comprises aluminum and at least one element selected from the group consisting of Si, Mg, V, Nb, Ta, La, Zr, Hf, Ti, Zn, In, and Sn. In one embodiment, the concentration of aluminum in the aluminum alloy layer is in the range of about 66% to about 97%. [Brief explanation of the drawings]

[0013] The present disclosure, as well as the method of operation and function of the associated elements of construction, and the combination of parts and economies of manufacture, will become more apparent from a consideration of the following description and appended claims, with reference to the accompanying drawings, all of which form a part of this specification, and in which like reference numerals indicate corresponding parts in the various views. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a limitation on the scope of the invention.

[0014] [Figure 1] FIG. 1 illustrates a Josephson junction circuit 100 according to some embodiments of the present invention.

[0015] [Figure 2A] 1 is a cross-sectional side view of a Josephson junction according to some embodiments of the present invention.

[0016] [Figure 2B] 2B is a top cutaway view of the Josephson junction of FIG. 2A according to some embodiments of the present invention.

[0017] [Figure 3A] 1 shows a portion of the bottom aluminum layer before annealing according to some embodiments of the present invention.

[0018] [Figure 3B] 10 shows a portion of the bottom aluminum layer after annealing according to some embodiments of the present invention.

[0019] [Figure 3C] 10 illustrates a portion of the bottom aluminum layer overlying a Josephson junction after alloying of the bottom aluminum layer according to some embodiments of the present invention.

[0020] [Figure 4] 1 shows an X-ray diffraction (XRD) intensity graph as a function of temperature for aluminum, according to some embodiments of the present invention.

[0021] [Figure 5A]1 is a graph showing the presence of an XRD Al(111) peak as a function of temperature, according to some embodiments of the present invention. [Figure 5B] 1 is a graph illustrating the presence of an XRD Al(111) peak as a function of time, according to some embodiments of the present invention.

[0022] [Figure 6A] 1 is a graph showing XRD measurements of deposited aluminum before annealing, according to some embodiments of the present invention. [Figure 6B] 1 is a graph showing XRD measurements of deposited aluminum after annealing, according to some embodiments of the present invention.

[0023] [Figure 7] 1A-1C are transmission electron microscope images showing the effect of annealing Al(111) on Si(100) according to some embodiments of the present invention.

[0024] [Figure 8] 10A-10C are transmission electron microscope images showing the effect of annealing Al(111) on Si(100) over a larger area of the device, according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0025] To address the issues resulting from the superconducting grains having a size similar to that of the Josephson junction, in some embodiments the microstructure of the Josephson junction is controlled to make the size of the superconducting grains much larger than the size of the Josephson junction or much smaller than the size of the Josephson junction.

[0026] In one embodiment, increasing the grain size of a superconducting material (e.g., aluminum) can be achieved by using high temperature annealing and subsequent cooling of the superconducting material. By dramatically increasing the grain size, it becomes possible to provide Josephson junctions in a single crystal grain superconducting material that are equivalent to those constructed with single crystal superconducting material.

[0027] Instead of making the grain size of the superconducting material larger than the size of the Josephson junction, the grain size of the superconducting material may be controlled to be much smaller than the size of the Josephson junction. For example, the grain size of the superconducting material can be reduced by alloying the superconducting material. Josephson junctions constructed using smaller grains of superconducting material to reduce the grain size can contain hundreds of grains, which can be similar per Josephson junction, thus reducing the variation in Josephson junction structure due to the grain size of the superconducting material. Finally, amorphous superconducting material alloy layers can also have uniform material per Josephson junction, similar to junctions of single superconducting material grains. According to some embodiments, the alloyed superconducting material can be formed via evaporation or sputtering.

[0028] 1 illustrates a Josephson junction circuit 100 according to some embodiments. The Josephson junction circuit 100 includes a Josephson junction element 110 and a circuit element 120 coupled to the Josephson junction (JJ) element 110.

[0029] 2A is a cross-sectional side view of a Josephson junction (JJ) device according to some embodiments of the present invention. The Josephson junction device includes a bottom superconducting material layer 210 formed on a substrate 220. A top superconducting material layer 230 is formed on the bottom superconducting material layer 210, and a thin oxide layer 240, which functions as a tunneling layer, is disposed between the bottom superconducting material layer 210 and the top superconducting material layer 230.

[0030] In one embodiment, the bottom or lower superconducting material layer 210 is formed of single crystal grains. In one embodiment, the lower superconducting material layer 210 is epitaxial with the substrate 220. In one embodiment, the lower superconducting material layer 210 and / or the upper superconducting material layer 230 are formed of aluminum. In one embodiment, the substrate 220 comprises silicon (Si) and / or sapphire. In one embodiment, the thin oxide layer (tunnel junction layer) 240 comprises a thin oxide of the lower superconducting material layer 210.

[0031] Figure 2B is a top cutaway view of the Josephson junction device of Figure 2A, showing Josephson junction (JJ) 260, with a thin oxide layer 240 contacting and separating bottom superconducting material layer 210 from top superconducting material layer 230. The size of Josephson junction 260 is outlined in Figure 2B by a pattern showing the areas where bottom superconducting material layer 210 and top aluminum layer 230 contact thin oxide layer 240, which acts as a tunneling barrier.

[0032] Although the Josephson junction device in FIGS. 2A and 2B shows a single Josephson junction, the Josephson junction device may have multiple (ie, two or more) Josephson junctions.

[0033] FIG. 3A shows a portion of bottom superconducting material layer 210 before annealing region A, with the grains of bottom superconducting material layer 210 visible in the region of Josephson junction 260.

[0034] Annealing to Increase Grain Size: FIG. 3B illustrates a portion of bottom superconducting material layer 210 overlying Josephson junction 260 having a size of area A after annealing bottom superconducting material layer 210, with the grains of bottom superconducting material layer 210 shown in the region of Josephson junction 260. In one embodiment, the grains of bottom or lower superconducting material layer 210 are formed by annealing to increase the size of the grains. Comparing FIGS. 3A and 3B, it can be seen that annealing bottom superconducting material layer 210 increases the grain size such that a single grain in bottom superconducting material layer 210 overlies the region of Josephson junction 260. Bottom superconducting material layer 210 is annealed such that bottom superconducting material layer 210 has a single grain across the width and length of the Josephson junction of the device. Annealing can be performed, for example, at a temperature range of about 200° C. to about 570° C., preferentially about 400° C. to about 570° C.

[0035] While FIG. 3B shows that annealing bottom superconducting material layer 210 increases the grain size so that a single crystal grain in bottom superconducting material layer 210 overlaps the region of Josephson junction 260, top superconducting material layer 230 may alternatively be annealed to increase the grain size so that a single crystal grain in top superconducting material layer 230 overlaps the region of Josephson junction 260.

[0036] 2A, the substrate 220 may be formed of silicon, such as Si(001). Upon annealing, at least the bottom superconducting material (e.g., aluminum) layer 210 may be formed with single-crystal grains and may be epitaxial with the substrate 220, where the single-crystal grains are formed by increasing the grain size of the superconducting material (e.g., aluminum) upon annealing.

[0037] Figure 4 shows an X-ray diffraction (XRD) intensity graph of a superconducting material (e.g., aluminum) as a function of temperature. In situ XRD was performed using a linear detector while annealing a 35 nm thick superconducting material (e.g., aluminum) on a Si(001) substrate in a purified He atmosphere at a ramp rate of 4.5 °C / s. At low temperatures, the deposited Al exhibits a (111) plane oriented parallel to the surface of the silicon substrate. The Al(111) peak and X-ray scattering background disappear approximately 50 °C below the eutectic melting temperature. Melting of the superconducting material was detected by an increase in background X-rays near the eutectic melting temperature of approximately 577 °C.

[0038] Figures 5A and 5B show the presence of the XRD Al(111) peak as a function of temperature and time, respectively. The Al(111) peak disappears at higher temperatures as the sample cools before reaching the melting point. Cooling the aluminum after annealing does not result in the Al(111) peak reappearing. Quenching in the featureless temperature zone did not reveal an Al peak for the detector geometry within the region of K-space probed. After quenching, no Al(111) peak was detected for the detector geometry. Therefore, creating a (111) orientation in aluminum followed by a quench produced aluminum without an Al(111) peak.

[0039] Figure 6A shows that θ2θ XRD measurements performed on the as-deposited aluminum film show only an Al(111) peak with a rocking FWHM (full width at half maximum) of approximately 8 degrees omega (fiber width). Figure 6B shows that θ2θ XRD measurements performed on the annealed aluminum show no detectable Al(111) peak after quenching.

[0040] Figure 7 shows a transmission electron microscope image of Al(111) on Si(100) by annealing it to a temperature just below the eutectic melting point where the (111) peak disappears, followed by rapid cooling. This increases the aluminum grain size so that the single grains are much larger than the Josephson junction size. Furthermore, the aluminum orientation changes from (111) to (110). A grain size of more than 5 microns is achieved for the aluminum, which is epitaxially formed on the silicon substrate. The aluminum film texture changes from (111) to (110) and is highly aligned to the Si(100) substrate. The mismatch between the aluminum and silicon films is accommodated by a few oxide islands at the interface and a low density of stacking faults and threading dislocations. The oxidation for the Josephson junction is therefore performed on a single grain in the bottom, or lower, aluminum layer, eliminating variations from grain boundaries.

[0041] FIG. 8 is a transmission electron microscope image showing the aluminum layer after quenching at a lower resolution; the aluminum grain boundaries are not present in the image, and only small defects are present in the aluminum layer.

[0042] Alloying to Reduce Grain Size: FIG. 3C illustrates a portion of bottom superconducting material layer 210 overlying Josephson junction 260, having a size of area A, after alloying bottom superconducting material layer 210, with the grains of bottom superconducting material layer 210 visible within the region of Josephson junction 260. Comparing FIGS. 3A and 3C, it can be seen that alloying bottom superconducting material layer 210 reduces the grain size such that multiple grains of bottom superconducting material layer 210 overlie the region of Josephson junction 260. Alloying bottom superconducting material layer 210 results in bottom superconducting material layer 210 having an average grain size that is smaller than the width and length of the Josephson junction of the device. In one embodiment, the average grain size of bottom superconducting material layer 210 may be, for example, less than 20 nm. In another embodiment, the average grain size of bottom superconducting material layer 210 may be, for example, less than 10 nm. In one embodiment, the number of grains in the bottom superconducting material layer 210 that contacts and overlies the Josephson junctions may be, for example, 10 or more. In another embodiment, the number of grains in the bottom superconducting material layer 210 that contacts and overlies the Josephson junctions may be, for example, 50 or more. In a further embodiment, the number of grains in the bottom superconducting material layer 210 that contacts and overlies the Josephson junctions may be, for example, 100 or more. The bottom superconducting material layer 210 may have, for example, a reduced grain size or may be amorphous. Alternatively or in addition to the bottom superconducting material layer 210 having a reduced grain size or being amorphous, the top superconducting material layer 230 may have a reduced grain size or be amorphous by alloying the superconducting material.

[0043] It is beneficial that the grain size of the superconducting material is small compared to the junction. When a Josephson junction contains hundreds of grains of superconducting material overlapping the junction, the junction-to-junction material variation is substantially reduced. At the limit of reducing the grain size of the superconducting material, the superconducting material becomes amorphous, eliminating junction-to-junction variation. Because amorphous superconducting materials have no crystal planes, the superconducting material surface is the same regardless of the surface angle of the superconducting material; i.e., the sidewalls and edges of the superconducting material film have the same surface.

[0044] The superconducting material alloy (e.g., aluminum alloy) can include aluminum and at least one alloying element. The alloying element may include Si, Mg, V, Nb, Ta, La, Zr, Hf, Ti, Zn, In, or Sn, or a combination thereof. The concentration of aluminum in the aluminum alloy ranges from about 66% to about 97%. The alloy aluminum, according to some embodiments, can be formed via evaporation or sputtering.

[0045] In one embodiment, Mg can be used as an alloying element to form a light amorphous aluminum layer. In some embodiments, the aluminum alloy may be formed with low concentrations of Si, Mg, V, Nb, Ta, La, Zr, Hf, Ti, Zn, In, or Sn, or a combination thereof. In some embodiments, alloying elements may be added to scavenge oxygen in solution, such as low concentrations of Zr, Hf, or Ti, or a combination thereof.

[0046] The descriptions of various embodiments are presented for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method of forming a Josephson junction device, comprising: forming a layer of superconducting material on a substrate; annealing the layer of superconducting material so that the layer of superconducting material has a single grain across the width and length of the Josephson junction of the Josephson junction device; A method comprising:

2. 2. The method of claim 1, wherein the layer of superconducting material is an aluminum layer.

3. The method of claim 1 or 2, wherein the single grain is epitaxially aligned with the substrate.

4. The method of claim 1 , wherein the substrate comprises at least one of silicon (Si) and sapphire.

5. The method according to any one of claims 1 to 4, wherein the annealing is carried out in a temperature range of 200°C to 570°C.

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