Photoelectric conversion device and electronic device

Abstract

To provide a photoelectric conversion device and an electronic device capable of efficiently transmitting signals while reducing the number of wires.SOLUTION: The photoelectric conversion device includes a pixel unit in which pixels for generating signals by photoelectric conversion are arranged in matrix form, a plurality of determination circuits for determining the amplitude of signals read out from the pixel unit through vertical signal lines that differ from each other, and a shared signal line that is shared by the plurality of determination circuits and transmits the determination results from the plurality of determination circuits to a circuit inside the photoelectric conversion device.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and an electronic device. [Background technology]

[0002] Patent Document 1 shows a solid-state imaging device that includes a sample and hold section having two sample and hold circuits in parallel for one vertical signal line, and an analog-to-digital section that converts pixel signals output from the sample and hold section into digital signals. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 069614 Summary of the Invention [Problem to be solved by the invention]

[0004] The number of pixels in solid-state imaging devices is expected to continue to increase, but this increases the amount of wiring and peripheral circuitry. On the other hand, miniaturizing pixels can lead to a decrease in image quality. Therefore, there is a demand for a configuration that can efficiently transmit signals and data using fewer wiring.

[0005] In view of such demands, an object of the present invention is to provide a photoelectric conversion device and an electronic device that can transmit signals efficiently while reducing the number of wirings. [Means for solving the problem]

[0006] The object of the present invention is to provide a photoelectric conversion device including: a pixel section in which pixels that generate signals by photoelectric conversion are arranged in a matrix; a plurality of determination circuits that determine the amplitude of signals read out from the pixel section through different vertical signal lines; and a shared signal line that is shared by the plurality of determination circuits and transmits the determination results from the plurality of determination circuits to a circuit inside the photoelectric conversion device. a holding circuit connected to each of the vertical signal lines and holding a signal; and an analog-to-digital conversion circuit for analog-to-digital conversion of the signal held in the holding circuit, wherein one analog-to-digital conversion circuit is provided for a plurality of determination circuits;The object is achieved by a photoelectric conversion device characterized by the above. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a photoelectric conversion device and an electronic device that can transmit signals efficiently while reducing the number of wirings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing an example of the arrangement of a photoelectric conversion device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Figure 3] 2 is a circuit diagram showing an example of the configuration of a sample-and-hold unit and a conversion unit of the photoelectric conversion device of FIG. 1. [Figure 4] 2 is a circuit diagram showing an example of the configuration of a determination circuit of the photoelectric conversion device of FIG. 1; [Figure 5] 2 is a timing chart showing an example of the operation of the photoelectric conversion device shown in FIG. 1; [Figure 6] 1. FIG. 4 is a circuit diagram showing another example of the configuration of the determination circuit of the photoelectric conversion device of FIG. [Figure 7] 1. FIG. 4 is a circuit diagram showing yet another example of the configuration of the determination circuit of the photoelectric conversion device of FIG. [Figure 8] FIG. 3 is a block diagram showing another example of the configuration of the photoelectric conversion device according to the first embodiment. [Figure 9] FIG. 9 is a block diagram showing an example of a circuit arrangement in the photoelectric conversion device of FIG. 8. [Figure 10] FIG. 10 is a block diagram showing an example of the arrangement of a photoelectric conversion device according to a second embodiment. [Figure 11] 11 is a timing chart showing an example of the operation of the photoelectric conversion device shown in FIG. 10. [Figure 12] 11 is a timing chart showing an example of the operation of the photoelectric conversion device shown in FIG. 10. [Figure 13] FIG. 11 is a block diagram showing an example of a circuit arrangement in the photoelectric conversion device of FIG. [Figure 14] FIG. 11 is a block diagram showing an example of a circuit arrangement in a modified example of the photoelectric conversion device of FIG. [Figure 15]FIG. 1 is a diagram showing an example of the configuration of a camera incorporating a photoelectric conversion device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] In FIG. 1, the photoelectric conversion device 1000 has a structure in which a first substrate 1 and a second substrate 2 are electrically connected. The first substrate has a pixel section 5. The second substrate has a current source 40, a decision circuit 20, a sample-and-hold section (SH) 50, a conversion section (AD) 60, a selection circuit (MUX) 70, a data processing section 90, and an output section 100. The photoelectric conversion device 1000 may be, for example, a CMOS image sensor. Note that in this specification, when multiple components are collectively referred to, they may be denoted by the reference numeral X0 (X is an integer). For example, a description of vertical signal line 30 applies to all vertical signal lines 31 to 3n.

[0011] In the pixel section 5, pixels 10, each having a photoelectric conversion element such as a photodiode, are arranged in a matrix. In the following description, the left-right direction in FIG. 1 is referred to as the row direction or horizontal direction, and the up-down direction in FIG. 1 is referred to as the column direction or vertical direction. In addition, a group of pixels arranged along the row direction in the pixel section 5 is referred to as a pixel row, and a group of pixels arranged along the column direction is referred to as a pixel column. In addition, with respect to the signal transmission direction, the direction toward the pixels 10 is referred to as the upstream or previous stage, and the direction toward the output section 100 is referred to as the downstream or subsequent stage.

[0012] Each pixel 10 generates a signal having a voltage value corresponding to the amount of light incident thereon during an exposure time. The pixel unit 5 is provided with vertical signal lines 30 corresponding to pixel columns. While FIG. 1 shows an example in which one vertical signal line 30 is provided for each pixel column, multiple vertical signal lines 30 may be provided for each pixel column. The vertical signal line 30 transmits signals from pixels 10 that belong to a pixel row selected by an external vertical scanning circuit among the connected pixels 10 to the decision circuit 20 and the sample-and-hold unit 50.

[0013] The current sources 40 are provided corresponding to the respective vertical signal lines 30. The current sources 40 supply bias currents via the vertical signal lines 30 to the pixels 10 selected to read out signals.

[0014] The determination circuit 20 determines the amplitude of the signal supplied via the vertical signal line 30 and outputs the determination result. The amplitude represents the amount of change from a certain reference potential. The amplitude determination may be, for example, a determination of whether the amplitude is larger or smaller than a reference value. The determination result can be used for subsequent processing in the photoelectric conversion device 1000 or for processing in a circuit external to the photoelectric conversion device 1000. The determination result can be used depending on the circuit and purpose that uses it, and the use of the determination result is not limited.

[0015] In this embodiment, a determination circuit 20 is provided for each vertical signal line 30. Furthermore, multiple determination circuits 20 connected to adjacent vertical signal lines 30 share a signal line for transmitting the determination results to an internal circuit within the photoelectric conversion device 1000. The internal circuit within the photoelectric conversion device 1000 to which the determination results are transmitted is, for example, a circuit provided on the second substrate 2, different from the determination circuit 20. FIG. 1 shows an example configuration in which two determination circuits 20, 21 connected to two vertical signal lines 30, 31 provided in adjacent pixel columns output their determination results to the data processing unit 90 through one shared signal line. However, a configuration in which three or more determination circuits 20 output their determination results through one shared signal line is also possible.

[0016] The sample and hold unit 50 is a holding circuit that samples and holds signals generated by the photoelectric conversion elements of each pixel 10 via the vertical signal lines 30 from the pixel unit 5. The sample and hold unit 50 has a sample and hold circuit that samples and holds a reset signal and a sample and hold circuit that samples and holds a data signal, each connected to the vertical signal lines 30. The reset signal is a signal generated when the charge accumulated in the pixel is reset. The data signal is a signal based on the charge generated by the photoelectric conversion elements during the exposure period.

[0017] The selection circuit 70 selects a plurality of sample and hold units. 50 , and outputs a signal held by one sample-and-hold unit in response to a selection signal MUX to the conversion unit 60. In the example of FIG. 1, sample-and-hold units 50 corresponding to two adjacent pixel columns are connected to one selection circuit 70. Note that three or more sample-and-hold units 50 may be connected to one selection circuit 70.

[0018] The conversion unit 60 is an A / D conversion circuit that performs analog-to-digital (A / D) conversion on the signal output from the selection circuit 70 and outputs it as a digital signal. Specific examples of A / D conversion circuits include, but are not limited to, a slope-type analog-to-digital conversion circuit, a successive approximation type analog-to-digital conversion circuit, and a delta-sigma (ΔΣ) analog-to-digital conversion circuit. In FIG. 1, two sample-and-hold units 50 are connected to one selection circuit 70, which corresponds to a configuration in which one conversion unit 60 is shared by two sample-and-hold units 50. Note that one conversion unit 60 may also be shared by three or more sample-and-hold units 50.

[0019] The data processing unit 90 applies predetermined processing to the digital signal output from the conversion unit 60 and outputs the result. For example, the data processing unit 90 can apply digital gain to the digital signal, or apply correction processing or interpolation processing. The output unit 100 outputs the digital signal processed by the data processing unit 90 to the outside of the photoelectric conversion device 1000.

[0020] 1, the current source 40, the decision circuit 20, and the sample-and-hold unit 50 are each provided for each vertical signal line 30. On the other hand, the selection circuit 70 and the conversion unit 60 are provided for every two vertical signal lines 30. Therefore, m=n / 2 in FIG.

[0021] FIG. 2 is a circuit diagram showing an example configuration of a pixel 10. The pixel 10 includes a photoelectric conversion element 400 such as a photodiode, a transfer transistor 410, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. One of the main electrodes of the photoelectric conversion element 400 is connected to a ground potential 450, and the photoelectric conversion element 400 generates a signal charge (e.g., photoelectrons) in an amount corresponding to the amount of received light. The other of the main electrodes of the photoelectric conversion element 400 is electrically connected to the gate electrode of the amplification transistor 430 via the transfer transistor 410. A node 420 electrically connected to the gate electrode of the amplification transistor 430 functions as a floating diffusion (FD). The floating diffusion is a charge-voltage converter that converts the charge generated by the photoelectric conversion element 400 into a voltage.

[0022] A transfer signal TX is supplied to the gate electrode of the transfer transistor 410. When the transfer transistor 410 becomes conductive in response to the transfer signal TX, the charge generated in the photoelectric conversion element 400 and stored in the photoelectric conversion element 400 is transferred to a node 420, which is a floating diffusion. The potential of the node 420 in the state in which the charge has been transferred corresponds to the data signal described above.

[0023] The reset transistor 455 is connected between a power supply potential 460 and a node 420. In this specification, when a transistor is connected between A and B, it means that one of the main electrodes of the transistor is connected to A and the other is connected to B, and the gate electrode of the transistor is not connected to A or B.

[0024] A reset signal RES is supplied to the gate electrode of the reset transistor 455. When the reset transistor 455 becomes conductive in response to the reset signal RES, the potential of the node 420 (floating diffusion) is reset to the power supply potential 460. The potential of the node 420 when the reset transistor 455 is in the conductive state corresponds to the above-mentioned reset signal.

[0025] The amplifier transistor 430 has a gate electrode connected to the node 420, one main electrode connected to a power supply potential 460, and the other main electrode connected to the selection transistor 440. The amplifier transistor 430 is an input section of a source follower that outputs a signal generated by photoelectric conversion of the photoelectric conversion element 400 in the pixel 10 to the vertical signal line 30. Therefore, the other main electrode of the amplifier transistor 430 is electrically connected to the vertical signal line 30 via the selection transistor 440. The amplifier transistor 430 and the current source 40 connected to the vertical signal line 30 configure a source follower that converts the voltage of the node 420 into the potential of the vertical signal line 30.

[0026] The selection transistor 440 is connected between the amplification transistor 430 and the vertical signal line 30. A selection signal SEL is supplied to the gate electrode of the selection transistor 440. When the selection transistor 440 becomes conductive in response to the selection signal SEL, the pixel 10 is placed in a selected state. Therefore, a signal is read out to the vertical signal line 30 from the pixel 10 in the selected state.

[0027] The circuit configuration of the pixel 10 is not limited to the configuration shown in FIG. 2 . For example, the selection transistor 440 may be connected between the power supply potential 460 and the amplification transistor 430. Although the configuration shown in FIG. 2 illustrates a four-transistor (4Tr.) configuration of the pixel 10 including the transfer transistor 410, the reset transistor 455, the amplification transistor 430, and the selection transistor 440, the configuration is not limited to this. For example, the selection transistor 440 may be omitted, and a three-transistor configuration in which the amplification transistor 430 also functions as the selection transistor may be employed. Furthermore, a five-transistor or more configuration with an increased number of transistors may be employed depending on the specifications required for the photoelectric conversion device 1000. The pixel 10 may sequentially output a reset signal generated when the reset transistor 455 resets the potential of the node 420 and resets the photoelectric conversion element 400, and a data signal representing the signal level when photoelectric conversion is performed by the photoelectric conversion element 400.

[0028] FIG. 3 is a diagram showing a configuration example of the photoelectric conversion device 1000, focusing on the circuits included in the second substrate 2. Here, the circuitry connected to the vertical signal lines 31 and 32 is representatively shown. A sample-and-hold circuit 210 that samples and holds a reset signal and a sample-and-hold circuit 211 that samples and holds a data signal are connected to the vertical signal line 31. The sample-and-hold circuits 210 and 211 form a sample-and-hold unit 51. A sample-and-hold circuit 212 that samples and holds a reset signal and a sample-and-hold circuit 213 that samples and holds a data signal are connected to the vertical signal line 32. The sample-and-hold circuits 212 and 213 form a sample-and-hold unit 52. The output of the sample-and-hold unit 51 is output from the sample-and-hold circuit 211, and the output of the sample-and-hold unit 52 is output from the sample-and-hold circuit 213 to the selection circuit 70.

[0029] The determination circuit 20 and the sample-and-hold unit 50 are provided for each vertical signal line 30. Therefore, if the number of vertical signal lines 30 increases due to an increase in the number of pixels, the space required to arrange these circuits also increases. In this embodiment, these circuits are arranged on a second substrate 2 that is different from the first substrate 1 on which the pixel unit 5 is provided, and by stacking the first substrate 1 and the second substrate 2, it is possible to reduce restrictions on circuit arrangement and reduce the chip area.

[0030] The determination circuits 21 and 22 use a reference value REF to determine the amplitude of the signals read out from the pixels 11 and 12 to the vertical signal lines 31 and 32. The reference value REF is supplied to the determination circuits 21 and 22 from, for example, a reference value circuit 202 included in the photoelectric conversion device 1000 or an external circuit. By providing multiple types of reference value REF, multiple types of determinations for different purposes can be performed.

[0031] Here, as an example, the result of the amplitude determination is used for automatic gain control (AGC) of the signal. Therefore, the result of the determination is used to control the analog gain (resistance values of the variable resistors 241 and 242) and the digital gain (magnification or coefficient applied by the data processing unit 90). However, the use of the amplitude determination result is not limited to this, and the output destination of the amplitude determination result can also be changed depending on the use.

[0032] The decision circuit 21 outputs a decision result in accordance with a control signal MTX1, and the decision circuit 22 outputs a decision result in accordance with a control signal MTX2. The control signals MTX1 and MTX2 can be supplied from a circuit within the photoelectric conversion device 1000 (for example, a timing generator) or from a circuit external to the photoelectric conversion device 1000. In the configuration shown in FIG. 3, the outputs of the decision circuits 21 and 22 are directly connected to a shared signal line. Therefore, the control signals MTX1 and MTX2 are supplied so that the decision circuits 21 and 22 output decision results in different periods.

[0033] In addition, when a switching circuit (switch) is used to switch the decision circuit connected to the supply signal line, a control signal is supplied to control the switching circuit so that decision circuit 21 is connected to the shared signal line during the first period and decision circuit 22 is connected to the shared signal line during the second period. Note that, since the decision result of decision circuit 21 is a binary signal having a high level or a low level, a switching circuit with a simple configuration can be used. Specifically, the circuit size can be smaller than that of selection circuit 70, which selectively supplies the output of sample-and-hold unit 50, which is the target of analog-to-digital conversion, to conversion unit 60.

[0034] The determination results by the determination circuits 21 and 22 are supplied to a data processing unit 90, which is an example of a circuit inside the photoelectric conversion device 1000, via a shared signal line. The circuit that supplies the determination results may vary depending on the application of the determination results. In this embodiment, multiple determination circuits 20 output their determination results via the same shared signal line. Therefore, the number of signal lines can be significantly reduced compared to a configuration in which the determination results are output via individual signal lines.

[0035] 3, in which the determination result is used in an internal circuit downstream of the analog-to-digital conversion circuit 390, such as the data processing unit 90, if a shared signal line is not used, many wires would extend through the analog-to-digital conversion circuit 390 to the data processing unit 90. In this case, the wires passing through the analog-to-digital conversion circuit 390 can become a noise source, so reducing the amount of wiring is also advantageous from the perspective of analog-to-digital conversion accuracy. Therefore, the determination circuit 20 and the shared signal line are connected near the determination circuit 20, at least at a position closer to the pixel 10 than the selection circuit 70. This applies whether a switching circuit is provided or not.

[0036] The circuit configuration of the sample-and-hold unit 51 will be described. The sample-and-hold circuit 210 for the reset signal includes a capacitive element 120 and an inverting amplifier 220. The switch 110 switches between a connected state and a disconnected state between the vertical signal line 30 and the capacitive element 120 in accordance with a control signal Smp_n. The inverting amplifier 220 can be configured by combining a source-grounded circuit and a source-follower circuit. The inverting amplifier 220 includes transistors 130, 140, 150, and 160, switches 170, 180, and 190, and a current source 200. The switch 170 is connected between the inverting input terminal and the output terminal of the inverting amplifier 220 and is controlled by a control signal Smpa_n. A reset signal is output from the inverting amplifier 220 in accordance with a control signal Hold_n.

[0037] The sample-and-hold circuit 211 for the data signal may have a configuration similar to that of the sample-and-hold circuit 210 for the reset signal. Specifically, the sample-and-hold circuit 211 includes a capacitive element 121 and an inverting amplifier 221. The switch 111 switches between a connected state and a disconnected state between the vertical signal line 30 and the capacitive element 121 in accordance with a control signal Smp_s. The inverting amplifier 221 may be configured by combining a common-source circuit and a source follower circuit. The inverting amplifier 221 includes transistors 131, 141, 151, and 161, switches 171, 181, and 191, and a current source 201. The switch 171 is connected between the inverting input terminal and the output terminal of the inverting amplifier 221, and is connected to the inverting input terminal of the inverting amplifier 221 in accordance with a control signal Smp_s. s The data signal is output from the inverting amplifier 221 in accordance with the control signal Hold_s.

[0038] A variable resistance element 241 is provided between the output terminal of the sample and hold circuit 210 for the reset signal and the output terminal of the sample and hold circuit 211 for the data signal. The resistance value of the variable resistance element 241 is controlled according to the result of the determination by the determination circuit 21. For example, when the amplitude of the signal is small (smaller than the reference value REF1), the determination circuit 21 reduces the resistance value of the variable resistance element 241 more than when the amplitude is not small. This increases the gain for signals with small amplitude, making it possible to reduce dark noise in the captured image.

[0039] The resistance value of the variable resistance element 241 is called the analog gain because it is the gain applied to the analog signal. When the analog gain is changed, a gain that offsets the change is applied in the signal processing unit 90. The gain applied by the signal processing unit 90 is called the digital gain because it targets the digital signal after A / D conversion. The values of the analog gain and the digital gain are determined so that their product is 1. Therefore, when the analog gain is made greater than 1, the digital gain becomes less than 1.

[0040] The current I flowing through the variable resistance element 241 is expressed as follows, where Vn is the potential of the output terminal of the sample and hold circuit 210, i.e., the potential of the reset signal, Vs is the potential of the output terminal of the sample and hold circuit 211, i.e., the potential of the data signal, and R is the resistance value of the variable resistance element 240: I=(Vn-Vs) / R is.

[0041] The current I is input to the analog-to-digital conversion circuit 390 via the selection circuit 71. The current I flowing through the variable resistance element 241 is proportional to the difference between the potential Vn of the pixel's reset signal and the potential Vs of the data signal. Therefore, the current I after correlated double sampling (CDS) is input to the analog-to-digital conversion circuit 390 of the conversion unit 60. In addition, by reducing the resistance value R of the variable resistance element 241 below the reference value, a positive gain can be applied to the data signal (Vn-Vs) after CDS.

[0042] Unlike the circuit configuration described here, a configuration may be adopted in which the outputs of the sample-and-hold circuits 210 and 211 are input, and a CDS circuit that obtains the difference between the data signal and the reset signal is used to obtain the data signal after CDS.

[0043] The sample and hold section 52 (the sample and hold circuit 212 for the reset signal and the sample and hold circuit 213 for the data signal) connected to the vertical signal line 31 has a similar configuration and operates in a similar manner.

[0044] The selection circuit 70 is connected to the plurality of sample and hold units 50, and selectively supplies the output of one sample and hold unit 50 in response to a control signal to the analog-to-digital conversion circuit 390 included in the conversion unit 60. In Fig. 3, the selection circuit 71 is connected to the two sample and hold units 51 and 52, and supplies one of the outputs of the sample and hold circuits 211 and 213 for data signals to the analog-to-digital conversion circuit 390 in response to control signals MUX1 and MUX2.

[0045] By providing the selection circuit 70, multiple sample and hold units 50 can share the analog-to-digital conversion circuit 390. Therefore, compared to when an analog-to-digital conversion circuit 390 is provided for each sample and hold unit 50, the scale of the circuitry implemented on the second substrate 2 can be significantly reduced.

[0046] 3 shows a delta-sigma (ΔΣ) analog-to-digital conversion circuit 390 as an example of the analog-to-digital conversion circuit 390 included in the conversion unit 60. The ΔΣ analog-to-digital conversion circuit 390 includes a first integrator, a second integrator, a quantizer 370, and a decimation filter 380. In the analog-to-digital conversion circuit 390, the first integrator is configured with an integral capacitor 320. The second integrator is configured with a Gm cell 330 that converts voltage into current and an integral capacitor 360.

[0047] A digital-to-analog converter 305 including a current source 300 and a switch 310 is connected to the input node of the first integrator. The digital-to-analog converter 305 controls the current to the first integrator in accordance with the digital signal transmitted through the second integrator and the quantizer 370. A digital-to-analog converter 345 including a current source 340 and a switch 350 is connected to the input node of the second integrator. The digital-to-analog converter 345 controls the current to the second integrator in accordance with the result of quantizing the output of the second integrator by the quantizer 370.

[0048] In the ΔΣ analog-to-digital conversion circuit 390, the previous quantized value in the quantizer 370 is fed back to the second integrator and the first integrator via the digital-to-analog converters 305 and 345. In this way, second-order noise shaping characteristics can be obtained by passing the previous quantized value twice through the integrators while feeding it back to the digital-to-analog converters 304 and 345. Furthermore, high-frequency noise can be removed by the decimation filter 380 arranged downstream of the quantizer 370, thereby obtaining a highly accurate analog-to-digital conversion output.

[0049] The digital signal output from the decimation filter 380 is input to the data processing unit 90. The data processing unit 90 applies predetermined processing, including application of digital gain, to the digital signal and outputs the result to the output unit 100. The data processing unit 90 controls the magnitude of the digital gain to be applied to the digital signal based on the result of the first determination notified by the determination circuit 20. The application of the digital gain may be multiplication of the value of the digital signal by a gain coefficient.

[0050] 4 is a circuit diagram showing an example configuration of the decision circuit 20. The decision circuit 20 has a comparator 600 as a decider, a latch 610 as storage means for storing the output of the comparator 600, i.e., the decision result, and a switch 620 provided between the latch 610 and an output line. The comparator 600 can be configured as a differential amplifier in which a reference value is input to an inverting input and a data signal is input to a non-inverting input via the vertical signal line 30. The comparator 600 outputs a high level or a low level depending on the magnitude relationship between the potential (signal amplitude) of the vertical signal line 30 and the reference value.

[0051] A latch 610 that stores the determination result outputs the result to a shared signal line when a switch 620 is turned on (conductive) by a control signal MTX. Note that in a configuration in which the determination circuit 20 does not have a switch and the determination result is output to a shared signal line using a switching circuit connected to a plurality of determination circuits 20, the control signal MTX controls the switching circuit to switch the selection circuit connected to the shared signal line.

[0052] The reference value REF used by the determination circuit 20 can be supplied from a reference value circuit 21 provided inside the photoelectric conversion device 1000 or from outside the photoelectric conversion device 1000.

[0053] FIG. 5 is a diagram showing an example of the potential change of the vertical signal line 30 according to the amount of incident light on the selected pixel, the operation timing of each switch of the sample-and-hold circuits 210 and 211, and the control signals MTX and MUX.

[0054] Here, examples of potential changes of the vertical signal line 30 are shown for three cases: when the amount of incident light on the pixel 10 is low (low luminance), when it is high (high luminance), and when it is extremely high (ultra-high luminance). Note that ultra-high luminance corresponds to a condition where charges generated in the pixel's photoelectric conversion element leak into the floating diffusion (also known as blooming). Low luminance and high luminance are typical examples of low and high incident light amounts within a range where blooming does not occur. In this embodiment, the pixel 10 accumulates electrons through photoelectric conversion. Therefore, the potential of the vertical signal line 30 decreases from the reference potential as the amount of incident light on the pixel 10 increases.

[0055] Control signals Smp_n, Smpa_n, Hlod_n, smp_s, smpa_s, and hlod_s in Fig. 5 are control signals for switches with the same names in Fig. 3. Here, while the control signal is at a high level, the corresponding switch is in an on state (conductive state), and while the control signal is at a low level, the corresponding switch is in an off state (non-conductive state).

[0056] First, at time t1, the control signals Smp_n and Smpa_n go to high level, and the switches 110 and 170 turn on in the reset signal sample-and-hold circuit 210. Next, at time t2 when the control signal Smpa_n transitions from high level to low level, the potential Vn of the reset signal is sampled and stored in the capacitive element 120.

[0057] Next, at time t3, the control signal Smp_n transitions from high to low. Furthermore, the control signal Hold_n goes high, turning on the switches 180 and 190, causing the capacitance element 120 in the sample-and-hold circuit 210 to hold the potential Vn of the reset signal. The charge sampled and held in the capacitance element 120 is output from the sample-and-hold circuit 210 for the reset signal.

[0058] At time t4, a signal generated by the photoelectric conversion element 400 from the pixel 10 is output to the vertical signal line 30. Next, at time t5, the control signals Smp_s and Smpa_s go high, and the switches 111 and 171 in the data signal sample-and-hold circuit 211 are turned on. Next, at time t6 when the control signal Smpa_s transitions from high to low, the potential Vs of the data signal is sampled and stored in the capacitive element 121. The determination circuit 20 performs amplitude determination during the period from time t5 to t6.

[0059] Next, at time t7, the control signal Smpa_s transitions from high to low. At time t8, the control signal Hold_n transitions to high, turning on the switches 181 and 191, causing the capacitive element 121 to hold the potential Vs of the data signal in the sample-and-hold circuit 211. The charge sampled and held in the capacitive element 121 is output from the sample-and-hold circuit 211 for data signals.

[0060] As described above, a current corresponding to the difference between the potential Vn of the reset signal at the output terminal of the sample and hold circuit 210 and the potential Vs of the data signal at the output terminal of the sample and hold circuit 211 is input to the analog-to-digital conversion circuit 390.

[0061] At time t8, the control signals MUX1 and MTX1 transition from low to high. The control signals MUX2 and MTX2 remain low. As a result, the output of the sample-and-hold circuit 51 is input to the conversion circuit 60 via the selection circuit 70, and the decision result of the decision circuit 21 is input to the data processing unit 90 via the shared signal line.

[0062] Next, at time t9, the control signals MUX1 and MTX1 go low, and the control signals MUX2 and MTX2 transition from low to high, causing the output of the sample-and-hold circuit 52 to be input to the conversion circuit 60 via the selection circuit 70, and the determination result of the determination circuit 22 to be input to the data processing unit 90 via the shared signal line.

[0063] At time t10, the control signals Hold_n, Hold_s, MUX2, and MTX2 go low, and sampling of the reset signal and data signal of the next pixel 10 begins.

[0064] Next, we will explain the relationship between the amount of incident light on a pixel and the amplitude determination result in the determination circuit 20. Here, we assume that a reference value REF is supplied for the purpose of AGC control. Therefore, the reference value REF has a value for detecting a signal with a brightness level that falls within a predetermined range in which the analog gain is increased.

[0065] When the amount of light incident on a pixel is small and a signal corresponding to low brightness is output, the potential drop on the vertical signal line 30 at time t4 is small and does not fall below the reference value REF. As a result, the comparator 600 of the decision circuit 20 outputs a high level as a decision result. This means that the read data signal is within a brightness range that increases the analog gain.

[0066] When the amount of incident light is large and a signal corresponding to high brightness is output, the potential drop of the vertical signal line 30 at time t4 becomes large and falls below the reference value REF. As a result, the comparator 600 of the decision circuit 20 outputs a low level as a decision result. This means that the read data signal is not a signal within the brightness range that increases the analog gain.

[0067] The result of the determination is held in the latch 610 and can be used for at least one of subsequent processing within the photoelectric conversion device 1000 and processing outside the photoelectric conversion device 1000. Here, the result of the determination is used to adjust the resistance value (analog gain) of the variable resistance element 240 by the determination circuit 20 and to adjust the digital gain applied by the data processing unit 90. For example, for a low-luminance data signal, the analog gain can be set to 8 times (×8) the reference value (×1), and the digital gain can be set to 1 / 8 (×1 / 8) of the reference value (×1). As mentioned above, the purpose of the determination is not limited to the AGC control exemplified here. Two or more types of determinations may also be performed. For example, the low-luminance range may be divided into multiple sections, and the number of types of determinations may be increased to perform more detailed AGC control.

[0068] By having a judgment circuit that judges the amplitude of the signal read out from the pixel to the vertical signal line, the photoelectric conversion device of this embodiment makes it possible to perform appropriate processing based on the judgment result, either inside or outside the photoelectric conversion device.

[0069] (Variation 1) When the comparator 600 used in the decision circuit 20 is realized by a differential amplifier, input offset can cause a decrease in accuracy. Therefore, by using a comparator 600 configured to correct the input offset, the decision accuracy can be improved. Figure 6 is a diagram showing an example of the configuration of a comparator capable of correcting input offset, which can be used as the comparator 600 in the decision circuit 20.

[0070] 6(a), a comparator 600 has two input capacitance elements 500 and 510 and feedback switches 520 and 530. One end of the feedback switch 520 is connected to the inverting input terminal and the other end is connected to the non-inverting output terminal. Also, one end of the feedback switch 530 is connected to the non-inverting input terminal and the other end is connected to the inverting output terminal.

[0071] The output of the comparator 600 is a non-inverting output terminal, which is connected to the input terminal of the latch 610. The inverting input terminal is connected to a capacitive element 500, and the non-inverting input terminal is connected to a capacitive element 510. A reference value is supplied to the inverting input terminal via the capacitive element 500, and the vertical signal line 30 is connected to the non-inverting input terminal via the capacitive element 500.

[0072] With a reset signal supplied to the non-inverting input and a reference value REF supplied to the inverting input, when switches 520 and 530 are turned on (conducting) and then turned off, the capacitive elements 500 and 510 have the same potential difference, respectively. This allows the input offset voltage of comparator 600 to be canceled. The determination result held in latch 610 is output when switch 620 is in the conducting state.

[0073] 6(b) is the same as FIG. 6(a) except that the differential amplifier constituting the comparator 600 is single-ended. With this configuration as well, the input offset voltage of the comparator 600 can be canceled by turning on (conducting) the switches 520 and 530 and then turning them off while a reset signal is supplied to the non-inverting input and a reference value REF is supplied to the inverting input.

[0074] The comparator 600 may have any known configuration as a so-called auto-zero differential amplifier. The configuration shown in FIG. 6 is merely an example.

[0075] (Variation 2) FIG. 7 shows a configuration in which the decision circuit 20 is driven by a current source 40 of a vertical signal line 30, thereby realizing a reduction in power consumption compared to when the decision circuit 20 is driven by a separate power supply.

[0076] The comparator has an N-type MOS transistor 540, P-type MOS transistors 550 and 560, and a reset switch 570. The vertical signal line 30 is connected to the source of the transistor 540, and a reference value REF is input to the gate. The transistor 550 is connected to the power supply voltage and the transistor 540, and a bias voltage is applied to the gate. The transistor 560 is connected to the power supply voltage and the latch 610, and the voltages of the transistors 540 and 550 are connected to the gate. 0 A voltage is applied to the connection point of transistor 560. The output of transistor 560 is input to latch 610. Reset switch 570 is a switch that resets latch 610 when turned on. The determination result held in latch 610 is output when switch 620 is in a conductive state.

[0077] When the potential of the vertical signal line 30 drops below (reference voltage REF-threshold voltage Vth of transistor 540), the transistor 540 turns on. When the transistor 540 turns on, a current flows toward the current source 40. This causes the gate voltage of the transistor 560 to drop, turning the transistor 560 on. This causes the latch 610 to hold a high level. When making multiple determinations, the reset switch 570 is turned on to reset the previous determination result before making a new determination.

[0078] According to this modification, the determination circuit 20 is driven by the current source 40 of the vertical signal line 30, so that power consumption can be reduced.

[0079] (Variation 3) 8 is a diagram showing an example of the configuration of a photoelectric conversion device 1000 in which multiple vertical signal lines are provided for one pixel column. The pixel section provided on the first substrate 1 is omitted, and only an example of the circuit configuration of the second substrate 2 is shown. Furthermore, the same reference numerals as in FIG. 1 are used for the components already described.

[0080] Here, two vertical signal lines 30A and 30B are provided for one pixel column, and the vertical signal lines 30A and 30B are each connected to a plurality of different pixel rows. As an example, the vertical signal line 30A is connected to odd-numbered pixel rows, and the vertical signal line 30B is connected to even-numbered pixel rows. However, there are no limitations on the number of vertical signal lines per pixel column or the connection pattern to the pixel rows.

[0081] In this configuration, the decision circuits provided for the respective vertical signal lines in the same pixel column can output their decision results through a shared signal line. In the example shown in Fig. 8, in the leftmost pixel column, the decision results of the decision circuit 21A connected to the vertical signal line 31A and the decision circuit 21B connected to the vertical signal line 31B are transmitted to the data processing unit 90 through the shared signal line. A control signal MTX1 is input to the decision circuit 21A, and a control signal MTX2 is input to the decision circuit 21B, and the decision circuits are controlled so as to output their decision results to the shared signal line at different periods.

[0082] A conversion unit 60 is provided for each pixel column and is shared by the sample-and-hold units 50A and 50B connected to the vertical signal lines of the same pixel column. Accordingly, a selection circuit 70 is also provided for each pixel column, and selectively outputs the signals held in the sample-and-hold units 50A and 50B to the conversion unit 60 in response to control signals MUX1 and MUX2.

[0083] 1 in that multiple decision circuits that output decision results through a shared signal line and multiple sample-and-hold units that share a conversion unit are each provided in the same pixel column, and that a selection circuit 70 and a conversion unit 60 are provided for each pixel column. However, the control signals supplied to the switches of the decision circuit 20, the selection circuit 70, and the sample-and-hold unit 50 may be the same as those shown in the time chart of FIG.

[0084] In this modification, it is also possible to reduce the number of signal lines for transmitting the determination results from the multiple determination circuits, and by sharing a conversion unit among multiple sample-and-hold units, it is possible to reduce the number of conversion units.

[0085] (Variation 4) Figure 9 shows another example of circuit layout for the leftmost pixel column in Figure 8. Specifically, when multiple circuits of the same type are provided for the same pixel column, the circuits of the same type are arranged adjacent to each other. By using this circuit layout, it is possible to suppress variations in characteristics between circuits due to the manufacturing process.

[0086] 9 shows an example in which multiple similar circuits provided in the same pixel column are a current source, a decision circuit, and a sample-and-hold unit, and are arranged in this order from closest to the pixel unit: current sources 41 and 42, decision circuits 21 and 22, and sample-and-hold units 51 and 52. Note that while circuits such as conversion unit 60 and selection circuit 70 that are provided one for each pixel column are not shown in FIG. 9, they are connected downstream of sample-and-hold units 51 and 52.

[0087] According to this modification, in addition to the effect of the third modification, the conversion performance of the conversion unit can be improved.

[0088] As described above, the photoelectric conversion device according to this embodiment includes a determination circuit that determines the amplitude of a signal read from a pixel or the amplitude of a signal based on the read signal. The determination circuit performs amplitude determinations of various types or at various timings, allowing appropriate processing to be performed inside or outside the photoelectric conversion device based on the determination results. Using the determination results, for example, it is possible to detect dark spots and adjust the gain applied to the data signal, thereby improving image quality.

[0089] ●(Second embodiment) Next, a second embodiment of the present invention will be described. Fig. 10 is a diagram showing an example of the configuration of a photoelectric conversion device 2000 according to the second embodiment. The same components as those in the first embodiment are assigned the same reference numerals as in Fig. 1. The photoelectric conversion device 2000 of this embodiment has a conversion unit 720 (721 to 72n) which is a slope-type analog-to-digital conversion circuit for each pixel column or vertical signal line 30 (31 to 3n). The photoelectric conversion device 2000 also has a ramp generator 700.

[0090] A slope-type analog-to-digital conversion circuit compares the signal to be converted with a ramp signal whose potential changes over time, and calculates the converted digital value based on, for example, the time elapsed until the relative magnitudes of the two signals change. A circuit that uses one type of ramp signal is called a single-slope type, while one that can use multiple types of ramp signals is called a multi-slope type. Here, we will use a dual-slope analog-to-digital conversion circuit, which uses two types of ramp signals, out of the multi-slope types.

[0091] Specifically, the ramp generator 700 generates a first ramp signal rampL and a second ramp signal ramppH having different amounts of potential change per unit time, and supplies them to each of the conversion units 721 to 72n via a first wiring 710 and a second wiring 711. Here, the second ramp signal ramppH has a larger amount of potential change per unit time than the first ramp signal rampL.

[0092] In a multi-slope analog-to-digital conversion circuit, a ramp signal suitable for analog-to-digital conversion of a data signal can be selected according to the result of amplitude determination of the data signal. In such a multi-slope analog-to-digital conversion circuit, the wiring for transmitting the amplitude determination result to a circuit inside the photoelectric conversion device 2000 can be shared by multiple conversion units, thereby reducing the number of signal lines. Here, it is assumed that the internal circuit that transmits the result of amplitude determination is the horizontal scanning circuit 890.

[0093] Since the conversion units 721 to 72n each have the same configuration, the following describes the configuration of the conversion unit 721 as a representative. The conversion unit 721 includes a comparator 761, a selection unit 731, a column control unit 771, and an inverter 921.

[0094] The selection unit 731 has a switch 741 and a switch 751. The column control unit 771 has a memory 781, a NAND gate 791, a NAND gate 801, and a switch 901. A control signal s1, a control signal s2, and a control signal s3 are supplied to the memory 781, the NAND gate 791, and the NAND gate 801 of the column control unit 771, respectively, from, for example, a timing generator (not shown).

[0095] Furthermore, the output of the column control unit 771 is supplied to the memory unit 811, the selection unit 731, and the horizontal scanning circuit 890. A control signal MTX1 is supplied to the switch 901 from the timing generator. The switch 901 is turned on (conductive) when the control signal MTX1 is at a high level. The control signal MTX1 is supplied to the conversion units 720 of odd-numbered pixel columns, and the control signal MTX2 is supplied to the conversion units 720 of even-numbered pixel columns. When the switch 901 is turned on, the amplitude determination result held by the column control unit 771 is output to the horizontal scanning circuit 890. When the switch 902 is turned on, the amplitude determination result held by the column control unit 772 is output to the horizontal scanning circuit 890.

[0096] The switches 901 and 902 are connected to a common signal line. Therefore, the signal lines for transmitting the amplitude determination results held by the column control units 771 and 772 include a shared signal line. By supplying control signals MTX1 and MTX2 so that the switches 901 and 902 are turned on exclusively, the amplitude determination results of the multiple conversion units 720 can be output to the horizontal scanning circuit 890 using a single signal line. In this way, the number of signal lines for transmitting the amplitude determination results can also be reduced in this embodiment.

[0097] The memory section 811 includes a pulse generator 820 , a selector 831 , a memory 841 , a memory 851 , a memory 861 , and a selector 871 .

[0098] The photoelectric conversion device 2000 further includes a counter 880 that outputs a count signal cnt obtained by counting the clock to the conversion units 721 to 72n, and a horizontal scanning circuit 890 that reads out digital signals from each of the conversion units 721 to 72n.

[0099] 11 and 12, the operation of the conversion unit 720 will be described. The conversion unit 720 of this embodiment selects either the first ramp signal rampL or the second ramp signal ramppH for analog-to-digital conversion based on the magnitude of the signal output by the pixel 10 in response to incident light.

[0100] First, the operation of analog-to-digital conversion of a signal output from the pixel 10 to which low-luminance light is incident will be described with reference to Fig. 11. In this embodiment, too, the photoelectric conversion element of the pixel 10 accumulates electrons through photoelectric conversion.

[0101] At time t0, the control signal s2 is at a low level, and the control signal s3 is at a high level. Therefore, the output of the column control unit 771 (NAND gate 801) is at a low level. As a result, in the selection unit 731, the switch 741 is turned on and the switch 751 is turned off. As a result, the first ramp signal rampL is input to the non-inverting input of the comparator 761 via the first wiring 710.

[0102] The potential of the vertical signal line 30 corresponds to the potential of the reset signal of the pixel 10. Therefore, the voltage of the non-inverting input of the comparator 761 is higher than the voltage of the inverting input, and the comparator 761 outputs a high level.

[0103] During the period from time t0 to time t2, the ramp generator 700 decreases the potential of the first ramp signal rampL by a first change amount. Hereinafter, the reset potential of the potentials of the first ramp signal rampL and the second ramp signal ramppH will be referred to as the ramp reset potential. Furthermore, the timing at which the potentials of the first ramp signal rampL and the second ramp signal ramppH start to change will be referred to as the ramp start timing. Furthermore, the counter 880 starts counting up the count signal cnt in accordance with the ramp start timing. Hereinafter, it is assumed that the counter 880 starts counting up the count signal cnt in accordance with the ramp start timing of the first ramp signal rampL. Hereinafter, the timing at which the counter 880 starts counting up will be referred to as the count start timing. Ideally, the ramp start timing and the count start timing coincide with each other.

[0104] At time t1, the potential of the first ramp signal rampL falls below the potential of the vertical signal line 31. This causes the output of the comparator 761 to change from high to low. In response to the change in the output of the comparator 761, the pulse generator 821 generates a pulse (one-shot pulse) that remains high for only a predetermined period. This predetermined period is typically several clock cycles long. The selector 831 supplies this pulse to the memory 841. As a result of this operation, the count signal cnt is written to the memory 841 at time t1. This is the digital signal obtained as the result of analog-to-digital conversion using the first ramp signal rampL relative to the reset level.

[0105] At time t2, the ramp generator 700 resets the potential of the first ramp signal rampL to the ramp reset potential, causing the output of the comparator 761 to return from low to high, and the counter 880 resets the count signal cnt to the value at the count start timing.

[0106] After that, at time t3, a timing generator (not shown) sets the control signal s3 to low level. As a result, the output of the column control unit 771 becomes high level, the switch 741 of the selection unit 731 turns off, and the switch 751 turns on. Therefore, the second ramp signal rampH is input to the non-inverting input node of the comparator 761 via the second wiring 711.

[0107] During the period from time t3 to time t5, the ramp generator 700 decreases the potential of the second ramp signal ramppH by a second amount of change that is greater than the first amount of change. In addition, in synchronization with the start of the change in the potential of the second ramp signal ramppH, the counter 880 counts up the count signal cnt.

[0108] At time t4, the potential of the second ramp signal ramp pH falls below the potential of the vertical signal line 30. This causes the output of the comparator 761 to change from high to low. The pulse generator 820 generates a pulse (one-shot pulse) that remains high for a predetermined period in response to the change in the output of the comparator 761. The selector 831 supplies this pulse to the memory 851. As a result of this operation, the count signal cnt is written to the memory 851 at time t4. This is the digital signal obtained as the result of AD conversion using the second ramp signal ramp pH relative to the reset level.

[0109] At time t5, the second ramp signal rampL and the count signal cnt are reset. The output of the comparator 761 returns from low to high. Furthermore, as the control signal s3 returns to high, the output of the column control unit 771 goes low, the switch 741 turns on, and the switch 751 turns off. As a result, the first ramp signal rampL is again input to the non-inverting input of the comparator 761.

[0110] Between time t5 and time t6, the pixel 10 starts outputting a data signal. As a result, the potential of the vertical signal line 31 decreases in accordance with the amount of light incident on the pixel 10. Although not shown, a CDS (Correlated Double Sampling) circuit may be provided upstream of the comparator 761. In this case, a signal obtained by subtracting a noise signal of the pixel 10 from the data signal is input to the comparator 761. Furthermore, an amplifier may be provided upstream of the comparator 761. In this case, a signal obtained by amplifying the data signal generated by the pixel 10 is input to the comparator 761.

[0111] At time t6, the ramp generator 700 reduces the potential of the first ramp signal rampL to the level of the decision threshold. The decision threshold corresponds to the reference value REF in the first embodiment. The comparator 761 compares the decision threshold with the data signal. As described above, in this embodiment, the comparator 761 included in the slope-type analog-to-digital conversion circuit is used as the decision circuit 20 in the first embodiment. Therefore, there is no need to provide a separate decision circuit 20, which is advantageous in terms of mounting area, etc.

[0112] As described above, FIG. 11 illustrates the analog-to-digital conversion of a signal output from a pixel 10 receiving low-luminance light. Therefore, the potential of the vertical signal line 31 is higher than that of the first ramp signal rampL. In other words, the amplitude of the vertical signal line 31 is smaller than the amplitude of the determination threshold of the first ramp signal rampL. Therefore, the output of the comparator 761 becomes low. At this time, the control signal s1 is set to high from time t6 to t7, and the low level, which is the determination result, is written to the memory 781.

[0113] At time t8, the ramp generator 700 returns the first ramp signal rampL to the potential at the start of the ramp, causing the output of the comparator 761 to return to a high level.

[0114] Then, at time t9, a timing generator (not shown) sets the control signal s2 to high level, whereby the determination result written in the memory 781 is reflected in the connection state of the switch in the selection unit 731.

[0115] Now, because a low level is written in the memory 781, the switch 741 is turned on and the switch 751 is turned off in the selection unit 731. Therefore, the non-inverting input node of the comparator 761 is connected to the first wiring 710, and the first ramp signal rampL is input thereto.

[0116] After time t9, the ramp generator 700 decreases the potential of the first ramp signal rampL by a first change amount. The counter 880 also counts up the count signal cnt. At time t10, the output of the comparator 761 changes to a low level. This causes the result of AD conversion of the optical signal-based signal using the first ramp signal rampL to be written to the memory 861.

[0117] 2, the selector 871 selects and outputs the AD conversion result written in the memory 841 based on the determination result written in the memory 781. That is, the selector 871 outputs the AD conversion result corresponding to the reset level, which is generated using a ramp signal having the same amount of potential change per unit time as the ramp signal used in the AD conversion of the signal based on the optical signal.

[0118] After time t11, the determination results and AD conversion results written in the memories 781, 841, and 861 are horizontally transferred via the horizontal scanning circuit 890. At this time, by setting the control signal MTX1 to high level between times t11 and t12, the switch 901 is turned on, and the amplitude determination results stored in the memory 781 are output to the horizontal scanning circuit 890 via the shared signal line. In addition, by setting the control signal MTX2 to high level between times t12 and t13, the switch 902 is turned on, and the amplitude determination results stored in the memory 782 included in the column control unit 772 of the conversion unit 722 are output to the horizontal scanning circuit 890 via the shared signal line.

[0119] Next, the operation of analog-to-digital conversion of a signal output from the pixel 10 to which high-luminance light is incident will be described with reference to Fig. 12. Up to time t6, the operation is as described with reference to Fig. 11.

[0120] When high-intensity light is incident, the drop (amplitude) in the potential of the vertical signal line 30 at time t6 is large, so the output of the comparator 760 remains at a high level. Therefore, the determination result written to the memory 781 between times t6 and t7 is a high level. In this way, the result written to the memory 781 changes depending on the result of the comparison between the signal level (amplitude) of the vertical signal line 30 and the determination threshold value (reference value REF).

[0121] As a result, from time t9 onwards, the second wiring 711 is connected to the non-inverting input node of the comparator 760, and the second ramp signal rampH is input thereto.

[0122] At time t10, the AD conversion result based on the second ramp signal rampH for the signal level is written to the memory 861. In the case of Fig. 12, based on the determination result written to the memory 781, the selector 871 selects and outputs the AD conversion result written to the memory 851.

[0123] After time t11, the determination results and AD conversion results written in the memories 781, 841, and 861 are horizontally transferred via the horizontal scanning circuit 890. At this time, by setting the control signal MTX1 to high level between times t11 and t12, the switch 901 is turned on, and the amplitude determination results stored in the memory 781 are output to the horizontal scanning circuit 890 via the shared signal line. In addition, by setting the control signal MTX2 to high level between times t12 and t13, the switch 902 is turned on, and the amplitude determination results stored in the memory 782 included in the column control unit 772 of the conversion unit 722 are output to the horizontal scanning circuit 890 via the shared signal line.

[0124] If it is determined from the amplitude determination result that the second ramp signal ramppH is used for analog-to-digital conversion, a gain corresponding to the ratio of the slopes of the first ramp signal rampL and the second ramp signal ramppH is applied to the analog-to-digital conversion result. X The periods during which MTX1 and MTX2 are at high level do not have to be adjacent to each other.

[0125] In this way, in a configuration using a slope-type analog-to-digital conversion circuit, amplitude determination can be performed by a comparator included in the analog-to-digital conversion circuit, so there is no need for a separate determination circuit. Also, by sharing the signal line for transmitting the determination result between multiple analog-to-digital conversion circuits, the same effects as in the first embodiment, such as a reduction in the number of wiring, can be achieved.

[0126] (Variation 1) Fig. 13 is a diagram showing an example of a circuit layout when multiple vertical signal lines are provided for each pixel column in the second embodiment. Fig. 13 shows an example of a circuit layout that can be adopted by the conversion unit 720 in a configuration in which two vertical signal lines are provided for each pixel column, with respect to the conversion unit 721 on the left side of Fig. 10. Similar circuit layouts can also be adopted for the other conversion units 722 to 72n.

[0127] 13(a) shows an example in which, when multiple circuits of the same type are provided for the same pixel column, circuits related to the same vertical signal line are arranged together (close to each other). That is, a selection unit 731A, a comparator 761A, and a column control unit 771A related to vertical signal line 31A are arranged together, and a selection unit 731B, a comparator 761B, and a column control unit 771B related to vertical signal line 31B are arranged together.

[0128] On the other hand, Figure 13(b) shows an example in which circuits of the same type are arranged together, similar to Figure 9. By arranging circuits of the same type together, it is possible to suppress variations in characteristics between circuits caused by the manufacturing process.

[0129] In this way, this embodiment can also accommodate a configuration in which a plurality of vertical signal lines are provided for each pixel column.

[0130] (Variation 2) Even when a slope-type analog-to-digital conversion circuit is used, amplitude determination may be performed in the same manner as in the first embodiment. For example, the determination circuit 20 described in the first embodiment may be provided between the pixel unit 5 and the conversion unit 720, and the amplitude determination result may be output from the determination circuit 20 to the selection unit 731 or the horizontal scanning circuit 890. In this case, the inputs of the switches 901 and 902 may be the determination circuit instead of the column control units 771 and 772, and the amplitude determination result may be supplied from the determination circuit to the selector 870.

[0131] FIG. 14(a) shows an example of a circuit arrangement when a determination circuit 20 is provided in a configuration in which two vertical signal lines are provided for each pixel column, for the pixel column on the left side of FIG. 10. A similar circuit arrangement can be adopted for the other pixel columns. A determination circuit 21A is provided for the vertical signal line 31A, and a determination circuit 21B is provided for the vertical signal line 31B. The configurations of the determination circuits 21A and 21B may be the same as those described in the first embodiment.

[0132] The amplitude determination result by the determination circuit 21A is supplied to the selection unit 731A, and the amplitude determination result by the determination circuit 21B is supplied to the selection unit 731B. The amplitude determination results by the determination circuit 21A and the amplitude determination results by the determination circuit 21B are supplied to the horizontal scanning circuit 890. By controlling the control signals MTX1 and MTX2 supplied to the determination circuits 21A and 21B to be exclusively at a high level, the determination results can be output individually from the determination circuit 21A to the selection unit 731A and from the determination circuit 21B to 731B. By controlling the control signals MTX1 and MTX2 supplied to the determination circuits 21A and 21B to be exclusively at a high level, the amplitude determination results of the determination circuits 21A and 21B can be output individually to the horizontal scanning circuit 890 using a single signal line. This modification also makes it possible to reduce the number of signal lines for transmitting the amplitude determination results.

[0133] (Variation 3) In this embodiment, a configuration using a dual-slope analog-to-digital conversion circuit has been described. However, by using a single-slope analog-to-digital conversion circuit and changing the gain applied to the data signal, it is possible to obtain the same effect as with the dual-slope type.

[0134] Fig. 14(b) is a diagram showing an example of a circuit configuration in which the gain is changed instead of switching the ramp signal in the configuration shown in Fig. 14(a). Variable-gain amplifier circuits 1011A and 1011B are provided instead of selectors 731A and 731B.

[0135] The gains applied by the amplifier circuits 1101A and 1101B are controlled based on the determination results of the determination circuits 21A and 21B. By applying a higher gain when the amplitude is less than the reference value REF than when the amplitude is equal to or greater than the reference value REF, it is possible to improve the resolution for low-level data signals. The ratio of the applied gains may be the same as the ratio of the slopes of the ramp signals.

[0136] The converter 720 performs analog-to-digital conversion using one type of ramp signal. Therefore, it is sufficient to measure the reset signal level only once. For data signals that have been analog-to-digital converted using a high gain, the reciprocal of the gain ratio is applied to the analog-to-digital conversion result.

[0137] 14(c) shows an example of the circuit configuration of the amplifier circuit 1011. The amplifier circuit 1011 has a capacitor 1020, an amplifier 1030, a variable capacitor 1050, and a switch 1040. One end of the capacitor 1020 is connected to a vertical signal line. The other end of the capacitor 1020 is connected to an input terminal of the amplifier 1030. The variable capacitor 1050 and the switch 1040 are provided to connect the output terminal and input terminal of the amplifier 1030.

[0138] Switch 1040 is a reset switch and is normally off. The value of variable capacitance element 1050 is controlled based on the amplitude determination result of determination circuit 21. Variable capacitance element 1050 has two switchable capacitance values, and when the determination result indicates that the amplitude is less than reference value REF, it has a first capacitance value, and when the determination result indicates that the amplitude is equal to or greater than reference value REF, it has a second capacitance value. Here, the first capacitance value is smaller than the second capacitance value. This allows a higher gain to be applied to signal data when the amplitude is determined to be less than reference value REF than when the amplitude is determined to be equal to or greater than reference value REF.

[0139] The timing of supplying the control signals MTX1 and MTX2 for transmitting the amplitude determination results over a common signal line may be the same as in Modification 2. This modification also makes it possible to reduce the number of signal lines for transmitting the amplitude determination results.

[0140] (Other embodiments) An application example of the photoelectric conversion device 1000 according to the above embodiment will be described below. FIG. 15 is a schematic diagram of an electronic device EQP equipped with the photoelectric conversion device 1000. FIG. 15 shows a camera as an example of the electronic device EQP. Here, the concept of a camera includes not only a device whose main purpose is to take pictures, but also a device that has a supplementary photography function (for example, a personal computer or a mobile terminal such as a smartphone).

[0141] The photoelectric conversion device 1000 may be a semiconductor chip with a stacked structure provided with a pixel section 5. As shown in FIG. 15 , the photoelectric conversion device 1000 is housed in a semiconductor package PKG. The package PKG may include a base to which the photoelectric conversion device 1000 is fixed, a lid facing the photoelectric conversion device 1000, and a conductive connecting member that connects terminals provided on the base with terminals provided on the photoelectric conversion device 1000. The lid may be made of glass, for example. The connecting member may be a bonding wire, a bump, or the like. The equipment EQP may further include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, and a memory device MMRY.

[0142] The optical system OPT forms an image on the photoelectric conversion device 1000 and may be, for example, a lens, shutter, or mirror. The control device CTRL controls the operation of the photoelectric conversion device 1000 and may be, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device 1000 and may be, for example, a semiconductor device such as a CPU or ASIC. The display device DSPL may be an EL display device or a liquid crystal display device that displays image data obtained by the photoelectric conversion device 1000. The memory device MMRY is a magnetic device or a semiconductor device that stores image data obtained by the photoelectric conversion device 1000. The memory device MMRY may be a volatile memory such as an SRAM or DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving or propulsive part such as a motor or engine. In a camera, the mechanical device MCHN can drive components of the optical system OPT for zooming, focusing, and shutter operation. The device EQP displays the image data output from the photoelectric conversion device 1000 on the display device DSPL, or transmits it to the outside via a communication device (not shown) included in the device EQP. For this reason, the device EQP may include a memory device MMRY and a processing device PRCS.

[0143] A camera incorporating the photoelectric conversion device 1000 can be used as a surveillance camera or an on-board camera mounted on transportation equipment such as automobiles, railroad cars, ships, aircraft, or industrial robots. In addition, a camera incorporating the photoelectric conversion device 1000 can be used not only in transportation equipment but also in a wide range of equipment that uses object recognition, such as an intelligent transport system (ITS).

[0144] The present invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Therefore, the following claims are appended to clarify the scope of the invention. [Explanation of symbols]

[0145] 5: pixel unit, 10: pixel, 30: vertical signal line, 720: conversion unit, 760: comparator, 1000, 2000: photoelectric conversion device

Claims

1. A photoelectric conversion device, a pixel section in which pixels that generate signals by photoelectric conversion are arranged in a matrix; a plurality of determination circuits for determining amplitudes of signals read from the pixel unit through different vertical signal lines; a shared signal line shared by the plurality of determination circuits and transmitting the determination results from the plurality of determination circuits to a circuit inside the photoelectric conversion device; a holding circuit connected to each of the vertical signal lines and holding the signal; an analog-to-digital conversion circuit that converts the signal held in the holding circuit into an analog-to-digital conversion signal; The photoelectric conversion device is characterized in that one analog-to-digital conversion circuit is provided for a plurality of the determination circuits.

2. A photoelectric conversion device, a pixel section in which pixels that generate signals by photoelectric conversion are arranged in a matrix; a plurality of determination circuits for determining amplitudes of signals read from the pixel unit through different vertical signal lines; a shared signal line shared by the plurality of determination circuits and transmitting the determination results from the plurality of determination circuits to a circuit inside the photoelectric conversion device; a plurality of analog-to-digital conversion circuits connected to the vertical signal lines, respectively, for performing analog-to-digital conversion on the signals read from the vertical signal lines; the plurality of analog-to-digital conversion circuits are slope type; the plurality of determination circuits are comparators included in the plurality of analog-to-digital conversion circuits, a plurality of analog-to-digital conversion circuits each controlling a slope of a ramp signal used for the analog-to-digital conversion based on a result of the determination;

3. A photoelectric conversion device, a pixel section in which pixels that generate signals by photoelectric conversion are arranged in a matrix; a plurality of determination circuits for determining amplitudes of signals read from the pixel unit through different vertical signal lines; a shared signal line shared by the plurality of determination circuits and transmitting the determination results from the plurality of determination circuits to a circuit inside the photoelectric conversion device; a plurality of amplifier circuits that control gains applied to the signals based on the results of the determinations made by the plurality of determination circuits; a plurality of analog-to-digital conversion circuits connected to the vertical signal lines, respectively, for performing analog-to-digital conversion on the signals read from the vertical signal lines; each of the plurality of analog-to-digital conversion circuits performs analog-to-digital conversion on the signal to which a gain has been applied by one of the plurality of amplifier circuits; A photoelectric conversion device characterized by:

4. A photoelectric conversion device according to any one of claims 1 to 3, characterized in that one of the plurality of judgment circuits outputs the result of the judgment to the shared signal line after another of the plurality of judgment circuits outputs the result of the judgment to the shared signal line.

5. 5. The photoelectric conversion device according to claim 1, wherein each of the plurality of determination circuits is connected to the vertical signal line provided for a different pixel column.

6. 5. The photoelectric conversion device according to claim 1, wherein each of the plurality of determination circuits is connected to a different one of the vertical signal lines provided for the same pixel column.

7. 2. The photoelectric conversion device according to claim 1, further comprising a selection circuit that selectively outputs the plurality of signals held by the plurality of holding circuits to the analog-to-digital conversion circuit.

8. a switching circuit that selectively connects the plurality of determination circuits to the shared signal line; 8. The photoelectric conversion device according to claim 7, wherein the switching circuit is provided closer to the pixel unit than the selection circuit.

9. 9. The photoelectric conversion device according to claim 8, wherein the switching circuit has a circuit scale smaller than that of the selection circuit.

10. 8. The photoelectric conversion device according to claim 7, wherein the plurality of determination circuits are connected to the shared signal line at a position closer to the pixel unit than the selection circuit.

11. 9. The photoelectric conversion device according to claim 1, wherein the plurality of determination circuits output the determination results to the shared signal line in mutually different periods.

12. A photoelectric conversion device according to any one of claims 1 to 11, characterized in that when multiple vertical signal lines are provided for the same pixel column, the circuits provided for each vertical signal line are arranged so that circuits of the same type are adjacent to each other.

13. A photoelectric conversion device as described in any one of claims 1 and 3 to 12, characterized in that each of the multiple judgment circuits is an auto-zero type differential amplifier that receives the signal and a reference value used for the judgment as input and has the function of canceling input offset.

14. 14. The photoelectric conversion device according to claim 1, wherein each of the plurality of determination circuits is driven by a current source connected to a vertical signal line of the pixel.

15. The photoelectric conversion device according to any one of claims 1 to 14, a control device that controls the operation of the photoelectric conversion device; An electronic device comprising:

16. A substrate laminated on a substrate provided with a pixel portion in which pixels that generate signals by photoelectric conversion are arranged in a matrix, a plurality of determination circuits for determining amplitudes of signals read from the pixel unit through different vertical signal lines; a shared signal line shared by the plurality of determination circuits and transmitting the determination results from the plurality of determination circuits to a circuit provided on the substrate that is different from the plurality of determination circuits; a holding circuit connected to each of the vertical signal lines and holding the signal; an analog-to-digital conversion circuit that converts the signal held in the holding circuit into an analog-to-digital conversion signal; The substrate, wherein one analog-to-digital conversion circuit is provided for each of the plurality of determination circuits.

17. A substrate laminated on a substrate having a pixel section in which pixels that generate signals by photoelectric conversion are arranged in a matrix, comprising: a plurality of determination circuits for determining amplitudes of signals read from the pixel unit through different vertical signal lines; a shared signal line shared by the plurality of determination circuits and transmitting the determination results from the plurality of determination circuits to a circuit provided on the substrate that is different from the plurality of determination circuits; a plurality of analog-to-digital conversion circuits connected to the respective vertical signal lines, for performing analog-to-digital conversion of the signals read from the vertical signal lines; the plurality of analog-to-digital conversion circuits are slope type; the plurality of determination circuits are comparators included in the plurality of analog-to-digital conversion circuits, a first input / output terminal for inputting a first signal to a first analog-to-digital converter circuit, the first input / output terminal being connected to the first analog-to-digital converter circuit, the second input / output terminal being connected to the first analog-to-digital converter circuit, and the third input / output terminal being connected to the first analog-to-digital converter circuit;

18. A substrate laminated on a substrate having a pixel section in which pixels that generate signals by photoelectric conversion are arranged in a matrix, comprising: a plurality of determination circuits for determining amplitudes of signals read from the pixel unit through different vertical signal lines; a shared signal line shared by the plurality of determination circuits and transmitting the determination results from the plurality of determination circuits to a circuit provided on the substrate that is different from the plurality of determination circuits; a plurality of amplifier circuits that control gains applied to the signals based on the results of the determinations made by the plurality of determination circuits; a plurality of analog-to-digital conversion circuits connected to the respective vertical signal lines, for performing analog-to-digital conversion of the signals read from the vertical signal lines; A substrate, characterized in that each of the plurality of analog-to-digital conversion circuits performs analog-to-digital conversion on the signal to which a gain has been applied by one of the plurality of amplifier circuits.

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