Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving resistance to an overcurrent.SOLUTION: A semiconductor device comprises a semiconductor part, a first electrode on a rear face of the semiconductor part, a second electrode on a front face of the semiconductor part, and a control electrode between the semiconductor part and the second electrode. The semiconductor part includes first, third, and fifth layers of a first conductivity type, and second, fourth, sixth, and seventh layers of a second conductivity type. The first layer is provided between the first and second electrodes. The second layer is provided between the first layer and the second electrode. The third layer is provided between the second layer and the second electrode. The fourth and fifth layers are provided between the first layer and the first electrode, and arranged along the first electrode. The sixth layer surrounds the second and third layers at the front face side. The seventh layer is provided between the first layer and the first electrode, separated from the fourth and fifth layers, and located inside an outer edge of the sixth layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] It is desirable for power control semiconductor devices to have a high resistance to overcurrent in the ON state. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-103376 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device that can improve the resistance to overcurrent. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a semiconductor portion, a first electrode, a second electrode, and a control electrode. The first electrode is provided on a back surface of the semiconductor portion, and the second electrode is provided on a surface of the semiconductor portion opposite the back surface. The control electrode is provided between the semiconductor portion and the second electrode. The semiconductor portion has an active region and a termination region surrounding the active region, and includes a first layer of a first conductivity type, a second layer of a second conductivity type, a third layer of the first conductivity type, a fourth layer of the second conductivity type, a fifth layer of the first conductivity type, a sixth layer of the second conductivity type, and a seventh layer of the second conductivity type. The first layer is provided between the first electrode and the second electrode, and the second layer is provided between the first layer and the second electrode. The third layer is provided between the second layer and the second electrode. The fourth and fifth layers are provided between the first layer and the first electrode and are aligned along the first electrode. The sixth layer is provided in the termination region and surrounds the second layer and the third layer on the surface side of the semiconductor portion. The seventh layer is provided in the termination region between the first layer and the first electrode, spaced apart from the fourth layer and the fifth layer, surrounds the fourth layer and the fifth layer, and is located closer to the active region than the sixth layer. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment; [Figure 2] 1 is a schematic plan view showing a semiconductor device according to an embodiment; [Figure 3] 1 is a graph showing characteristics of a semiconductor device according to an embodiment. [Figure 4] FIG. 10 is a schematic diagram showing a semiconductor device according to a modified example of the embodiment. [Figure 5] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to another modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Identical parts in the drawings are assigned the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be explained as upward and the opposite direction as downward.

[0009] 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is a reverse conducting insulated gate bipolar transistor (RCIGBT). The semiconductor device 1 includes, for example, a semiconductor portion 10, a collector electrode 20, an emitter electrode 30, and a gate electrode 40. The semiconductor portion 10 is made of, for example, silicon.

[0010] The collector electrode 20 (first electrode) is provided on the back surface of the semiconductor portion 10. The emitter electrode 30 (second electrode) is provided on the front surface opposite to the back surface of the semiconductor portion 10. The gate electrode 40 (control electrode) is provided between the semiconductor portion 10 and the emitter electrode 30.

[0011] The semiconductor portion 10 includes a plurality of gate trenches GT provided on the front surface side. A gate electrode 40 is provided inside each of the plurality of gate trenches GT. The gate electrode 40 is electrically insulated from the semiconductor portion 10 by a gate insulating film 43 (first insulating film). The gate electrode 40 is also electrically insulated from the emitter electrode 30 by an interlayer insulating film 45 (second insulating film).

[0012] The semiconductor portion 10 includes, for example, an n-type base layer 11, a p-type base layer 13, an n-type emitter layer 15, a p-type emitter layer 16, a p-type collector layer 17, and an n-type cathode layer 19. Here, the first conductivity type will be described as n-type, and the second conductivity type will be described as p-type.

[0013] The n-type base layer 11 (first layer) extends between the collector electrode 20 and the emitter electrode 30. The n-type base layer 11 extends, for example, in the X and Y directions and spreads across the entire semiconductor portion 10. The gate trench GT is provided so as to extend from the surface of the semiconductor portion 10 into the n-type base layer 11. Similar to the gate trench GT, the gate electrode 40 provided in the gate trench GT via a gate insulating film 43 is also provided so as to extend from the surface side of the semiconductor portion 10 into the n-type base layer 11.

[0014] The p-type base layer 13 (second layer) is provided between the n-type base layer 11 and the emitter electrode 30. The p-type base layer 13 is provided between adjacent gate electrodes 40. The p-type base layer 13 is provided so as to face the gate electrode 40 in the X direction, for example, with the gate insulating film 43 interposed therebetween.

[0015] The n-type emitter layer 15 (third layer) is provided between the p-type base layer 13 and the emitter electrode 30. The n-type emitter layer 15 is provided so as to be in contact with the gate insulating film 43. The n-type emitter layer 15 contains a higher concentration of n-type impurities than the n-type impurities in the n-type base layer 11.

[0016] The p-type emitter layer 16 is provided between the p-type base layer 13 and the emitter electrode 30, and is arranged next to the n-type emitter layer 15. The p-type emitter layer 16 contains a higher concentration of p-type impurities than the p-type impurities in the p-type base layer 13.

[0017] The n-type emitter layer 15 and the p-type emitter layer 16 are arranged, for example, along the surface of the semiconductor portion 10. The emitter electrode 30 is in contact with and electrically connected to the n-type emitter layer 15 and the p-type emitter layer 16. The emitter electrode 30 is also electrically connected to the p-type base layer 13 via the p-type emitter layer 16.

[0018] The p-type collector layer 17 (fourth layer) is provided between the n-type base layer 11 and the collector electrode 20. The p-type collector layer 17 is in contact with the collector electrode 20 and is electrically connected thereto.

[0019] The n-type cathode layer 19 (fifth layer) is arranged next to the p-type collector layer 17 between the n-type base layer 11 and the collector electrode 20. The p-type collector layers 17 and the n-type cathode layers 19 are arranged alternately, for example, along the back surface of the semiconductor portion 10. The n-type cathode layer 19 is in contact with and electrically connected to the collector electrode 20.

[0020] The semiconductor portion 10 has, for example, an active region AR and a termination region TR. The active region AR includes a p-type base layer 13, an n-type emitter layer 15, a p-type emitter layer 16, a p-type collector layer 17, and an n-type cathode layer 19, and is a region that serves as a main path of current during operation of the semiconductor device 1. In a plan view parallel to the surface of the semiconductor portion 10 (XY plane), the termination region TR surrounds the active region AR.

[0021] The semiconductor section 10 further includes, for example, a p-type guard ring layer 21, a p-type assist layer 23, and an n-type buffer layer 25. The p-type guard ring layer 21 and the p-type assist layer 23 are provided in the termination region TR.

[0022] The p-type guard ring layer 21 (sixth layer) is provided on the surface side of the semiconductor portion 10. The p-type guard ring layer 21 is provided on the n-type base layer 11 at the boundary between the active region AR and the termination region TR. The boundary between the active region AR and the termination region TR is, for example, the position where the gate trench GT located closest to the termination region TR in the X direction is provided. Furthermore, in the direction from the collector electrode 20 toward the emitter electrode 30, for example, in the Z direction, the boundary between the n-type base layer 11 and the p-type guard ring layer 21 is located below the boundary between the n-type base layer 11 and the p-type base layer 13.

[0023] The p-type assist layer 23 (seventh layer) is provided in the termination region TR between the n-type base layer 11 and the collector electrode 20. The p-type assist layer 23 is in contact with and electrically connected to the collector electrode 20. The p-type assist layer 23 is also located between the p-type guard ring layer 21 and the collector electrode 20. The p-type impurity concentration of the p-type assist layer 23 is, for example, at the same level as the p-type impurity concentration of the p-type collector layer 17.

[0024] The p-type assist layer 23 is provided at a distance from the p-type collector layer 17. A distance d1 in the X direction from the p-type assist layer 23 to the p-type collector layer 17 is longer than a width d2 in the X direction of the p-type assist layer 23. Furthermore, the width d2 of the p-type assist layer 23 is narrower than the minimum width of the p-type collector layer 17, for example, a width d3 in the X direction.

[0025] The n-type buffer layer 25 (eighth layer) extends into the active region AR and the termination region TR. The n-type buffer layer 25 (eighth layer) is provided between the n-type base layer 11 and the p-type collector layer 17. The n-type buffer layer 25 extends between the n-type base layer 11 and the n-type cathode layer 19 and between the n-type base layer 11 and the p-type assist layer 23. The n-type buffer layer 25 is provided in the termination region TR between the n-type base layer 11 and the collector electrode 20 and is in contact with the collector electrode 20. The n-type buffer layer 25 also extends between the p-type collector layer 17 and the p-type assist layer 23, which are spaced apart from each other.

[0026] 2(a) and 2(b) are schematic plan views showing the semiconductor device 1 according to the embodiment. FIG. 2(a) is a plan view showing the front surface of the semiconductor portion 10. FIG. 2(b) is a plan view showing the back surface of the semiconductor portion 10. In FIG. 2(a), p The n-type emitter layer 15 and the p-type emitter layer 16 (see FIG. 1) on the base layer 13 are omitted.

[0027] As shown in FIG. 2(a), a plurality of gate electrodes 40 are provided. Each of the gate electrodes 40 extends in the Y direction along the surface of the semiconductor portion 10. The plurality of gate electrodes 40 are arranged, for example, in the X direction. A p-type base layer 13 is provided between each pair of adjacent gate electrodes 40.

[0028] The p-type guard ring layer 21 is provided to surround the p-type base layer 13. The p-type guard ring layer 21 is Be The p-type guard ring layer 21 is provided so as to be connected to the p-type base layer 13. The p-type base layer 13 and the p-type guard ring layer 21 may be provided integrally. The p-type guard ring layer 21 also surrounds the n-type emitter layer 15 and the p-type emitter layer 16, which are not shown.

[0029] The p-type assist layer 23 is provided so as to surround the p-type base layer 13. The p-type assist layer 23 is provided so as to surround the n-type emitter layer 15 and the p-type emitter layer 16, which are not shown.

[0030] 2(b), the p-type collector layer 17 and the n-type cathode layer 19 each extend, for example, in the Y direction along the rear surface of the semiconductor portion 10. The p-type collector layer 17 and the n-type cathode layer 19 are arranged alternately, for example, in the X direction.

[0031] The p-type assist layer 23 is provided so as to surround the p-type collector layer 17 and the n-type cathode layer 19. The p-type assist layer 23 is located inside the outer edge 21e of the p-type guard ring layer 21. The p-type assist layer 23 is provided at a distance from the p-type collector layer 17 and the n-type cathode layer 19. In the Y direction, the distance d1 from the p-type collector layer 17 to the p-type assist layer 23 is the same as the separation distance d1 between the p-type collector layer 17 and the p-type assist layer 23 in the X direction. In the Y direction, the distance d1 from the n-type cathode layer 19 to the p-type assist layer 23 is the same as the separation distance d1 between the p-type collector layer 17 and the p-type assist layer 23.

[0032] For example, an n-type buffer layer 25 extends between the p-type assist layer 23 and the p-type collector layer 17 and between the p-type assist layer 23 and the n-type cathode layer 19. The n-type buffer layer 25 is in contact with the collector electrode 20 between the p-type collector layer 17 and the p-type assist layer 23. The n-type buffer layer 25 is also provided on the outside of the p-type assist layer 23.

[0033] In the semiconductor device 1, the provision of the p-type assist layer 23 in the termination region TR can improve the withstand capability against overcurrent. That is, when a large current flows in the on-state, for example, during a short circuit, the p-type assist layer 23 injects holes into the n-type base layer 11 and suppresses an increase in the electric field in the n-type base layer 11. This can improve the short-circuit withstand capability of the semiconductor device 1.

[0034] When the semiconductor device 1 operates at, for example, a rated current or less, a collector current flows between the collector electrode 20 and the emitter electrode 30. At this time, electrons are injected into the n-type base layer 11 through an inversion layer induced between the p-type base layer 13 and the gate insulating film 43, and holes are injected from the p-type collector layer 17 into the n-type base layer 11 accordingly. When the semiconductor device 1 operates at a current less than the rated current, the electrons and holes in the n-type base layer 11 are balanced, and the potential difference between the p-type base layer 13 and the p-type collector layer 17 does not become high enough to inject holes into the n-type base layer 11 from the p-type assist layer 23 in the termination region TR.

[0035] On the other hand, when a large current such as a short-circuit current flows between the collector electrode 20 and the emitter electrode 30, an excess of electrons are injected into the n-type base layer 11 through the inversion layer between the p-type base layer 13 and the gate insulating film 43, making it impossible to maintain charge balance in the n-type base layer 11. This increases the potential difference between the p-type base layer 13 and the p-type collector layer 17, and holes are injected from the p-type assist layer 23 into the n-type base layer 11. This suppresses the charge imbalance in the n-type base layer 11, and prevents a further increase in the potential difference between the p-type base layer 13 and the p-type collector layer 17.

[0036] For example, if the p-type assist layer 23 is not provided, a charge imbalance in the n-type base layer 11 increases the potential difference between the p-type base layer 13 and the p-type collector layer 17. In the active region AR, the charge imbalance is corrected by hole injection from the p-type collector layer 17, and this potential difference is eliminated. However, because the p-type collector layer 17 is not provided in the termination region TR, the charge imbalance is not corrected by hole injection. As a result, the potential difference at the boundary between the active region AR and the termination region TR is not eliminated, and diffusion current generated in the non-depleted region of the n-type base layer 11 flows concentratedly at the boundary between the active region AR and the termination region TR, which may lead to short-circuit breakdown of the semiconductor device 1.

[0037] In the semiconductor device 1, by providing the p-type assist layer 23, hole injection also occurs in the termination region TR, improving the short-circuit resistance. However, if the p-type assist layer 23 extends over the entire termination region TR, the breakdown voltage at the outer edge 21e of the p-type guard ring layer 21 decreases. That is, the avalanche resistance at turn-off decreases. For this reason, the p-type assist layer 23 is preferably located inside the outer edge 21e of the p-type guard ring layer 21 in a plan view parallel to the back surface of the semiconductor section 10 (see FIG. 2(b)). That is, in the X direction (or Y direction), the p-type assist layer 23 is preferably located closer to the active region AR than the outer edge 21e of the p-type guard ring layer 21.

[0038] Fig. 3 is a graph showing the characteristics of the semiconductor device 1 according to the embodiment. Fig. 3 is a graph showing the relationship between the collector current Ice at which hole injection from the p-type assist layer 23 to the n-type base layer 11 starts and the width d2 of the p-type assist layer 23. The horizontal axis is the width d2 of the p-type assist layer 23. The vertical axis is the collector current Ice.

[0039] As the width d2 of the p-type assist layer 23 narrows, the amount of holes injected into the n-type base layer 11 decreases, approaching the characteristics obtained when the p-type assist layer 23 is not provided. On the other hand, as the width of the p-type assist layer 23 widens, a non-negligible amount of holes is injected from the p-type assist layer 23 into the n-type base layer 11 even when the operating current is below the rated current. This increases the switching loss during turn-off. In other words, to ensure that the p-type assist layer 23 operates effectively, the width d2 is preferably within a certain range. For example, when hole injection is to occur at a current of 150 A or more, which is twice the rated current, the width d2 of the p-type assist layer 23 is preferably 25 micrometers or more and 70 micrometers or less.

[0040] 4(a) and 4(b) are schematic diagrams showing a semiconductor device 2 according to a modified example of the embodiment, where Fig. 4(a) is a cross-sectional view and Fig. 4(b) is a plan view showing the back surface of the semiconductor portion 10.

[0041] 4(a), in the semiconductor device 2, a p-type low concentration layer 27 (ninth layer) is provided between the p-type collector layer 17 and the p-type assist layer 23. The p-type low concentration layer 27 is located between the collector electrode 20 and the n-type buffer layer 25 in the Z direction. The p-type low concentration layer 27 is in contact with the collector electrode 20 and the n-type buffer layer 25.

[0042] The p-type low-concentration layer 27 contains a p-type impurity at a concentration lower than the p-type impurity concentration of the p-type collector layer 17 and the p-type impurity concentration of the p-type assist layer 23. In other words, the level of hole injection from the p-type low-concentration layer 27 into the n-type base layer 11 is lower than the level of hole injection from the p-type collector layer 17 into the n-type base layer 11.

[0043] 4(b), the p-type low-concentration layer 27 is provided so as to surround the p-type collector layer 17 and the n-type cathode layer 19. The width d4 of the p-type low-concentration layer 27 in the X and Y directions is greater than, for example, the width d2 of the p-type assist layer 23 in the X and Y directions. The width d4 of the p-type low-concentration layer is also smaller than the minimum width of the p-type collector layer 17, for example, the width d3 in the X direction.

[0044] 5 is a schematic cross-sectional view showing a semiconductor device 3 according to another modified example of the embodiment. The semiconductor device 3 has a second p-type low-concentration layer 29 (tenth layer). The p-type low-concentration layer 29 is provided outside the p-type assist layer 23, for example, in the entire termination region TR (see FIG. 1). In the termination region TR, the p-type low-concentration layer 29 is provided between the collector electrode 20 and the n-type buffer layer 25.

[0045] The p-type impurity concentration of the p-type low concentration layer 29 is lower than the p-type impurity concentration of the p-type collector layer 17 and the p-type impurity concentration of the p-type assist layer 23. Therefore, in the semiconductor device 3, the avalanche resistance at the outer edge 21e of the p-type guard ring layer 21 can be increased.

[0046] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0047] 1, 2, 3... semiconductor device, 10... semiconductor portion, 11... n-type base layer, 13... p-type base layer, 15... n-type emitter layer, 16... p-type emitter layer, 17... p-type collector layer, 19... n-type cathode layer, 20... collector electrode, 21... p-type guard ring layer, 21e... outer edge, 23... p-type assist layer, 25... n-type buffer layer, 27, 29... p-type low concentration layer, 30... emitter electrode, 40... gate electrode, 43... gate insulating film, 45... interlayer insulating film, AR... active region, GT... gate trench, TR... termination region

Claims

1. a semiconductor portion having an active region and a termination region surrounding the active region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion opposite to the back surface; a control electrode provided between the semiconductor portion and the second electrode; Equipped with the semiconductor portion includes a first layer of a first conductivity type, a second layer of a second conductivity type, a third layer of the first conductivity type, a fourth layer of the second conductivity type, a fifth layer of the first conductivity type, a sixth layer of the second conductivity type, and a seventh layer of the second conductivity type; the first layer is provided between the first electrode and the second electrode, the second layer is provided between the first layer and the second electrode, the third layer is provided between the second layer and the second electrode, the fourth layer and the fifth layer are provided between the first layer and the first electrode and are aligned along the first electrode, the sixth layer is provided in the termination region and surrounds the second layer and the third layer on the front surface side of the semiconductor portion; the seventh layer is provided in the termination region between the first layer and the first electrode, is spaced apart from the fourth layer and the fifth layer, surrounds the fourth layer and the fifth layer, and is located closer to the active region than the sixth layer; the semiconductor portion further includes a ninth layer of the second conductivity type provided between the fourth layer and the seventh layer and between the fifth layer and the seventh layer, the ninth layer contains a second conductivity type impurity at a concentration lower than the second conductivity type impurity concentrations of the fourth layer and the seventh layer.

2. the semiconductor portion further includes a tenth layer that is provided closer to the termination region than the seventh layer and is located between the first layer and the first electrode, 2. The semiconductor device according to claim 1, wherein the tenth layer contains the second conductivity type impurity at a concentration lower than the second conductivity type impurity of the fourth layer and the seventh layer.

3. A semiconductor portion having an active region and a termination region surrounding the active region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion opposite to the back surface; a control electrode provided between the semiconductor portion and the second electrode; Equipped with the semiconductor portion includes a first layer of a first conductivity type, a second layer of a second conductivity type, a third layer of the first conductivity type, a fourth layer of the second conductivity type, a fifth layer of the first conductivity type, a sixth layer of the second conductivity type, and a seventh layer of the second conductivity type; the first layer is provided between the first electrode and the second electrode, the second layer is provided between the first layer and the second electrode, the third layer is provided between the second layer and the second electrode, the fourth layer and the fifth layer are provided between the first layer and the first electrode and are aligned along the first electrode, the sixth layer is provided in the termination region and surrounds the second layer and the third layer on the front surface side of the semiconductor portion; the seventh layer is provided in the termination region between the first layer and the first electrode, is spaced apart from the fourth layer and the fifth layer, surrounds the fourth layer and the fifth layer, and is located closer to the active region than the sixth layer; the semiconductor portion further includes an eighth layer of the first conductivity type that is provided between the first layer and the fourth layer, between the first layer and the fifth layer, and between the first layer and the seventh layer, and that contains first conductivity type impurities at a concentration higher than that of the first conductivity type impurities of the first layer and lower than that of the first conductivity type impurities of the fifth layer; the eighth layer is provided between the fourth layer and the seventh layer and between the fifth layer and the seventh layer; the eighth layer extends entirely between the fourth layer and the seventh layer while being in contact with the first electrode.

4. 4. The semiconductor device according to claim 3, wherein the fifth layer has a higher concentration of the first conductivity type impurity than the eighth layer.

5. a semiconductor portion having an active region and a termination region surrounding the active region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion opposite to the back surface; a control electrode provided between the semiconductor portion and the second electrode; Equipped with the semiconductor portion includes a first layer of a first conductivity type, a second layer of a second conductivity type, a third layer of the first conductivity type, a fourth layer of the second conductivity type, a fifth layer of the first conductivity type, a sixth layer of the second conductivity type, and a seventh layer of the second conductivity type; the first layer is provided between the first electrode and the second electrode, the second layer is provided between the first layer and the second electrode, the third layer is provided between the second layer and the second electrode, the fourth layer and the fifth layer are provided between the first layer and the first electrode and are aligned along the first electrode, the sixth layer is provided in the termination region and surrounds the second layer and the third layer on the front surface side of the semiconductor portion; the seventh layer is provided in the termination region between the first layer and the first electrode, is spaced apart from the fourth layer and the fifth layer, surrounds the fourth layer and the fifth layer, and is located closer to the active region than the sixth layer; the semiconductor portion has a trench extending from the surface into the first layer, the control electrode is provided inside the trench, is electrically insulated from the semiconductor portion by a first insulating film, and is electrically insulated from the second electrode by a second insulating film; The sixth layer is in contact with the first insulating film.

6. The semiconductor device according to claim 5 , wherein said sixth layer is in contact with said first insulating film at a lower end of said trench.

7. a semiconductor portion having an active region and a termination region surrounding the active region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion opposite to the back surface; a control electrode provided between the semiconductor portion and the second electrode; Equipped with the semiconductor portion includes a first layer of a first conductivity type, a second layer of a second conductivity type, a third layer of the first conductivity type, a fourth layer of the second conductivity type, a fifth layer of the first conductivity type, a sixth layer of the second conductivity type, and a seventh layer of the second conductivity type; the first layer is provided between the first electrode and the second electrode, the second layer is provided between the first layer and the second electrode, the third layer is provided between the second layer and the second electrode, the fourth layer and the fifth layer are provided between the first layer and the first electrode and are aligned along the first electrode, the sixth layer is provided in the termination region and surrounds the second layer and the third layer on the front surface side of the semiconductor portion; the seventh layer is provided in the termination region between the first layer and the first electrode, is spaced apart from the fourth layer and the fifth layer, surrounds the fourth layer and the fifth layer, and is located closer to the active region than the sixth layer; the fourth layer and the fifth layer are repeatedly arranged in a direction parallel to the rear surface, a distance between the fourth layer, which is closest to the termination region in the direction parallel to the back surface, and the termination region, is shorter than a distance between the fifth layer, which is closest to the termination region in the direction parallel to the back surface, and the termination region.

8. 7. The semiconductor device according to claim 1, wherein a distance from the fourth layer to the seventh layer in a direction parallel to the back surface of the semiconductor portion is longer than a width of the seventh layer in the direction parallel to the back surface of the semiconductor portion.

9. The semiconductor device according to claim 8 , wherein the minimum width of the fourth layer in the direction parallel to the back surface of the semiconductor portion is wider than the width of the seventh layer.

10. The semiconductor device according to claim 1 , wherein the seventh layer surrounds the second layer and the third layer.

11. 10. The semiconductor device according to claim 1, wherein the seventh layer has a width of 25 micrometers or more and 70 micrometers or less.

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