Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing turn-on loss and turn-off loss.SOLUTION: A second semiconductor layer is provided between a first semiconductor layer and a third semiconductor layer, the third semiconductor layer is provided between the second semiconductor layer and a first electrode and electrically connected to the first electrode, and a fourth semiconductor layer is provided between the first semiconductor layer and a second electrode and electrically connected to the second electrode. When S1 represents an area where a first gate electrode faces the third semiconductor layer via a first insulating film, S2 represents an area where a second gate electrode faces the third semiconductor layer via a second insulating film, and S3 represents an area where a third gate electrode faces the third semiconductor layer via a third insulating film, S1≤S2<S3 is satisfied.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] IGBTs (Insulated Gate Bipolar Transistors) are widely used as power semiconductor devices that can handle high voltages and large currents. IGBTs used as switching devices are required to have low on-state voltages and low switching losses during turn-on and turn-off. A double-gate structure, in which the gate electrode is divided into two and one gate electrode is turned off first, is one method for reducing turn-off losses while maintaining a low on-state voltage. However, increasing the channel density reduces short-circuit resistance, making it difficult to reduce turn-on losses. Therefore, as shown in Patent Document 1, an IGBT has been proposed that divides the gate electrode into three and drives all three gate electrodes only during turn-on, thereby reducing turn-on losses. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-141304 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device capable of reducing turn-on loss and turn-off loss. [Means for solving the problem]

[0005] According to an embodiment, a semiconductor device includes a first electrode, a second electrode, a semiconductor section provided between the first electrode and the second electrode, the semiconductor section having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of a second conductivity type, a first gate electrode, a second gate electrode, and a third gate electrode provided between the semiconductor section and the first electrode, facing the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and electrically isolated from each other, a first insulating film provided between the first gate electrode and the semiconductor section, a second insulating film provided between the second gate electrode and the semiconductor section, and a fourth insulating film provided between the third gate electrode and the first electrode. the second semiconductor layer is provided between the first semiconductor layer and the third semiconductor layer, the third semiconductor layer is provided between the second semiconductor layer and the first electrode and is electrically connected to the first electrode, the fourth semiconductor layer is provided between the first semiconductor layer and the second electrode and is electrically connected to the second electrode, and when an area where the first gate electrode and the third semiconductor layer face each other via the first insulating film is S1, an area where the second gate electrode and the third semiconductor layer face each other via the second insulating film is S2, and an area where the third gate electrode and the third semiconductor layer face each other via the third insulating film is S3, S1≦S2 <S3である。 [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional perspective view of a semiconductor device according to a first embodiment; [Figure 2] FIG. 10 is a cross-sectional perspective view of a semiconductor device according to a second embodiment. [Figure 3] 3 is a cross-sectional view taken along the line AA in FIG. 2. [Figure 4] 3 is a cross-sectional view of FIG. 2 taken along line B-B. [Figure 5] FIG. 10 is a cross-sectional perspective view of a semiconductor device according to a third embodiment. [Figure 6] 10(a) to 10(c) are timing charts showing an example of a control method for a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings, in which the same components are denoted by the same reference numerals.

[0008] [First embodiment] 1 is a cross-sectional perspective view of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 is, for example, an IGBT.

[0009] The semiconductor device 1 includes a first electrode 21, a second electrode 22, a semiconductor portion 10, a first gate electrode G1, a second gate electrode G2, a third gate electrode G3, a first insulating film 41, a second insulating film 42, and a third insulating film 43. In Fig. 1, the first electrode 21 is represented by a two-dot chain line to clearly show the surface of the semiconductor portion 10 covered with the first electrode 21.

[0010] The first electrode 21 and the second electrode 22 are positioned apart in a first direction Z. In FIG. 1, two directions perpendicular to the first direction Z are defined as a second direction X and a third direction Y. The second direction X and the third direction Y are perpendicular to each other. The first electrode 21 is, for example, an emitter electrode of an IGBT. The second electrode 22 is, for example, a collector electrode of the IGBT.

[0011] The semiconductor portion 10 is provided between the first electrode 21 and the second electrode 22 in the first direction Z. The material of the semiconductor portion 10 is, for example, silicon. The material of the semiconductor portion 10 can also be, for example, silicon carbide or gallium nitride.

[0012] The semiconductor section 10 has a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 12 of a second conductivity type, a third semiconductor layer 13 of the first conductivity type, and a fourth semiconductor layer 14 of the second conductivity type. In this embodiment, for example, the first conductivity type is n-type and the second conductivity type is p-type.

[0013] The semiconductor portion 10 has a plurality of mesa portions 30 that are spaced apart from each other in the second direction X. Each mesa portion 30 extends in the third direction Y. Each mesa portion 30 has a part of the first semiconductor layer 11, a second semiconductor layer 12, and a third semiconductor layer 13.

[0014] The first semiconductor layer 11 is, for example, an n-type drift layer in an IGBT. The second semiconductor layer 12 is, for example, a p-type base layer in an IGBT. The second semiconductor layer 12 is provided between the first semiconductor layer 11 and the third semiconductor layer 13 in the first direction Z.

[0015] The third semiconductor layer 13 is, for example, an n-type emitter layer of an IGBT. The n-type impurity concentration of the third semiconductor layer 13 is higher than the n-type impurity concentration of the first semiconductor layer 11. The third semiconductor layer 13 is provided between the second semiconductor layer 12 and the first electrode 21 in the first direction Z and is electrically connected to the first electrode 21.

[0016] The fourth semiconductor layer 14 is, for example, a p-type collector layer in an IGBT. The p-type impurity concentration of the fourth semiconductor layer 14 is higher than the p-type impurity concentration of the second semiconductor layer 12. The fourth semiconductor layer 14 is provided between the second electrode 22 and the first semiconductor layer 11 in the first direction Z and is electrically connected to the second electrode 22.

[0017] The semiconductor section 10 may further include a fifth semiconductor layer 15 of the second conductivity type and a sixth semiconductor layer 16 of the first conductivity type.

[0018] The fifth semiconductor layer 15 is, for example, a p-type base contact layer in an IGBT. The p-type impurity concentration of the fifth semiconductor layer 15 is higher than the p-type impurity concentration of the second semiconductor layer 12. The fifth semiconductor layer 15 is provided between the second semiconductor layer 12 and the first electrode 21 and is electrically connected to the first electrode 21. The fifth semiconductor layer 15 is included in a mesa portion 30. On the second semiconductor layer 12 of the mesa portion 30, the third semiconductor layers 13 and the fifth semiconductor layers 15 are alternately arranged in the third direction Y.

[0019] The sixth semiconductor layer 16 is, for example, an n-type buffer layer in an IGBT. The n-type impurity concentration of the sixth semiconductor layer 16 is higher than the n-type impurity concentration of the first semiconductor layer 11. The sixth semiconductor layer 16 is provided between the fourth semiconductor layer 14 and the first semiconductor layer 11 in the first direction Z.

[0020] The first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 are provided between the semiconductor portion 10 and the first electrode 21 in the first direction Z. The first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 are electrically isolated from each other. The first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may be made of, for example, polycrystalline silicon.

[0021] 1 is repeated multiple times in the second direction X. That is, multiple first gate electrodes G1, multiple second gate electrodes G2, and multiple third gate electrodes G3 are arranged spaced apart from each other in the second direction X. The first gate electrodes G1, the second gate electrodes G2, and the third gate electrodes G3 extend in the third direction Y.

[0022] The first insulating film 41 is provided between the first gate electrode G1 and the semiconductor portion 10. The first gate electrode G1 is adjacent to the mesa portion 30 in the second direction X, with the first insulating film 41 interposed therebetween. The side surface of the first gate electrode G1 in the second direction X faces the first semiconductor layer 11, the second semiconductor layer 12, the third semiconductor layer 13, and the fifth semiconductor layer 15 of the mesa portion 30, with the first insulating film 41 interposed therebetween. The first insulating film 41 is also provided between the upper end of the first gate electrode G1 and the first electrode 21.

[0023] The second insulating film 42 is provided between the second gate electrode G2 and the semiconductor portion 10. The second gate electrode G2 is adjacent to the mesa portion 30 through the second insulating film 42 in the second direction X. The side surface of the second gate electrode G2 in the second direction X faces the first semiconductor layer 11, the second semiconductor layer 12, the third semiconductor layer 13, and the fifth semiconductor layer 15 of the mesa portion 30 through the second insulating film 42. The second insulating film 42 is also provided between the upper end of the second gate electrode G2 and the first electrode 21.

[0024] The third insulating film 43 is provided between the third gate electrode G3 and the semiconductor portion 10. The third gate electrode G3 is adjacent to the mesa portion 30 through the third insulating film 43 in the second direction X. The side surface of the third gate electrode G3 in the second direction X faces the first semiconductor layer 11, the second semiconductor layer 12, the third semiconductor layer 13, and the fifth semiconductor layer 15 of the mesa portion 30 through the third insulating film 43. The third insulating film 43 is also provided between the upper end of the third gate electrode G3 and the first electrode 21.

[0025] As the first insulating film 41, the second insulating film 42, and the third insulating film 43, for example, a silicon oxide film or a silicon nitride film can be used.

[0026] Let the area where the first gate electrode G1 and the third semiconductor layer 13 face each other through the first insulating film 41 be S1, the area where the second gate electrode G2 and the third semiconductor layer 13 face each other through the second insulating film 42 be S2, and the area where the third gate electrode G3 and the third semiconductor layer 13 face each other through the third insulating film 43 be S3. Then, S1≦S2<S3.

[0027] In the first embodiment, by making the number of the third gate electrodes G3 larger than the number of the second gate electrodes G2 and making the number of the second gate electrodes G2 equal to or more than the number of the first gate electrodes G1, S1≦S2<S3 is achieved. Between each mesa portion 30, the arrangement positions and volume ratios of the third semiconductor layer 13 and the fifth semiconductor layer 15 on the second semiconductor layer 12 are the same.

[0028] 6(a) to 6(c) are timing charts showing an example of a method for controlling the semiconductor device 1. FIG. 6(a) shows a timing chart showing an example of a method for controlling the semiconductor device 1. The timing chart shows a timing chart of a potential (first control potential) V applied to the first gate electrode G1. G1 6(b) shows the potential (second control potential) V applied to the second gate electrode G2. G2 6(c) shows the potential (third control potential) V applied to the third gate electrode G3. G3 Represents.

[0029] The first control potential V of the first gate electrode G1 G1 , the second control potential V of the second gate electrode G2 G2 , and the third control potential V of the third gate electrode G3 G3 are controlled independently of each other.

[0030] During operation of the semiconductor device 1, for example, the potential of the first electrode 21 is maintained at a potential lower than the potential of the second electrode 22. The semiconductor device 1 is turned on at a first time point t1 and turned off at a sixth time point t6.

[0031] At a first time point t1, a first control potential V applied to the first gate electrode G1 G1 is made higher than the first threshold voltage of the first gate electrode G1. As a result, a first channel (n-type inversion layer) is induced in a region of the second semiconductor layer 12 facing the first gate electrode G1. Electrons are injected from the first electrode 21 into the first semiconductor layer 11 via the third semiconductor layer 13 and the first channel. Correspondingly, holes are injected from the fourth semiconductor layer 14 into the first semiconductor layer 11 via the sixth semiconductor layer 16.

[0032] At the second time point t2, the second control potential V applied to the second gate electrode G2 G2is made higher than the second threshold voltage of the second gate electrode G2. As a result, a second channel (n-type inversion layer) is induced in a region of the second semiconductor layer 12 facing the second gate electrode G2. Electrons are injected from the first electrode 21 into the first semiconductor layer 11 via the third semiconductor layer 13 and the second channel. Correspondingly, holes are injected into the first semiconductor layer 11 from the fourth semiconductor layer 14 via the sixth semiconductor layer 16.

[0033] At a third time point t3, the third control potential V G3 is made higher than the third threshold voltage of the third gate electrode G3. As a result, a third channel (n-type inversion layer) is induced in a region of the second semiconductor layer 12 facing the third gate electrode G3. Electrons are injected from the first electrode 21 into the first semiconductor layer 11 via the third semiconductor layer 13 and the third channel. Correspondingly, holes are injected from the fourth semiconductor layer 14 into the first semiconductor layer 11 via the sixth semiconductor layer 16.

[0034] For example, the first time point t1, the second time point t2, and the third time point t3 are simultaneous. The first time point t1, the second time point t2, and the third time point t3 may be set at different times. In order to reduce turn-on loss of the semiconductor device 1, it is preferable that the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 are turned on simultaneously.

[0035] At a fourth time point t4 that is later than the first time point t1, the second time point t2, and the third time point t3, the third control potential V G3 is made lower than the third threshold voltage, whereby the third channel in the region of the second semiconductor layer 12 facing the third gate electrode G3 disappears.

[0036] At a fifth time point t5 after the fourth time point t4, the second control potential V G2 is made lower than the second threshold voltage, whereby the second channel in the region of the second semiconductor layer 12 facing the second gate electrode G2 disappears.

[0037] At a sixth time point t6 after the fifth time point t5, the first control potential VG1 is made lower than the first threshold voltage. As a result, the first channel in the region of the second semiconductor layer 12 facing the first gate electrode G1 disappears.

[0038] The period between the second time point t2 and the fifth time point t5 is longer than the period between the fifth time point t5 and the sixth time point t6. The period between the fourth time point t4 and the fifth time point t5 is longer than the period between the fifth time point t5 and the sixth time point t6.

[0039] The semiconductor device 1 is turned on and off by the first gate electrode G1. The second gate electrode G2 is turned off before the first gate electrode G1 when the semiconductor device 1 is turned off. The third gate electrode G3 is turned on only for a short time when the semiconductor device 1 is turned on.

[0040] According to the present embodiment, as described above, there is a relationship of S1≦S2<S3 in the area where each of the gate electrodes G1, G2, G3 faces the third semiconductor layer 13. As a result, at the time of turn-on, the amount of electrons injected into the first semiconductor layer 11 can be increased in a short time to reduce the turn-on loss. During the on period, by turning off the third gate electrode G3 (eliminating the third channel), the saturation current can be kept low and the short-circuit withstand capacity can be ensured. Also, by turning off the second gate electrode G2 before the first gate electrode G1, the amount of electrons injected into the first semiconductor layer 11 can be restricted, and the turn-off loss can be reduced. Therefore, according to the first embodiment, it is possible to reduce the switching loss when the semiconductor device 1 is turned on and off.

[0041] [Second Embodiment] FIG. 2 is a cross-sectional perspective view of a semiconductor device 2 according to the second embodiment. FIG. 3 is a cross-sectional view taken along line A-A in FIG. 2. FIG. 4 is a cross-sectional view taken along line B-B in FIG. 2.

[0042] In the second embodiment, by changing the volume ratio of the third semiconductor layer 13 in each mesa portion 30, the area where the third semiconductor layer 13 faces the first gate electrode G1 through the first insulating film 41, the area where the third semiconductor layer 13 faces the second gate electrode G2 through the second insulating film 42, and the area where the third semiconductor layer 13 faces the third gate electrode G3 through the third insulating film 43 are changed. As a result, when the area where the first gate electrode G1 and the third semiconductor layer 13 face each other through the first insulating film 41 is S1, the area where the second gate electrode G2 and the third semiconductor layer 13 face each other through the second insulating film 42 is S2, and the area where the third gate electrode G3 and the third semiconductor layer 13 face each other through the third insulating film 43 is S3, S1≦S2<S3 is satisfied. The number of the first gate electrodes G1, the number of the second gate electrodes G2, and the number of the third gate electrodes G3 may be the same as or different from each other.

[0043] Also in the second embodiment, as in the first embodiment, the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 are controlled. At turn-on, the amount of electron injection into the first semiconductor layer 11 can be increased in a short time to reduce the turn-on loss. During the on period, by turning off the third gate electrode G3, the saturation current can be kept low and the short-circuit withstand capacity can be ensured. Also, by turning off the second gate electrode G2 earlier than the first gate electrode G1, the amount of electron injection into the first semiconductor layer 11 can be restricted, and the turn-off loss can be reduced. Also in the second embodiment, it is possible to reduce the switching loss when the semiconductor device 2 is turned on and off.

[0044] [Third Embodiment] FIG. 5 is a cross-sectional perspective view of a semiconductor device 3 according to the third embodiment.

[0045] Also in the third embodiment, as in the second embodiment, by changing the area of the third semiconductor layer 13 facing the first gate electrode G1 through the first insulating film 41, the area of the third semiconductor layer 13 facing the second gate electrode G2 through the second insulating film 42, and the area of the third semiconductor layer 13 facing the third gate electrode G3 through the third insulating film 43, S1≦S2<S3 is achieved. Thereby, it becomes possible to reduce the switching loss when the semiconductor device 3 turns on and off.

[0046] Further, the fifth semiconductor layer 15 is not disposed on the upper surface of the mesa portion 30, but is located near the interface where the second semiconductor layer 12 and the third semiconductor layer 13 contact in the first direction Z. The first electrode 21 has a trench contact portion 21a. The trench contact portion 21a penetrates the third semiconductor layer 13 in the first direction Z and contacts the fifth semiconductor layer 15. By the trench contact portion 21a, the contact area between the first electrode 21 and the third semiconductor layer 13 can be increased, and the contact resistance between the first electrode 21 and the third semiconductor layer 13 can be reduced.

[0047] For example, in the upper portion of the mesa portion 30, n-type impurities can be implanted into the p-type second semiconductor layer 12 and then thermally diffused to form the n-type third semiconductor layer 13. When the implanted n-type impurities are thermally diffused, the trench contact portion 21a divides the upper portion of the mesa portion 30 in the second direction X. Therefore, in the mesa portion 30 between the first gate electrode G1 and the second gate electrode G2, the n-type impurities implanted into a region facing the second gate electrode G2 can be prevented from diffusing to a region facing the first gate electrode G1 by being blocked by the trench contact portion 21a. Furthermore, in the mesa portion 30 between the second gate electrode G2 and the third gate electrode G3, the n-type impurities implanted into a region facing the third gate electrode G3 can be prevented from diffusing to a region facing the second gate electrode G2 by being blocked by the trench contact portion 21a. Furthermore, in the mesa portion 30 between the third gate electrode G3 and the first gate electrode G1, the n-type impurity implanted into the region facing the third gate electrode G3 is blocked by the trench contact portion 21a and can be prevented from diffusing to the region facing the first gate electrode G1. That is, the trench contact portion 21a makes it easy to control the volume ratio of the third semiconductor layer 13 in each mesa portion 30.

[0048] In addition, even in the semiconductor device 1 of the first embodiment, the fifth semiconductor layer 15 can be provided near the interface where the second semiconductor layer 12 and the third semiconductor layer 13 meet in the first direction Z, and the first electrode 21 can be configured to have a trench contact portion 21a that reaches the fifth semiconductor layer 15.

[0049] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0050] Reference Signs List 1 to 3: semiconductor device, 10: semiconductor portion, 11: first semiconductor layer, 12: second semiconductor layer, 13: third semiconductor layer, 14: fourth semiconductor layer, 15: fifth semiconductor layer, 16: sixth semiconductor layer, 21: first electrode, 21a: trench contact portion, 22: second electrode, 30: mesa portion, 41: first insulating film, 42: second insulating film, 43: third insulating film, G1: first gate electrode, G2: second gate electrode, G3: third gate electrode

Claims

1. A first electrode; A second electrode; a semiconductor section provided between the first electrode and the second electrode, the semiconductor section having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of the second conductivity type; a first gate electrode, a second gate electrode, and a third gate electrode that are provided between the semiconductor portion and the first electrode, face the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and are electrically isolated from each other; a first insulating film provided between the first gate electrode and the semiconductor portion; a second insulating film provided between the second gate electrode and the semiconductor portion; a third insulating film provided between the third gate electrode and the semiconductor portion; Equipped with the second semiconductor layer is provided between the first semiconductor layer and the third semiconductor layer, the third semiconductor layer is provided between the second semiconductor layer and the first electrode and is electrically connected to the first electrode; the fourth semiconductor layer is provided between the first semiconductor layer and the second electrode and is electrically connected to the second electrode; where S1 is an area where the first gate electrode and the third semiconductor layer face each other with the first insulating film interposed therebetween, S2 is an area where the second gate electrode and the third semiconductor layer face each other with the second insulating film interposed therebetween, and S3 is an area where the third gate electrode and the third semiconductor layer face each other with the third insulating film interposed therebetween, S1≦S2<S3; a potential of the first gate electrode, a potential of the second gate electrode, and a potential of the third gate electrode are controlled independently of each other; At a first time point, a first control potential applied to the first gate electrode is set to be higher than a first threshold voltage of the first gate electrode; At a second time point, a second control potential applied to the second gate electrode is made higher than a second threshold voltage of the second gate electrode; At a third time point, a third control potential applied to the third gate electrode is made higher than a third threshold voltage of the third gate electrode; at a fourth time point that is later than the first time point, the second time point, and the third time point, the third control potential is made lower than the third threshold voltage; At a fifth time point that is later than the fourth time point, the second control potential is made lower than the second threshold voltage; At a sixth time point that is later than the fifth time point, the first control potential is made lower than the first threshold voltage.

2. A first electrode; A second electrode; a semiconductor section provided between the first electrode and the second electrode, the semiconductor section having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of the second conductivity type; a first gate electrode, a second gate electrode, and a third gate electrode that are provided between the semiconductor portion and the first electrode, face the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and are electrically isolated from each other; a first insulating film provided between the first gate electrode and the semiconductor portion; a second insulating film provided between the second gate electrode and the semiconductor portion; a third insulating film provided between the third gate electrode and the semiconductor portion; Equipped with the second semiconductor layer is provided between the first semiconductor layer and the third semiconductor layer, the third semiconductor layer is provided between the second semiconductor layer and the first electrode and is electrically connected to the first electrode; the fourth semiconductor layer is provided between the first semiconductor layer and the second electrode and is electrically connected to the second electrode; The semiconductor portion is a first mesa portion located between the first gate electrode and the second gate electrode; a second mesa portion located between the second gate electrode and the third gate electrode; a third mesa portion located between the third gate electrode and the first gate electrode; and the third semiconductor layer has different shapes in the first mesa portion, the second mesa portion, and the third mesa portion; A semiconductor device in which S1 is an area where the first gate electrode and the third semiconductor layer face each other via the first insulating film, S2 is an area where the second gate electrode and the third semiconductor layer face each other via the second insulating film, and S3 is an area where the third gate electrode and the third semiconductor layer face each other via the third insulating film, satisfies S1≦S2<S3.

3. 3. The semiconductor device according to claim 1, wherein the number of said third gate electrodes is greater than the number of said second gate electrodes, and the number of said second gate electrodes is equal to or greater than the number of said first gate electrodes.

4. 3. The semiconductor device according to claim 1, wherein the first electrode has a trench contact portion.

5. the semiconductor portion further includes a fifth semiconductor layer of a second conductivity type that is provided between the second semiconductor layer and the first electrode, is electrically connected to the first electrode, and has a second conductivity type impurity concentration higher than that of the second semiconductor layer; The semiconductor device according to claim 4 , wherein the trench contact portion penetrates the third semiconductor layer and contacts the fifth semiconductor layer.

6. A semiconductor device as described in claim 2, wherein the volume ratios of the third semiconductor layer in the first mesa portion, the second mesa portion, and the third mesa portion are different.

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