MEMORY DEVICE INCLUDING BOTTOM ELECTRODE BRIDGE AND METHOD FOR MANUFACTURING SAME - Patent application

Abstract

To provide a magnetic memory device and a method of forming the same.SOLUTION: A magnetic memory device includes a bottom electrode bridge, and a spin-orbit torque structure overlapping and physically coupled to the bottom electrode bridge. In an embodiment, the memory includes a first electrode located in a first via, a second electrode located in a second via, a spin-orbit torque structure physically and electrically coupled to the first electrode and the second electrode and overlapping the first electrode and the second electrode, and a magnetic tunnel junction located in the spin-orbit torque structure.SELECTED DRAWING: Figure 2

Description

[Background technology]

[0001] Semiconductor memory is used in integrated circuits in electronic applications, including, for example, radios, televisions, mobile phones, and personal computers. Semiconductor memory includes two broad categories: volatile memory and non-volatile memory. Volatile memory includes random access memory (RAM), which is further divided into two subcategories: static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they lose the information stored in them when power is removed.

[0002] Nonvolatile memory, on the other hand, can preserve its stored data. One type of nonvolatile semiconductor memory is magnetoresistive random-access memory (MRAM). Multiple MRAM cells can be arranged in an MRAM array, with each MRAM cell storing one bit of data. Each MRAM cell may include a magnetic tunnel junction (MTJ) stack, which includes two ferromagnetic plates separated by a thin insulator. The magnetic pole of the first ferromagnetic plate is fixed, while the magnetic pole of the second ferromagnetic plate is free. By changing the polarity of the second ferromagnetic plate, a logic "0" or a logic "1" can be stored in the MTJ. Summary of the Invention

[0003] An embodiment of the present disclosure aims to propose a memory including a first electrode located in a first via, a second electrode located in a second via, a spin-orbit torque (SOT) structure physically and electrically coupled to the first electrode and the second electrode and overlapping the first electrode and the second electrode, and a magnetic tunnel junction located in the SOT structure.

[0004] An embodiment of the present disclosure aims to propose a method for manufacturing a memory device, comprising the steps of forming a first bottom electrode bridge and a second bottom electrode bridge in a first dielectric layer, depositing a spin-orbit torque structure on the first dielectric layer, the first bottom electrode bridge and the second bottom electrode bridge, depositing a magnetic tunnel junction stack on the spin-orbit torque structure, forming a patterned photoresist on the magnetic tunnel junction stack having a first width in a first direction that is greater than a first distance in the first direction between the first bottom electrode bridge and the second bottom electrode bridge, and forming a magnetic tunnel junction by patterning the magnetic tunnel junction stack using the patterned photoresist as a mask.

[0005] An embodiment of the present disclosure aims to propose another memory device including a first dielectric layer located in a semiconductor substrate, first and second bottom electrodes located in the first dielectric layer, a spin-orbit torque structure located in the first and second bottom electrodes, and a magnetic tunnel junction located in the spin-orbit torque structure and overlapping with the first and second bottom electrodes in a first direction perpendicular to a major surface of the semiconductor substrate. [Brief explanation of the drawings]

[0006] Aspects of the present disclosure can be best understood based on the following detailed description taken in conjunction with the drawings, in which: It should be noted that, in accordance with industry standard practice, various features are not drawn to scale, and in fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. [Figure 1A] FIG. 1 is a circuit diagram of a memory array according to some embodiments. [Figure 1B] 1 illustrates a write path in a selected unit cell of a memory array according to some embodiments. [Figure 1C] 1 illustrates a read path in a selected unit cell of a memory array according to some embodiments. [Figure 2] 1 is a schematic three-dimensional view of a unit cell of a memory array according to some embodiments. [Figure 3] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 4] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 5] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 6] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 7A] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 7B] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 7C] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 8A] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 8B] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 8C] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 9A] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 9B] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 9C] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 10A] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 10B] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 10C] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 11A] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 11B] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 11C] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 12A] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 12B] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 12C] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 13] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 14] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 15A] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 15B] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 16A] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 16B] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 17A] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 17B] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. [Figure 18] 1A to 1C are cross-sectional views of intermediate stages in manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0007] The following disclosure provides many different embodiments or examples for implementing different features of the provided objectives. Below, specific examples of elements and arrangements are described to simplify the disclosure. Of course, these are merely examples and are not intended to limit the disclosure. For example, in the description, a first feature formed above or on a second feature may include an embodiment in which the first feature and the second feature are in direct contact, or an embodiment in which an additional feature is formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeatedly reference numbers and / or letters in various examples. This repetition is for simplicity and clarity and is not itself used to indicate a relationship between the various embodiments and / or configurations described.

[0008] Additionally, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to facilitate the description of the relationship of one element or feature to other elements or features shown in the figures. These spatially relative terms are intended to encompass different orientations during use or operation of the device other than the orientation depicted in the figures. A device can be positioned differently (e.g., rotated 90 degrees or at another orientation) and still have the same corresponding interpretation of the spatially relative descriptions used herein.

[0009] Various embodiments provide an improved method for forming a magnetoresistive random-access memory (MRAM) device and the MRAM device formed thereby. The method includes forming a bottom electrode bridge on a bottom electrode, forming a spin-orbit torque (SOT) structure on the bottom electrode bridge, forming a magnetic tunnel junction (MTJ) thin film stack on the SOT structure, and patterning the MTJ thin film stack and the SOT structure. The bottom electrode bridge can be formed from a material such as tungsten (W), platinum (Pt), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), aluminum (Al), combinations thereof, multilayers thereof, or the like. The bottom electrode bridge can be formed from a variety of materials, and forming the bottom electrode bridge from the listed materials can improve contact resistance between the bottom electrode and the SOT structure. The SOT structure and the MTJ thin film stack are patterned so that the SOT structure and the MTJ thin film stack at least partially overlap the bottom electrode bridges. The SOT structure can be patterned so that the opposing sides of the SOT structure do not extend laterally beyond the sides of a pair of adjacent bottom electrode bridges. The SOT structure is formed directly on the bottom electrode bridges and is in physical contact with the bottom electrode bridges. The bottom electrode bridges can be used as an etch stop layer for patterning the SOT structure to prevent over-etching of the SOT structure. This reduces damage to the underlying structure, improves the process window for patterning the SOT structure, reduces device defects, and increases device yield.In addition, the SOT structure can be fully etched while preventing shunting below the MTJ thin film stack, resulting in improved tunnel magnetoresistance (TMR) effect and improved device performance.

[0010] Figure 1A is a circuit diagram illustrating a memory array 100 according to some embodiments. Figure 1B illustrates a write path in a selected unit cell 102 of the memory array 100 of Figure 1A. Figure 1C illustrates a read path in a selected unit cell 102 of the memory array 100 of Figure 1A.

[0011] In FIG. 1A, the memory array 100 is a magnetoresistive random-access memory (MRAM) array. The memory array 100 includes a plurality of unit cells 102 arranged along rows and columns. The unit cells 102 in each row may be arranged along a direction X, while the unit cells 102 in each column may be arranged along a direction Y. In some embodiments, each column of unit cells 102 is coupled to a pair of write word lines WWL and read word lines RWL, and each column of unit cells 102 is coupled to a bit line BL and a pair of source lines SL. Each unit cell 102 may be defined between one of the write word lines WWL and one of the read word lines RWL, and between one of the bit lines BL and one of the source lines SL. The write word lines WWL and read word lines RWL may extend along the Y direction, and the bit lines BL and source lines SL may extend along the X direction.

[0012] Each unit cell 102 includes a magnetic tunnel junction (MTJ) 108 and a spin-orbit torque (SOT) structure 106. The MTJ 108 functions as a memory element, and the SOT structure 106 is used to switch the magnetization orientation and resistance of the MTJ 108. The magnetic orientation of ferromagnetic layers within the MTJ 108 determines the resistance of the MTJ 108. The MTJ 108 has a low resistance state when the magnetic orientations are parallel. The MTJ 108 has a high resistance state when the magnetic orientations are antiparallel. By changing the magnetic orientations of the ferromagnetic layers within the MTJ 108, the MTJ 108 can be programmed to store complementary logic states (e.g., a logic high state representing a high resistance state and a logic low state representing a low resistance state).

[0013] The MTJs 108 can be programmed using the spin Hall effect. Each MTJ 108 is formed on a spin-orbit torque (SOT) structure 106. During a program operation, a charging current flowing in-plane through the SOT structure 106 is converted into a perpendicular spin current by the spin Hall effect. The perpendicular spin current then flows into the ferromagnetic layer in the MTJ 108, switching the magnetic orientation of the ferromagnetic layer through the spin-orbit torque (SOT). Therefore, the memory array 100 may be referred to as a spin-orbit torque MRAM (SOT-MRAM) array. In this manner, the magnetic orientation of the MTJ 108 (e.g., the resistance of the MTJ 108) can be changed, and bit data can be programmed into the MTJ 108. During a read operation, the resistance state of the MTJ 108 can be sensed, and the bit data stored in the MTJ 108 can be read.

[0014] As shown in FIG. 1A , each unit cell 102 further includes a write transistor WT and a read transistor RT. The write transistor WT and the read transistor RT in each unit cell 102 are coupled to an SOT structure 106. The write transistor WT and the read transistor RT can be coupled to multiple portions of the SOT structure 106 on opposite sides of the MTJ 108, thereby placing the MTJ 108 on a write current path (e.g., the in-plane charging current) between the write transistor WT and the read transistor RT. Thus, the MTJ 108 can be programmed by a write current. The write transistor WT and the read transistor RT can be three-terminal devices. The gate terminal of each write transistor WT can be coupled to one side of a write word line WWL, and the gate terminal of each read transistor RT can be coupled to one side of a read word line RWL. The write transistor WT and the read transistor RT in each unit cell 102 are coupled to the SOT structure 106 via a first source / drain terminal and to one side of a source line SL via a second source / drain terminal. The write transistor WT and the read transistor RT in each unit cell 102 can be coupled to both source lines SL. One end of each MTJ 108 is coupled to the underlying SOT structure 106, and the other end of each MTJ 108 is coupled to one of the bit lines BL.

[0015] A word line driver circuit WD, which controls the switching of the write transistor WT and the read transistor RT via the write word line WWL and the read word line RWL, is coupled to the write word line WWL and the read word line RWL. A current source circuit CS is coupled to the source line SL. The current source circuit CS is arranged to provide a write current (e.g., the in-plane charging current) used to program the MTJ 108 and a read current used to sense the resistance state of the MTJ 108. The current source circuit CS is used in combination with the word line driver circuit WD. A bit line driver circuit BD is coupled to the bit line BL. The bit line driver circuit BD is used to sense the read current flowing through the MTJ 108 to recognize the resistance state of the MTJ 108.

[0016] 1A and 1B, during a program operation, the write transistor WT and the read transistor RT of the selected unit cell 102 are both turned on, and a write current WP (e.g., the in-plane charging current) flows through the write transistor WT, the read transistor RT, and the SOT structure 106 between the write transistor WT and the read transistor RT. As a result of spin-orbit interaction, the write current WP flowing through the SOT structure 106 generates a spin-orbit torque (SOT) in the MTJ 108, programming the MTJ 108. The write transistor WT and the read transistor RT are turned on by grounding the corresponding write word line WWL and the corresponding read word line RWL, and the write current WP is provided by setting a voltage difference between the two corresponding source lines SL. The bit line BL may be floating.

[0017] 1A and 1C, during a read operation, the read transistor RT of the selected unit cell 102 is turned on, while the write transistor WT of the selected unit cell 102 is turned off. A voltage difference can be set between the bit line BL and a source line SL coupled to the read transistor RT so that a read current RP flows through the MTJ 108 coupled between the read transistor RT and the bit line BL. The MTJ 108 can have different resistances depending on whether the ferromagnetic layers in the MTJ 108 have parallel magnetic orientations (e.g., indicating that the MTJ 108 is in a low resistance state) or antiparallel magnetic orientations (e.g., indicating that the MTJ 108 is in a high resistance state). This variable resistance affects the value of the read current RP and the value of the voltage drop across the MTJ 108. Therefore, the bit data (e.g., resistance state) stored in the MTJ 108 can be read. The source line SL coupled to the write transistor WT may be floating.

[0018] FIG. 2 is a three-dimensional schematic view of one of the unit cells 102 of FIG. 1A. In FIG. 2, the write transistor WT and the read transistor RT of the unit cell 102 are formed in a front-end-of-line (FEOL) structure FE of a device wafer. The gate terminal of the write transistor WT may be supplied by a write word line WWL on a substrate 200. Similarly, the gate terminal of the read transistor RT may be supplied by a read word line RWL on the substrate 200. The write word line WWL and the read word line RWL may be laterally spaced apart from each other and may extend along the direction Y. The source and drain terminals (not shown separately) of the write transistor WT are located on opposite sides of the write word line WWL, and the source and drain terminals (not shown separately) of the read transistor RT are located on opposite sides of the read word line RWL.

[0019] In an embodiment in which the write transistor WT and the read transistor RT are planar-type transistors, the write word line WWL and the read word line RWL are located on a planar surface of the substrate 200. The source and drain ends of the write transistor WT and the read transistor RT may be doped regions or epitaxial structures (not shown separately) formed in the substrate 200. In an embodiment in which the write transistor WT and the read transistor RT are fin-type transistors (e.g., FinFETs), the write word line WWL and the read word line RWL are located in fin structures on the substrate 200. The source and drain ends of the write transistor WT and the read transistor RT may be epitaxial structures (not shown separately) that may be formed in the fin structures on opposite sides of the write word line WWL and the read word line RWL. In embodiments in which the write transistor WT and the read transistor RT are nanostructure (e.g., nanosheet, nanowire, gate-all-around, etc.) field effect transistors (NSFETs), the stack of nanostructures on the substrate 200 is covered by a write word line WWL or a read word line RWL. The source and drain ends of the write transistor WT and the read transistor RT may be epitaxial structures (not shown separately) that can be formed to abut (e.g., laterally abut) the stack of nanostructures on opposite sides of the write word line WWL and the read word line RWL. Contact plugs 202 may be located at the source / drain ends of the write transistor WT and the read transistor RT. The contact plugs 202 are electrically coupled to the source / drain ends and provide connections between the source / drain ends and conductive elements coated thereon.

[0020] In some embodiments, a dummy word line DWL is formed between the write word line WWL and the read word line RWL. The dummy word line DWL, the write word line WWL, and the read word line RWL may extend in the same direction, e.g., along the direction Y. The gate terminal of a dummy transistor DT formed between the write transistor WT and the read transistor RT may be coupled to the dummy word line DWL. The dummy transistor DT may have the same or similar configuration as the write transistor WT and the read transistor RT. The write transistor WT and the read transistor RT may each share one of their source / drain terminals with the dummy transistor DT. In some embodiments, the dummy word line DWL is used to receive a gate voltage, which can ensure the dummy transistor DT is in an off state. This reduces interference between the write transistor WT and the read transistor RT. Therefore, the dummy transistor DT including the dummy word line DWL may be referred to as an isolation transistor.

[0021] The source lines SL, the SOT structures 106, and the MTJs 108, along with the bit lines BL, may be formed in a back-end-of-line (BEOL) structure BE, which is formed on a front-end-of-line (FEOL) structure FE. In some embodiments, the source lines SL coupled to the write transistor WT and the read transistor RT may be portions of a bottom metallization layer in the back-end-of-line (BEOL) structure BE, and the source lines SL may extend along the direction X. The source lines SL are coupled to the source / drain ends of the write transistor WT and the read transistor RT via contact plugs 202. The other of the source / drain ends of the write transistor WT and the read transistor RT is coupled to landing pads 204, which may be formed in the bottom metallization layer of the back-end-of-line (BEOL) structure BE. The landing pads 204 may be coupled to the source / drain ends of the write transistor WT and the read transistor RT via the contact plugs 202.

[0022] The SOT structure 106 and the MTJ 108 can be formed in the bottom metallization layer. The SOT structure 106 can be coupled to a landing pad 204 in the bottom metallization layer through a bottom via 206, along with a bottom electrode bridge 14. The bottom via 206 may also be referred to as a bottom electrode. As shown in FIG. 2 , the SOT structure 106 can extend at least partially above the bottom electrode bridge 14 and be physically and electrically coupled to the bottom electrode bridge 14. The bottom electrode bridge 14 may be included to prevent device defects due to overetching the SOT structure 106 and to improve contact resistance between the bottom via 206 and the SOT structure 106, thereby reducing device defects and improving device performance. The SOT structure 106 can be coupled to the source / drain ends of the write transistor WT and the read transistor RT through the bottom electrode bridge 14, the bottom via 206, the landing pad 204, and the contact plug 202. The MTJ 108 is formed on the SOT structure 106 between the bottom vias 206. The MTJ 108 is located in the path of the write current that flows through the bottom via 206. The bit line BL may be formed in a metallization layer above the MTJ 108 and may extend along the direction X. In some embodiments, the bit line BL is electrically connected to the MTJ 108 through the top via 208.

[0023] Figures 3-6, 7A-7C, 8A-8C, 9A-9C, 10A-10C, 11A-11C, 12A-12C, 13-14, 15A-15B, 16A-16B, 17A-17B, and 18 are cross-sectional and top views illustrating intermediate steps in forming the memory array 100 of Figure 1A. Figures 7B, 8B, 9B, 10B, 11B, 12B, 15A, 16A, and 17A are enlarged, detailed cross-sectional views illustrating intermediate steps in forming the bottom electrode bridge 14, the SOT structure 106, and the MTJ 108. 7C, 8C, 9C, 10C, 11C, 12C, 15B, 16B and 17B are enlarged, detailed top views showing intermediate steps in forming the bottom electrode bridge 14, the SOT structure 106 and the MTJ 108.

[0024] In FIG. 3 , the write transistor WT, the read transistor RT, and the dummy transistor DT are formed on a substrate 200. As described above with reference to FIGS. 1A-1C and 2 , each unit cell 102 can include one write transistor WT and one read transistor RT. In embodiments where the transistors are planar transistors, the write transistor WT includes a write word line WWL formed on the planar surface of the substrate 200 and a source / drain region 700 formed in the substrate 200. The read transistor RT includes a read word line RWL formed on the planar surface of the substrate 200 and a source / drain region 700 formed in the substrate 200. The write word line WWL and the read word line RWL are separated from the substrate 200 by a gate dielectric layer 702. In some embodiments, a dummy transistor DT is formed along with the write transistor WT and the read transistor RT. A dummy word line DWL can be formed between the write transistor WT and the adjacent read transistor RT and separated from the substrate 200 by a gate dielectric layer 702.

[0025] The write transistor WT, the read transistor RT, and the dummy transistor DT have been described as planar transistors. However, in some embodiments, the write transistor WT, the read transistor RT, and the dummy transistor DT may be FinFETs, NSFETs, etc., as described with reference to FIG. 2, and the configurations of the elements in the write transistor WT, the read transistor RT, and the dummy transistor DT may be modified accordingly.

[0026] Substrate 200 may be a semiconductor substrate, such as doped or undoped silicon, or the active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate may also include other semiconductor materials such as germanium, compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide, silicon germanium (SiGe), alloy semiconductors including GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates, such as multilayer substrates or graded substrates, may also be used.

[0027] 4, a dielectric layer 704 and contact plugs 202 are formed on the write transistor WT, the read transistor RT, and the dummy transistor DT. The dielectric layer 704 may cover the write transistor WT, the read transistor RT, and the dummy transistor DT. The contact plugs 202 may penetrate the dielectric layer 704 and be physically and electrically coupled to the source / drain regions 700. In some embodiments, the dielectric layer 704 and the contact plugs 202 are formed by a damascene process (e.g., a single damascene process).

[0028] In some embodiments, the dielectric layer 704 is formed of a suitable dielectric material, such as a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), SiOC, SiOCN, SiCN, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, or a combination thereof. In some embodiments, the dielectric layer 704 may be a low-k dielectric material, e.g., a dielectric material having a dielectric constant (k value) of less than about 3.0. In some embodiments, the contact plug 202 is fabricated from one or more of aluminum, cobalt, copper, a copper alloy, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, alloys thereof, or the like, or a combination thereof. The contact plug 202 can include a barrier layer and / or an adhesive layer surrounding the sides of the via, the barrier layer and / or adhesive layer being formed, for example, from one or more layers of titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, ruthenium, rhodium, platinum, other noble metals, other refractory metals, nitrides thereof, combinations thereof, or the like.

[0029] 5 , a dielectric layer 706, a source line SL, and a landing pad 204 are formed on the dielectric layer 704 and the contact plug 202. The dielectric layer 706 can laterally surround the source line SL and the landing pad 204. The source line SL and the landing pad 204 can be physically and electrically coupled to the contact plug 202. A pair of the source line SL and the landing pad 204 can be coupled to the source / drain region 700 of each write transistor WT through the contact plug 202. Similarly, a pair of the source line SL and the landing pad 204 can be coupled to the source / drain region 700 of each read transistor RT through the contact plug 202. In some embodiments, the dielectric layer 706, the source line SL, and the landing pad 204 are formed by a damascene process (e.g., a single damascene process). The dielectric layer 706 can be formed of a similar or the same material as the dielectric layer 704, and the source line SL and the landing pad 204 can be formed of a similar or the same material as the contact plug 202.

[0030] 6 , a dielectric layer 708 and a bottom via 206 are formed on the dielectric layer 706, the source line SL, and the landing pad 204. The bottom via 206 can penetrate the dielectric layer 708 and be physically and electrically coupled to the landing pad 204. Accordingly, a first source / drain region 700 of each write transistor WT is connected to a source line SL, and a second source / drain region 700 of each write transistor WT is coupled to the bottom via 206 via the landing pad 204 and the contact plug 202. Similarly, a first source / drain region 700 of each read transistor RT is coupled to a source line SL, and a second source / drain region 700 of each read transistor RT is coupled to the bottom via 206 via the landing pad 204 and the contact plug 202. In some embodiments, the dielectric layer 708 and the bottom via 206 are formed by a damascene process (e.g., a single damascene process). The dielectric layer 708 may be formed of a similar or the same material as the dielectric layer 704 , and the bottom via 206 may be formed of a similar or the same material as the contact plug 202 .

[0031] 7A-7C, a dielectric layer 716 is formed over the dielectric layer 708 and the bottom via 206. FIG. 7B is a detailed view of region 711 of FIG. 7A. FIG. 7C is a top view of region 711 of FIG. 7A. The dielectric layer 716 can be formed of a material similar to or the same as the dielectric layer 704. The dielectric layer 716 can be formed using any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), other similar processes, or a combination thereof. The dielectric layer 716 can be patterned to form an opening 715 that exposes the bottom via 206 and portions of the dielectric layer 708. A bottom electrode bridge can then be formed within the opening 715. The dielectric layer 716 can be patterned using an appropriate photolithography and etching process. For example, a photoresist structure (not separately shown) can be formed on the dielectric layer 716 and patterned. Using the patterned photoresist structure as an etch mask, the dielectric layer 716 can be etched to form the opening 715. The dielectric layer 716 can be etched by an appropriate etching process, such as a wet etching process or a dry etching process. The patterned photoresist structure can then be removed, for example, by an acceptable ashing process.

[0032] The portions of the dielectric layer 716 laterally retained between the adjacent write transistor WT and read transistor RT can have a width W1 in the range of about 20 nanometers to about 200 nanometers. By etching the dielectric layer 716, the remaining portions of the dielectric layer 716 between the write transistor WT and read transistor RT have a predetermined width that ensures that the bottom electrode bridges subsequently formed in the openings 715 are separated from each other, and that the SOT structures subsequently formed on the bottom electrode bridges extend to the bottom electrode bridges without being too long.

[0033] 8A-8C, the bottom electrode bridge layer 13 is formed on the dielectric layer 708, the dielectric layer 716, and the bottom via 206, and fills the opening 715. The bottom electrode bridge layer 13 may be formed of a suitable material, such as tungsten (W), platinum (Pt), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), aluminum (Al), combinations thereof, multilayers thereof, or the like. The bottom electrode bridge layer 13 may be deposited using a suitable process, such as CVD, PVD, atomic layer deposition (ALD), plating, or other similar processes. The bottom electrode bridge layer 13 may be formed of a conductive material that is highly etch-resistant to the material of the SOT structure to be subsequently formed, so that the bottom electrode bridge layer 13 can function as an etch stop layer.

[0034] 9A to 9C, a planarization process, such as CMP, is performed on the bottom electrode bridge layer 13 to form the bottom electrode bridge 14. After the planarization process, in a process modification, the top surfaces of the dielectric layer 716 and the bottom electrode bridge 14 may be flush with each other. Therefore, the top surface of the dielectric layer 716 is exposed through the bottom electrode bridge 14.

[0035] 10A-10C, a multilayer thin film stack 15 is formed on the bottom electrode bridge 14 and the dielectric layer 716. The multilayer thin film stack 15 includes an SOT structure 16, a free layer 18, a barrier layer 20, a reference layer 22, a pinned layer 24, a top electrode layer 26, and a patterned photoresist 28. The layers of the multilayer thin film stack 15 illustrated in FIGS. 10A-10C are representative examples, and SOT MRAM devices can be formed with different layers, different materials, different arrangements, different compositions, or different sizes, and such variations are considered within the scope of this disclosure. Depending on the materials being deposited, one or more appropriate deposition techniques can be used to deposit the layers of the multilayer thin film stack 15. Such deposition techniques include, for example, techniques such as CVD, PVD, ALD, sputtering, plating, or other similar processes, or combinations thereof.

[0036] The SOT structure 16 can be deposited on the dielectric layer 716 and the bottom electrode bridge 14. In some embodiments, the SOT structure 16 physically contacts the dielectric layer 716, and the SOT structure 16 is physically and electrically coupled to the bottom electrode bridge 14. The SOT structure 16 functions as a generator of spin-polarized current in the later-completed unit cell 102. Passing a current through the SOT structure 16 generates a transverse spin-polarized current, which is used to control the magnetic moment of the overlying free layer 18.

[0037] In some embodiments, the SOT structure 16 is formed of a heavy metal or metal alloy, such as tungsten (W), platinum (Pt), tantalum (Ta), multilayers thereof, alloys thereof, combinations thereof, or the like. The thickness of the SOT structure 16 may be in the range of about 3 nanometers to about 20 nanometers. In some embodiments, the SOT structure 16 may be formed of multiple sub-layers. For example, the SOT structure 16 may include multiple heavy metal layers and multiple dusting layers interspersed among the multiple heavy metal layers. The dusting layer may comprise an insulating or non-insulating material, and may include cobalt (Co), cobalt iron (CoFe), cobalt iron boron (CoFeB), tantalum (Ta), ruthenium (Ru), magnesium (Mg), magnesium oxide (MgO), iron oxide (FeOx), cobalt oxide (CoOx), tantalum oxide (TaOx), combinations, alloys, or composites thereof, or the like. In some embodiments, the top and bottom layers of the SOT structure 16 may include heavy metal layers. The SOT structure 16 may include any number of layers, for example, four heavy metal layers and three dusting layers. However, more or fewer heavy metal layers and dusting layers may be provided. The ratio of the total thickness of the dusting layers to the total thickness of the heavy metal layers in the SOT structure 16 may be within a range of about 1:19 to about 1:4. In some embodiments, the thickness of the multiple layers of the SOT structure 16 may be optimized for the composition and / or other properties of the SOT structure 16 .

[0038] The free layer 18 can be deposited on the SOT structure 16. The free layer 18 serves as a state-keeping layer in the unit cell 102, with its magnetic state determining the state of the unit cell 102. For example, the magnetic torque of the free layer 18 can be controlled (e.g., by controlling the current flowing through the SOT structure 16), and controlling the magnetic torque of the free layer 18 in this manner can cause the resistance of the unit cell 102 to be in a high-resistance state or a low-resistance state. Whether the unit cell 102 is in a high-resistance state or a low-resistance state depends on the relative orientations of the spin polarization of the free layer 18 and the reference layer 22. The free layer 18 can be formed of one or more ferromagnetic materials, such as one or more layers of CoFe, NiFe, CoFeB, CoFeBW, Ru, alloys thereof, or the like, or combinations thereof. The free layer 18 can include multiple layers of different materials, such as one layer of Ru between two layers of CoFeB. In some embodiments, the material of the free layer 18 includes a crystalline material that is deposited to have a particular crystalline orientation, such as a (100) orientation. The appropriate thickness of the free layer 18 can be determined by the composition of the free layer 18 and the magnetic properties of the free layer 18.

[0039] A barrier layer 20 can be deposited on the free layer 18. In some embodiments, the barrier layer 20 is formed of one or more materials, such as MgO, AlO, AlN, or the like, or a combination thereof. In some embodiments, the material of the barrier layer 20 comprises a crystalline material that is deposited to have a particular crystal orientation (e.g., a (100) orientation). The material of the barrier layer 20 can be deposited to have the same crystal orientation as the free layer 18. The thickness of the barrier layer 20 can be controlled to adjust the resistance (R MTJIt can be controlled. For example, when the barrier layer 20 is thick, the resistance of the MTJ 108 can be increased. The barrier layer 20 can be made thin enough so that electrons can tunnel through the barrier layer 20.

[0040] The reference layer 22 can be deposited on the barrier layer 20. The reference layer 22 may be formed of a ferromagnetic material, and the ferromagnetic material described above may be, for example, one or more layers of CoFe, NiFe, CoFeB, CoFeBW, alloys thereof, or other similar ones, or combinations thereof. In some embodiments, the material of the reference layer 22 includes a crystalline material deposited so as to have a specific crystal orientation, for example, a (100) orientation. The material of the reference layer 22 can be deposited so as to have the same crystal orientation as the barrier layer 20. The appropriate thickness of the reference layer 22 can be determined by the components of the reference layer 22 and the magnetism of the reference layer 22.

[0041] Due to the magnetic orientations of the reference layer 22 and the free layer 18, the resistance of the MTJ 108 changes, and this phenomenon is used to store data in the obtained MRAM cell. The reference layer 22 may be a permanent magnet with a fixed polarity, and the magnetic polarity of the free layer 18 can be changed by applying an electric field. When the polarity of the free layer 18 and the polarity of the reference layer 22 are the same, the MRAM cell is in a low-resistance state. When the polarity of the free layer 18 and the polarity of the reference layer 22 are opposite, the MRAM cell is in a high-resistance state.

[0042] The pinning layer 24 can be deposited on the reference layer 22. The pinning layer 24 may be arranged to pin the magnetic direction of the reference layer 22 by exchange coupling with the reference layer 22. In some embodiments, the pinning layer 24 is formed of an anti-ferromagnetic material. The anti-ferromagnet may be, for example, IrMn, PtMn, Ni x Mn 1-x (0.1 < x < 0.5) may be included.

[0043] In some embodiments, a synthetic antiferromagnet (SAF) structure (not separately shown) is provided on the reference layer 22. In such embodiments, the SAF structure may be located between the pinned layer 24 and the reference layer 22. The SAF structure can enhance pinning of the magnetic direction in the reference layer 22, and the SAF structure may include antiferromagnetic layers separated by non-magnetic spacer layers. The antiferromagnetic layers may include cobalt / platinum (Co / Pt) multilayers, cobalt / palladium (Co / Pd) multilayers, or the like, while the spacer layers may include ruthenium layers or the like. In some embodiments, the multilayer thin film stack 15 includes an SAF structure for pinning the magnetic direction in the reference layer 22, and the pinned layer 24 is omitted.

[0044] A top electrode layer 26 may be provided on the pinned layer 24. The top electrode layer 26 may be used to provide electrical connection to a conductive pattern coupled to the top of the MTJ 108. In some embodiments, the top electrode layer 26 may function as a hard mask layer. The top electrode layer 26 may be formed of any suitable material, such as titanium, titanium nitride, tantalum, tantalum nitride, tungsten, or the like, or a combination thereof.

[0045] A patterned photoresist 28 can be deposited on the top electrode layer 26. The patterned photoresist 28 serves as a mask used to etch the multiple layers of the multilayer thin film stack 15 to form the MTJ 108. A photoresist layer (not shown separately) can be deposited on the top electrode layer 26 by spin coating or other similar process. The photoresist layer can be patterned by exposing it to a patterning energy source (e.g., a patterning light source) and developing it to remove exposed or unexposed portions of the photoresist layer, thereby forming the patterned photoresist 28. As shown in FIG. 10C , the patterned photoresist 28 can have a circular (e.g., elliptical) shape in top view. However, in some embodiments, the patterned photoresist 28 can have a rectangular or other shape. The patterned photoresist 28 can have a width W2 in the range of about 20 nanometers to about 30 nanometers. The width of the patterned photoresist 28 can be greater than the width of a portion of the dielectric layer 716 disposed between a pair of adjacent bottom electrode bridges 14. In the subsequent etching, i.e., etching the SOT structure 16 simultaneously with the formation of the MTJ 108, the patterned photoresist 28 is provided with a predetermined width to ensure that the SOT structure 16 at least partially overlaps the bottom electrode bridge 14. Thus, during the etching of the SOT structure 16, the bottom electrode bridge 14 acts as an etching stop and prevents damage to the underlying structure.

[0046] 11A-11C, the top electrode layer 26, pinned layer 24, reference layer 22, barrier layer 20, free layer 18, and SOT structure 16 are patterned, and the patterning photoresist 28 is removed. The patterning photoresist 28 is used as a mask to pattern the underlying multilayers. The top electrode layer 26 is patterned to form a top electrode 27. The combination of the top electrode 27, pinned layer 24, reference layer 22, barrier layer 20, and free layer 18 forms each MTJ 108. One or more etching processes (e.g., anisotropic etching processes) can be used to pattern the MTJ 108. In some embodiments, the etching process can include reactive ion etching (RIE), neutral beam etching (NBE), or other similar processes, or a combination thereof. After etching the MTJ 108, the patterned photoresist 28 can be removed, for example, by a photoresist stripping process or an ashing process. As shown in FIG. 11C , the top electrode 27 can have a circular (e.g., elliptical) shape in top view. However, in some embodiments, the top electrode 27 can have a rectangular or other shape. The multilayer of the MTJ 108 can have tapered sidewalls that gradually narrow away from the substrate 200. The SOT structure 16 can have tapered sidewalls that gradually narrow away from the substrate 200 and are continuous with the tapered sidewalls of the MTJ 108.

[0047] 11A-11C show a portion of the SOT structure 16 being etched through, but as will be described in more detail below, the SOT structure 16 may remain relatively unetched after the formation of the MTJ 108, or may be etched through during the formation of the MTJ 108. In embodiments where the SOT structure 16 is etched through, the bottom electrode bridge 14 acts as an etch stop layer for etching the SOT structure 16. This prevents over-etching of the underlying structures and damage to the dielectric layer 716, increases the process window for the SOT structure 16, prevents shunting current below the MTJ 108, reduces device defects, and improves device performance.

[0048] 12A-12C, the SOT structure 16 is patterned to form SOT structures 106. The SOT structures 16 can be patterned using appropriate photolithography and etching techniques. As shown in FIG. 12C, the SOT structures 106 may have a rectangular shape in top view. However, in some embodiments, the SOT structures 106 may have a circular or other shape. Etching the SOT structures 16 during the formation of the MTJs 108 can result in the SOT structures 106 having a stepped structure. The top of the SOT structure 106 may have a circular shape in plan view, while the bottom of the SOT structure 106 may have a rectangular shape in plan view. As shown in FIGS. 12A-12C, the side surfaces of each SOT structure 106 may be laterally flanked by a pair of bottom electrode bridges 14. Therefore, the bottom electrode bridges 14 function as an etching stopper during etching of the SOT structures 16. This prevents over-etching of the underlying structures and prevents damage to the dielectric layer 716, increases the process window of the SOT structure 16, ensures good TMR, allows the SOT structure 16 to be etched, prevents shunting current below the MTJ 108, reduces device defects, and improves device performance. In some embodiments, the sides of the SOT structure 106 can be laterally aligned with the sides of the bottom electrode bridge 14.

[0049] 12A-12C, a dielectric layer 718 is formed on the structure of FIGS. 12A-12C, and a top via 208 is formed in the dielectric layer 718. For ease of explanation, the MTJ 108 and the SOT structure 106 are simplified in FIG. 13 and subsequent figures. The dielectric layer 718 can be deposited on the MTJ 108, the SOT structure 106, the bottom electrode bridge 14, and the dielectric layer 716. The dielectric layer 718 can be formed of a material similar to or the same as the dielectric layer 704, and the formation of the dielectric layer 718 can use an acceptable deposition process, such as spin coating, PVD, CVD, or other similar processes, or a combination thereof.

[0050] The top via 208 can be formed by patterning the dielectric layer 718 to form an opening (not shown separately) that exposes the MTJ 108. The dielectric layer 718 can be patterned using appropriate photolithography and etching processes. For example, a photoresist structure (not shown separately) can be formed on the dielectric layer 718 and patterned. The patterned photoresist structure can be used as an etching mask to etch the dielectric layer 718 to form the opening. The etching of the dielectric layer 718 can be performed using an appropriate etching process, such as wet etching or dry etching. The patterned photoresist structure can then be removed, for example, by an acceptable ashing process. A liner (not shown separately), such as a diffusion barrier layer or adhesion layer, is formed in the opening with a conductive material. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, copper alloy, silver, gold, tungsten, ruthenium, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from above the surface of the dielectric layer 718. The remaining portion of the liner, together with the conductive material, forms the top via 208 in the opening. The top via 208 may be physically and electrically coupled to the MTJ 108. The dielectric layer 718 may laterally surround the SOT structure 106, the MTJ 108, and the top via 208.

[0051] 14, a dielectric layer 720 and a bit line BL are formed on the dielectric layer 718 and the top via 208. The dielectric layer 720 may laterally surround the bit line BL. The bit line BL may be physically and electrically coupled to the top via 208. In some embodiments, the method used to form the dielectric layer 720 and the bit line BL includes a damascene process (e.g., a single damascene process). In some embodiments, the dielectric layer 718, the dielectric layer 720, the top via 208, and the bit line BL are formed by a dual damascene process.

[0052] 14, unit cells 102 are further formed. Each unit cell 102 includes a bit line BL, an MTJ 108, an SOT structure 106, two bottom electrode bridges 14, two bottom vias 206, two source lines SL, a write word line WWL, a read word line RWL, a write transistor WT, and a read transistor RT. The bottom electrode bridges 14 can reduce the contact resistance between the SOT structure 106 and the bottom vias 206. The bottom electrode bridges 14 act as an etch stop layer during patterning of the SOT structure 106, which prevents damage to underlying layers (e.g., the dielectric layer 716 and the dielectric layer 708), enhances the process window for patterning the SOT structure 106, ensures good TMR, reduces device defects, improves device performance, and increases yield.

[0053] Although the SOT structure 106 and the MTJ 108 are described as being formed between first and second metallization layers starting from the bottom of the BEOL structure BE, the SOT structure 106 and the MTJ 108 may be formed between other metallization layers adjacent above or below the BEOL structure BE, and more conductive features may be formed in the BEOL structure BE to route the SOT structure 106 and the MTJ 108. Further BEOL processes may be performed to form the semiconductor device. The semiconductor device may undergo a packaging process to form a packaged semiconductor device.

[0054] 15A and 15B illustrate an embodiment in which the SOT structure 106 is formed by etching through the SOT structure 16 during the etching process used to pattern the MTJ 108. The etching process used to etch through the SOT structure 16 and form the SOT structure 106 may be the same as or similar to the process discussed above in FIGS. 11A-11C, except that the SOT structure 106 is etched for a longer period of time. The multiple layers of the MTJ 108 may have tapered sidewalls that taper away from the substrate 200. The SOT structure 106 may include tapered sidewalls that taper away from the substrate 200 and are continuous with the tapered sidewalls of the MTJ 108.

[0055] As shown in FIGS. 15A and 15B , the SOT structure 106 at least partially overlaps the bottom electrode bridge 14. Opposing sides of the SOT structure 106 may be laterally located between opposing sides of the underlying bottom electrode bridge 14. The bottom electrode bridge 14 functions as an etch stop layer used in etching the SOT structure 16 to form the SOT structure 106. This prevents over-etching of the underlying structures (e.g., dielectric layer 716 and dielectric layer 708), preventing damage to the underlying structures, increasing the process window of the SOT structure 16, reducing device defects, and improving device yield. Forming the SOT structure 106 at least partially extending to the bottom electrode bridge also prevents shunt current below the MTJ 108, improving TMR, and improving device performance. The SOT structure 106 may be located between the bottom vias 206 but not overlapping them. 15B, the SOT structure 106 may have a circular (e.g., oval) shape in top view, however, in some embodiments, the SOT structure 106 and the MTJ 108 may have a rectangular or other shape.

[0056] 16A and 16B illustrate an embodiment in which the SOT structure 16 is essentially not etched in the etching process used to pattern the MTJ 108. The SOT structure 16 can be etched using the same or similar processes as discussed above in FIGS. 12A-12C. The SOT structure 106 can have a flat top surface rather than a stepped profile. In the embodiment of FIGS. 16A and 16B, the SOT structure 16 functions as an etch stop layer used to pattern the MTJ 108, while the bottom electrode bridge 14 functions as an etch stop layer used to pattern the SOT structure 106.

[0057] As shown in FIGS. 16A and 16B , the SOT structure 106 at least partially overlaps the bottom electrode bridge 14. Opposing sides of the SOT structure 106 may be laterally located between opposing sides of the underlying bottom electrode bridge 14. Using the bottom electrode bridge 14 as an etch stop layer during patterning of the SOT structure 106 can prevent over-etching of the underlying structures (e.g., dielectric layer 716 and dielectric layer 708), preventing damage to the underlying structures, increasing the process window of the SOT structure 106, reducing device defects, and improving device yield. Additionally, forming the SOT structure 106 at least partially extending over the bottom electrode bridge can prevent shunt current below the MTJ 108, improving TMR, and improving device performance. As shown in FIG. 16B , the SOT structure 106 can have a rectangular shape in top view. However, in some embodiments, the SOT structure 106 can have a circular or other shape.

[0058] 17A and 17B illustrate an embodiment in which the bottom electrode 107 is formed in the dielectric layer 708 using a dual damascene process. In this embodiment, the dielectric layer 716 is omitted, and the individual bottom electrode bridge 14 and bottom via 206 are replaced with the bottom electrode 107. The bottom electrode can be formed by patterning the dielectric layer 708 to form a first opening (not shown separately). The dielectric layer 708 can be patterned using appropriate photolithography and etching processes. For example, a first photoresist structure (not shown separately) can be formed on the dielectric layer 708 and patterned. The first patterned photoresist structure can be used as an etching mask to etch the dielectric layer 708 to form the first opening. The etching of the dielectric layer 708 can be performed using an appropriate etching process, such as wet etching or dry etching. The patterned photoresist structure can then be removed, for example, by an acceptable ashing process. This patterning process is then repeated using a second patterned photoresist to extend the first opening and form a second opening (not shown separately). The bottom electrode 107 is then deposited in the first and second openings. The bottom electrode 107 can be formed using a suitable material, such as tungsten (W), platinum (Pt), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), aluminum (Al), combinations thereof, multilayers thereof, or the like. The bottom electrode 107 can be deposited using a suitable process, such as CVD, PVD, ALD, plating, or other similar processes. The bottom electrode 107 can be formed of a conductive material that is highly etch-resistant with respect to the material of the SOT structure 106, allowing the bottom electrode 107 to function as an etch stop layer. Forming the bottom electrode 107 using a dual damascene process reduces the number of materials and process steps required to form the unit cell 102, thereby reducing costs and reducing the thickness of the unit cell 102.

[0059] The portions of the dielectric layer 708 laterally reserved between adjacent bottom electrodes 107 can have a width W1 in the range of about 20 nanometers to about 200 nanometers. The dielectric layer 708 is etched to ensure that the remaining portions of the dielectric layer 708 between the bottom electrodes 107 have a predetermined width, separating the bottom electrodes 107, and thereafter, the SOT structures 106 formed on the bottom electrodes 107 extend to the bottom electrodes 107 without being too long.

[0060] 18 illustrates the embodiment of FIGS. 17A and 17B after performing the same or similar processes as discussed in FIGS. 10A-10C, 11A-11C, 12A-12C, and 13-14 to form the SOT structure 106, the MTJ 108, the top via 208, the bit line BL, the dielectric layer 718 laterally surrounding the SOT structure 106, the MTJ 108, and the top via 208, and the dielectric layer 720 laterally surrounding the bit line BL. As explained above, forming the bottom electrode 107 using a dual damascene process reduces the materials and processes for forming the unit cell 102, reduces costs, and reduces the thickness of the unit cell 102, while still providing the same or similar effects as those achieved by including the bottom electrode bridge 14.

[0061] Advantages may be realized according to the embodiment. For example, the bottom electrode bridge 14 may be formed of multiple materials and may reduce the contact resistance between the bottom via 206 and the SOT structure 106. The bottom electrode bridge 14 may act as an etch stop during patterning of the MTJ 108 and the SOT structure 106 and prevent damage to underlying structures. The SOT structure 106 may be patterned to extend at least partially along the bottom electrode bridge 14, further reducing the contact resistance between the SOT structure 106 and the bottom electrode bridge 14, reducing shunting below the MTJ 108, and improving TMR. In this manner, device defects may be reduced, device yield may be increased, and device performance may be improved.

[0062] According to one embodiment, a memory includes a first electrode located in a first via, a second electrode located in a second via, a spin-orbit torque structure (SOT) physically and electrically coupled to the first electrode and the second electrode and overlapping the first electrode and the second electrode, and a magnetic tunnel junction (MTJ) located in the spin-orbit torque structure. In one embodiment, the spin-orbit torque structure has a stepped structure. In one embodiment, the spin-orbit torque structure includes a plurality of first side surfaces having a rectangular shape in a plan view, and the spin-orbit torque structure includes a plurality of second side surfaces having a circular shape in a plan view. In one embodiment, the magnetic tunnel junction has a circular shape together with the spin-orbit torque structure in a plan view. In one embodiment, the spin-orbit torque structure has a rectangular shape in a plan view, and the magnetic tunnel junction has a circular shape in a plan view. In one embodiment, a first portion of a top surface of the first electrode is physically coupled to the spin-orbit torque structure, and a second portion of a top surface of the first electrode is not in contact with the spin-orbit torque structure. In one embodiment, the first electrode is separated from the second electrode by a first distance in a first direction, and the magnetic tunnel junction has a first width in the first direction that is greater than the first distance. In one embodiment, the first distance is greater than or equal to 20 nanometers, and the first width is less than or equal to 30 nanometers. In one embodiment, the spin-orbit torque structure includes a multilayer stack including multiple alternating layers of a heavy metal material and a first material different from the heavy metal material. In one embodiment, the heavy metal material includes tungsten, platinum, or tantalum, and the first material includes cobalt, cobalt iron, cobalt iron boron, tantalum, ruthenium, magnesium, magnesium oxide, iron oxide, cobalt oxide, or tantalum oxide.

[0063] According to another embodiment, a method includes the steps of forming a first bottom electrode bridge and a second bottom electrode bridge in a first dielectric layer; depositing a spin-orbit torque structure on the first dielectric layer, the first bottom electrode bridge, and the second bottom electrode bridge; depositing a magnetic tunnel junction stack on the spin-orbit torque structure; forming a patterned photoresist on the magnetic tunnel junction stack having a first width in a first direction that is greater than a first distance in the first direction between the first bottom electrode bridge and the second bottom electrode bridge; and forming a magnetic tunnel junction by patterning the magnetic tunnel junction stack using the patterned photoresist as a mask. In one embodiment, the method further includes forming a first via and a second via in the second dielectric layer, depositing a first dielectric layer over the first via, the second via, and the second dielectric layer, and etching the first dielectric layer to form a plurality of first openings exposing the first via and the second via, wherein a first bottom electrode bridge and a second bottom electrode bridge electrically coupled to the first via and the second via, respectively, are formed in the plurality of first openings. In one embodiment, the spin-orbit torque structure is partially etched by patterning the magnetic tunnel junction stack, so that the spin-orbit torque structure has a step structure after patterning the magnetic tunnel junction stack. In one embodiment, the spin-orbit torque structure is etched by patterning the magnetic tunnel junction stack, so that the spin-orbit torque structure has a plurality of sidewalls continuous with the magnetic tunnel junction stack after patterning the magnetic tunnel junction stack.

[0064] According to yet another embodiment, a memory device includes a first dielectric layer located in a semiconductor substrate, first and second bottom electrodes located in the first dielectric layer, a spin-orbit torque structure located in the first and second bottom electrodes, and a magnetic tunnel junction located in the spin-orbit torque structure and overlapping the first and second bottom electrodes in a first direction perpendicular to a major surface of the semiconductor substrate. In one embodiment, the first and second bottom electrodes comprise tungsten, platinum, tantalum, tantalum nitride, titanium nitride, or aluminum. In one embodiment, the spin-orbit torque structure includes a multilayer stack including multiple alternating layers of a heavy metal material and a first material different from the heavy metal material, wherein a ratio of a total thickness of the multilayer including the first material to a total thickness of the multilayer including the heavy metal material is in the range of 1:19 to 1:4. In one embodiment, the spin-orbit torque structure includes four layers of the heavy metal material and three layers of the first material. In one embodiment, the spin-orbit torque structure is physically and electrically coupled to the first and second bottom electrodes. In one embodiment, the first bottom electrode is separated from the second bottom electrode in a second direction parallel to the major surface of the semiconductor substrate by a first distance greater than 20 nanometers, and the magnetic tunnel junction has a first width in the second direction less than 30 nanometers.

[0065] The above outlines the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present disclosure to achieve the same purposes and / or advantages of the embodiments presented herein. Those skilled in the art should recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made to such equivalent structures without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0066] 13 Bottom electrode bridge layer 14 Bottom Electrode Bridge 15 Multilayer Thin Film Stack 16,106 Spin-orbit torque (SOT) structure 18 Free Tier 20 Barrier Layer 22 Reference layer 24 Pinned Layer 26 Top electrode layer 27 Top electrode 28 Patterning Photoresist 100 memory array 102 unit cells 107 Bottom electrode 108 Magnetic Tunnel Junction (MTJ) 200 boards 202 Contact plug 204 Landing Pad 206 bottom via 208 Top Beer 700 Source / Drain Region 702 Gate dielectric layer 704, 706, 708, 716, 718, 720 Dielectric layers 711 area 715 Aperture BD bit line driver circuit BE Back End Line (BEOL) Structure BL bit line CS current source circuit DT dummy transistor DWL Dummy Word Line FE Front End Line (FEOL) Structure RP read current RT readout transistor RWL Read Word Line SL Source Line WD Word line driver circuit WP Write current WT write transistor WWL Write Word Line W1, W2 width X, Y direction

Claims

1. a first electrode located in a first via; a second electrode located in the second via; a spin-orbit torque structure physically and electrically coupled to the first electrode and the second electrode and overlapping the first electrode and the second electrode, the spin-orbit torque structure having a step structure with an upper wall, a lower wall horizontally offset from the upper wall, and a horizontal plane connecting the lower wall and the upper wall, the horizontal plane of the step structure overlapping the first electrode in its entirety, and in a cross-sectional view, a length of the horizontal plane of the step structure of the spin-orbit torque structure is shorter than a length of an interface formed by the first electrode and the spin-orbit torque structure; a magnetic tunnel junction located in the spin-orbit torque structure; Memory containing

2. The memory of claim 1 , wherein the spin-orbit torque structure includes a first side having a rectangular shape in a plan view, and the spin-orbit torque structure includes a second side having a circular shape in the plan view.

3. The memory of claim 1 , wherein the magnetic tunnel junction and the spin-orbit torque structure have a circular shape in a plan view.

4. The memory according to claim 1 , wherein the spin-orbit torque structure has a rectangular shape in a plan view, and the magnetic tunnel junction has a circular shape in the plan view.

5. 2. The memory of claim 1, wherein a first portion of a top surface of the first electrode is physically coupled to the spin-orbit torque structure, but a second portion of the top surface of the first electrode does not contact the spin-orbit torque structure.

6. forming a first bottom electrode bridge and a second bottom electrode bridge in a first dielectric layer; depositing a spin-orbit torque structure on the first dielectric layer, the first bottom electrode bridge, and the second bottom electrode bridge; depositing a magnetic tunnel junction stack onto the spin-orbit torque structure; forming a patterned photoresist on the magnetic tunnel junction stack, the patterned photoresist having a first width in a first direction greater than a first distance in the first direction between the first bottom electrode bridge and the second bottom electrode bridge; patterning the magnetic tunnel junction stack using the patterned photoresist as a mask to form a magnetic tunnel junction; after patterning the magnetic tunnel junction stack, etching the spin-orbit torque structure to form a patterned spin-orbit torque structure having a step structure with an upper wall, a lower wall horizontally offset from the upper wall, and a horizontal surface joining the lower wall and the upper wall, the horizontal surface of the step structure overlapping the first bottom electrode bridge entirely, and in a cross-sectional view, a length of the horizontal surface of the step structure of the spin-orbit torque structure is shorter than a length of an interface formed by the first bottom electrode bridge and the spin-orbit torque structure; A method for manufacturing a memory device comprising:

7. forming a first via and a second via in the second dielectric layer; depositing the first dielectric layer over the first via, the second via, and the second dielectric layer; etching the first dielectric layer to form a plurality of first openings exposing the first vias and the second vias, wherein the first bottom electrode bridge and the second bottom electrode bridge electrically coupled to the first vias and the second vias, respectively, are formed in the plurality of first openings; The method of claim 6 further comprising:

8. a first dielectric layer located on the semiconductor substrate; a first bottom electrode located within the first dielectric layer; a second bottom electrode located within the first dielectric layer; a spin-orbit torque structure located on the first bottom electrode and the second bottom electrode, wherein an overlapping area between the first bottom electrode and a bottom surface of the spin-orbit torque structure is larger than an overlapping area between the first bottom electrode and a top surface of the spin-orbit torque structure, the spin-orbit torque structure having a step structure with an upper wall, a lower wall horizontally offset from the upper wall, and a horizontal plane connecting the lower wall and the upper wall, the horizontal plane of the step structure overlapping the first bottom electrode in its entirety, and wherein in a cross-sectional view, the length of the horizontal plane of the step structure of the spin-orbit torque structure is shorter than the length of an interface formed by the first bottom electrode and the spin-orbit torque structure; a magnetic tunnel junction located in the spin-orbit torque structure and overlapping the first bottom electrode and the second bottom electrode in a first direction perpendicular to a major surface of the semiconductor substrate; 1. A memory device comprising:

9. 9. The memory device of claim 8, wherein the spin-orbit torque structure includes a multilayer stack including a plurality of alternating layers of a heavy metal material and a first material different from the heavy metal material, and wherein a ratio of a total thickness of the multilayer including the first material to a total thickness of the multilayer including the heavy metal material is in a range of 1:19 to 1:4.

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