Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing switching loss and improving reverse breakdown voltage.SOLUTION: A semiconductor device includes first and second semiconductor layers of a first conductivity type, a third semiconductor layer of a second conductivity type, a plurality of electrodes, and a plurality of first insulating films. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer and includes a first surface at a side opposite to the first semiconductor layer. The plurality of electrodes extends inside trenches from the first surface into the second semiconductor layer. The first insulating films are each provided between the third semiconductor layer and one of the plurality of electrodes and between the second semiconductor layer and the one of the plurality of electrodes. The plurality of electrodes includes a first electrode group and a second electrode group. The first electrode group is arranged in one column in a first direction and apart from each other by a first distance on the first surface. The second electrode group is arranged in another column in the first direction and apart from each other by the first distance, and is apart from the first electrode group by a second distance in a second direction. The first distance is equal to or less than 2 micrometers.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and diodes are used in power converters such as inverters. For example, diodes are connected in anti-parallel to IGBTs as so-called FWDs (Free Wheeling Diodes). To improve the efficiency of such power converters, it is important to improve the characteristics of the FWDs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-115596 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device that reduces switching loss and improves reverse breakdown voltage. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a second semiconductor layer of the first conductivity type, multiple electrodes, and multiple first insulating films. The second semiconductor layer is provided on the first semiconductor layer and contains first conductivity type impurities at a concentration lower than that of the first conductivity type impurities of the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer and has a first surface on the opposite side to the first semiconductor layer, extending in a first direction and a second direction intersecting the first direction. The multiple electrodes are provided on the second semiconductor layer and extend into multiple trenches from the first surface into the second semiconductor layer. The multiple first insulating films are provided between the multiple electrodes and the third semiconductor layer and between the multiple electrodes and the second semiconductor layer, respectively. The plurality of electrodes includes a first electrode group arranged in a row on the first surface, spaced a first distance apart in the first direction, and a second electrode group arranged in a row in the first direction, spaced the first distance apart, and spaced a second distance apart from the first electrode group in the second direction. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic diagram illustrating a semiconductor device according to an embodiment; [Figure 2] 5A and 5B are schematic diagrams showing characteristics of the semiconductor device according to the embodiment; [Figure 3] 10 is a graph showing other characteristics of the semiconductor device according to the embodiment. [Figure 4] 1 is a schematic diagram showing a trench arrangement in a semiconductor device according to an embodiment; [Figure 5] FIG. 10 is a schematic diagram showing a trench arrangement of a semiconductor device according to a modified example of the embodiment. [Figure 6] FIG. 10 is a schematic diagram showing a trench arrangement in a semiconductor device according to another modified example of the embodiment. [Figure 7] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a modified example of the embodiment. [Figure 8] 10A and 10B are schematic diagrams showing a method of providing wiring in a semiconductor device according to another modified example of the embodiment. [Figure 9]1A and 1B are schematic diagrams showing how wiring is provided in a semiconductor device according to an embodiment. [Figure 10] 10A and 10B are schematic diagrams showing another example of how to provide wiring in the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Identical parts in the drawings are assigned the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be explained as upward and the opposite direction as downward.

[0009] 1(a) and 1(b) are schematic diagrams showing a semiconductor device 1 according to an embodiment. Fig. 1(a) is a cross-sectional view taken along the XZ plane. Fig. 1(b) is a plan view showing a cross section taken along line AA in Fig. 1(a).

[0010] The semiconductor device 1 is, for example, a diode. The semiconductor device 1 is used, for example, integrated with an IGBT. Note that the following embodiments are merely examples, and the present invention is not limited to these.

[0011] 1(a), the semiconductor device 1 includes a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 12 of the first conductivity type, and a third semiconductor layer 13 of a second conductivity type. The second semiconductor layer 12 is provided on the first semiconductor layer 11. The third semiconductor layer 13 is provided on the second semiconductor layer 12. The second semiconductor layer 12 contains a lower concentration of first conductivity type impurities than the first conductivity type impurities of the first semiconductor layer 11.

[0012] The first semiconductor layer 11 is, for example, an n-type cathode layer. The third semiconductor layer 13 is, for example, a p-type anode layer. In the following description, the first conductivity type is referred to as n-type, and the second conductivity type is referred to as p-type.

[0013] The semiconductor device 1 further includes an electrode 30. The electrode 30 is provided inside a trench AT having a depth that reaches from the surface of the third semiconductor layer 13 to the second semiconductor layer 12. The electrode 30 extends into the third semiconductor layer 13 and the second semiconductor layer 12. The electrode 30 is made of, for example, conductive polysilicon. The electrode 30 is electrically insulated from the third semiconductor layer 13 and the second semiconductor layer 12 by, for example, an insulating film 33. The insulating film 33 is provided between the electrode 30 and the third semiconductor layer 13 and between the electrode 30 and the second semiconductor layer 12. The insulating film 33 is, for example, a silicon oxide film.

[0014] The first semiconductor layer 11 is electrically connected to the electrode 10 (cathode electrode). The third semiconductor layer 13 is electrically connected to the electrode 20 (anode electrode). The electrode 30 is, for example, electrically connected to the electrode 20 and has the same potential as the third semiconductor layer 13. However, the embodiment is not limited to this, and for example, the electrode 30 may be electrically connected to another electrode (not shown) and biased to a potential different from that of the third semiconductor layer 13.

[0015] 1(b), a plurality of electrodes 30 are provided, each provided inside a plurality of trenches AT. Some of the plurality of electrodes 30, for example, form a plurality of rows aligned in the Y direction, and the rows of electrodes 30 aligned in the Y direction are aligned in the X direction.

[0016] The multiple trenches AT are arranged such that regions located between adjacent trenches AT in the second semiconductor layer 12 are depleted under a predetermined reverse bias, for example, 1 V, applied between the first semiconductor layer 11 and the third semiconductor layer 13. In other words, the maximum width WM between adjacent trenches AT is set so that the space between the adjacent trenches AT is pinched off.

[0017] For example, the second semiconductor layer 12 When a line including any point on the XY plane is drawn from the point, the length of the line including the point sandwiched between different trenches AT is the distance between adjacent trenches AT. The distance or interval between trenches AT and the length of the trench are measured based on the position of the sidewall of the trench AT or the outer edge of the insulating film 33 of the trench AT. layer 12 The maximum distance between adjacent trenches AT in the above is the maximum width WM.

[0018] 2(a) to 2(c) and 3 are schematic diagrams showing the characteristics of the semiconductor device 1 according to the embodiment. 2(a) to 2(c) and 3 are cross-sectional views from the surface between adjacent trenches AT to the trench bottom when the depth of the trenches AT is, for example, 5.5 μm. 2(a) to 2(c) show the depletion layers in the third semiconductor layer 13 and the second semiconductor layer 12, respectively, under a predetermined reverse bias, for example, 1 V. FIG. 3 is a graph showing the reverse breakdown voltage of the semiconductor device 1.

[0019] As shown in Figures 2(a) to 2(c), the spacing between adjacent trenches AT (see Figure 1) is 1.6 micrometers (hereinafter, μm), 2.0 μm, and 2.5 μm, respectively. The equipotential surfaces shown in each figure represent the extent of the depletion layer.

[0020] 2(a) and 2(b), when the interval between adjacent trenches AT is 1.6 μm or 2.0 μm, the portions of the second semiconductor layer 12 located between adjacent trenches AT are depleted. On the other hand, when the interval between adjacent trenches AT is 2.5 μm, as shown in FIG. 2(c), the second semiconductor layer 12 includes portions that are not depleted between adjacent trenches AT.

[0021] 3 shows the relationship between the distance between adjacent trenches AT and the reverse breakdown voltage (breakdown voltage). As shown in FIG. 3, the breakdown voltage decreases as WM becomes wider.

[0022] The semiconductor device 1 according to the embodiment includes an electrode 30 having a trench structure in order to ensure a high reverse breakdown voltage and a high breakdown voltage between the anode and cathode. However, providing the electrode 30 reduces the area of the second semiconductor layer 12 in the XY plane. This narrows the conduction path of carriers and increases the carrier density (density of electrons and holes) in the third semiconductor layer 13 compared to when the electrode 30 is not provided.

[0023] For example, in power conversion devices such as inverters, it is desirable to improve characteristics such as on-state voltage (voltage drop in the conductive state), recovery time (time it takes for the recovery current to disappear during reverse recovery), safe operating area during recovery (operating area where breakdown does not occur even if voltage is applied while reverse recovery current is flowing), and current-voltage oscillation during recovery. Among these, it is important to shorten the recovery time while widening the safe operating area during recovery.

[0024] In the semiconductor device 1, by providing the trenches AT in which the electrodes 30 are arranged, a uniform avalanche phenomenon can be generated at the bottom of the trenches AT, thereby improving the breakdown voltage. Furthermore, by making the spacing WM between adjacent trenches AT narrower than the spacing at which pinch-off occurs when a reverse bias is applied, the reverse breakdown voltage can be improved.

[0025] However, the formation of trench AT increases the carrier density in second semiconductor layer 12 and third semiconductor layer 13. This deteriorates the recovery characteristics when transitioning from an on state to an off state, resulting in a larger recovery loss than when electrode 30 is not provided.

[0026] Therefore, in the semiconductor device 1, the density of holes injected from the third semiconductor layer 13 to the second semiconductor layer 12 is reduced by reducing the occupancy ratio of the trench AT in the XY cross section of the third semiconductor layer 13. This makes it possible to reduce recovery loss while suppressing a decrease in reverse withstand voltage and breakdown voltage.

[0027] 4(a) and 4(b) are schematic plan views illustrating the configuration of the semiconductor device 1 according to the embodiment. 4(a) and 4(b) are plan views illustrating the arrangement of the trenches AT. Note that the electrode 30, the insulating film 33, and the third semiconductor layer 13 are omitted from the arrangement diagram of the trenches AT shown below.

[0028] As shown in FIG. 4(a), the trench AT has, for example, a rectangular XY cross section with sides extending in the X and Y directions. The trenches AT are arranged in a matrix by lining up in rows in the X direction and lining up in columns in the Y direction. The length LY of the trench AT in the Y direction is longer than the length LX of the trench AT in the X direction. The distance between adjacent trenches AT is, for example, maximum in the diagonal direction of the arrangement of the trenches AT. The diagonal direction is the sum of LX+WDX in the X direction and LY+WDY in the Y direction. The maximum distance WM is, for example, the distance between the ends of adjacent trenches AT in the diagonal direction, and is 2 μm or less.

[0029] In the example shown in FIG. 4(b), the trenches AT included in a first column aligned in the Y direction among the plurality of trenches AT are arranged so as to be aligned in the X direction with the spaces between the trenches AT in a second column adjacent to the first column. The plurality of trenches AT are arranged in a matrix by being aligned in columns in the Y direction and in rows in the X direction. The distance WDY between adjacent trenches AT in the Y direction is narrower than the length LY of the trench AT in the Y direction. Furthermore, WDX is, for example, 1 μm or less. In this case, the distance WM between adjacent trenches AT is the maximum between adjacent trenches AT in the Y direction. The distance WM between adjacent trenches AT is, for example, 2 μm or less.

[0030] 5(a) and 5(b) are schematic diagrams illustrating the configuration of a semiconductor device 1 according to a modified example of the embodiment, and are plan views illustrating the arrangement of trenches AT.

[0031] As shown in FIG. 5(a), the trenches AT included in a first row of the multiple trenches AT aligned in the Y direction are arranged so as to be aligned in the X direction with the spaces between the trenches AT in a second row adjacent to the first row. The spacing WDY between adjacent trenches AT in the Y direction is wider than the length LY of the trench AT in the Y direction. Furthermore, WDX is, for example, 1 μm or less. In this case, too, the spacing WM between adjacent trenches AT is the maximum between adjacent trenches AT in the Y direction. The spacing WM between adjacent trenches AT is, for example, 2 μm or less.

[0032] 5(b), the trenches AT may be provided to have, for example, a circular XY cross section. The trenches AT are arranged, for example, in a diagonal direction of the arrangement. The interval WM between adjacent trenches AT in the diagonal direction is, for example, 2 μm or less.

[0033] 6(a) and 6(b) are schematic diagrams showing the configuration of a semiconductor device 1 according to another modified example of the embodiment, and are plan views illustrating the arrangement of trenches AT.

[0034] As shown in FIG. 6(a), the trench AT may be provided to have, for example, a circular ring-shaped cross section. The trench AT is provided to surround a portion of the third semiconductor layer 13 and a portion of the second semiconductor layer 12. The trenches AT are arranged, for example, in a diagonal direction. The distance WM between adjacent trenches AT in the diagonal direction is, for example, 2 μm or less. Furthermore, the inner diameter of the trench AT is, for example, 2 μm or less.

[0035] As shown in FIG. 6(b), the trench AT has, for example, a hexagonal ring-shaped cross section. The trenches AT are arranged, for example, diagonally. The distance WM between adjacent trenches AT in the diagonal direction is, for example, 2 μm or less. Furthermore, the inner diameter of the trench is, for example, 2 μm or less. Note that the outer shape of the cross section of the trench AT is not limited to a hexagon and may be another polygonal shape.

[0036] In the above arrangement of the trenches AT, it is preferable that the total XY cross-sectional area of the trenches AT is smaller than, for example, the area in the XY plane of the third semiconductor layer 13. This makes it possible to reduce the density of holes injected from the third semiconductor layer 13 into the second semiconductor layer 12, and thus the carrier density in the second semiconductor layer 12 can be reduced.

[0037] 7(a) and (b) are schematic diagrams showing semiconductor devices 2 and 3 according to modifications of the embodiment.

[0038] 7(a), the trench AT is provided in an inverted tapered shape such that the width in the X direction of the bottom located in the second semiconductor layer 12 is wider than the width in the X direction of the portion located in the third semiconductor layer 13. The electrode 30 provided inside the trench AT also has a similar XY cross-sectional shape.

[0039] In the semiconductor device 2, a distance WM in the X direction is ensured between the bottom surfaces of adjacent trenches AT. The distance WM is a distance at which pinch-off occurs under reverse bias. In contrast, the width of the third semiconductor layer 13 in the X direction is wider than the distance WM between the bottom surfaces of the trenches AT.

[0040] 7(b), the trench AT is provided so that the width in the X direction of a portion located in the second semiconductor layer 12 is wider than the width in the X direction of a portion located on the third semiconductor layer 13. The electrode 30 provided inside the trench AT also has a similar XY cross-sectional shape.

[0041] In the semiconductor device 3, a distance WM in the X direction is ensured between the portions of adjacent trenches AT located in the second semiconductor layer 12. The distance WM is a distance at which pinch-off occurs under reverse bias. In contrast, the width of the upper portion of the third semiconductor layer 13 in the X direction is wider than the distance WM.

[0042] Thus, in the semiconductor devices 2 and 3, the trenches AT are arranged such that the distance WM between the bottoms of adjacent trenches AT is narrower than the pinch-off distance. Since the distance between the tops of the third semiconductor layer 13 can be made wider than WM, it is possible to reduce the carrier density by increasing the occupancy rate of the third semiconductor layer 13 in the XY plane.

[0043] FIG. 8 is a schematic diagram showing how the wiring 40 of the semiconductor device 4 according to the embodiment is provided. In the semiconductor device 4, similar to the semiconductor device 1 shown in FIG. 1, the third semiconductor layer 13 and the electrode 30 are electrically connected by a wiring 40. The wiring 40 is, for example, a metal film provided on the third semiconductor layer 13, the electrode 30, and the insulating film 33. The wiring 40 is connected to the anode electrode 20. All of the semiconductor devices according to the embodiments can be provided with the wiring 40 as shown in FIG.

[0044] 9(a) and 9(b) are schematic diagrams showing how to provide wiring in the semiconductor device 5 according to the embodiment. In the semiconductor device 5 according to the embodiment, different potentials can be applied to the third semiconductor layer 13 and the electrode 30. In addition to the configuration of the semiconductor device 1, the semiconductor device 5 further includes an insulating film 50, wiring 40A, and wiring 40B. FIG. 9(a) is a schematic plan view showing an example in which wirings 40A and 40B are provided in the configuration of the semiconductor device shown in FIG. 4(a). FIG. 9(b) is a cross-sectional view taken along line BB shown in FIG. 9(a).

[0045] An insulating film 50 is provided on the third semiconductor layer 13, the electrode 30, and the insulating film 33. Wiring 40A (shown by dashed lines in FIG. 9(a)) is provided on the insulating film 50, extending in the X direction. The multiple wirings 40A are connected to electrodes 20A extending in the Y direction.

[0046] The wiring 40A is connected to the plurality of electrodes 30 via contacts 30c (shown by the hatched areas in FIG. 9(a)) that penetrate the insulating film 50. The wiring 40A is electrically isolated from the third semiconductor layer 13.

[0047] The wiring 40B is provided on the insulating film 50, extending in the X direction. The wiring 40B (shown by dashed lines in FIG. 9(a)) is connected to the third semiconductor layer 13 via contacts 13c that penetrate the insulating film 50. The multiple wirings 40B are connected to electrodes 20B that extend in the Y direction. The wiring 40B is electrically isolated from the electrode 30. The wiring 40A and the wiring 40B are provided at a distance from each other in the Y direction and are electrically insulated. The wiring 40A and the wiring 40B are provided alternately in the Y direction. The wiring 40A and the wiring 40B are, for example, metal films.

[0048] Fig. 10 is a schematic diagram showing another example of how to provide the wiring 40 in the semiconductor device 5 according to the embodiment. Fig. 10 is a schematic plan view showing an example in which wirings 40A and 40B are provided in the configuration of the semiconductor device shown in Fig. 4(b). In Fig. 10, the contact of wiring 40B is omitted.

[0049] As shown in FIG. 10, by providing the contact 30c of the wiring 40A at the Y-direction end of the trench AT, the ratio of the contact area to the area occupied by the wiring 40A can be made larger than when the contact 30c is provided in the center of the trench AT.

[0050] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0051] REFERENCE SIGNS LIST 1, 2, 3... semiconductor device; 10, 20, 20A, 20B, 30... electrode; 11... first semiconductor layer; 12... second semiconductor layer; 13... third semiconductor layer; 13c, 30c... contact; 33, 50... insulating film; 40, 40A, 40B... wiring; AT... trench

Claims

1. a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and containing first conductivity type impurities at a concentration lower than that of the first conductivity type impurities of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer and having a first surface extending in a first direction and a second direction intersecting the first direction on the opposite side to the first semiconductor layer; a plurality of electrodes provided on the second semiconductor layer and extending into the trenches from the first surface into the second semiconductor layer; a plurality of first insulating films respectively provided between the plurality of electrodes and the third semiconductor layer and between the plurality of electrodes and the second semiconductor layer; A semiconductor device as a diode comprising: a maximum distance between each of the plurality of trenches and the adjacent trenches around it is equal to or less than a distance at which a portion of the second semiconductor layer located between the two adjacent trenches is depleted when a predetermined voltage is applied between the first semiconductor layer and the third semiconductor layer.

2. a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and containing first conductivity type impurities at a concentration lower than that of the first conductivity type impurities of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer and having a first surface extending in a first direction and a second direction intersecting the first direction on the opposite side to the first semiconductor layer; a plurality of electrodes provided on the second semiconductor layer and extending into the trenches from the first surface into the second semiconductor layer; a plurality of first insulating films respectively provided between the plurality of electrodes and the third semiconductor layer and between the plurality of electrodes and the second semiconductor layer; A semiconductor device as a diode comprising: The semiconductor device, wherein the maximum distance between each of the plurality of trenches and the adjacent trenches around it is 2 micrometers or less.

3. The plurality of electrodes include a first electrode group arranged in a row on the first surface at a first distance apart in the first direction, and a second electrode group arranged in a row at the first distance apart in the first direction and spaced a second distance apart from the first electrode group in the second direction; the plurality of trenches have a first length in the first direction; The semiconductor device according to claim 1 , wherein the first length is longer than the first distance.

4. A first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and containing first conductivity type impurities at a concentration lower than that of the first conductivity type impurities of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer and having a first surface extending in a first direction and a second direction intersecting the first direction on the opposite side to the first semiconductor layer; a plurality of electrodes provided on the second semiconductor layer and extending into the trenches from the first surface into the second semiconductor layer; a plurality of first insulating films respectively provided between the plurality of electrodes and the third semiconductor layer and between the plurality of electrodes and the second semiconductor layer; A semiconductor device as a diode comprising: the plurality of electrodes include a first electrode group arranged in a row on the first surface at a first distance apart in the first direction, and a second electrode group arranged in a row in the first direction at the first distance apart and spaced a second distance apart from the first electrode group in the second direction, the first distance is equal to or less than a distance at which a portion of the second semiconductor layer located between the two adjacent trenches is depleted when a predetermined voltage is applied between the first semiconductor layer and the third semiconductor layer; A semiconductor device, wherein the maximum distance between each of the plurality of trenches and the surrounding adjacent trenches is the first distance.

5. A first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and containing first conductivity type impurities at a concentration lower than that of the first conductivity type impurities of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer and having a first surface extending in a first direction and a second direction intersecting the first direction on the opposite side to the first semiconductor layer; a plurality of electrodes provided on the second semiconductor layer and extending into the trenches from the first surface into the second semiconductor layer; a plurality of first insulating films respectively provided between the plurality of electrodes and the third semiconductor layer and between the plurality of electrodes and the second semiconductor layer; A semiconductor device as a diode comprising: the plurality of electrodes include a first electrode group arranged in a row on the first surface at a first distance apart in the first direction, and a second electrode group arranged in a row in the first direction at the first distance apart and spaced a second distance apart from the first electrode group in the second direction, the first distance is equal to or less than a distance at which a portion of the second semiconductor layer located between the two adjacent trenches is depleted when a predetermined voltage is applied between the first semiconductor layer and the third semiconductor layer; a surface area of the third semiconductor layer on the first surface being larger than a sum of an area of the first insulating films and an area of the electrodes on the first surface;

6. 6. The semiconductor device according to claim 3, wherein the second distance is equal to or less than 1 micrometer.

7. A first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and containing first conductivity type impurities at a concentration lower than that of the first conductivity type impurities of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer and having a first surface extending in a first direction and a second direction intersecting the first direction on the opposite side to the first semiconductor layer; a plurality of electrodes provided on the second semiconductor layer and extending into the trenches from the first surface into the second semiconductor layer; a plurality of first insulating films respectively provided between the plurality of electrodes and the third semiconductor layer and between the plurality of electrodes and the second semiconductor layer; A semiconductor device as a diode comprising: the plurality of electrodes include a first electrode group arranged in a row on the first surface at a first distance apart in the first direction, and a second electrode group arranged in a row in the first direction at the first distance apart and spaced a second distance apart from the first electrode group in the second direction, the first distance is equal to or less than a distance at which a portion of the second semiconductor layer located between the two adjacent trenches is depleted when a predetermined voltage is applied between the first semiconductor layer and the third semiconductor layer; A semiconductor device, wherein each of the electrodes has a cross section parallel to the first surface that is either circular or circular ring-shaped.

8. A first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and containing first conductivity type impurities at a concentration lower than that of the first conductivity type impurities of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer and having a first surface extending in a first direction and a second direction intersecting the first direction on the opposite side to the first semiconductor layer; a plurality of electrodes provided on the second semiconductor layer and extending into the trenches from the first surface into the second semiconductor layer; a plurality of first insulating films respectively provided between the plurality of electrodes and the third semiconductor layer and between the plurality of electrodes and the second semiconductor layer; A semiconductor device as a diode comprising: the plurality of electrodes include a first electrode group arranged in a row on the first surface at a first distance apart in the first direction, and a second electrode group arranged in a row in the first direction at the first distance apart and spaced a second distance apart from the first electrode group in the second direction, the first distance is equal to or less than a distance at which a portion of the second semiconductor layer located between the two adjacent trenches is depleted when a predetermined voltage is applied between the first semiconductor layer and the third semiconductor layer; a second electrode electrically connected to the first semiconductor layer; a second insulating film provided on the first plane; a first wiring provided above the first plane, electrically connected to the third semiconductor layer, and having a plurality of portions extending in the second direction; a plurality of wirings provided on the second insulating film, electrically connected to the plurality of electrodes, spaced apart from the first wirings in the first direction, and extending in the second direction.

9. A first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and containing first conductivity type impurities at a concentration lower than that of the first conductivity type impurities of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer and having a first surface extending in a first direction and a second direction intersecting the first direction on the opposite side to the first semiconductor layer; a plurality of electrodes provided on the second semiconductor layer and extending into the trenches from the first surface into the second semiconductor layer; a plurality of first insulating films respectively provided between the plurality of electrodes and the third semiconductor layer and between the plurality of electrodes and the second semiconductor layer; A semiconductor device as a diode comprising: the plurality of electrodes include a first electrode group arranged in a row on the first surface at a first distance apart in the first direction, and a second electrode group arranged in a row in the first direction at the first distance apart and spaced a second distance apart from the first electrode group in the second direction, the first distance is less than or equal to 2 micrometers; a second electrode electrically connected to the first semiconductor layer; a second insulating film provided on the first plane; a first wiring provided above the first plane, electrically connected to the third semiconductor layer, and having a plurality of portions extending in the second direction; a plurality of wirings provided on the second insulating film, electrically connected to the plurality of electrodes, spaced apart from the first wirings in the first direction, and extending in the second direction.

10. A semiconductor device described in any one of claims 1 to 9, wherein the shortest distance between adjacent trenches in the second semiconductor layer is shorter than the shortest distance between adjacent trenches in the third semiconductor layer.

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