Semiconductor devices and electronic devices

Abstract

Provided is a semiconductor device capable of achieving high detection efficiency and low jitter without depending on the thickening of a substrate. The semiconductor device comprises a plurality of pixels each having formed therein an avalanche photodiode element that photoelectrically converts incident light, wherein each of the plurality of pixels includes a substrate that includes a first semiconductor material and a lamination part that is laminated on a light incident-side surface of the substrate and includes a second semiconductor material that is different from the first semiconductor material.

Description

[Technical Field]

[0001] The present disclosure (present technology) relates to a semiconductor device and an electronic device including the semiconductor device. [Background technology]

[0002] Avalanche photodiodes (APDs) are available in two modes: Geiger mode, which operates at a bias voltage higher than the breakdown voltage, and linear mode, which operates at a slightly higher bias voltage close to the breakdown voltage. Geiger mode avalanche photodiodes are also called single photon avalanche photodiodes (SPADs).

[0003] A SPAD is a device that can detect a single photon at each pixel by multiplying carriers generated by photoelectric conversion in a high-electric field PN junction region provided at each pixel. Incidentally, there has long been a demand for improving the sensitivity of SPAD pixels, and to this end, a method has been proposed for improving detection efficiency, known as PDE (Photon Detection Efficiency), by ensuring a large area for the multiplication region (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-201005 Summary of the Invention [Problem to be solved by the invention]

[0005] However, because the SPAD uses silicon (Si) for the substrate, its sensitivity in the infrared (IR) region is low, and in order to increase the PDE, it is necessary to thicken the Si film. Increasing the Si thickness increases the time it takes for photoelectrically converted electrons to reach the multiplication region, which raises concerns about deterioration of jitter characteristics when used as a LIDAR (Laser Imaging Detection and Ranging).

[0006] The present disclosure has been made in view of the above circumstances, and aims to provide a semiconductor device and electronic equipment that can achieve high detection efficiency and low jitter without relying on thickening the substrate. [Means for solving the problem]

[0007] One aspect of the present disclosure is a semiconductor device comprising a plurality of pixels each having an avalanche photodiode element that photoelectrically converts incident light, and each of the plurality of pixels comprising a substrate including a first semiconductor material and a stacked portion stacked on the light incident surface of the substrate and including a second semiconductor material different from the first semiconductor material.

[0008] Another aspect of the present disclosure is an electronic device including a semiconductor device having a plurality of pixels, each of which is formed with an avalanche photodiode element that photoelectrically converts incident light, and each of the plurality of pixels having a substrate including a first semiconductor material and a stacked portion stacked on the light incident surface of the substrate and including a second semiconductor material different from the first semiconductor material. [Brief explanation of the drawings]

[0009] [Figure 1A] 1 is a schematic configuration diagram showing a pixel circuit using a SPAD as a solid-state imaging device according to a first embodiment of the present technology. [Figure 1B] 4A to 4C are diagrams for explaining an operation when a pixel is set as an active pixel in the first embodiment of the present technology. [Figure 2] 1 is a cross-sectional view showing an example of three pixels according to a first embodiment of the present technology. [Figure 3] FIG. 10 is a cross-sectional view showing an example of three pixels in a comparative example. [Figure 4] FIG. 10 is a cross-sectional view showing an example of three pixels in a modified example of the first embodiment of the present technology. [Figure 5] FIG. 10 is a cross-sectional view showing an example of three pixels according to a second embodiment of the present technology. [Figure 6] FIG. 10 is a cross-sectional view showing an example of three pixels according to a first modified example of the second embodiment of the present technology. [Figure 7] FIG. 10 is a cross-sectional view showing an example of three pixels in a second modified example of the second embodiment of the present technology. [Figure 8] FIG. 11 is a cross-sectional view showing an example of three pixels according to a third embodiment of the present technology. [Figure 9] FIG. 13 is a cross-sectional view showing an example of three pixels according to a first modified example of the third embodiment of the present technology. [Figure 10] FIG. 13 is a cross-sectional view showing an example of three pixels in a second modified example of the third embodiment of the present technology. [Figure 11] FIG. 13 is a cross-sectional view showing an example of three pixels according to a fourth embodiment of the present technology. [Figure 12] FIG. 13 is a cross-sectional view showing an example of three pixels in a modified example of the fourth embodiment of the present technology. [Figure 13] FIG. 13 is a cross-sectional view showing an example of three pixels according to a fifth embodiment of the present technology. [Figure 14] FIG. 20 is a cross-sectional view showing an example of three pixels according to a sixth embodiment of the present technology. [Figure 15] FIG. 23 is a cross-sectional view showing an example of three pixels in a first modified example of the sixth embodiment of the present technology. [Figure 16] FIG. 23 is a cross-sectional view showing an example of three pixels in a second modified example of the sixth embodiment of the present technology. [Figure 17] FIG. 20 is a cross-sectional view showing an example of three pixels according to a seventh embodiment of the present technology. [Figure 18] FIG. 23 is a cross-sectional view showing an example of three pixels in a modified example of the seventh embodiment of the present technology. [Figure 19]FIG. 20 is a cross-sectional view showing an example of three pixels according to an eighth embodiment of the present technology. [Figure 20] FIG. 23 is a cross-sectional view showing an example of three pixels in a first modified example of the eighth embodiment of the present technology. [Figure 21] FIG. 23 is a cross-sectional view showing an example of three pixels in a second modified example of the eighth embodiment of the present technology. [Figure 22] FIG. 13 is a cross-sectional view showing an example of three pixels according to a ninth embodiment of the present technology. [Figure 23] FIG. 23 is a cross-sectional view showing an example of three pixels in a first modified example of the ninth embodiment of the present technology. [Figure 24] FIG. 23 is a cross-sectional view showing an example of three pixels in a second modified example of the ninth embodiment of the present technology. [Figure 25] FIG. 23 is a cross-sectional view showing an example of three pixels according to a tenth embodiment of the present technology. [Figure 26] FIG. 29 is a cross-sectional view showing an example of three pixels in a first modified example of the tenth embodiment of the present technology. [Figure 27] FIG. 29 is a cross-sectional view showing an example of three pixels in a second modified example of the tenth embodiment of the present technology. [Figure 28] FIG. 23 is a cross-sectional view showing an example of three pixels according to an eleventh embodiment of the present technology. [Figure 29] FIG. 29 is a cross-sectional view showing an example of three pixels in a modified example of the eleventh embodiment of the present technology. [Figure 30] FIG. 29 is a cross-sectional view showing an example of three pixels according to a twelfth embodiment of the present technology. [Figure 31] FIG. 29 is a cross-sectional view showing an example of three pixels in a modified example of the twelfth embodiment of the present technology. [Figure 32] FIG. 29 is a cross-sectional view showing an example of three pixels according to a thirteenth embodiment of the present technology. [Figure 33] FIG. 29 is a cross-sectional view showing an example of three pixels in a modified example of the thirteenth embodiment of the present technology. [Figure 34] FIG. 29 is a cross-sectional view showing an example of three pixels according to a fourteenth embodiment of the present technology. [Figure 35] FIG. 29 is a cross-sectional view showing an example of three pixels in a modified example of the fourteenth embodiment of the present technology. [Figure 36] 1 is a block diagram of a light receiving element including pixels according to first to fourteenth embodiments of the present technology. [Figure 37] FIG. 37 is a block diagram showing an example of the configuration of an embodiment of a distance measuring system incorporating the light receiving element shown in FIG. 36. [Figure 38] FIG. 38 is a block diagram showing an example of the configuration of a smartphone as an electronic device equipped with the ranging system shown in FIG. 37. [Figure 39] 1 is a block diagram illustrating an example of the configuration of an embodiment of an imaging device as an electronic device to which the present technology is applied. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings referred to in the following description, identical or similar parts will be designated by identical or similar reference numerals, and redundant description will be omitted. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios. In this specification, the "first conductivity type" refers to either p-type or n-type, and the "second conductivity type" refers to either p-type or n-type, which is different from the "first conductivity type." Furthermore, the "+" or "-" attached to "n" or "p" means that the semiconductor region has a relatively high or low impurity density, respectively, compared to a semiconductor region without the "+" or "-" attached. However, even if the semiconductor region has the same "n" and "n" attached, this does not mean that the impurity density of each semiconductor region is strictly the same.

[0011] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed. The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0012] First Embodiment <Overall configuration example of solid-state imaging device> The solid-state imaging device as a semiconductor device according to the first embodiment can be applied to a distance measuring sensor that measures distances by a ToF (Time of Flight) method, etc. The solid-state imaging device has a photoelectric conversion function for light having a wavelength ranging from the visible region of about 380 nm or more and less than 780 nm to the infrared region of about 780 nm or more and less than 2400 nm.

[0013] A solid-state imaging device performs photoelectric conversion on incident light and captures an image using a two-dimensional array of multiple pixels, each having a SPAD that stores carriers such as electrons or holes. 1A shows a pixel circuit using a SPAD. A solid-state imaging device 1 includes a pixel P. The pixel P in FIG. 1A includes a SPAD element 2, a constant current source 102, a transistor 103, and an inverter 104.

[0014] The cathode of the SPAD element 2 is connected to the constant current source 102, and is also connected to the input terminal of the inverter 104 and the drain of the transistor 103. The anode of the SPAD element 2 is connected to the power supply VSPAD. The SPAD element 2 is a photodiode (single-photon avalanche photodiode) that, when incident light is incident, avalanche-amplifies the electrons generated and outputs a signal of the cathode voltage Vs. The power supply VSPAD supplied to the anode of the SPAD element 2 is set to, for example, a negative bias (negative potential) that is the same voltage as the breakdown voltage VBD of the SPAD element 2.

[0015] The constant current source 102 is configured, for example, with a P-type MOS transistor that operates in the saturation region, and performs passive quenching by acting as a quenching resistor. A power supply voltage VE (VE>0) is supplied to the constant current source 102. Note that the constant current source 102 may also use a pull-up resistor or the like instead of a P-type MOS transistor. To detect light (photons) with sufficient efficiency, a voltage (hereinafter referred to as excess bias) greater than the breakdown voltage VBD of the SPAD element 2 is applied to the SPAD element 2.

[0016] The drain of the transistor 103 is connected to the cathode of the SPAD element 2, the input terminal of the inverter 104, and the constant current source 102, and the source of the transistor 103 is connected to ground (GND). A gating control signal VG is supplied to the gate of the transistor 103 from a pixel drive unit that drives the pixel P. When pixel P is set as an active pixel, a Lo (Low) gating control signal VG is supplied from the pixel driving unit to the gate of transistor 103. On the other hand, when pixel P is set as an inactive pixel, a Hi (High) gating control signal VG is supplied from the pixel driving unit to the gate of transistor 103. The inverter 104 outputs a PFout signal of Hi when the cathode voltage VS as an input signal is Lo, and outputs a PFout signal of Lo when the cathode voltage VS is Hi.

[0017] Next, the operation when pixel P is set as an active pixel will be described with reference to Fig. 1B, which is a graph showing the change in the cathode voltage VS of the SPAD element 2 in response to the incidence of photons and the detection signal PFout. First, when pixel P is an active pixel, transistor 103 is set to off by the gating control signal VG at Lo.

[0018] 1B, the power supply voltage VE is supplied to the cathode of the SPAD element 2, and the power supply VSPAD is supplied to the anode, so that a reverse voltage greater than the breakdown voltage VBD is applied to the SPAD element 2, setting the SPAD element 2 in the Geiger mode. In this state, the cathode voltage VS of the SPAD element 2 is equal to the power supply voltage VE. When a photon is incident on the SPAD element 2 set in the Geiger mode, avalanche multiplication occurs and a current flows through the SPAD element 2.

[0019] If avalanche multiplication occurs at time t0 and current flows through SPAD element 2, then after time t0, current flows through SPAD element 2, causing current to flow through the P-type MOS transistor acting as constant current source 102, and a voltage drop occurs due to the resistance component of the MOS transistor. At time t2, when the cathode voltage VS of the SPAD element 2 falls below 0 V, it becomes lower than the breakdown voltage VBD, and so avalanche amplification stops. Here, the current generated by the avalanche amplification flows into the constant current source 102, causing a voltage drop, and the cathode voltage VS becomes lower than the breakdown voltage VBD due to the voltage drop, and this operation, which stops the avalanche amplification, is the quench operation.

[0020] When the avalanche amplification stops, the current flowing through the constant current source 102 (P-type MOS transistor) gradually decreases, and at time t4, the cathode voltage VS returns to the original power supply voltage VE, making it possible to detect the next new photon (recharge operation). The inverter 104 outputs a Lo (Low) PFout signal when the cathode voltage VS, which is the input voltage, is equal to or higher than a predetermined threshold voltage Vth (=VE / 2), and outputs a Hi (High) PFout signal when the cathode voltage VS is lower than the predetermined threshold voltage Vth. In the example of FIG. 1B, a Hi (High) PFout signal is output during the period from time t1 to time t3.

[0021] When pixel P is set to an inactive pixel, a high gating control signal VG is supplied from the pixel drive unit to the gate of transistor 103, turning on transistor 103. As a result, the cathode voltage VS of SPAD element 2 becomes 0 V (GND) and the anode-cathode voltage of SPAD element 2 becomes equal to or lower than the breakdown voltage VBD, so that even if photons enter SPAD element 2, it does not react.

[0022] <Pixel configuration> Fig. 2 shows cross sections of three pixels P. In Fig. 2, the solid-state imaging device 1 is illustrated as a back-illuminated type. Hereinafter, the surface of each component of the solid-state imaging device 1 on the light incident side (upper side in Fig. 2) will be referred to as the "back side," and the surface of each component of the solid-state imaging device 1 on the opposite side to the light incident side (lower side in Fig. 2) will be referred to as the "front side." Furthermore, since the three pixels P have the same structure, the pixel P on the left side in Fig. 2 will be described as a representative.

[0023] 2, in the solid-state imaging device 1, a substrate 10, a dislocation layer 20, a laminated material portion 30 having a laminated structure formed by crystal growth, a p-type well region 61, and an inter-brow film 62 are laminated in this order. An on-chip lens 50 is laminated on the back surface of the inter-brow film 62 for each pixel P. Furthermore, a wiring layer 40 is laminated on the surface of the substrate 10. The substrate 10 is formed of a semiconductor substrate made of, for example, single crystal silicon. The substrate 10 has a controlled concentration of impurities that exhibit p-type (first conductivity type) or n-type (second conductivity type), and a SPAD element 2 is formed for each pixel P.

[0024] In the wiring layer 40, wiring for supplying a voltage to be applied to the SPAD element 2, wiring for extracting electrons (carriers) generated in the SPAD element 2 from the substrate 10, and the like are formed. A pixel P includes a SPAD element 2 and a pixel separator 60. A plurality of pixels P are arranged in each of the X and Y directions, which are orthogonal to each other, via the pixel separator 60. A pixel P is electrically and optically separated from adjacent pixels P by the pixel separator 60.

[0025] The pixel separating section 60 includes a trench TrA (hereinafter referred to as a full trench TrA) in which a metal film 63 is sandwiched between glabella films 62 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. The pixel separating section 60 including the full trench TrA extends from the front surface of the substrate 10 to the rear surface of the laminate material section 30. The metal film 63 is formed of a light-reflecting metal film, such as a tungsten (W) film. The glabella film 62 is formed of an insulating film, such as a silicon oxide film.

[0026] The SPAD element 2 has a light absorbing section 3 provided in the laminate material section 30 and the dislocation layer 20, and a Geiger multiplier section 4 provided in the substrate 10 and the dislocation layer 20. The light absorbing section 3 is a photoelectric conversion section that absorbs light incident from the on-chip lens 50 through the glabrous film 62 and the p-type well region 61 to generate electrons (carriers). The light absorbing section 3 then transfers the electrons generated by photoelectric conversion to the Geiger multiplier section 4 by using an electric field.

[0027] The Geiger multiplier 4 avalanche-multiplies the electrons transferred from the light absorbing section 3. The Geiger multiplier 4 includes a p-type first electrode region 11 provided on the surface side of the substrate 10, and an n-type second electrode region 12 provided at a position shallower than the p-type first electrode region 11 to form a p-n junction with the p-type first electrode region 11, and an avalanche multiplication region 13 is formed at the interface of the p-n junction.

[0028] Within the substrate 10, the p-type first electrode region 11 is composed of a p-type semiconductor region with a high impurity concentration within the Geiger multiplier section 4, and the n-type second electrode region 12 is composed of an n-type semiconductor region with a high impurity concentration within the Geiger multiplier section 4. The avalanche multiplication region 13 is a high electric field region (depletion layer) formed at the interface of the pn junction between the p-type first electrode region 11 and the n-type second electrode region 12 by a negative voltage higher than the breakdown voltage applied to the n-type second electrode region 12, and multiplies electrons generated by one photon by the light absorption section 3.

[0029] The p-type well region 61 is provided along the wall surface of the pixel separator 60 and the back surface of the laminate material portion 30. The p-type well region 61 is composed of a p-type semiconductor region having a higher impurity concentration than the p-type first electrode region 11, and accumulates holes as carriers. The p-type well region 61 is electrically connected to the anode 43 formed in the wiring layer 40, allowing bias adjustment. This strengthens the hole concentration in the p-type well region 61 and strengthens pinning, making it possible to suppress the generation of dark current, for example.

[0030] The wiring layer 40 is formed on the surface side of the substrate 10 and includes a wiring 41, a cathode 42, and an anode 43. The cathode 42 is formed from an n-type semiconductor region having a higher impurity concentration than the n-type second electrode region 12, and is electrically connected to the n-type second electrode region 12 via the wiring 41.

[0031] Therefore, in the pixel P, a negative voltage higher than the breakdown voltage applied to the n-type second electrode region 12 can be supplied from a logic circuit (not shown) to the cathode 42. Also, in the pixel P, bias adjustment for the p-type well region 61 can be made possible via the anode 43.

[0032] In the solid-state imaging device 1 having the above configuration, light is irradiated, the irradiated light passes through the on-chip lens 50, and the transmitted light is photoelectrically converted by the SPAD element 2, thereby generating electrons. The generated electrons are then output to the inverter 104 by the wiring 41 in the wiring layer 40.

[0033] <Comparative Example> Incidentally, in the past, silicon (Si) was used for the substrate, which resulted in low sensitivity in the infrared (IR) region, and in order to increase the PDE, it was necessary to make the Si film thicker.

[0034] Fig. 3 is a cross-sectional view showing an example of a solid-state imaging device 1 in a comparative example. In Fig. 3, the same parts as those in Fig. 2 are given the same reference numerals and detailed description thereof will be omitted. In the comparative example, if the substrate 10 made of Si is made thicker, the time it takes for the photoelectrically converted electrons to reach the multiplication region becomes longer, and there is a concern that the jitter characteristics may deteriorate when used as a LIDAR (Laser Imaging Detection and Ranging).

[0035] <Measures according to the first embodiment> Returning to Figure 2, in the first embodiment of the present technology, a laminated material portion 30 containing a semiconductor material different from the semiconductor material of the substrate 10 is laminated on the light incident side surface of the substrate 10, thereby increasing the IR light absorption efficiency and improving the PDE.

[0036] The semiconductor materials included in the laminated material portion 30 include silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), cadmium telluride (CdTe), cadmium sulfur (CdS), etc., which can be grown as crystals on silicon. Since these semiconductor materials are not lattice-matched to silicon, a dislocation layer 20 must be interposed between the substrate 10 and the laminated material portion 30.

[0037] For example, SiGe, Ge, InGaAs, etc. are narrow bandgap semiconductors with a smaller bandgap energy than silicon, and have optical absorption sensitivity in the infrared (IR) light region, which is longer in wavelength than the visible light region.

[0038] In addition, when gallium arsenide (GaAs) or indium phosphide (InP) is used for the substrate 10, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), cadmium tellurium (CdTe), cadmium sulfur (CdS), etc. are used for the laminate material portion 30, just like silicon.

[0039] <Effects of the First Embodiment> As described above, according to the first embodiment, by stacking the laminated material section 30 containing a semiconductor material different from the silicon used in the substrate 10 on the light incident side surface of the substrate 10 via the dislocation layer 20, the IR light absorption efficiency can be increased and the PDE can be improved, and by making the film thickness of the pixel P thinner than that of a pixel P composed only of a silicon substrate, the jitter characteristics can be improved. Furthermore, according to the first embodiment, by providing the pixel isolation section 60 with the full trench TrA that insulates and separates the adjacent pixels P, crosstalk to the adjacent pixels P can be suppressed.

[0040] <Modification of the first embodiment> 4 is a cross-sectional view showing an example of a solid-state imaging device 1 according to a modified example of the first embodiment of the present technology. In FIG. 4, the same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0041] As shown in FIG. 4, a pixel separating portion 60A in the modified example is not provided with a full trench TrA in which a metal film 63 is sandwiched between glabella films 62 on both sides. This modification of the first embodiment also makes it possible to increase the IR light absorption efficiency and improve the PDE, and to improve jitter characteristics by making the film thickness of the pixel P thinner than that of a pixel P made only of a silicon substrate.

[0042] <Second embodiment> Fig. 5 is a cross-sectional view showing an example of a solid-state imaging device 1A according to the second embodiment of the present technology. In Fig. 5, the same parts as those in Fig. 2 above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0043] 5, the pixel separating portion 60B in the second embodiment includes a trench TrB (hereinafter referred to as a surface trench TrB) only on the substrate 10 side. This surface trench TrB sandwiches a metal film 65 between insulating films 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. The surface trench TrB extends from the surface of the substrate 10 to the back surface of the substrate 10.

[0044] <Effects of the second embodiment> As described above, according to the second embodiment, the solid-state imaging device 1A can be easily manufactured by forming the pixel separating section 60B by processing only the substrate 10.

[0045] <First Modification of the Second Embodiment> 6 is a cross-sectional view showing an example of a solid-state imaging device 1A according to a first modified example of the second embodiment of the present technology. In FIG. 6, the same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0046] 6, the pixel separating portion 60C in the first modified example of the second embodiment has a trench TrC (hereinafter referred to as a back surface trench TrC) only on the laminate material portion 30 side. This back surface trench TrC sandwiches both sides of a metal film 66 between inter-layer films 62 in a direction perpendicular to the thickness direction (Z direction) of the laminate material portion 30. The back surface trench TrC extends from the back surface of the laminate material portion 30 to the front surface of the laminate material portion 30.

[0047] <Operation and effect of the first modification of the second embodiment> As described above, according to the first modification of the second embodiment, the pixel separating section 60B is formed by processing only the laminated material section 30, and thus the solid-state imaging device 1A can be easily manufactured.

[0048] <Second Modification of the Second Embodiment> 7 is a cross-sectional view showing an example of a solid-state imaging device 1A according to a second modified example of the second embodiment of the present technology. In Fig. 7, the same parts as those in Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 7, a solid-state imaging device 1A according to the second modification of the second embodiment has a structure in which an on-chip lens 50 is not provided.

[0049] <Operation and effect of the second modification of the second embodiment> As described above, according to the second variant of the second embodiment, similarly to the first embodiment, the solid-state imaging device 1A can be easily manufactured by processing the substrate 10, the dislocation layer 20, and the laminated material portion 30 to form the pixel separation portion 60, and by providing the pixel separation portion 60 with a full trench TrA that insulates and separates adjacent pixels P, crosstalk to adjacent pixels P can be suppressed.

[0050] <Third embodiment> Fig. 8 is a cross-sectional view showing an example of a solid-state imaging device 1B according to the third embodiment of the present technology. In Fig. 8, the same parts as those in Fig. 2 above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0051] 8, a pixel separating portion 60D in the third embodiment extends from the front surface of the substrate 10 to the rear surface of the substrate 10. The pixel separating portion 60D includes a front surface trench TrB in which a metal film 65 is sandwiched between insulating films 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. A p-type well region 67 is provided on the wall surface of the pixel separating portion 60D. The laminated material portion 30 in the third embodiment is an n-type semiconductor region.

[0052] <Effects of the third embodiment> As described above, according to the third embodiment, the same effects as those of the second embodiment can be obtained, and the region capable of absorbing light can be expanded by not making the laminated material portion 30 p-type.

[0053] <First Modification of the Third Embodiment> 9 is a cross-sectional view showing an example of a solid-state imaging device 1B according to a first modified example of the third embodiment of the present technology. In Fig. 9, the same parts as those in Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0054] 9, the pixel separating portion 60E in the first modified example of the third embodiment has a trench TrC (hereinafter referred to as a back surface trench TrC) only on the laminate material portion 30 side. This back surface trench TrC sandwiches both sides of a metal film 66 between inter-layer films 62 in a direction perpendicular to the thickness direction (Z direction) of the laminate material portion 30. The back surface trench TrC extends from the back surface of the laminate material portion 30 to the front surface of the laminate material portion 30. A p-type well region 68 is provided on the wall surface of the pixel separating section 60E. A p-type well region 14 electrically connected to the anode 43 of the wiring layer 40 is provided on the front surface side of the substrate 10.

[0055] <Operation and effect of the first modified example of the third embodiment> As described above, according to the first modified example of the third embodiment, it is possible to obtain the same effects as those of the first modified example of the second embodiment, and also to suppress color mixing on the light incident side.

[0056] <Second Modification of the Third Embodiment> 10 is a cross-sectional view showing an example of a solid-state imaging device 1B according to a second modified example of the third embodiment of the present technology. In Fig. 10, the same parts as those in Fig. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0057] As shown in FIG. 10, a pixel separating portion 60F in the second modified example does not have a trench in which a metal film 65 is sandwiched between insulating films 64 on both sides, and only a p-type well region 67 is provided. This second modification of the third embodiment also provides the same effects as those of the third embodiment.

[0058] <Fourth embodiment> Fig. 11 is a cross-sectional view showing an example of a solid-state imaging device 1C according to the fourth embodiment of the present technology. In Fig. 11, the same parts as those in Fig. 2 above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0059] 11, a solid-state imaging device 1C according to the fourth embodiment is provided with an anti-reflection layer (RIG) 69 having a moth-eye structure on the back surface side of the laminated material portion 30. The RIG 69 prevents reflection of incident light.

[0060] <Effects of the Fourth Embodiment> As described above, according to the fourth embodiment, the provision of the RIG 69 makes it possible to further improve quantum efficiency and suppress flare by reducing surface reflection.

[0061] <Modification of the Fourth Embodiment> Fig. 12 is a cross-sectional view showing an example of a solid-state imaging device 1C according to a modification of the fourth embodiment of the present technology. In Fig. 12, the same parts as those in Fig. 11 are denoted by the same reference numerals and detailed description thereof will be omitted. As shown in FIG. 12, a solid-state imaging device 1C according to a modification of the fourth embodiment has a structure in which the on-chip lens 50 provided for each pixel P is eliminated.

[0062] <Operations and Effects of the Modification of the Fourth Embodiment> As described above, according to the first modification of the fourth embodiment, by eliminating the on-chip lens 50, surface reflection can be further reduced, thereby suppressing flare.

[0063] <Fifth embodiment> Fig. 13 is a cross-sectional view showing an example of a solid-state imaging device 1D according to the fifth embodiment of the present technology. In Fig. 13, the same parts as those in Fig. 2 above are denoted by the same reference numerals and detailed description thereof will be omitted. As shown in FIG. 13, in a solid-state imaging device 1D according to the fifth embodiment, a transparent electrode 44 functioning as an anode is provided between a p-type well region 61 and an on-chip lens 50.

[0064] The p-type well region 61 is electrically connected to the transparent electrode 44, allowing bias adjustment, thereby making it possible to increase the transfer electric field on the back surface. Therefore, in the pixel P, a negative voltage higher than the breakdown voltage applied to the n-type second electrode region 12 can be supplied from a logic circuit (not shown) to the cathode 42. Also, in the pixel P, bias adjustment for the p-type well region 61 can be made possible via the transparent electrode 44.

[0065] <Effects of the Fifth Embodiment> As described above, according to the fifth embodiment, the provision of the transparent electrode 44 eliminates the need for an anode on the front surface, thereby making it possible to enlarge the multiplication region and improve the multiplication probability. Furthermore, by increasing the transfer electric field on the back surface, further improvement in jitter characteristics can be expected.

[0066] Sixth Embodiment Fig. 14 is a cross-sectional view showing an example of a solid-state imaging device 1E according to the sixth embodiment of the present technology. In Fig. 14, the same parts as those in Fig. 2 above are denoted by the same reference numerals and detailed description thereof will be omitted. 14, in the solid-state imaging device 1E of the sixth embodiment, a substrate 10, a laminated material portion 30, a p-type well region 61, and an inter-ocular film 62 are laminated in this order. The laminated material portion 30 is made of a semiconductor material formed by crystal growth and lattice-matched to the substrate 10. For example, when gallium arsenide (GaAs) is used for the substrate 10, germanium (Ge) or gallium arsenide (GaAs) is used for the laminated material portion 30. Furthermore, for example, when indium phosphide (InP) is used for the substrate 10, indium gallium arsenide (InGaAs) is used for the laminated material portion 30.

[0067] <Effects of the Sixth Embodiment> As described above, according to the sixth embodiment, by using a semiconductor material that is lattice-matched to the substrate 10 for the laminated material part 30, defects at the bonding interface between the substrate 10 and the laminated material part 30 can be prevented.

[0068] <First Modification of the Sixth Embodiment> 15 is a cross-sectional view showing an example of a solid-state imaging device 1E according to a first modified example of the sixth embodiment of the present technology. In Fig. 15, the same parts as those in Fig. 14 are denoted by the same reference numerals and detailed description thereof will be omitted. As shown in FIG. 15, the laminated material portion 31 in the first modified example of the sixth embodiment has a multi-layered (quantum well) structure.

[0069] <Operation and effect of the first modified example of the sixth embodiment> According to the first modification of the sixth embodiment, the band gap is controlled by the stacked material part 31 having a quantum well structure, and the absorption efficiency of IR light is improved, so that specific wavelengths can be efficiently absorbed in the subbands of the quantum well structure.

[0070] <Second Modification of the Sixth Embodiment> 16 is a cross-sectional view showing an example of a solid-state imaging device 1E according to a second modified example of the sixth embodiment of the present technology. In Fig. 16, the same parts as those in Fig. 14 are denoted by the same reference numerals and detailed description thereof will be omitted. As shown in FIG. 16, the laminate material part 32 in the second modification of the sixth embodiment has a quantum dot structure.

[0071] <Operation and effect of the second modification of the sixth embodiment> According to the second modification of the sixth embodiment, the band gap is controlled by the stacked material part 32 having a quantum dot structure, and the absorption efficiency of IR light is improved, so that specific wavelengths can be efficiently absorbed in the subband of the quantum dot structure.

[0072] Seventh Embodiment Fig. 17 is a cross-sectional view showing an example of a solid-state imaging device 1F according to the seventh embodiment of the present technology. In Fig. 17, the same parts as those in Fig. 2 above are denoted by the same reference numerals and detailed description thereof will be omitted. As shown in FIG. 17, in a solid-state imaging device 1F according to the seventh embodiment, a substrate 10, an n-type laminated material portion 33, a p-type laminated material portion 34, a p-type well region 61, and an inter-eye film 62 are laminated in this order.

[0073] A SPAD element 5 is formed for each pixel P. The SPAD element 5 has a linear multiplication section 6 provided in the n-type laminate material section 33 and the p-type laminate material section 34, and a Geiger multiplication section 4 provided on the substrate 10. The linear multiplication section 6 absorbs light incident from the on-chip lens 50 via the glabrous membrane 62 and the p-type well region 61 to generate electrons (carriers) and linearly multiplies the electrons. The linear multiplication section 6 then transfers the linearly multiplied electrons to the Geiger multiplication section 4 by an electric field.

[0074] The linear multiplication section 6 forms a pn junction with the n-type laminated material section 33 and the p-type laminated material section 34, and forms a linear multiplication region at the interface of the pn junction. The linear multiplication region linearly multiplies electrons generated by one photon by a slightly high negative voltage near the breakdown voltage applied to the n-type laminated material section 33.

[0075] <Effects of the Seventh Embodiment> As described above, according to the seventh embodiment, a higher PDE can be realized by adopting a two-stage multiplication structure in which linear multiplication is performed by the linear multiplication section 6, rather than relying on Geiger multiplication by the Geiger multiplication section 4 alone.

[0076] <Modification of the Seventh Embodiment> Fig. 18 is a cross-sectional view showing an example of a solid-state imaging device 1E according to a modification of the seventh embodiment of the present technology. In Fig. 18, the same parts as those in Fig. 17 are denoted by the same reference numerals and detailed description thereof will be omitted. As shown in FIG. 18, in the modification of the seventh embodiment, a dislocation layer 20 is interposed between the substrate 10 and the n-type laminate material portion 33.

[0077] <Operations and Effects of the Modification of the Seventh Embodiment> Even in the modified example of the seventh embodiment, the same effects as those of the seventh embodiment can be obtained, and the substrate 10 and the n-type laminate material portion 33 can be laminated even if a semiconductor material that does not lattice match is used.

[0078] Eighth Embodiment Fig. 19 is a cross-sectional view showing an example of a solid-state imaging device 1G according to the eighth embodiment of the present technology. In Fig. 19, the same parts as those in Fig. 5 above are denoted by the same reference numerals, and detailed description thereof will be omitted. 19, in the solid-state imaging device 1G of the eighth embodiment, a substrate 10, a laminated material portion 70, a p-type well region 61, and an inter-ocular film 62 are laminated in this order. The laminated material portion 70 uses a semiconductor material made of a nanocrystalline film that is lattice-matched to the substrate 10. For example, the semiconductor material contained in the laminated material portion 70 uses palladium sulfide (PdS), CsPbI3, CuGaSe2, CuInSe2, etc. for silicon. The same applies to gallium arsenide (GaAs) and indium phosphide (InP).

[0079] The pixel separating section 60B in the eighth embodiment includes a trench TrB (hereinafter referred to as a surface trench TrB) only on the substrate 10 side. This surface trench TrB sandwiches a metal film 65 between insulating films 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. The surface trench TrB extends from the surface of the substrate 10 to the back surface of the substrate 10.

[0080] <Effects of the Eighth Embodiment> As described above, according to the eighth embodiment, it is possible to obtain an absorption efficiency higher than that of ordinary crystals by using nanocrystals in the laminate material portion 70. Furthermore, by forming the pixel separating portion 60B by processing only the substrate 10, the solid-state imaging device 1G can be easily manufactured.

[0081] <First Modification of Eighth Embodiment> Fig. 20 is a cross-sectional view showing an example of a solid-state imaging device 1G according to a first modified example of the eighth embodiment of the present technology. In Fig. 20, the same parts as those in Fig. 19 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0082] 20, the pixel separating portion 60B in the first modified example of the eighth embodiment includes a full trench TrA. In this full trench TrA, a metal film 63 is sandwiched between insulating films 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. The full trench TrA extends from the front surface of the substrate 10 to the rear surface of the laminate material portion 70.

[0083] <Operation and effect of the first modified example of the eighth embodiment> As described above, according to the first modification of the eighth embodiment, light leakage to adjacent pixels P can be prevented.

[0084] <Second Modification of Eighth Embodiment> 21 is a cross-sectional view showing an example of a solid-state imaging device 1G according to a second modified example of the eighth embodiment of the present technology. In Fig. 21, the same parts as those in Fig. 19 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0085] As shown in FIG. 21, a pixel isolation section 60F in the second modified example is not provided with a full trench TrA. This second modification of the eighth embodiment also provides the same effects as those of the eighth embodiment.

[0086] <Ninth embodiment> Fig. 22 is a cross-sectional view showing an example of a solid-state imaging device 1H according to the ninth embodiment of the present technology. In Fig. 22, the same parts as those in Fig. 19 are denoted by the same reference numerals and detailed description thereof will be omitted. As shown in FIG. 22, in a solid-state imaging device 1H according to the ninth embodiment, a transparent electrode 44 that functions as an anode is provided between a laminate material portion 70 and an on-chip lens 50.

[0087] The laminated material portion 70 is electrically connected to the transparent electrode 44, allowing for bias adjustment, thereby making it possible to increase the transfer electric field on the rear surface. Therefore, in the pixel P, a negative voltage higher than the breakdown voltage applied to the n-type second electrode region 12 can be supplied from a logic circuit (not shown) to the cathode 42. Also, in the pixel P, bias adjustment for the laminate material portion 70 can be made via the transparent electrode 44.

[0088] <Effects of the ninth embodiment> As described above, according to the ninth embodiment, the provision of the transparent electrode 44 eliminates the need for an anode on the front surface, thereby making it possible to enlarge the multiplication region and improve the multiplication probability. Furthermore, by increasing the transfer electric field on the rear surface, further improvement in jitter characteristics can be expected.

[0089] <First Modification of the Ninth Embodiment> Fig. 23 is a cross-sectional view showing an example of a solid-state imaging device 1H according to a first modified example of the ninth embodiment of the present technology. In Fig. 23, the same parts as those in Fig. 22 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0090] 23, the pixel separating portion 60B in the first modified example of the ninth embodiment includes a full trench TrA. This full trench TrA has a metal film 63 sandwiched between insulating films 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. The full trench TrA extends from the front surface of the substrate 10 to the back surface of the laminate material portion 70.

[0091] <Operation and effect of the first modified example of the ninth embodiment> As described above, according to the first modified example of the ninth embodiment, the same effects as those of the ninth embodiment can be obtained.

[0092] <Second Modification of the Ninth Embodiment> 24 is a cross-sectional view showing an example of a solid-state imaging device 1H according to a second modified example of the ninth embodiment of the present technology. In Fig. 24, the same parts as those in Fig. 22 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0093] As shown in FIG. 24, a pixel isolation section 60F in the second modified example is not provided with a full trench TrA. This second modification of the ninth embodiment also provides the same effects as those of the ninth embodiment.

[0094] <Tenth embodiment> Fig. 25 is a cross-sectional view showing an example of a solid-state imaging device 11 according to a tenth embodiment of the present technology. In Fig. 25, the same parts as those in Fig. 22 above are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 25, in a solid-state imaging device 1I according to the tenth embodiment, a substrate 10, an n-type laminated material portion 71, a p-type laminated material portion 72, and a transparent electrode 44 are laminated in this order.

[0095] A SPAD element 5 is formed for each pixel P. The SPAD element 5 has a linear multiplication section 6 provided in an n-type laminate material section 71 and a p-type laminate material section 72, and a Geiger multiplication section 4 provided on the substrate 10. The linear multiplication section 6 absorbs light incident from the on-chip lens 50 via the transparent electrode 44 to generate electrons (carriers), and linearly multiplies the electrons. The linear multiplication section 6 then transfers the linearly multiplied electrons to the Geiger multiplication section 4 by an electric field.

[0096] The linear multiplication section 6 forms a pn junction between an n-type laminated material section 71 and a p-type laminated material section 72, and forms a linear multiplication region at the interface of the pn junction. The linear multiplication region linearly multiplies electrons generated by one photon by a slightly high negative voltage near the breakdown voltage applied to the n-type laminated material section 71.

[0097] <Effects of the Tenth Embodiment> As described above, according to the tenth embodiment, the same effects as those of the ninth embodiment can be obtained, and a higher PDE can be realized by adopting a two-stage multiplication structure in which linear multiplication is performed by the linear multiplication unit 6, rather than relying on Geiger multiplication by the Geiger multiplication unit 4 alone.

[0098] <First Modification of the Tenth Embodiment> Fig. 26 is a cross-sectional view showing an example of a solid-state imaging device 1I according to a first modified example of the tenth embodiment of the present technology. In Fig. 26, the same parts as those in Fig. 25 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0099] 26, a pixel separating portion 60B in the first modified example of the tenth embodiment includes a full trench TrA. In the full trench TrA, a metal film 63 is sandwiched between insulating films 64 in a direction perpendicular to the thickness direction (Z direction) of the substrate 10. The full trench TrA extends from the front surface of the substrate 10 to the rear surface of the laminate material portion 30.

[0100] <Operation and effect of the first modified example of the tenth embodiment> As described above, according to the first modified example of the tenth embodiment, the same effects as those of the tenth embodiment can be obtained.

[0101] <Second Modification of the Tenth Embodiment> Fig. 27 is a cross-sectional view showing an example of a solid-state imaging device 1I according to a second modified example of the tenth embodiment of the present technology. In Fig. 27, the same parts as those in Fig. 25 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0102] As shown in FIG. 27, a pixel isolation section 60F in the second modified example is not provided with a full trench TrA. This second modification of the tenth embodiment also provides the same effects as those of the tenth embodiment.

[0103] <Eleventh embodiment> In the eleventh embodiment of the present technology, it is not necessary to bond the readout circuit formed for each pixel with Cu (copper), thereby reducing the manufacturing cost. Fig. 28 is a cross-sectional view showing an example of a solid-state imaging device 1J according to the eleventh embodiment of the present technology. In Fig. 28, the same parts as those in Fig. 25 above are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 28, in the solid-state imaging device 1J of the eleventh embodiment, a p-type substrate 81, an n-type substrate 82, an n-type laminated material portion 71, a p-type laminated material portion 72, and a transparent electrode 44 are laminated in this order.

[0104] An electronic readout circuit is mounted on a p-type substrate 81 and an n-type substrate 82. An n-type electrode region 811, an n-type well region 812, and a p-type electrode region 813 are formed in the p-type substrate 81. An n-type contact region 821 is formed in the n-type substrate 82.

[0105] The n-type contact region 821 is electrically connected to the n-type laminate material portion 71 and functions as a cathode. The n-type contact region 821 is also electrically connected to the n-type electrode region 811. The n-type electrode region 811 is connected to a logic circuit (not shown).

[0106] Therefore, in pixel P, a negative voltage higher than the breakdown voltage applied to the n-type laminated material portion 71 can be supplied from a logic circuit (not shown) to the n-type contact region 821 functioning as a cathode. Also, in pixel P, bias adjustment for the p-type laminated material portion 72 can be made possible via the transparent electrode 44.

[0107] In the solid-state imaging device 1J having the above configuration, light is irradiated, the irradiated light passes through the on-chip lens 50, and the transmitted light is photoelectrically converted in the n-type laminate material portion 71 and the p-type laminate material portion 72, thereby generating and multiplying electrons. The multiplied electrons are then read out from the n-type contact region 821 functioning as a cathode and output as a pixel signal to the vertical signal line 153 shown in FIG. 1 via the n-type electrode region 811 of the p-type substrate 81.

[0108] <Effects of the eleventh embodiment> As described above, according to the eleventh embodiment, by forming the electronic readout circuit on the p-type substrate 81 and the n-type substrate 82, the cost of bonding using Cu (copper) can be reduced.

[0109] <Modification of the eleventh embodiment> Fig. 29 is a cross-sectional view showing an example of a solid-state imaging device 1J according to a modification of the eleventh embodiment of the present technology. In Fig. 29, the same parts as those in Fig. 28 above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0110] 29, in the modification of the eleventh embodiment, a back surface trench TrC is provided in an n-type laminate material portion 71 and a p-type laminate material portion 72. In this back surface trench TrC, a metal film 66 is sandwiched between insulating films 64 on both sides.

[0111] <Operations and effects of the modified example of the eleventh embodiment> As described above, according to the modification of the eleventh embodiment, the same effects as those of the eleventh embodiment can be obtained.

[0112] <Twelfth embodiment> Fig. 30 is a cross-sectional view showing an example of a solid-state imaging device 1K according to the twelfth embodiment of the present technology. In Fig. 30, the same parts as those in Fig. 28 above are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in Figure 30, in the solid-state imaging device 1K of the 12th embodiment, a p-type substrate 81, an n-type substrate 82, a p-type laminated material portion 72, an n-type laminated material portion 71, and a transparent electrode 45 serving as a cathode are laminated in this order.

[0113] A hole readout circuit is mounted on the p-type substrate 81 and the n-type substrate 82. A p-type contact region 822 is formed on the n-type substrate 82. The p-type contact region 822 is electrically connected to the p-type laminate material portion 72 and functions as an anode. The p-type contact region 822 is also electrically connected to a p-type electrode region 813 formed in the n-type well region 812. The p-type electrode region 813 is connected to a logic circuit (not shown).

[0114] Therefore, in the pixel P, a negative voltage higher than the breakdown voltage applied to the p-type laminated material portion 72 can be supplied from a logic circuit (not shown) to the p-type contact region 822 functioning as an anode. Also, in the pixel P, bias adjustment for the n-type laminated material portion 72 can be made possible via the transparent electrode 45.

[0115] In the solid-state imaging device 1K having the above configuration, light is irradiated, the irradiated light passes through the on-chip lens 50, and the transmitted light is photoelectrically converted in the n-type laminate material portion 71 and the p-type laminate material portion 72, thereby generating and multiplying holes. The multiplied holes are then read out from the p-type contact region 822 functioning as an anode, and output as a pixel signal to the vertical signal line 153 shown in FIG. 1 via the p-type electrode region 813 of the p-type substrate 81.

[0116] <Effects of the twelfth embodiment> As described above, according to the twelfth embodiment, by forming the hole readout circuit on the p-type substrate 81 and the n-type substrate 82, the cost of bonding using Cu (copper) can be reduced.

[0117] <Modification of the twelfth embodiment> Fig. 31 is a cross-sectional view showing an example of a solid-state imaging device 1K according to a modification of the twelfth embodiment of the present technology. In Fig. 31, the same parts as those in Fig. 30 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0118] 31, in the modification of the twelfth embodiment, a back surface trench TrC is provided in an n-type laminate material portion 71 and a p-type laminate material portion 72. In this back surface trench TrC, a metal film 66 is sandwiched between insulating films 64 on both sides.

[0119] <Operations and Effects of the Modification of the Twelfth Embodiment> As described above, according to the modified example of the twelfth embodiment, the same effects as those of the twelfth embodiment can be obtained.

[0120] <Thirteenth embodiment> Fig. 32 is a cross-sectional view showing an example of a solid-state imaging device 1L according to the thirteenth embodiment of the present technology. In Fig. 32, the same parts as those in Fig. 28 above are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 32, in a solid-state imaging device 1L according to the thirteenth embodiment, a p-type substrate 81, an n-type substrate 82, an n-type laminated material portion 91, a p-type laminated material portion 92, and a transparent electrode 44 are laminated in this order.

[0121] The n-type laminated material portion 91 and the p-type laminated material portion 92 use a semiconductor material made of an organic film that is lattice-matched to the substrate 10. For example, the semiconductor material included in the n-type laminated material portion 91 and the p-type laminated material portion 92 uses F6-OC6F5 or the like for silicon.

[0122] An electronic readout circuit is mounted on a p-type substrate 81 and an n-type substrate 82. An n-type electrode region 811, an n-type well region 812, and a p-type electrode region 813 are formed in the p-type substrate 81. An n-type contact region 821 is formed in the n-type substrate 82.

[0123] The n-type contact region 821 is electrically connected to the n-type laminate material portion 91 and functions as a cathode. The n-type contact region 821 is also electrically connected to the n-type electrode region 811. The n-type electrode region 811 is connected to a logic circuit (not shown).

[0124] Therefore, in pixel P, a negative voltage higher than the breakdown voltage applied to n-type laminated material portion 91 can be supplied from a logic circuit (not shown) to n-type contact region 821 functioning as a cathode. Also, in pixel P, bias adjustment for p-type laminated material portion 92 can be made possible via transparent electrode 44.

[0125] In the solid-state imaging device 1L having the above configuration, light is irradiated, the irradiated light passes through the on-chip lens 50, and the transmitted light is photoelectrically converted in the n-type laminated material portion 91 and the p-type laminated material portion 92, thereby generating and multiplying electrons. The multiplied electrons are then read out from the n-type contact region 821 functioning as a cathode and output as a pixel signal to the vertical signal line 153 shown in FIG. 1 via the n-type electrode region 811 of the p-type substrate 81.

[0126] <Effects of the thirteenth embodiment> As described above, according to the thirteenth embodiment, the same effects as those of the eleventh embodiment can be obtained.

[0127] <Modification of the thirteenth embodiment> Fig. 33 is a cross-sectional view showing an example of a solid-state imaging device 1L according to a modification of the thirteenth embodiment of the present technology. In Fig. 33, the same parts as those in Fig. 32 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0128] 33, in the modification of the thirteenth embodiment, a back surface trench TrC is provided in an n-type laminate material portion 91 and a p-type laminate material portion 92. In this back surface trench TrC, a metal film 66 is sandwiched between insulating films 64 on both sides.

[0129] <Effects of the Modification of the Thirteenth Embodiment> As described above, according to the modification of the thirteenth embodiment, the same effects as those of the thirteenth embodiment can be obtained.

[0130] <Fourteenth embodiment> Fig. 34 is a cross-sectional view showing an example of a solid-state imaging device 1M according to the fourteenth embodiment of the present technology. In Fig. 34, the same parts as those in Fig. 32 above are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in Figure 34, in the solid-state imaging device 1M of the 14th embodiment, a p-type substrate 81, an n-type substrate 82, a p-type laminated material portion 92, an n-type laminated material portion 91, and a transparent electrode 45 serving as a cathode are laminated in this order.

[0131] A hole readout circuit is mounted on the p-type substrate 81 and the n-type substrate 82. A p-type contact region 822 is formed on the n-type substrate 82. The p-type contact region 822 is electrically connected to the p-type laminate material portion 92 and functions as an anode. The p-type contact region 822 is also electrically connected to a p-type electrode region 813 formed in the n-type well region 812. The p-type electrode region 813 is connected to a logic circuit (not shown).

[0132] Therefore, in the pixel P, a negative voltage higher than the breakdown voltage applied to the p-type laminated material portion 92 can be supplied from a logic circuit (not shown) to the p-type contact region 822 functioning as an anode. Also, in the pixel P, bias adjustment for the n-type laminated material portion 92 can be made possible via the transparent electrode 45.

[0133] In the solid-state imaging device 1M having the above configuration, light is irradiated, the irradiated light passes through the on-chip lens 50, and the transmitted light is photoelectrically converted in the n-type laminate material portion 91 and the p-type laminate material portion 92, thereby generating and multiplying holes. The multiplied holes are then read out from the p-type contact region 822 functioning as an anode, and output as a pixel signal to the vertical signal line 153 shown in FIG. 1 via the p-type electrode region 813 of the p-type substrate 81.

[0134] <Effects of the Fourteenth Embodiment> As described above, according to the fourteenth embodiment, the same effects as those of the twelfth embodiment can be obtained.

[0135] <Modification of the 14th embodiment> Fig. 35 is a cross-sectional view showing an example of a solid-state imaging device 1M according to a modification of the fourteenth embodiment of the present technology. In Fig. 35, the same parts as those in Fig. 34 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0136] 35, a back surface trench is provided in an n-type laminated material portion 91 and a p-type laminated material portion 92 in the modified example of the fourteenth embodiment. In this back surface trench, a metal film 66 is sandwiched between insulating films 64 on both sides.

[0137] <Operation and effect of the modified example of the fourteenth embodiment> As described above, according to the modification of the fourteenth embodiment, the same effects as those of the fourteenth embodiment can be obtained.

[0138] <Other embodiments> As described above, the present technology has been described using the first to fourteenth embodiments and modifications. However, the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Understanding the gist of the technical content disclosed in the first to fourteenth embodiments will make it clear to those skilled in the art that various alternative embodiments, examples, and operational techniques may be included in the present technology. Furthermore, the configurations disclosed in the first to fourteenth embodiments and modifications may be combined as appropriate within a range that does not result in contradiction. For example, configurations disclosed in multiple different embodiments may be combined, or configurations disclosed in multiple different modifications of the same embodiment may be combined.

[0139] <Configuration example of a photodetector> The pixels P according to the first to fourteenth embodiments described above can be applied to the pixels of the light receiving element shown in FIG. 36, for example. FIG. 36 is a block diagram of a light receiving element including the pixel P described above. The light receiving element 5010 in FIG. 36 includes a pixel driving section 5110, a pixel array 5120, a MUX (multiplexer) 5130, a time measurement section 5140, and an input / output section 5150.

[0140] The pixel array 5120 has a configuration in which pixels 5210, which detect incident photons and output a detection signal PFout indicating the detection result as a pixel signal, are arranged two-dimensionally in a matrix in row and column directions. Here, the row direction refers to the arrangement direction of the pixels 5210 in a pixel row, i.e., the horizontal direction, and the column direction refers to the arrangement direction of the pixels 5210 in a pixel column, i.e., the vertical direction. Due to space limitations in Figure 36, the pixel array 5120 is shown as having a pixel arrangement configuration of 10 rows and 12 columns, but the number of rows and columns of the pixel array 5120 is not limited to this and can be any number.

[0141] Pixel drive lines 5220 are wired horizontally for each pixel row in the matrix-like pixel arrangement of the pixel array 5120. The pixel drive lines 5220 transmit drive signals for driving the pixels 5210. The pixel drive unit 5110 drives each pixel 5210 by supplying a predetermined drive signal to each pixel 5210 via the pixel drive lines 5220. Specifically, the pixel drive unit 5110 controls the pixels 5210 arranged two-dimensionally in a matrix to act as active pixels and act as inactive pixels at a predetermined timing synchronized with a light emission timing signal supplied from the outside via the input / output unit 5150. An active pixel is a pixel that detects incident photons, and an inactive pixel is a pixel that does not detect incident photons. The configuration of this pixel 5210 can be any of the first to fourteenth embodiments of the pixel P described above.

[0142] 36, the pixel drive line 5220 is shown as a single wire, but may be configured with multiple wires. One end of the pixel drive line 5220 is connected to an output terminal of the pixel drive unit 5110 corresponding to each pixel row. The MUX 5130 selects the output from the active pixel in accordance with the switching between active and inactive pixels in the pixel array 5120. The MUX 5130 then outputs the pixel signal input from the selected active pixel to the time measurement unit 5140.

[0143] The time measurement unit 5140 generates a count value corresponding to the time from when the light source emits light to when the active pixel receives the light, based on the pixel signal of the active pixel supplied from the MUX 5130 and an emission timing signal indicating the emission timing of the light source (light source 6320 in FIG. 37). The emission timing signal is supplied from the outside (control unit 6420 of the imaging device 6220 in FIG. 37) via the input / output unit 5150.

[0144] The input / output unit 5150 outputs the count value of the active pixels supplied from the time measurement unit 5140 to the outside (signal processing circuit 6530 in FIG. 37) as a pixel signal. The input / output unit 5150 also supplies a light emission timing signal supplied from the outside to the pixel drive unit 5110 and the time measurement unit 5140.

[0145] <Example of distance measurement system configuration> FIG. 37 is a block diagram showing an example of the configuration of an embodiment of a distance measuring system incorporating the light receiving element 5010 of FIG. The ranging system 6110 is a system that captures a distance image using, for example, the ToF method. Here, the distance image is an image that detects the depth distance from the ranging system 6110 to the subject for each pixel and is composed of distance pixel signals based on the detected distances.

[0146] The ranging system 6110 includes an illumination device 6210 and an imaging device 6220 . The lighting device 6210 includes a lighting control unit 6310 and a light source 6320 . The illumination control unit 6310 controls the pattern in which the light source 6320 emits light under the control of the control unit 6420 of the imaging device 6220. Specifically, the illumination control unit 6310 controls the pattern in which the light source 6320 emits light in accordance with an illumination code included in an illumination signal supplied from the control unit 6420. For example, the illumination code consists of two values, 1 (High) and 0 (Low), and the illumination control unit 6310 turns on the light source 6320 when the value of the illumination code is 1, and turns off the light source 6320 when the value of the illumination code is 0.

[0147] The light source 6320 emits light in a predetermined wavelength range under the control of the illumination control unit 6310. The light source 6320 is formed, for example, by an infrared laser diode. Note that the type of light source 6320 and the wavelength range of the irradiated light can be set arbitrarily depending on the application of the distance measurement system 6110, etc. The imaging device 6220 is a device that receives reflected light that is generated when light (irradiated light) emitted from the lighting device 6210 is reflected by the subject 6120, the subject 6130, etc. The imaging device 6220 includes an imaging unit 6410, a control unit 6420, a display unit 6430, and a storage unit 6440.

[0148] The imaging unit 6410 includes a lens 6510, a light receiving element 6520, and a signal processing circuit 6530. Lens 6510 forms an image of incident light on the light receiving surface of light receiving element 6520. Lens 6510 may have any configuration, and for example, lens 6510 may be configured by a group of multiple lenses.

[0149] The light receiving element 6520 is composed of, for example, a sensor using a SPAD for each pixel. Under the control of the control unit 6420, the light receiving element 6520 receives reflected light from the object 6120, the object 6130, etc., and supplies the resulting pixel signal to the signal processing circuit 6530. This pixel signal represents a digital count value that counts the time from when the illumination device 6210 emits irradiation light to when the light receiving element 6520 receives the light. A light emission timing signal that indicates the timing at which the light source 6320 emits light is also supplied from the control unit 6420 to the light receiving element 6520. The light receiving element 5010 of FIG. 36 that includes the above-mentioned pixel P is adopted as the configuration of this light receiving element 6520.

[0150] The signal processing circuit 6530 processes pixel signals supplied from the light receiving element 6520 under the control of the control unit 6420. For example, the signal processing circuit 6530 detects the distance to the subject for each pixel based on the pixel signals supplied from the light receiving element 6520 and generates a distance image indicating the distance to the subject for each pixel. Specifically, the signal processing circuit 6530 acquires the time (count value) from when the light source 6320 emits light to when each pixel of the light receiving element 6520 receives the light multiple times (e.g., thousands to tens of thousands of times) for each pixel. The signal processing circuit 6530 creates a histogram corresponding to the acquired time. Then, by detecting peaks in the histogram, the signal processing circuit 6530 determines the time it takes for light emitted from the light source 6320 to be reflected by the subject 6120 or the subject 6130 and return. Furthermore, the signal processing circuit 6530 performs a calculation to determine the distance to the object based on the determined time and the speed of light. The signal processing circuit 6530 supplies the generated distance image to the control unit 6420.

[0151] The control unit 6420 is configured with a control circuit, a processor, etc., such as an FPGA (Field Programmable Gate Array) or a DSP (Digital Signal Processor). The control unit 6420 controls the illumination control unit 6310 and the light receiving element 6520. Specifically, the control unit 6420 supplies an irradiation signal to the illumination control unit 6310 and a light emission timing signal to the light receiving element 6520. The light source 6320 emits irradiation light in response to the irradiation signal. The light emission timing signal may be the irradiation signal supplied to the illumination control unit 6310. The control unit 6420 also supplies the distance image acquired from the imaging unit 6410 to the display unit 6430, causing the display unit 6430 to display the distance image. The control unit 6420 also causes the storage unit 6440 to store the distance image acquired from the imaging unit 6410.

[0152] Furthermore, the control unit 6420 outputs the distance image acquired from the imaging unit 6410 to the outside. The display unit 6430 is made up of a panel type display device such as a liquid crystal display device or an organic EL (Electro Luminescence) display device. The storage unit 6440 can be configured with any storage device or storage medium, and stores distance images and the like.

[0153] By adopting the above-described pixel P structure in the photodetector 5010 and distance measurement system 6110, it is possible to generate and output a distance image that achieves high PDE (Photon Detection Efficiency) while preventing edge breaks.

[0154] <Application example 1 to electronic devices> The above-described distance measurement system 6110 can be installed in electronic devices such as smartphones, tablet terminals, mobile phones, personal computers, game consoles, television sets, wearable terminals, digital still cameras, and digital video cameras. FIG. 38 is a block diagram showing an example of the configuration of a smartphone as an electronic device equipped with a distance measuring system 6110.

[0155] 38, the smartphone 7010 includes a ranging module 7020, an imaging device 7030, a display 7040, a speaker 7050, a microphone 7060, a communication module 7070, a sensor unit 7080, a touch panel 7090, and a control unit 7100, all connected via a bus 7110. The control unit 7100 also has functions as an application processing unit 7210 and an operation system processing unit 7220 by the CPU executing a program.

[0156] 37 is applied to the distance measurement module 7020. For example, the distance measurement module 7020 is disposed on the front surface of the smartphone 7010, and by measuring the distance to the user of the smartphone 7010, the distance measurement module 7020 can output depth values of the surface shapes of the user's face, hands, fingers, etc. as distance measurement results.

[0157] The imaging device 7030 is disposed on the front side of the smartphone 7010, and captures an image of the user of the smartphone 7010 by capturing an image of the user as a subject. Although not shown, the smartphone 7010 may also be configured so that another imaging device 7030 is disposed on the back side thereof. The display 7040 displays an operation screen for performing processing by the application processing unit 7210 and the operation system processing unit 7220, and images captured by the imaging device 7030. The speaker 7050 and the microphone 7060 output the voice of the other party and pick up the voice of the user when making a call using the smartphone 7010, for example.

[0158] The communication module 7070 performs communication via a communication network. The sensor unit 7080 senses speed, acceleration, proximity, etc., and the touch panel 7090 acquires touch operations by the user on the operation screen displayed on the display 7040.

[0159] The application processing unit 7210 performs processing for providing various services via the smartphone 7010. For example, the application processing unit 7210 can perform processing to create a computer graphics face that virtually reproduces the user's facial expression based on the depth map supplied from the distance measurement module 7020, and display the face on the display 7040. Furthermore, the application processing unit 7210 can perform processing to create, for example, three-dimensional shape data of any three-dimensional object based on the depth map supplied from the distance measurement module 7020.

[0160] The operation system processing unit 7220 performs processing for realizing the basic functions and operations of the smartphone 7010. For example, the operation system processing unit 7220 can perform processing for authenticating the user's face and unlocking the smartphone 7010 based on the depth map supplied from the ranging module 7020. The operation system processing unit 7220 can also perform processing for recognizing the user's gestures based on the depth map supplied from the ranging module 7020 and inputting various operations in accordance with the gestures.

[0161] The smartphone 7010 configured in this manner can generate a depth map with high accuracy and speed by applying the above-described ranging system 6110. This allows the smartphone 7010 to detect ranging information more accurately.

[0162] <Application example 2 to electronic devices> FIG. 39 is a block diagram showing an example of the configuration of an embodiment of an imaging device as an electronic device to which the present technology is applied.

[0163] 39 is a video camera, a digital still camera, etc. The imaging device 1000 is made up of a lens group 1001, a solid-state imaging element 1002, a DSP circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other via a bus line 1009.

[0164] The lens group 1001 captures incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging element 1002. The solid-state imaging element 1002 is configured as any one of the first to fourteenth embodiments of the solid-state imaging device described above. The solid-state imaging element 1002 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the signal as a pixel signal to the DSP circuit 1003.

[0165] The DSP circuit 1003 performs predetermined image processing on the pixel signals supplied from the solid-state image sensor 1002, and supplies the processed image signals to a frame memory 1004 on a frame-by-frame basis for temporary storage.

[0166] The display unit 1005 is formed of a panel display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays an image based on pixel signals temporarily stored in the frame memory 1004 on a frame-by-frame basis. The recording unit 1006 is made up of a DVD (Digital Versatile Disk), a flash memory, or the like, and reads out and records the pixel signals in units of frames that are temporarily stored in the frame memory 1004 .

[0167] An operation unit 1007, under user operation, issues operation commands for various functions of the imaging device 1000. A power supply unit 1008 supplies power to the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, and operation unit 1007 as appropriate. The electronic device to which this technology is applied may be any device that uses a solid-state imaging device in its image capture section (photoelectric conversion section), and in addition to the imaging device 1000, includes a portable terminal device with an imaging function and a copier that uses a solid-state imaging device in its image reading section.

[0168] <Examples of using solid-state imaging devices> The above-described solid-state imaging device can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows. ·Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes - Devices used for traffic purposes, such as in-vehicle sensors that take pictures of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping, and for recognizing the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. A device used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and operate the appliances according to those gestures. -Medical and healthcare equipment, such as endoscopes and devices used for angiography using infrared light - Security devices such as surveillance cameras for crime prevention and cameras for person authentication Cosmetic devices such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp - Devices used for sports, such as action cameras and wearable cameras for sports purposes Agricultural equipment such as cameras for monitoring the condition of fields and crops The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0169] The present disclosure can also be configured as follows. (1) a plurality of pixels each formed with an avalanche photodiode element for photoelectrically converting incident light; Each of the plurality of pixels is a substrate comprising a first semiconductor material; a laminated portion laminated on the light incident surface of the substrate and including a second semiconductor material different from the first semiconductor material; A semiconductor device comprising: (2) The substrate is The semiconductor device described in (1) above includes a first electrode region of a first conductivity type provided on the surface opposite to the light incident side of the substrate, a second electrode region of a second conductivity type provided to form a pn junction with the first electrode region, and a multiplication section in which an avalanche multiplication region is formed at the interface of the pn junction. (3) the laminated portion is a light absorbing layer, The semiconductor device according to (2), wherein the multiplication section is a Geiger multiplication section that avalanche-multiplies carriers photoelectrically converted by the light absorption layer. (4) the laminated section is a linear multiplication section that avalanche-multiplies carriers generated by photoelectric conversion, The semiconductor device according to (2), wherein the multiplication section is a Geiger multiplication section that avalanche-multiplies the carriers multiplied by the linear multiplication section. (5) the stacked section is a Geiger multiplication section that avalanche-multiplies carriers generated by photoelectric conversion, The substrate further includes a readout circuit for reading out carriers multiplied by the Geiger multiplier. The semiconductor device according to (1) above. (6) The semiconductor device according to (3) or (4), wherein the laminated portion uses a substance capable of crystal growth as the second semiconductor material. (7) The semiconductor device according to (6), wherein the laminated portion has a laminated structure formed by crystal growth including a dislocation layer. (8) The semiconductor device according to (6), wherein the laminated portion has a laminated structure formed by lattice-matched crystal growth. (9) The semiconductor device according to (8), wherein the layered structure formed by the lattice-matched crystal growth is a quantum well type or quantum dot type layered structure. (10) The semiconductor device according to any one of (3) to (5), wherein the laminated portion uses nanocrystals as the second semiconductor material. (11) The semiconductor device according to any one of (3) to (5), wherein the laminated portion uses an organic film as the second semiconductor material. (12) The semiconductor device according to any one of (1) to (11), further comprising a pixel separating section that separates and insulates the plurality of adjacent pixels. (13) The semiconductor device according to (12), wherein the pixel separating section separates pixels by a full trench formed from the substrate to the stacked section. (14) The semiconductor device according to (12), wherein the pixel separating section separates pixels by a back surface trench formed in the stacked section. (15) The semiconductor device according to (12), wherein the pixel separating section separates pixels by a surface trench formed in the substrate. (16) The semiconductor device according to any one of (11) to (15), further comprising an on-chip lens provided on the light incident side of each of the plurality of pixels. (17) The semiconductor device according to any one of (11) to (16), wherein the plurality of pixels include an anti-reflection portion that prevents reflection of the incident light. (18) a plurality of pixels each formed with an avalanche photodiode element for photoelectrically converting incident light; Each of the plurality of pixels is a substrate comprising a first semiconductor material; a stacked portion stacked on the light incident surface of the substrate and including a second semiconductor material different from the first semiconductor material, electronic equipment. [Explanation of symbols]

[0170] 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 1K, 1L, 1M... Solid-state imaging device, 2, 5... SPAD element, 3... Light absorption section, 4... Geiger multiplication section, 6... Linear multiplication section, 10, 81, 82... Substrate, 11... First electrode region, 12... Second electrode region, 13... Avalanche multiplication region, 14, 61, 67, 68, 812... Well region, 20... Dislocation layer, 30, 31, 32, 33, 34, 70, 71, 72, 91, 92... Laminated material section, 40... Wiring layer, 41... Wiring, 42... Cathode, 4 3...anode, 44, 45...transparent electrode, 50...on-chip lens, 60, 60A, 60B, 60C, 60D, 60E, 60F...pixel separation section, 62...inter-brow membrane, 63, 65, 66...metal film, 64...insulating film, 102...constant current source, 103...transistor, 104...inverter, 811, 813...electrode region, 821, 822...contact region, 1000, 6220, 7030...imaging device, 1001...lens group, 1002...solid-state imaging element, 1003...DSP circuit, 1004...frame memory, 1 005...display unit, 1006...recording unit, 1007...operation unit, 1008...power supply unit, 1009...bus line, 5010...light receiving element, 5110...pixel driving unit, 5120...pixel array, 5140...time measurement unit, 5150...input / output unit, 5210,P...pixel, 5220...pixel driving line, 6110...range measuring system, 6120...object, 6130...object, 6210...illumination device, 6310...illumination control unit, 6320...light source, 6410...imaging unit, 6420...control unit, 6430...display unit, 6440...storage unit, 65 10...lens, 6520...light receiving element, 6530...signal processing circuit, 7010...smartphone, 7020...range measuring module, 7040...display, 7050...speaker, 7060...microphone, 7070...communication module, 7080...sensor unit, 7090...touch panel, 7100...control unit, 7110...bus, 7210...application processing unit, 7220...operation system processing unit, TrA...full trench, TrB...surface trench, TrC...back trench

Claims

1. a plurality of pixels each formed with an avalanche photodiode element for photoelectrically converting incident light; Each of the plurality of pixels is a substrate comprising a first semiconductor material; a laminated portion laminated on the light incident surface of the substrate and including a second semiconductor material different from the first semiconductor material; Equipped with The substrate is a multiplication section including a first electrode region of a first conductivity type provided on a surface of the substrate opposite to the light incident surface, and a second electrode region of a second conductivity type provided to form a pn junction with the first electrode region, and an avalanche multiplication region formed at an interface of the pn junction; the laminated section is a linear multiplication section that avalanche-multiplies carriers generated by photoelectric conversion, The multiplication section is a Geiger multiplication section that avalanche-multiplies the carriers multiplied by the linear multiplication section. Semiconductor device.

2. The semiconductor device according to claim 1 , wherein the laminated portion uses a substance capable of crystal growth as the second semiconductor material.

3. 3. The semiconductor device according to claim 2, wherein the laminated portion has a laminated structure formed by crystal growth and including a dislocation layer.

4. 3. The semiconductor device according to claim 2, wherein the laminated portion has a laminated structure formed by lattice-matched crystal growth.

5. 5. The semiconductor device according to claim 4, wherein the layered structure formed by lattice-matched crystal growth is a quantum well type or quantum dot type layered structure.

6. The semiconductor device according to claim 1 , wherein the laminated portion uses nanocrystals as the second semiconductor material.

7. The semiconductor device according to claim 1 , wherein the laminated portion uses an organic film as the second semiconductor material.

8. The semiconductor device according to claim 1 , further comprising a pixel separating portion that separates the plurality of adjacent pixels by insulating them from each other.

9. 9. The semiconductor device according to claim 8, wherein the pixel separating portion separates pixels by a full trench formed from the substrate to the stacked portion.

10. The semiconductor device according to claim 8 , wherein the pixel separating portion separates pixels by a back surface trench formed in the stacked portion.

11. The semiconductor device according to claim 8 , wherein the pixel separating portion separates pixels by a surface trench formed in the substrate.

12. 12. The semiconductor device according to claim 7, further comprising an on-chip lens provided on a light incident side of each of the plurality of pixels.

13. 13. The semiconductor device according to claim 7, wherein the plurality of pixels include an anti-reflection portion that prevents reflection of the incident light.

14. a plurality of pixels each formed with an avalanche photodiode element for photoelectrically converting incident light; Each of the plurality of pixels is a substrate comprising a first semiconductor material; a laminated portion laminated on a light incident surface of the substrate and including a second semiconductor material different from the first semiconductor material; The substrate is a multiplication section including a first electrode region of a first conductivity type provided on a surface of the substrate opposite to the light incident surface, and a second electrode region of a second conductivity type provided to form a pn junction with the first electrode region, and an avalanche multiplication region formed at an interface of the pn junction; the laminated section is a linear multiplication section that avalanche-multiplies carriers generated by photoelectric conversion, The multiplication section is a Geiger multiplication section that avalanche-multiplies the carriers multiplied by the linear multiplication section. A semiconductor device is provided. electronic equipment.

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