Imaging device and camera system

Abstract

This imaging device 101 comprises: a charge accumulation unit 37; a first transistor 81 having a first source, a first drain, and a first gate electrode electrically connected to one of the first source and the first drain; and a first capacitance element 71 for holding the charge and having a first terminal. One of the first source and the first drain is supplied with a fixed potential and is always electrically connected to the first terminal of the capacitance element for at least an exposure period.

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device and a camera system. [Background technology]

[0002] A stacked-type imaging device has been proposed as a MOS (Metal Oxide Semiconductor) type imaging device. In the stacked-type imaging device, a photoelectric conversion layer is stacked on a semiconductor substrate, and charges generated by photoelectric conversion in the photoelectric conversion layer are accumulated in a charge accumulation section. The accumulated charges are read out by a CCD (Charge Coupled Device) circuit or a CMOS (Complementary MOS) circuit provided on the semiconductor substrate. Patent Document 1 discloses such an imaging device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-164604 [Patent Document 2] Patent No. 4317115 [Patent Document 3] International Publication No. 2020 / 144910 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides techniques suitable for achieving a wide dynamic range. [Means for solving the problem]

[0005] The present disclosure provides: a charge storage unit that stores charges generated by photoelectric conversion; a first transistor having a first source, a first drain, and a first gate electrode electrically connected to one of the first source or the first drain; a first capacitance element that holds the charge and has a first terminal; the other of the first source and the first drain is supplied with a fixed potential and is always electrically connected to the first terminal of the capacitive element at least during an exposure period; An imaging device is provided. [Effects of the Invention]

[0006] The technology according to the present disclosure is suitable for realizing a wide dynamic range. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the first embodiment. [Figure 2] FIG. 2 is a schematic diagram illustrating an exemplary circuit configuration of the pixel shown in FIG. [Figure 3] FIG. 3 is a schematic diagram showing a circuit configuration according to the reference embodiment. [Figure 4] FIG. 4 is a timing chart for explaining an example of the operation of the transistor in the first mode of the imaging device according to the first embodiment. [Figure 5] FIG. 5 is a timing chart for explaining an example of the operation of the transistor in the second mode of the imaging device according to the first embodiment. [Figure 6] FIG. 6 is a schematic diagram showing a typical example of the potential state of the transistor in the first mode of the imaging device according to the first embodiment. [Figure 7] FIG. 7 is a graph schematically showing a typical example of change in the level of the electrical signal output from the amplifying transistor with respect to change in the amount of light incident on the photoelectric conversion unit in the first mode according to the first embodiment. [Figure 8] FIG. 8 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the imaging device according to the first embodiment. [Figure 9A]FIG. 9A is a graph schematically showing a typical example of change in the level of the electrical signal output from the amplifying transistor with respect to change in the amount of light incident on the photoelectric conversion unit in the second mode according to the first embodiment. [Figure 9B] FIG. 9B is a graph for explaining the gamma characteristic. [Figure 10] FIG. 10 is a graph for explaining the adjustment of the gamma characteristic. [Figure 11] FIG. 11 is a timing chart for explaining an example of the operation of the transistor in the second mode of the imaging device according to the second embodiment. [Figure 12] FIG. 12 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the imaging device according to the second embodiment. [Figure 13] FIG. 13 is a schematic diagram showing an example of the potential state of the transistor in the second mode of the imaging device according to the second embodiment. [Figure 14] FIG. 14 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device according to the third embodiment. [Figure 15] FIG. 15 is a schematic diagram illustrating an exemplary circuit configuration of the pixel shown in FIG. [Figure 16] FIG. 16 is a timing chart for explaining an example of the operation of the transistor in the first mode of the imaging device according to the third embodiment. [Figure 17] FIG. 17 is a timing chart for explaining an example of the operation of the transistor in the second mode of the imaging device according to the third embodiment. [Figure 18] FIG. 18 is a schematic diagram showing an exemplary circuit configuration of a pixel in an imaging device according to the fourth embodiment. [Figure 19A] FIG. 19A is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the fifth embodiment. [Figure 19B] FIG. 19B is a schematic diagram showing an exemplary circuit configuration of the imaging device according to the fifth embodiment. [Figure 20]FIG. 20 is a timing chart for explaining a typical example of the operation of the transistor in the second mode of the imaging device according to the fifth embodiment. [Figure 21] FIG. 21 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the imaging device according to the fifth embodiment. [Figure 22] FIG. 22 is a timing chart for explaining an example of the operation of the transistor in the second mode of the imaging device according to the fifth embodiment. [Figure 23] FIG. 23 is a schematic diagram showing an example of the potential state of the transistor in the second mode of the imaging device according to the fifth embodiment. [Figure 24] FIG. 24 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the sixth embodiment. [Figure 25] FIG. 25 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the seventh embodiment. [Figure 26] FIG. 26 is a diagram schematically illustrating a typical example of a change in the level of an electrical signal output from an amplifying transistor in response to a change in the amount of light incident on a photoelectric conversion unit in the second mode according to the seventh embodiment. [Figure 27] FIG. 27 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the eighth embodiment. [Figure 28] FIG. 28 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the imaging device according to the eighth embodiment. [Figure 29] FIG. 29 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the ninth embodiment. [Figure 30] FIG. 30 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the imaging device according to the ninth embodiment. [Figure 31] FIG. 31 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the tenth embodiment. [Figure 32] FIG. 32 is a diagram schematically showing an example of a change in the output of the horizontal signal readout circuit with respect to an increase in the amount of exposure. [Figure 33] FIG. 33 is a block diagram showing a schematic overview of the linearity compensation process. [Figure 34] FIG. 34 is a diagram illustrating an example of the correction table. [Figure 35] FIG. 35 is a diagram for explaining differences in linearity deviation between imaging devices or camera systems. [Figure 36] FIG. 36 is a block diagram showing a schematic overview of linearity compensation processing that cancels differences between image pickup devices or camera systems. [Figure 37] FIG. 37 is a diagram showing an example of a correction table stored in the memory of the imaging device of sample S1. [Figure 38] FIG. 38 is a diagram showing an example of a correction table stored in the memory of the imaging device of sample S2. [Figure 39] FIG. 39 is a diagram showing another example of the correction table stored in the memory. [Figure 40] FIG. 40 is a diagram showing a plot of the output values described in the correction table of FIG. [Figure 41] FIG. 41 is a diagram showing a schematic overview of linearity compensation processing including interpolation processing. [Figure 42] FIG. 42 is a schematic diagram showing an example of the configuration of a camera system. DETAILED DESCRIPTION OF THE INVENTION

[0008] (Summary of one aspect of the present disclosure) An imaging device according to a first aspect of the present disclosure includes: a charge storage unit that stores charges generated by photoelectric conversion; a first transistor having a first source, a first drain, and a first gate electrode electrically connected to one of the first source or the first drain; a first capacitance element that holds the charge and has a first terminal; The other of the first source or the first drain is supplied with a fixed potential and is always electrically connected to the first terminal of the capacitive element at least during an exposure period.

[0009] This configuration makes it possible to realize an imaging device having pseudo gamma characteristics.

[0010] The imaging device according to the second aspect of the present disclosure, for example, in the imaging device according to the first aspect, The charge storage device further includes an amplifying transistor that outputs an electrical signal according to the potential of the charge storage portion.

[0011] With this configuration, it is possible to detect an electrical signal corresponding to the illuminance of light incident on the imaging device.

[0012] The imaging device according to the third aspect of the present disclosure is, for example, the imaging device according to the first or second aspect, a second transistor having a second source, a second drain, and a second gate electrode; The other of the first source and the first drain is supplied with a fixed potential via the second transistor.

[0013] With this configuration, the charge stored in the first source or the first drain can be discharged during the reset period.

[0014] The imaging device according to the fourth aspect of the present disclosure is, for example, the imaging device according to the first or second aspect, a second transistor having a second source, a second drain, and a second gate electrode; one of the second source and the second drain is electrically connected to the other of the first source and the first drain; The other of the second source and the second drain is supplied with a fixed potential.

[0015] With this configuration, the charge stored in the first source or the first drain can be discharged during the reset period.

[0016] An imaging device according to a fifth aspect of the present disclosure is, for example, an imaging device according to any one of the first to fourth aspects, The gate electrode of the first transistor is connected to one of the first source and the first drain via the first capacitance element.

[0017] With this configuration, the capacitance value of the charge storage capacitor can be changed in response to a change in the potential of the charge storage section.

[0018] An imaging device according to a sixth aspect of the present disclosure is, for example, an imaging device according to any one of the first to fifth aspects, The device further includes a semiconductor substrate and a photoelectric conversion unit that generates the charge by photoelectric conversion, The photoelectric conversion portion is located within the semiconductor substrate.

[0019] This configuration allows the photodiode to be formed using a semiconductor substrate.

[0020] An imaging device according to a seventh aspect of the present disclosure is, for example, an imaging device according to any one of the first to fifth aspects, The device further includes a semiconductor substrate and a photoelectric conversion unit that generates the charge by photoelectric conversion, The photoelectric conversion portion is located on the semiconductor substrate.

[0021] This configuration allows the photodiode to be formed independently of the semiconductor substrate. An imaging device according to an eighth aspect of the present disclosure is, for example, an imaging device according to any one of the first to seventh aspects, The first capacitive element includes an MIM capacitor.

[0022] This configuration makes it possible to expand the dynamic range.

[0023] An imaging device according to a ninth aspect of the present disclosure includes: a charge storage unit that stores charges generated by photoelectric conversion; a node electrically connected to the charge storage unit; a circuit, the circuit includes a first transistor having a first source, a first drain, and a first gate electrode electrically connected to one of the first source or the first drain; a first capacitance element that holds the charge and has a first terminal; The other of the first source and the first drain is supplied with a fixed potential and is always electrically connected to the first terminal of the capacitive element.

[0024] This configuration makes it possible to realize an imaging device having pseudo gamma characteristics.

[0025] An imaging device according to a tenth aspect of the present disclosure, for example, in the imaging device according to the ninth aspect, When the capacitance electrically connected to the node is defined as a charge storage capacitance, the circuit changes the capacitance value of the charge storage capacitance in response to a change in the potential of the charge storage section.

[0026] This configuration makes it possible to realize an imaging device having pseudo gamma characteristics.

[0027] An imaging device according to an eleventh aspect of the present disclosure, for example, in the imaging device according to the tenth aspect, The circuit changes the capacitance value of the charge storage capacitor in response to a change in the potential of the charge storage section, depending on the capacitance value of the first capacitive element.

[0028] This configuration makes it possible to realize an imaging device having pseudo gamma characteristics.

[0029] An imaging device according to a twelfth aspect of the present disclosure is, for example, an imaging device according to the tenth or eleventh aspect, The circuit changes the capacitance value of the charge storage capacitor when the potential of the charge storage section changes across a first threshold potential.

[0030] With this configuration, it is possible to appropriately generate an electrical signal according to the amount of light even in areas where the amount of light is large.

[0031] An imaging device according to a thirteenth aspect of the present disclosure is, for example, the imaging device according to the twelfth aspect, Further comprising a control circuit; The control circuit controls the first threshold potential by applying a control potential to the circuit.

[0032] With this configuration, it is possible to appropriately generate an electrical signal according to the amount of light even in areas where the amount of light is large.

[0033] An imaging device according to a fourteenth aspect of the present disclosure is, for example, an imaging device according to the twelfth or thirteenth aspect, Further comprising a control circuit; The control circuit switches the first threshold potential depending on the imaging mode.

[0034] This configuration makes it possible to realize an imaging device that has pseudo gamma characteristics suited to the imaging mode.

[0035] A camera system according to a fifteenth aspect of the present disclosure includes: An imaging device and a control circuit are provided, The imaging device includes a charge accumulation unit that accumulates charges generated by photoelectric conversion, a first transistor having a first source, a first drain, and a first gate electrode electrically connected to one of the first source and the first drain, a first capacitance element that holds the charge and has a first terminal; The other of the first source and the first drain is supplied with a fixed potential and is always electrically connected to the first terminal of the capacitive element.

[0036] This configuration makes it possible to realize an imaging device having pseudo gamma characteristics.

[0037] An imaging device according to a sixteenth aspect of the present disclosure includes: a charge storage unit that stores charges generated by photoelectric conversion; a node electrically connected to the charge storage unit; a specific circuit having a first capacitance element; When the capacitance electrically connected to the node is defined as a charge storage capacitance, the specific circuit changes the capacitance value of the charge storage capacitance in response to a change in the potential of the charge storage section.

[0038] The technique according to the sixteenth aspect is suitable for realizing a wide dynamic range.

[0039] In a seventeenth aspect of the present disclosure, for example, in the imaging device according to the sixteenth aspect, The specifying circuit may change the capacitance value of the charge storage capacitor in response to a change in the potential of the charge storage section, depending on the capacitance value of the first capacitive element.

[0040] The configuration of the seventeenth aspect is a specific example of how to change the capacitance value of the charge storage capacitance.

[0041] In an eighteenth aspect of the present disclosure, for example, in the imaging device according to the sixteenth or seventeenth aspect, The specifying circuit may change the capacitance value of the charge storage capacitor when the potential of the charge storage section varies across a first threshold potential.

[0042] The configuration of the third aspect is a specific example of how to change the capacitance value of the charge storage capacitor.

[0043] In a nineteenth aspect of the present disclosure, for example, the imaging device according to the eighteenth aspect may further include a control circuit, The control circuit may control the first threshold potential by applying a control potential to the specific circuit.

[0044] According to the nineteenth aspect, the first threshold potential can be controlled.

[0045] In a twentieth aspect of the present disclosure, for example, the imaging device according to the eighteenth or nineteenth aspect may further include a control circuit, The control circuit may switch the first threshold potential depending on the imaging mode.

[0046] According to the twentieth aspect, the potential of the charge storage section when the capacitance value of the charge storage capacitor changes can be set for each imaging mode.

[0047] In a 21st aspect of the present disclosure, for example, in the imaging device according to the 20th aspect, The specific circuit may further include a first transistor, The imaging mode may include a first mode and a second mode, In the first mode, the first transistor may be maintained in an off state; In the second mode, the capacitance value of the charge storage capacitor may increase when or after the first transistor is turned on in response to a change in the potential of the charge storage portion.

[0048] The configuration of the 21st embodiment is one configuration example.

[0049] In the seventh aspect of the present disclosure, for example, in the imaging device according to any one of the sixteenth to twenty-first aspects, may further comprise an amplifying transistor; The amplifying transistor may output an electrical signal according to the potential of the charge storage section, When the illuminance of light incident on the imaging device increases beyond a threshold illuminance, the rate at which the level of the electrical signal increases relative to the increase in illuminance of light incident on the imaging device may decrease.

[0050] According to the 22nd aspect, pseudo gamma characteristics can be obtained.

[0051] In a 23rd aspect of the present disclosure, for example, in an imaging device according to any one of the 16th to 22nd aspects, The specific circuit may further include a first transistor, The first transistor may have a first source, a first drain, and a first gate electrode; The first capacitive element may have a first terminal and a second terminal; The first gate electrode may be electrically connected to the charge storage portion, The first source or the first drain may be electrically connected to the first terminal.

[0052] According to the 23rd aspect, the control potential is applied to the second terminal of the first capacitance element, thereby achieving the characteristics of the 16th aspect.

[0053] In a 24th aspect of the present disclosure, for example, in an imaging device according to any one of the 16th to 22nd aspects, The specific circuit may further include a first transistor, The first transistor may have a first source, a first drain, and a first gate electrode; The first capacitive element may have a first terminal and a second terminal; The first gate electrode may be electrically connected to the first terminal; The first source or the first drain may be electrically connected to the charge storage portion.

[0054] According to the 24th aspect, the control potential is applied to the second terminal of the first capacitance element, thereby achieving the characteristics of the 16th aspect.

[0055] In a 25th aspect of the present disclosure, for example, in an imaging device according to any one of the 16th to 22nd aspects, The specific circuit may further include a first transistor, The first transistor may have a first source, a first drain, and a first gate electrode; The first capacitive element may have a first terminal and a second terminal; The first gate electrode may be electrically connected to the first terminal and the charge storage portion, One of the first source and the first drain may be electrically connected to the second terminal.

[0056] According to the twenty-fifth aspect, the feature of the sixteenth aspect can be realized by applying a control potential to the other of the first source and the first drain.

[0057] In a 26th aspect of the present disclosure, for example, the imaging device according to the 25th aspect may further include a control circuit, a control potential may be applied to the other of the first source and the first drain from the control circuit; During a reset period, the control circuit may apply a reset potential to the charge storage unit, During a period included in the reset period, the control circuit may temporarily turn on the first transistor by changing the level of the reset potential in a pulsed manner.

[0058] According to the 26th aspect, during the reset period, the potential of the second terminal can be reset together with the potential of the charge accumulation section.

[0059] In a 27th aspect of the present disclosure, for example, the imaging device according to the 25th or 26th aspect may further include a control circuit, a control potential may be applied to the other of the first source and the first drain from the control circuit; During a reset period, the control circuit may apply a reset potential to the charge storage unit, During a period included in the reset period, the control circuit may temporarily short-circuit the first source and the first drain of the first transistor in an off state by changing the level of the control potential in a pulsed manner.

[0060] According to the 27th aspect, during the reset period, the potential of the second terminal can be reset together with the potential of the charge accumulation section.

[0061] In a 28th aspect of the present disclosure, for example, in the imaging device according to any one of the 16th to 27th aspects, The specific circuit may further include a second capacitance element, The specifying circuit may change the capacitance value of the charge storage capacitance when the potential of the charge storage section changes across a first threshold potential and when the potential of the charge storage section changes across a second threshold potential.

[0062] The configuration of the 28th embodiment is a specific example of how to change the capacitance value of the charge storage capacitor.

[0063] In a 29th aspect of the present disclosure, for example, in the imaging device according to any one of the 16th to 28th aspects, The first capacitance element may include at least one selected from the group consisting of an MIM capacitance, an MOM capacitance, and a MOS capacitance.

[0064] The MIM capacitor, the MOM capacitor, and the MOS capacitor are specific examples of the first capacitive element.

[0065] A camera system according to a twentieth aspect of the present disclosure includes: An imaging device and a control circuit are provided, the imaging device includes a charge accumulation unit that accumulates charges generated by photoelectric conversion, a node electrically connected to the charge accumulation unit, and a specific circuit having a first capacitance element; When a capacitance electrically connected to the node is defined as a charge storage capacitance, the specifying circuit changes a capacitance value of the charge storage capacitance when the potential of the charge storage unit changes across a first threshold potential, The control circuit controls the first threshold potential by applying a control potential to the specific circuit.

[0066] The technique according to the twentieth aspect is suitable for realizing a wide dynamic range.

[0067] In the embodiments, terms such as "upper" and "lower" are used merely to specify the relative positions of components, and are not intended to limit the orientation of the imaging device when in use.

[0068] In the embodiment, adjustments of each element due to the difference in the positive and negative polarities of the signal charges, such as changing the conductivity type of the impurity regions, can be made as appropriate. Furthermore, terminology can be replaced as appropriate due to the difference in the positive and negative polarities of the signal charges.

[0069] In the embodiments, the term "node" may be used. A node refers to an electrical connection between multiple elements in an electric circuit, and is a concept that includes wiring and the like that provides the electrical connection between the elements.

[0070] In the embodiments, the terms "illuminance" and "amount of light" may be used. Illuminance refers to the luminous flux incident per unit area, typically expressed in units of lux. Strictly speaking, "amount of light" refers to the time integral of the luminous flux over an exposure period belonging to one frame period. One frame period refers to one control cycle of timing control of a transistor in a pixel, as shown in FIG. 4, etc. "Amount of light" is also referred to as "exposure amount."

[0071] In the following embodiments, the expression "the charge accumulation unit is electrically connected to element X" may be used. Specifically, in the following embodiments, even if the charge accumulation unit is composed of part or all of element X, the expression may be used. Therefore, the expression should be interpreted as including the case where the charge accumulation unit is composed of part or all of element X. Furthermore, in the following embodiments, the charge accumulation unit and other elements may be listed, such as "having / comprising a charge accumulation unit and element X." Specifically, in the following embodiments, even if the charge accumulation unit is composed of part or all of element X, such a listing may be used. In such a situation, it should be acceptable for the charge accumulation unit to be composed of part or all of element X. For example, in the following embodiments, one of the first source and first drain of the first transistor may constitute the charge accumulation unit. One of the source and drain of the first reset transistor may constitute the charge accumulation unit. The photoelectric conversion unit may constitute the charge accumulation unit.

[0072] Furthermore, the expressions "the first capacitance element is connected to the first transistor" and "having / comprising the first capacitance element and the first transistor" should be interpreted as including the case where the first capacitance element is configured using the first transistor. In other words, this expression should be interpreted as including the case where the first capacitance element and the first transistor overlap partially or entirely.

[0073] In the embodiments, ordinal numbers such as 1st, 2nd, 3rd, etc. may be used. When an element is assigned an ordinal number, it is not necessary that there is an element of the same type with a lower number. Furthermore, the number of the ordinal number can be changed, deleted, or new ordinal numbers can be added as necessary.

[0074] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0075] However, more detailed descriptions than necessary may be omitted. For example, detailed descriptions of well-known matters or redundant descriptions of substantially identical configurations may be omitted. This is to avoid unnecessary redundancy in the following description and to facilitate understanding by those skilled in the art. Note that the accompanying drawings and the following description are intended to enable those skilled in the art to fully understand the present disclosure, and are not intended to limit the subject matter described in the claims.

[0076] In the drawings, elements that have substantially the same configuration, operation, and effect are denoted by the same reference numerals. All numerical values described below are examples for specifically explaining the present disclosure, and the present disclosure is not limited to the illustrated numerical values. The connection relationships between the components are examples for specifically explaining the present disclosure, and the connection relationships that realize the functions of the present disclosure are not limited to these.

[0077] (First embodiment) FIG. 1 schematically shows an exemplary circuit configuration of an imaging device 101 according to the first embodiment. The imaging device 101 shown in FIG. 1 includes a plurality of pixels 11a and peripheral circuits. The plurality of pixels 11a are arranged two-dimensionally on a semiconductor substrate to form a photosensitive region. The photosensitive region may also be referred to as a pixel region. The semiconductor substrate is, for example, a silicon substrate. The semiconductor substrate is not limited to a substrate whose entire surface is made of semiconductor. The semiconductor substrate may include an insulating substrate and a semiconductor layer provided on the insulating substrate. The photosensitive region may be formed on the semiconductor layer side.

[0078] In the illustrated example, the plurality of pixels 11a are arranged in a row direction and a column direction. In this specification, the row direction and the column direction refer to the directions in which the rows and the columns extend, respectively. In the drawings, the vertical direction on the paper surface is the column direction, and the horizontal direction is the row direction. The plurality of pixels 11a may be arranged one-dimensionally. In other words, the imaging device 101 may be a line sensor.

[0079] Each pixel 11a is connected to a power supply wiring 22. A predetermined power supply voltage is supplied to each pixel 11a via the power supply wiring 22. As will be described in detail later, each pixel 11a in this embodiment includes a photoelectric conversion unit stacked on a semiconductor substrate. The expression "photoelectric conversion unit stacked on a semiconductor substrate" is intended to encompass a configuration in which other elements are interposed between the semiconductor substrate and the photoelectric conversion unit. As shown in the figure, the imaging device 101 also has an accumulation control line 17 for applying the same constant voltage to all photoelectric conversion units.

[0080] Each of the pixels 11a is also connected to a reset voltage line 77. A reset potential Vrst is supplied to each of the pixels 11a via the reset voltage line 77.

[0081] The peripheral circuits of the imaging device 101 include a vertical scanning circuit 16, a load circuit 19, a column signal processing circuit 20, and a horizontal signal readout circuit 21. The vertical scanning circuit 16 may also be referred to as a row scanning circuit 16. The column signal processing circuit 20 may also be referred to as a row signal storage circuit 20. The horizontal signal readout circuit 21 may also be referred to as a column scanning circuit 21. The column signal processing circuit 20 and the load circuit 19 are arranged for each column of the two-dimensionally arranged pixels 11a. That is, in this example, the peripheral circuits include a plurality of column signal processing circuits 20 and a plurality of load circuits 19.

[0082] An address signal line 30 is provided for each row of pixels 11a. The pixels 11a in each row are electrically connected to the vertical scanning circuit 16 via the corresponding address signal line 30. The vertical scanning circuit 16 applies a predetermined voltage to the address signal line 30 to select the multiple pixels 11a arranged in each row on a row-by-row basis. This causes the electrical signals of the selected pixels 11a to be read out.

[0083] A reset signal line 26 is provided for each row of pixels 11a. The pixels 11a in each row are electrically connected to the vertical scanning circuit 16 via the corresponding reset signal line 26.

[0084] Each row of pixels 11a is provided with a specific reset signal line 75. The pixels 11a in each row are electrically connected to the vertical scanning circuit 16 via the corresponding specific reset signal line 75.

[0085] A vertical signal line 18 is provided for each column of pixels 11a. The pixels 11a in each column are electrically connected to the corresponding vertical signal line 18.

[0086] A load circuit 19 is provided for each vertical signal line 18. Each load circuit 19 is electrically connected to the corresponding vertical signal line 18.

[0087] A column signal processing circuit 20 is provided for each vertical signal line 18. Each column signal processing circuit 20 is electrically connected to the corresponding vertical signal line 18. The column signal processing circuit 20 performs noise suppression signal processing, analog-to-digital conversion (AD conversion), etc. The noise suppression signal processing is, for example, correlated double sampling. The multiple column signal processing circuits 20 are electrically connected to a horizontal signal readout circuit 21. The horizontal signal readout circuit 21 sequentially reads out signals from the multiple column signal processing circuits 20 to a horizontal common signal line 23.

[0088] Fig. 2 shows an exemplary circuit configuration of the pixel 11a shown in Fig. 1. The pixel 11a includes a photoelectric conversion unit 15, a signal detection circuit SC, and a specification circuit GSC.

[0089] In the pixel 11a, charges are generated by photoelectric conversion. Hereinafter, these charges may be referred to as signal charges. Specifically, the photoelectric conversion unit 15 converts light into charges.

[0090] In this embodiment, the photoelectric conversion unit 15 includes a counter electrode 15a, a photoelectric conversion layer 15b, and a pixel electrode 15c. The photoelectric conversion layer 15b is disposed between the counter electrode 15a and the pixel electrode 15c.

[0091] The photoelectric conversion layer 15b is stacked on the semiconductor substrate in the pixel region. The material of the photoelectric conversion layer 15b may be an organic material or an inorganic material. An example of an inorganic material is amorphous silicon. The photoelectric conversion layer 15b may include a layer made of an organic material and a layer made of an inorganic material. Typically, the photoelectric conversion layer 15b has a film shape.

[0092] The counter electrode 15a is provided on the light-receiving surface side of the photoelectric conversion layer 15b. Light is incident on the photoelectric conversion layer 15b through the photoelectric conversion layer 15b. Typically, the counter electrode 15a is made of a transparent conductive material. An example of the transparent conductive material is ITO (Indium Tin Oxide).

[0093] The pixel electrode 15c is provided on the side facing the counter electrode 15a via the photoelectric conversion layer 15b. The pixel electrode 15c collects signal charges generated by photoelectric conversion in the photoelectric conversion layer 15b. The pixel electrode 15c may be made of a material such as a metal, a metal compound, or polysilicon. Examples of metals include aluminum and copper. Examples of metal compounds include metal nitrides. The polysilicon may be doped with impurities to provide conductivity.

[0094] The counter electrode 15a is electrically connected to a storage control line 17. The pixel electrode 15c is electrically connected to a node 44. In the illustrated example, the node 44 may also be called a charge storage node or a floating diffusion node.

[0095] The potential of the counter electrode 15a is controlled via the accumulation control line 17. As a result, of the hole-electron pairs generated by photoelectric conversion in the photoelectric conversion layer 15b, either the holes or the electrons can be collected by the pixel electrode 15c. In this embodiment, the holes are collected by the pixel electrode 15c as signal charges.

[0096] When holes are used as signal charges, the potential of the counter electrode 15a is set so that the potential of the counter electrode 15a exceeds the potential of the pixel electrode 15c. The following describes an example in which holes are used as signal charges. A voltage of, for example, about 10 V is applied to the counter electrode 15a via the storage control line 17. However, electrons may also be used as signal charges.

[0097] A photodiode can also be used as the photoelectric conversion unit 15. The photodiode can be disposed within a semiconductor substrate.

[0098] The charge accumulation unit 37 is electrically connected to the node 44. Charges generated by photoelectric conversion are accumulated in the charge accumulation unit 37. Specifically, charges generated by photoelectric conversion in the photoelectric conversion unit 15 are accumulated in the charge accumulation unit 37. In this embodiment, the charge accumulation unit 37 is a diffusion region provided in a semiconductor substrate.

[0099] During exposure, the photoelectric conversion unit 15, the charge accumulation unit 37, and the specific circuit GSC are electrically connected. Note that, in the case where the photoelectric conversion unit 15 has a counter electrode 15a, a photoelectric conversion layer 15b, and a pixel electrode 15c, "exposure" can be achieved by applying a voltage to the counter electrode 15a. In the illustrated example, no transfer transistor is provided between the photoelectric conversion unit 15 and the charge accumulation unit 37, thereby realizing the above-mentioned electrical connection configuration.

[0100] The signal detection circuit SC includes an amplifier transistor 34, an address transistor 40, and a first reset transistor 36.

[0101] One of the source and drain of the first reset transistor 36 is electrically connected to the node 44. In this embodiment, one of the source and drain of the first reset transistor 36 forms a charge storage unit 37. The other of the source and drain of the first reset transistor 36 is electrically connected to a reset voltage line 77.

[0102] The gate electrode of the amplifier transistor 34 is electrically connected to the node 44, the charge storage unit 37, and the photoelectric conversion unit 15. Specifically, the gate electrode of the amplifier transistor 34 is electrically connected to the pixel electrode 15c. One of the source and drain of the amplifier transistor 34 is electrically connected to the power supply wiring 22. The other of the source and drain of the amplifier transistor 34 is electrically connected to one of the source and drain of the address transistor 40. The other of the source and drain of the address transistor 40 is electrically connected to the vertical signal line 18. The gate electrode of the address transistor 40 is connected to the address signal line 30.

[0103] In the illustrated example, the drain of the amplifier transistor 34 is electrically connected to the power supply wiring 22. The source of the amplifier transistor 34 is connected to the vertical signal line 18 via the address transistor 40.

[0104] In the illustrated example, the power supply wiring 22 is a source follower power supply. The amplifier transistor 34 and the load circuit 19 shown in FIG.

[0105] The charge storage section 37 has a potential corresponding to the amount of signal charge stored in the charge storage section 37. Therefore, a potential corresponding to the amount of signal charge stored in the charge storage section 37 is applied to the gate electrode of the amplification transistor 34. The amplification transistor 34 outputs an electrical signal corresponding to this potential. The electrical signal is selectively read out by the address transistor 40. Specifically, the electrical signal is a signal voltage.

[0106] The first reset transistor 36 resets the potential of the charge storage unit 37. Specifically, when the first reset transistor 36 is turned on, a reset potential Vrst is supplied to the charge storage unit 37 from the reset voltage line 77 via the first reset transistor 36, and the potential of the charge storage unit 37 is reset.

[0107] The specified circuit GSC includes a first capacitance element 71, a first transistor 81, and a specified reset transistor 76. The first capacitance element 71 includes a first terminal 71a, a second terminal 71b, and a dielectric layer.

[0108] The first capacitance element 71 may include at least one selected from the group consisting of a metal insulator metal (MIM) capacitance, a metal oxide metal (MOM) capacitance, and a metal oxide semiconductor (MOS) capacitance. This also applies to a second capacitance element 72 and a third capacitance element 73 described later.

[0109] In this embodiment, the first capacitance element 71 is an MIM capacitance or an MOM capacitance. When the first capacitance element 71 is an MIM capacitance or an MOM capacitance, it is easy to realize the first capacitance element 71 with a large capacitance value. This is advantageous from the viewpoint of realizing a wide dynamic range.

[0110] Specifically, the first capacitive element 71, which is an MIM capacitor or an MOM capacitor, can be provided outside the semiconductor substrate. Specifically, such a first capacitive element 71 can be provided between the semiconductor substrate and the photoelectric conversion unit 15. This means that the capacitance value of the first capacitive element 71 can be increased without being restricted by the layout of elements on the semiconductor substrate.

[0111] Note that some capacitive elements are both MIM and MOM capacitors. The phrase "the first capacitive element 71 is an MIM capacitor or an MOM capacitor" is intended to encompass the case where the first capacitive element 71 is both an MIM capacitor and an MOM capacitor.

[0112] Hereinafter, the source of the first transistor 81 may be referred to as a first source, the drain of the first transistor 81 may be referred to as a first drain, and the gate electrode of the first transistor 81 may be referred to as a first gate electrode.

[0113] In this embodiment, the first gate electrode is electrically connected to the charge accumulation unit 37. One of the first source and the first drain is electrically connected to the charge accumulation unit 37. The other of the first source and the first drain is electrically connected to the first terminal 71a. In this embodiment, a control potential VF is applied to the second terminal 71b from a control circuit of the imaging device 101. This control potential VF may be a fixed potential. The same applies hereinafter. A fixed potential refers to a constant potential or a ground potential.

[0114] Specifically, in this embodiment, one of the first source and the first drain constitutes the charge accumulation unit 37. More specifically, the charge accumulation unit 37 has the function of accumulating signal charges, the function as one of the source and the drain of the first reset transistor 36, and the function as one of the first source and the first drain of the first transistor 81.

[0115] In this embodiment, the first transistor 81 is electrically connected to the first capacitance element 71. Specifically, at least one selected from the group consisting of a first source, a first drain, and a first gate electrode of the first transistor 81 is electrically connected to at least one selected from the group consisting of a first terminal 71a and a second terminal 71b of the first capacitance element 71. As will be described later, the first capacitance element 71 may be configured using the first transistor 81.

[0116] In this embodiment, the control circuit is the vertical scanning circuit 16. However, the control circuit may be provided separately from the vertical scanning circuit 16.

[0117] Hereinafter, the node to which the control potential VF is supplied may be referred to as node 48. In this embodiment, node 48 is electrically connected to the second terminal 71b of the first capacitance element 71. Furthermore, a node electrically connected to the first source or first drain of the first transistor 81 and the first capacitance element 71 may be referred to as node 47. In this embodiment, node 47 is electrically connected to the other of the first source and first drain of the first transistor 81 and the first terminal 71a of the first capacitance element 71. Here, these only need to be electrically connected at least during the exposure period of the pixel.

[0118] In this embodiment, the control potential VF is a DC potential. The level of the control potential VF, which is a DC potential, may be different between one period and another period.

[0119] Hereinafter, the term "charge storage capacitance X" will be used. The charge storage capacitance X is a capacitance electrically connected to the node 44. The charge storage capacitance X stores charges generated by photoelectric conversion. The charge storage capacitance X may include the charge storage section 37. The charge storage capacitance X may include the first capacitive element 71. The charge storage capacitance X may also perform functions other than storing charges. The charge storage capacitance X may constitute a synthetic impedance capacitance.

[0120] In this embodiment, the specifying circuit GSC changes the capacitance value of the charge storage capacitance X in response to a change in the potential of the charge storage unit 37. This configuration is suitable for achieving a wide dynamic range. Specifically, this configuration is suitable for achieving a wide dynamic range while maintaining a good S / N ratio at low illuminance.

[0121] Specifically, the potential of the identification circuit GSC changes in accordance with the change in the potential of the charge accumulation unit 37. The identification circuit GSC changes the capacitance value of the charge accumulation capacitance X in response to the change in the potential of the identification circuit GSC. As can be understood from this explanation, in this embodiment, the capacitance value of the charge accumulation capacitance X can change automatically and in real time in an analog circuit provided in the imaging device 101 due to a change in the potential of the charge accumulation unit 37.

[0122] In this embodiment, the identification circuit GSC changes the capacitance value of the charge storage capacitance X according to the capacitance value of the first capacitance element 71 in response to a change in the potential of the charge storage unit 37. In one specific example, the identification circuit GSC changes the capacitance value of the charge storage capacitance X by the capacitance value of the first capacitance element 71 in response to a change in the potential of the charge storage unit 37. "Changing the capacitance value of the charge storage capacitance X by the capacitance value of the first capacitance element 71" means that the amount of change in the capacitance value of the charge storage capacitance X matches the capacitance value of the first capacitance element 71.

[0123] In this embodiment, the capacitance value of the first capacitance element 71 is larger than the capacitance value of the charge accumulation unit 37. However, the capacitance value of the first capacitance element 71 may be the same as the capacitance value of the charge accumulation unit 37, or may be smaller than the capacitance value of the charge accumulation unit 37.

[0124] In this embodiment, the specifying circuit GSC changes the capacitance value of the charge storage capacitor X when the potential of the charge storage unit 37 changes across the first threshold potential. Such a change in the capacitance value can be achieved using the first transistor 81.

[0125] In this embodiment, the control circuit controls the first threshold potential by applying a control potential VF to the specific circuit GSC. Specifically, the gate-source voltage of the first transistor 81 changes depending on the potential of the charge storage unit 37. The control circuit controls the gate-source voltage when the potential of the charge storage unit 37 is at the reset potential Vrst.

[0126] In this embodiment, the first transistor 81 turns on in response to a change in the potential of the charge storage section 37. When or after the first transistor 81 turns on, the capacitance value of the charge storage capacitance X increases.

[0127] Specifically, the gate-source voltage of the first transistor 81 changes in accordance with the change in the potential of the charge storage unit 37. When or after the first transistor 81 is turned on due to the gate-source voltage changing across the threshold voltage, the capacitance value of the charge storage capacitance X increases.

[0128] The advantages of this embodiment will be further described below with reference to FIG.

[0129] FIG. 3 is a schematic diagram showing a circuit configuration according to the reference embodiment. In the reference embodiment, two readouts, a first readout and a second readout, are performed in one frame. The first readout is a readout of a signal from the floating diffusion FD. The second readout is a readout of a signal from the floating diffusion FD and the capacitance element C. S This is the readout of a signal from the combined capacitance part to which these are coupled.

[0130] The circuit configuration in Fig. 3 corresponds to Fig. 21 of Patent Document 2. The first readout corresponds to (E) of Fig. 25 of Patent Document 2. The second readout corresponds to (F) of Fig. 25 of Patent Document 2. Patent Document 2 describes a wide dynamic range as an effect.

[0131] However, the two readouts in the reference embodiment require a long time. This is disadvantageous from the viewpoint of increasing speed and reducing power consumption. Furthermore, it is necessary to combine images corresponding to the two readouts. Furthermore, the second readout is a readout of a signal from the combined capacitance section. The combined capacitance section has a large capacitance value. Therefore, it is difficult to ensure a sufficient variation range of the signal readout from the combined capacitance section. This means that it is difficult to ensure a sufficient S / N ratio. Furthermore, in the reference embodiment, the charge overflowing from the photodiode PD is transferred to the floating diffusion FD and the capacitance element C. S However, although the overflowing charge can be stored, the number of saturated charges is limited by the photodiode PD in the first readout, and the capacitance element C S The contribution of to decreases the S / N ratio, and therefore there is a limit to the expansion of the dynamic range by double readout.

[0132] In contrast, in this embodiment, signal readout is sufficient only once. This is advantageous from the viewpoint of increasing speed and reducing power consumption, and this embodiment does not require image synthesis. In this embodiment, the capacitance value of the charge storage capacitance X can be reduced under low illumination. This makes it easier to ensure an S / N ratio under low illumination. In this embodiment, the photoelectric conversion unit 15 and the charge storage unit 37 are electrically connected, and the first capacitance element 71 functions as part of the charge storage capacitance X in response to changes in the potential of the charge storage unit 37. This embodiment is advantageous from the viewpoint of realizing a wide dynamic range.

[0133] In this embodiment, each of the amplification transistor 34, the first reset transistor 36, the address transistor 40, the first transistor 81, and the specific reset transistor 76 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), specifically an N-channel MOSFET. However, these transistors may also be P-channel MOS. It is not necessary for all of these transistors to be unified as either N-channel MOS or P-channel MOS. This also applies to the second reset transistor 38, the second transistor 82, and the third transistor 83, which will be described later. Furthermore, as described above, the signal charge may be either a hole or an electron.

[0134] In this embodiment, the imaging device 101 includes a control circuit. The control circuit switches a first threshold potential depending on the imaging mode. Specifically, the imaging mode includes a first mode and a second mode. The control circuit can switch the imaging mode between the first mode and the second mode by changing the first threshold potential. As described above, in this embodiment, the control circuit is the vertical scanning circuit 16.

[0135] The second mode may be a mode with higher saturation than the first mode, and the first mode may be a mode with higher sensitivity than the second mode.

[0136] In this embodiment, in the second mode, the capacitance value of the charge storage capacitance X increases when or after the first transistor 81 is turned on in response to a change in the potential of the charge storage unit 37. Specifically, an increase in the capacitance value of the charge storage capacitance X originating from the first capacitive element 71 occurs. On the other hand, in the first mode, the first transistor 81 is maintained in the off state. Therefore, an increase in the capacitance value of the charge storage capacitance X originating from the first capacitive element 71 does not occur.

[0137] In this embodiment, as photoelectric conversion progresses, the potential of the charge accumulation unit 37 changes, thereby decreasing the gate-source voltage of the first transistor 81. The gate-source voltage when the potential of the charge accumulation unit 37 is at the reset potential Vrst in the second mode is smaller than the gate-source voltage when the potential of the charge accumulation unit 37 is at the reset potential Vrst in the first mode. Specifically, such a magnitude relationship is set by a control circuit.

[0138] In the examples shown in FIGS. 4 to 9B below, in the second mode, the control potential VF is set so that the specific circuit GSC can change the capacitance value of the charge storage capacitance X in response to a change in the potential of the charge storage unit 37. In the second mode, pseudo-gamma characteristics can be obtained within the pixel 11a without using downstream image processing in the imaging device 101. Therefore, the state in which the imaging mode is the second mode can be referred to as "auto gamma ON." On the other hand, in the first mode, the specific circuit GSC sets the control potential VF so that the capacitance value of the charge storage capacitance X does not change. Therefore, the state in which the imaging mode is the first mode can be referred to as "auto gamma OFF." In this way, in this example, the control potential VF can be controlled to switch between auto gamma ON and auto gamma OFF.

[0139] FIG. 4 is a timing chart illustrating an example of transistor operation in the first mode of the imaging device 101 according to the first embodiment. In FIG. 4, ADD schematically illustrates an example of a change in the potential of the gate electrode of the address transistor 40. RST1 schematically illustrates an example of a change in the potential of the gate electrode of the first reset transistor 36. VF schematically illustrates an example of a change in the control potential VF. RST3 schematically illustrates an example of a change in the potential of the gate electrode of the specific reset transistor 76. In the example illustrated in FIG. 4, at time t0, the address transistor 40, the first reset transistor 36, and the specific reset transistor 76 are all off. The potential of the control potential VF is maintained at a high level. In FIG. 4, a high level is represented as "High." For simplicity, a description of the operation of the electronic shutter will be omitted below.

[0140] First, at time t1, the address transistor 40 is turned on by controlling the potential of the address signal line 30. At this time, the signal charge stored in the charge storage capacitor X is read out.

[0141] Next, at time t2, the first reset transistor 36 is turned on by controlling the potential of the reset signal line 26. As a result, a reset potential Vrst is supplied from the reset voltage line 77 to the charge storage unit 37, resetting the potential of the charge storage unit 37. The reset potential Vrst is, for example, 1 V. The reset potential Vrst may be 0 V depending on the threshold voltage Vt of the amplifier transistor 34. Here, the threshold voltage Vt refers to the gate-source voltage when a drain current begins to flow through the amplifier transistor 34.

[0142] At time t2, the specific reset transistor 76 is turned on by controlling the potential of the specific reset signal line 75. As a result, a control potential VF is supplied to the first terminal 71a of the first capacitive element 71 via the source and drain of the specific reset transistor 76, resetting the potential of the first terminal 71a. In the first mode, the control potential VF supplied to the first terminal 71a is at a high level.

[0143] Next, at time t3, the first reset transistor 36 and the specific reset transistor 76 are turned off. Hereinafter, the period from when the first reset transistor 36 and the specific reset transistor 76 are turned on at time t2 to when the first reset transistor 36 and the specific reset transistor 76 are turned off may be referred to as the "reset period." In FIG. 4, the reset period is the period from time t2 to time t3. In FIG. 4, the reset period is schematically indicated by an arrow Rst.

[0144] In this embodiment, the period during which the first reset transistor 36 is on and the period during which the specific reset transistor 76 is on are both from time t2 to t3, and are the same. This configuration enables simultaneous control of the transistors 36 and 76, thereby shortening the time required for one frame.

[0145] Next, at time t4, exposure begins. In the illustrated example, there is a time lag between when the first reset transistor 36 and the specific reset transistor 76 are turned off and when exposure begins. However, exposure may begin simultaneously with turning off the first reset transistor 36 and the specific reset transistor 76.

[0146] In Figure 4, the exposure period is indicated by an arrow Exp. During the exposure period, the reset voltage is read out at a predetermined timing. This timing corresponds to time t5. Note that, because the time required to read out the reset voltage is short, the reset voltage may be read out while the address transistor 40 remains in the on state.

[0147] The signal from which fixed noise has been removed is obtained by taking the difference between the signal read between time t1 and time t2 and the signal read at time t5. In this way, the signal from which fixed noise has been removed is obtained.

[0148] 5 is a timing chart for explaining an example of the operation of the transistors in the second mode of the imaging device 101 according to the first embodiment. As described above, the second mode is a more highly saturated mode than the first mode. As can be seen from FIGS. 4 and 5, the second mode differs from the first mode in that the control potential VF is maintained at a low level. In FIG. 5, the low level is represented as Low.

[0149] 6 is a schematic diagram showing a typical example of the potential state of a transistor in the first mode of the imaging device 101 according to the first embodiment. As described above, in this embodiment, the signal charges are holes. Therefore, FIG. 6 also relates to the case where the signal charges are holes.

[0150] State (a) in FIG. 6 is the state at the start of exposure. In state (a) in FIG. 6, the potential of the charge storage unit 37 is the reset potential Vrst. The potential of the first terminal 71a of the first capacitance element 71 is the control potential VF. The potential of the charge storage unit 37 is higher than the potential under the gate of the first transistor 81. The potential of the first terminal 71a of the first capacitance element 71 is higher than the potential of the charge storage unit 37. The first transistor 81 is off.

[0151] State (b) in Figure 6 is the state during exposure. Because the signal charges are holes, the potential of the charge accumulation unit 37 rises during exposure. The gate electrode of the first transistor 81 is electrically connected to the charge accumulation unit 37. Therefore, as the potential of the charge accumulation unit 37 rises, the potential under the gate of the first transistor 81 also rises.

[0152] State (c) in Figure 6 is the state at the end of exposure. In the first mode, the control potential VF is at a high level. Therefore, the potential under the gate of the first transistor 81 has not yet reached a level higher than the control potential VF. In addition, the first transistor 81 is off.

[0153] 6, the differential voltage ΔV is the difference between the potential of the charge accumulation unit 37 at the start of exposure, i.e., the reset potential Vrst, and the potential of the charge accumulation unit 37 at the end of exposure. An electrical signal corresponding to the differential voltage ΔV can be output from the amplification transistor 34. As described above, the electrical signal is specifically a signal voltage.

[0154] FIG. 7 is a graph schematically showing a typical example of a change in the level of the electrical signal output from the amplifying transistor 34 in response to a change in the amount of light incident on the photoelectric conversion unit 15 in the first mode. In the graph shown in FIG. 7, the horizontal axis represents the amount of light, and the vertical axis represents the level of the electrical signal output from the amplifying transistor 34. The values on the horizontal and vertical axes in FIG. 7 are normalized values. This also applies to FIG. 9A, which will be described later. As shown in FIG. 7, in the first mode, as the amount of light increases, the level of the electrical signal output from the amplifying transistor 34 continuously increases. However, when the amount of light is 1, the increase in the signal level reaches a plateau.

[0155] FIG. 8 is a schematic diagram showing a typical example of the potential state of the transistors in the second mode of the imaging device 101 according to the first embodiment.

[0156] State (a) in FIG. 8 is the state at the start of exposure. In state (a), the potential of the charge storage unit 37 is the reset potential Vrst. The potential of the first terminal 71a of the first capacitance element 71 is the control potential VF. The potential of the charge storage unit 37 is higher than the potential under the gate of the first transistor 81. The potential of the first terminal 71a of the first capacitance element 71 is higher than the potential of the charge storage unit 37. The first transistor 81 is off.

[0157] State (b) in Figure 8 is the state during exposure. Because the signal charges are holes, the potential of the charge accumulation unit 37 rises during exposure. The gate electrode of the first transistor 81 is electrically connected to the charge accumulation unit 37. Therefore, as the potential of the charge accumulation unit 37 rises, the potential under the gate of the first transistor 81 also rises.

[0158] In the second mode, the control potential VF is at a low level. Therefore, the potential of the first terminal 71a at the start of exposure shown in state (a) is also at a low level. Therefore, when the potential under the gate of the first transistor 81 increases together with the potential of the charge storage unit 37, the potential under the gate of the first transistor 81 eventually reaches the potential of the first terminal 71a.

[0159] Furthermore, when the potential of the gate electrode of the first transistor 81 rises during exposure, the gate-source voltage of the first transistor 81 eventually exceeds the threshold voltage, turning on the first transistor 81. This electrically connects the charge accumulation unit 37 and the first terminal 71 a via the first transistor 81.

[0160] In the illustrated example, the timing at which the first transistor 81 turns on is the same as the timing at which the potential under the gate of the first transistor 81 reaches the potential of the first terminal 71 a. However, the former timing may be earlier or later than the latter timing.

[0161] When exposure is performed and the first transistor 81 is in an on state, a situation may arise in which the potential under the gate of the first transistor 81 is higher than the potential of the first terminal 71a and the potential of the charge accumulation unit 37 is higher than the potential under the gate of the first transistor 81. In this situation, electrons are injected into the charge accumulation unit 37 from the first terminal 71a via the first transistor 81. The injection of electrons decreases the potential of the charge accumulation unit 37. Accordingly, the potential under the gate of the first transistor 81 also decreases. Meanwhile, the potential of the first terminal 71a increases.

[0162] Such electron injection balances the potential of the charge accumulation unit 37 and the potential of the first terminal 71a. During exposure, the potential of the charge accumulation unit 37 and the potential of the first terminal 71a may rise while this balance is maintained. In this situation, the voltage between the first terminal 71a and the second terminal 71b changes as signal charge is generated. In other words, the first capacitive element 71 functions as part of the charge accumulation capacitance X that accumulates charge, and the capacitance value of the charge accumulation capacitance X increases. This slows down the change in the potential of the charge accumulation unit 37.

[0163] State (c) in Figure 8 is the state at the end of exposure. In the second mode, the potential of the charge accumulation unit 37 changes more slowly as described above, and therefore the potential of the charge accumulation unit 37 at the end of exposure is lower than in the first mode shown in Figure 6. Therefore, the differential voltage ΔV is lower in the second mode than in the first mode.

[0164] FIG. 9A is a graph schematically illustrating a typical example of the change in the level of the electrical signal output from the amplifying transistor 34 with respect to the change in the amount of light incident on the photoelectric conversion unit 15 in the second mode. As shown in FIG. 9A, in the second mode, as the amount of light increases, the increase in the level of the electrical signal output from the amplifying transistor 34 becomes more gradual when the amount of light increases beyond the first threshold amount of light. This is because the phenomenon of the gradual change in the potential of the charge accumulation unit 37 described with reference to FIG. 8 occurs in a range where the amount of light is equal to or greater than the first threshold amount of light. In other words, this is because the capacitance value of the charge accumulation capacitance X increases when the amount of light increases beyond the first threshold amount of light. As can be seen from FIGS. 9A and 7, in the second mode, signal charge can be accumulated in the charge accumulation capacitance X up to a range of higher light amounts compared to the first mode. This means that an electrical signal corresponding to the amount of light can be appropriately generated even in a range of higher light amounts. In other words, the dynamic range is expanded.

[0165] It is possible to correct the data of the electrical signal in the high light intensity region so that the graph of the light intensity-electrical signal characteristics in the high light intensity region is positioned on an extension of the graph of the light intensity-electrical signal characteristics in the low light intensity region. This correction is schematically shown by the block arrow and dotted line in Figure 9A. A specific example of this correction will be described later with reference to Figure 32, etc.

[0166] As can be understood from the explanation with reference to FIGS. 5, 8, and 9A, when the first capacitive element 71 does not function as a capacitance for storing charge generated by photoelectric conversion, the first capacitive element 71 does not constitute part of the charge storage capacitance X. On the other hand, when the first capacitive element 71 functions as a capacitance for storing charge generated by photoelectric conversion, the first capacitive element 71 constitutes part of the charge storage capacitance X. In the examples of FIGS. 5, 8, and 9A, the first capacitive element 71 functions as a capacitance for storing charge generated by photoelectric conversion, thereby increasing the charge storage capacitance X. In other words, the charge storage capacitance X increases as the first capacitive element 71 becomes "visible" as a capacitance.

[0167] The charge storage capacitance X can be explained as follows. That is, the capacitance value of a capacitance that does not function as a capacitance for storing charge generated by photoelectric conversion in the imaging device 101 is not counted as the capacitance value of the charge storage capacitance X. On the other hand, the capacitance value of a capacitance that functions as a capacitance for storing charge generated by photoelectric conversion in the imaging device 101 is counted as the capacitance value of the charge storage capacitance X. In other words, the capacitance value of a capacitance that is "invisible" as a capacitance in the imaging device 101 is not counted as the capacitance value of the charge storage capacitance X. On the other hand, the capacitance value of a capacitance that is "visible" as a capacitance in the imaging device 101 is counted as the capacitance value of the charge storage capacitance X.

[0168] Human vision becomes more sensitive to weaker light and less sensitive to stronger light. To mimic this characteristic of human vision, some camera systems use gamma correction in the image processing stage after the imaging device.

[0169] Fig. 9B is a graph for explaining gamma correction. The horizontal axis of Fig. 9B represents the amount of light, and the vertical axis represents the signal level held by the camera system. The values on the horizontal and vertical axes of Fig. 9B are normalized values.

[0170] In Figure 9B, the two-dot chain curve represents the light intensity vs. signal level characteristic obtained by gamma correction in the image processing downstream of the imaging device. The single-dot chain line represents the light intensity vs. signal level characteristic obtained without gamma correction. The single-dot chain line indicates that without gamma correction, the light intensity and the signal level held by the camera system have the same value. From the two-dot chain curve, it can be seen that gamma correction increases the ratio of the light intensity to the signal level in areas with low light intensity. For example, in the two-dot chain curve, when the light intensity is 0.2, the signal level is 0.5.

[0171] In Fig. 9B, the solid line indicates the light intensity-signal level characteristic that can be obtained in the second mode of this embodiment. From Fig. 9B, it can be seen that the second mode of this embodiment achieves a pseudo-gamma characteristic in pixel 11a. Specifically, the pseudo-gamma characteristic achieved in this embodiment has the following advantages. These advantages are useful in a camera system. -Easy to maintain S / N ratio in low light areas -Easy to allocate rich gradation or bit depth to low light areas In areas with high light intensity, it is easy to secure the capacitance value of the charge storage capacitance X, which makes it easy to achieve a wide dynamic range and prevent overexposure. In areas where the amount of light is high, the potential rise of the charge storage section 37 can be suppressed, and a high voltage is not applied to the charge storage section 37, transistors, etc. for a long period of time, which makes it easier to ensure the reliability of the imaging device 101.

[0172] As can be understood from the description with reference to FIGS. 9A and 9B, in this embodiment, when the amount of light incident on the imaging device 101 increases beyond the first threshold amount of light, the ratio of the increase in the level of the electrical signal to the increase in the amount of light incident on the imaging device 101 decreases. Specifically, this behavior can occur in the second mode. In this context, the electrical signal is the electrical signal output by the amplification transistor 34 in accordance with the potential of the charge accumulation unit 37. The amount of light incident on the imaging device 101 is specifically the amount of light incident on the photoelectric conversion unit 15. Specifically, the ratio is a value obtained by differentiating the level of the electrical signal by the amount of light. In these descriptions, the term "amount of light" can be replaced with "illuminance."

[0173] The gamma characteristic can be adjusted by adjusting the control potential VF. FIG. 10 is a graph for explaining the adjustment of the gamma characteristic. The example of FIG. 10 illustrates the cases where the control potential VF is set to a potential VFA, where the control potential VF is set to a potential VFB, and where the control potential VF is set to a potential VFC. The potential VFA is greater than the potential VFB, and the potential VFB is greater than the potential VFC. The first threshold light intensity when the control potential VF is set to the potential VFA is the light intensity QA. The first threshold light intensity when the control potential VF is set to the potential VFB is the light intensity QB. The first threshold light intensity when the control potential VF is set to the potential VFC is the light intensity QC. The light intensity QA is greater than the light intensity QB, and the light intensity QB is greater than the light intensity QC.

[0174] As described above, potential VFA > potential VFB > potential VFC, and light quantity QA > light quantity QB > light quantity QC. As can be seen from this, in a dark scene, by setting the control potential VF to potential VFA, it is possible to allocate a richer range of gradations or bits to an area with a low amount of light. In a bright scene, by setting the control potential VF to potential VFC, it is possible to allocate a richer range of gradations or bits to an area with a high amount of light.

[0175] Several other embodiments will be described below. In the following, elements common to the embodiments already described and the embodiments to be described thereafter will be given the same reference numerals, and their description may be omitted. The descriptions of the respective embodiments may be mutually applicable unless technically inconsistent. The respective embodiments may be combined with each other unless technically inconsistent.

[0176] (Second embodiment) In the second mode of the second embodiment, the transistors operate at different timings than in the second mode of the first embodiment. Fig. 11 is a timing chart for explaining an example of the operation of the transistors in the second mode of the imaging device according to the second embodiment. In Fig. 11, the dotted line with the letters RST3 written on it schematically shows an example of a change in the potential of the gate electrode of the specific reset transistor 76 in the first embodiment. The dotted line with the letters ta written on it schematically shows an example of a change in the potential of the gate electrode of the specific reset transistor 76 in the second embodiment.

[0177] As described with reference to FIG. 5 , in the second mode of the first embodiment, the period during which the first reset transistor 36 is on and the period during which the specific reset transistor 76 is on are the same. In this case, if the control potential VF is low, the gate-source voltage of the first transistor 81 may exceed the threshold voltage during the period during which these transistors 36 and 76 are on, potentially causing a short circuit between the first source and the first drain of the first transistor 81. This may result in an overcurrent. Furthermore, in this case, the potentials of the charge storage unit 37 and the node 47 may be reset to an intermediate potential between the control potential VF and the reset potential Vrst. This may result in an unstable reset of the potentials of the charge storage unit 37 and the node 47.

[0178] Therefore, in the second embodiment, the period during which the first reset transistor 36 is on and the period during which the specific reset transistor 76 is on are shifted. Specifically, the period during which the specific reset transistor 76 is on is set before the period during which the first reset transistor 36 is on. In this way, even if the control potential VF is low, it is possible to avoid a situation in which the first source and first drain of the first transistor 81 are short-circuited.

[0179] Furthermore, when the control potential VF is low, the first threshold potential is low, so the threshold light intensity can be set to a low light intensity. This can be understood from FIG.

[0180] Furthermore, according to the second embodiment, the potential states of the charge accumulation section 37 and the node 47 can be stabilized.

[0181] Typically, there is a time lag between the period when the first reset transistor 36 is on and the period when the specific reset transistor 76 is on, but this time lag does not have to exist.

[0182] FIG. 12 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the imaging device according to the second embodiment.

[0183] State (a) of FIG. 12 is the state before the specific reset transistor 76 and the first reset transistor 36 are turned on.

[0184] 12 shows a state during which the specific reset transistor 76 is on. In state (b), the node 47 is set to the control potential VF. The potential of the charge storage unit 37 is also set to the control potential VF.

[0185] 12 shows a state during which the first reset transistor 36 is on. In state (c), the potential of the charge storage section 37 is reset to the reset potential Vrst. The potential of the node 47 is also reset to the reset potential Vrst.

[0186] Incidentally, the first transistor 81 may have a substrate bias effect. In this case, a potential difference may occur between the first source and the first drain of the first transistor 81. However, even in this case, the potential states of the charge accumulation unit 37 and the node 47 can be stabilized by the operation of the transistor based on the timing chart of FIG.

[0187] 13 is a schematic diagram showing another example of the potential state of the transistor in the second mode of the imaging device according to the second embodiment. Specifically, FIG. 13 relates to a case where the first transistor 81 has a body bias effect.

[0188] State (a) of FIG. 13 is the state before the specific reset transistor 76 and the first reset transistor 36 are turned on.

[0189] 13 shows a state during which the specific reset transistor 76 is on. In state (b), the potential of the node 47 is set to the control potential VF. The potential of the charge storage unit 37 is set to a potential slightly higher than the control potential VF due to the substrate bias effect.

[0190] 13 shows a state during which the first reset transistor 36 is on. In state (c), the potential of the charge storage section 37 is reset to the reset potential Vrst. The potential of the node 47 is reset to a potential slightly lower than the reset potential Vrst due to the substrate bias effect.

[0191] (Third embodiment) FIG. 14 is a schematic diagram showing an exemplary circuit configuration of an imaging device 201 according to the third embodiment.

[0192] An inverting amplifier 24 is provided for each vertical signal line 18. In this example, these inverting amplifiers 24 are included in the peripheral circuitry.

[0193] A feedback control line 28 is provided for each row of pixels 11b. The pixels 11b in each row are electrically connected to the vertical scanning circuit 16 via the corresponding feedback control line 28. When the vertical scanning circuit 16 applies a predetermined voltage to the feedback control line 28, a feedback circuit that negatively feeds back the output of the pixels 11b can be formed.

[0194] A control line 32 is provided for each row of pixels 11b. The pixels 11b in each row are electrically connected to the vertical scanning circuit 16 via the corresponding control line 32. The vertical scanning circuit 16 can supply a predetermined voltage to the plurality of pixels 11b via the control line 32.

[0195] Each column of pixels 11b is provided with a power supply wiring 22. The pixels 11b in each column are electrically connected to the corresponding power supply wiring 22.

[0196] The negative input terminal of the inverting amplifier 24 is connected to the corresponding vertical signal line 18. A predetermined voltage Vref is supplied to the positive input terminal of the inverting amplifier 24. The voltage Vref is, for example, a positive voltage of 1 V or close to 1 V. The output terminal of the inverting amplifier 24 is connected via a feedback line 25 to the plurality of pixels 11b connected to the negative input terminal of the inverting amplifier 24. The inverting amplifier 24 forms part of a feedback circuit that negatively feeds back the electrical signal from the pixels 11b. The inverting amplifier 24 may also be called a feedback amplifier. The inverting amplifier 24 includes a gain adjustment terminal 24a for changing the inverting amplification gain.

[0197] FIG. 15 is a schematic diagram showing an exemplary circuit configuration of the pixel 11b shown in FIG.

[0198] The pixel 11b includes a capacitance circuit 45 in which a capacitance element 41 and a capacitance element 42 are connected in series. The capacitance value of the capacitance element 42 is larger than the capacitance value of the capacitance element 41. One of the source and drain of the first reset transistor 36, one electrode of the capacitance element 41, the pixel electrode 15c, and a node 44 are electrically connected to each other.

[0199] The other of the source and drain of the first reset transistor 36, the other electrode of the capacitor 41, and one electrode of the capacitor 42 are electrically connected. The capacitor 41 is connected in parallel to the first reset transistor 36. This parallel connection may reduce transistor junction leakage to a node 44 and reduce dark current. A node 46 including the connection point between the capacitor 41 and the capacitor 42 is referred to as a reset drain node.

[0200] The other terminal of the capacitance element 42 is electrically connected to the control line 32. The control line 32 is used to control the potential of this terminal. The potential of the control line 32 is set to, for example, 0 V, i.e., the reference potential. The potential of the control line 32 does not need to be fixed when the imaging device 201 is in operation. For example, a pulse voltage may be supplied from the vertical scanning circuit 16. The control line 32 can be used to control the potential of the node 44. Of course, the potential of the control line 32 may be fixed when the imaging device 201 is in operation.

[0201] The pixel 11b includes a second reset transistor 38. One of the source and drain of the second reset transistor 38 is electrically connected to a node 46. The other of the source and drain of the second reset transistor 38 is electrically connected to a feedback line 25. That is, the node 46 and the feedback line 25 are connected via the second reset transistor 38. The gate electrode of the second reset transistor 38 is electrically connected to a feedback control line 28. By controlling the potential of the feedback control line 28, a feedback circuit FC that feeds back the output of the signal detection circuit SC can be formed. Specifically, the feedback circuit FC negatively feeds back the output of the signal detection circuit SC.

[0202] 16 is a timing chart illustrating an example of the operation of transistors in the first mode of the imaging device 201 according to the third embodiment. In FIG. 16, RST2 schematically illustrates an example of a change in the potential of the gate electrode of the second reset transistor 38. GCNT schematically illustrates an example of a change in the potential applied to the gain adjustment terminal 24a of the inverting amplifier 24. In the example illustrated in FIG. 16, at time t0, the second reset transistor 38 is off. Furthermore, the voltage of the gain adjustment terminal 24a of the inverting amplifier 24 is a predetermined value.

[0203] First, at time t1, the address transistor 40 is turned on by controlling the potential of the address signal line 30. At this time, the signal charge stored in the charge storage capacitor X is read out.

[0204] Next, at time t2, the first reset transistor 36 and the second reset transistor 38 are turned on by controlling the potentials of the reset signal line 26 and the feedback control line 28. As a result, the node 44 and the feedback line 25 are connected via the first reset transistor 36 and the second reset transistor 38, and a feedback circuit FC that negatively feeds back the output of the signal detection circuit SC is formed. By interposing the second reset transistor 38 between the node 46 and the feedback line 25, the feedback circuit FC can be selectively formed by the second reset transistor 38 to feed back the signal of the photoelectric conversion unit 15.

[0205] In this example, the feedback circuit FC is formed for one of the multiple pixels 11b that share the feedback line 25. By controlling the potential of the gate electrode of the address transistor 40, the pixel 11b for which the feedback circuit FC is to be formed can be selected, and at least one selected from the group consisting of reset and noise cancellation can be performed for the desired pixel 11b.

[0206] Here, the feedback circuit FC is a negative feedback amplifier circuit including an amplifier transistor 34, an inverting amplifier 24, and a second reset transistor 38. An address transistor 40, which is turned on at time t1, provides the output of the amplifier transistor 34 as an input to the feedback circuit FC.

[0207] The potential of the charge storage unit 37 is reset by electrically connecting the node 44 and the feedback line 25. At this time, the output of the signal detection circuit SC is negatively fed back, causing the potential of the vertical signal line 18 to converge to the potential Vref applied to the positive input terminal of the inverting amplifier 24. That is, in this example, the reference potential at the reset is the potential Vref. In the configuration illustrated in FIG. 15, the potential Vref can be set arbitrarily within the range between the power supply potential and the ground potential. In other words, any voltage within a certain range can be used as the reference potential at the reset. For example, a potential other than the power supply potential can be used as the reference potential at the reset. The power supply potential is, for example, 3.3 V. The ground potential is 0 V.

[0208] Also, at time t2, the potential of the gain adjustment terminal 24a of the inverting amplifier 24 is controlled to reduce the gain of the inverting amplifier 24. In the inverting amplifier 24, the product G×B of the gain G and the band B is constant, so reducing the gain G widens the band B. This makes it possible to speed up the convergence described above in the negative feedback amplifier circuit. Widening the band B means that the cutoff frequency becomes higher.

[0209] At time t2, the specific reset transistor 76 is turned on by controlling the potential of the specific reset signal line 75. As a result, a control potential VF is supplied to the first terminal 71a of the first capacitive element 71 via the source and drain of the specific reset transistor 76, resetting the potential of the first terminal 71a. In the first mode, the control potential VF supplied to the first terminal 71a is at a high level.

[0210] Next, at time t3, the first reset transistor 36 and the specific reset transistor 76 are turned off. Hereinafter, the period from when the first reset transistor 36, the second reset transistor 38, and the specific reset transistor 76 are turned on at time t2 until the first reset transistor 36 and the specific reset transistor 76 are turned off may be referred to as the "reset period." In FIG. 16, the reset period is the period from time t2 to time t3. In FIG. 16, the reset period is schematically indicated by the arrow Rst. Turning off the first reset transistor 36 at time t3 generates kTC noise. Therefore, kTC noise is added to the voltage of the charge storage unit 37 after reset.

[0211] 15, the feedback circuit FC remains formed while the second reset transistor 38 is on. Therefore, the kTC noise generated by turning off the first reset transistor 36 at time t3 is canceled to a magnitude of 1 / (1+A), where A is the gain of the feedback circuit FC.

[0212] In this example, the voltage of the vertical signal line 18 immediately before the first reset transistor 36 is turned off, i.e., immediately before noise cancellation begins, is approximately equal to the voltage Vref applied to the negative input terminal of the inverting amplifier 24. By keeping the voltage of the vertical signal line 18 at the start of noise cancellation close to the target voltage Vref after noise cancellation, kTC noise can be canceled in a relatively short time. Hereinafter, the period from when the first reset transistor 36 is turned off to when the second reset transistor 38 is turned off may be referred to as the "noise cancellation period." In FIG. 16, the noise cancellation period is the period from time t3 to time t4. In FIG. 16, the noise cancellation period is schematically indicated by the arrow Ncl.

[0213] At time t3, the gain of the inverting amplifier 24 is reduced, so that noise can be cancelled at high speed in the early stage of the noise cancellation period.

[0214] Next, at time t3', the potential of the gain adjustment terminal 24a of the inverting amplifier 24 is controlled to increase the gain of the inverting amplifier 24. This further reduces the noise level. The product G×B of the gain G and the bandwidth B is constant. Therefore, increasing the gain G narrows the bandwidth B, and the time required for convergence in the negative feedback amplifier circuit increases. However, between t3 and t3', the voltage of the vertical signal line 18 has already been controlled to be close to the convergence level. Therefore, the range of the voltage to be converged is already limited to a small range, and the increase in convergence time due to the narrowing of bandwidth B is limited. Note that narrowing bandwidth B refers to a lower cutoff frequency.

[0215] As described above, according to the third embodiment, it is possible to reduce the kTC noise that occurs when the first reset transistor 36 is turned off, and to cancel the generated kTC noise in a relatively short time.

[0216] Next, at time t4, the second reset transistor 38 is turned off, and exposure is performed for a predetermined period. Turning off the second reset transistor 38 at time t4 generates kTC noise. However, according to the second embodiment, by appropriately setting the capacitance values of the capacitive elements 41 and 42, it is possible to sufficiently reduce the kTC noise generated by turning off the second reset transistor 38.

[0217] In Figure 16, the exposure period is indicated by an arrow Exp. During the exposure period, the reset voltage from which the kTC noise has been cancelled is read out at a predetermined timing. This timing corresponds to time t5. Note that, because the time required to read out the reset voltage is short, the reset voltage may be read out while the address transistor 40 remains in the on state.

[0218] A signal from which fixed noise has been removed is obtained by taking the difference between the signal read between time t1 and time t2 and the signal read at time t5. In this way, a signal from which kTC noise and fixed noise have been removed is obtained.

[0219] 17 is a timing chart illustrating an example of the operation of the transistors in the second mode of the imaging device 201 according to the third embodiment. As described above, the second mode is a more highly saturated mode than the first mode. As can be seen from FIGS. 16 and 17, the second mode differs from the first mode in that the control potential VF is maintained at a low level.

[0220] (Fourth embodiment) 18 is a schematic diagram showing an exemplary circuit configuration of a pixel 11c in an image pickup device according to the fourth embodiment. As shown in FIG. 18, the image pickup device according to the fourth embodiment differs from the image pickup device 201 according to the third embodiment in that a switching circuit 50 is provided in each column of pixels 11c instead of an inverting amplifier 24. In the plurality of pixels 11c constituting each column of the image pickup device according to the fourth embodiment, the feedback line 25 does not connect the pixels 11c.

[0221] In each pixel 11c, one of the source and drain of the second reset transistor 38 is electrically connected to the node 46. The other of the source and drain of the second reset transistor 38 is electrically connected to the feedback line 25. One of the source and drain of the address transistor 40 is electrically connected to the feedback line 25 and the vertical signal line 18. The other of the source and drain of the address transistor 40 is electrically connected to one of the source and drain of the amplifier transistor 34. The other of the source and drain of the amplifier transistor 34 is electrically connected to the power supply wiring 22.

[0222] The switching circuit 50 includes switch elements 51 and 51', switch elements 52 and 52', and constant current sources 27 and 27'.

[0223] The switch elements 51 and 51′ are electrically connected to the power supply wiring 22. A power supply potential AVDD can be connected to the power supply wiring 22 via the switch element 51. A reference potential AVSS can be connected to the power supply wiring 22 via the switch element 51′.

[0224] The switch elements 52 and 52′ are electrically connected to the vertical signal line 18. A reference potential AVSS can be connected to the vertical signal line 18 via the constant current source 27 and the switch element 52 in this order. A power supply potential AVDD can be connected to the vertical signal line 18 via the constant current source 27′ and the switch element 52′ in this order.

[0225] During signal readout, a voltage is applied to the gate electrode of the address transistor 40 via the address signal line 30. This selects one of the pixels 11c in each column. Furthermore, by turning on the switch elements 51 and 52 of the switching circuit 50, a current flows from the constant current source 27 in a direction from the amplifier transistor 34 to the address transistor 40, and the potential of the charge storage unit 37 amplified by the amplifier transistor 34 is detected.

[0226] During the reset operation, the switch elements 51' and 52' of the switching circuit 50 are turned on. This causes a current to flow through the address transistor 40 and the amplifier transistor 34 in the opposite direction to that during signal readout. This forms a feedback circuit FC including the amplifier transistor 34, address transistor 40, feedback line 25, second reset transistor 38, and first reset transistor 36. Because the address transistor 40 and the amplifier transistor 34 are cascode-connected, a large gain can be obtained. Therefore, the feedback circuit FC can perform noise cancellation with a large gain.

[0227] The imaging device of this embodiment can reduce kTC noise, similarly to the third embodiment.

[0228] Furthermore, the imaging device of this embodiment does not include the inverting amplifier 24, and the address transistor 40 and the amplifying transistor 34 are included in the signal detection circuit SC and function as an amplifier in the feedback circuit FC. This allows the circuit area of the imaging device to be reduced. It also allows the power consumption of the imaging device to be reduced. Furthermore, since a large gain can be obtained by the cascode connection, it is possible to reduce kTC noise even when the capacitances of the capacitive elements 41 and 42 are small.

[0229] (Fifth embodiment) 19A is a schematic diagram illustrating an exemplary circuit configuration of an imaging device according to a fifth embodiment. The circuit configuration of a pixel 11d according to the fifth embodiment illustrated in FIG. 19A differs from the circuit configuration of the pixel 11a according to the first embodiment illustrated in FIG. 2 in that a specific circuit GSC is different.

[0230] In the fifth embodiment, a first gate electrode of the first transistor 81 is electrically connected to a first terminal 71a of the first capacitance element 71 and the charge storage portion 37. One of a first source and a first drain of the first transistor 81 is electrically connected to a second terminal 71b of the first capacitance element 71. In the present embodiment, a control potential VF is applied to the other of the first source and the first drain of the first transistor 81 from a control circuit.

[0231] In this embodiment, the node 47 is electrically connected to one of the first source and the first drain of the first transistor 81 and the second terminal 71b of the first capacitive element 71. The node 48 is electrically connected to the other of the first source and the first drain of the first transistor 81. In this embodiment, one of the source and the drain of the first reset transistor 36 forms the charge storage unit 37.

[0232] In this embodiment, the specification circuit GSC changes the capacitance value of the charge storage capacitor X in response to a change in the potential of the charge storage section 37 in the following manner.

[0233] When the potential of the charge storage unit 37 is low, the potential of the gate electrode of the first transistor 81 is also low. The first transistor 81 is off. The control potential VF is not supplied to the node 47 and the second terminal 71b of the first capacitance element 71. The node 47 and the second terminal 71b are in a floating state. In this case, the first capacitance element 71 does not function as a capacitance for storing charge generated by photoelectric conversion. Therefore, the capacitance value of the charge storage capacitance X is not increased by the first capacitance element 71.

[0234] During exposure, the potential of the charge storage unit 37 rises, and accordingly, the potential of the gate electrode of the first transistor 81 also rises. As the potential of the gate electrode of the first transistor 81 rises, the gate-source voltage of the first transistor 81 eventually exceeds the threshold voltage, turning on the first transistor 81. When the first transistor 81 is on, a control potential VF is supplied to the node 47 and the second terminal 71b of the first capacitive element 71 via the first source and first drain of the first transistor 81. In other words, the potentials of the node 47 and the second terminal 71b are fixed. In this case, the first capacitive element 71 functions as a capacitor that accumulates charges generated by photoelectric conversion. In this way, the capacitance value of the charge storage capacitance X increases due to the first capacitive element 71.

[0235] In this manner, in this embodiment, the capacitance value of the charge storage capacitance X is changed by floating control of the first capacitance element 71. For details of floating control, see Patent Document 3.

[0236] 20 is a timing chart illustrating a typical example of transistor operation in the second mode of the imaging device according to the fifth embodiment. The example shown in FIG. 20 relating to the fifth embodiment and the example shown in FIG. 5 relating to the first embodiment differ in the period during which the first reset transistor 36 is in the on state. Specifically, in the example shown in FIG. 20, the first reset transistor 36 is on during the period from time t2 to t4.

[0237] 20, Vrst schematically shows an example of changes in the reset potential Vrst applied to the reset voltage line 77. In the example shown in Fig. 20, the reset potential Vrst applied to the reset voltage line 77 is at a low level from time t0 to time t2, at a high level from time t2 to t3, and at a low level from time t3 onwards.

[0238] In the example of Fig. 20, the end of the reset period corresponds to the start of the exposure period, although there may be a time lag between the end of the reset period and the start of the exposure period.

[0239] 21 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the imaging device according to the fifth embodiment. The state in FIG. 21 can be obtained by the control in FIG.

[0240] State (a) in FIG. 21 represents the state during the period from time t2 to t3. During this period, the first reset transistor 36 is in the ON state, and the reset potential Vrst is at a high level. Therefore, the high-level reset potential Vrst is applied to the first gate electrode of the first transistor 81. The first transistor 81 is ON. The control potential VF is supplied not only to the node 48, but also to the node 47 and the second electrode 71b via the first source and first drain of the first transistor 81. Thus, the potentials of the node 47 and the second electrode 71b are reset to the control potential VF.

[0241] State (b) in FIG. 21 shows the state during the period from time t3 to t4. During this period, the first reset transistor 36 is on, but the reset potential Vrst is low. Therefore, the first transistor 81 is off. During this period, the potential of the charge storage unit 37 is reset to the low-level reset potential Vrst.

[0242] As can be understood from the above description, in the examples of FIGS. 19A, 20, and 21, during the reset period, the control circuit applies a reset potential Vrst to the charge accumulation unit 37. During a period included in the reset period, the control circuit temporarily turns on the first transistor 81 by changing the level of the reset potential Vrst in a pulsed manner. In this way, when the first transistor 81 is temporarily turned on, the control circuit applies a control potential VF to the second terminal 71b via the first source and first drain of the first transistor 81, thereby resetting the potential of the second terminal 71b. Thus, according to this example, during the reset period, the potential of the charge accumulation unit 37 and the potential of the second terminal 71b can be reset.

[0243] Specifically, the reset period has a first period and a second period following the first period. The first period is a period following the zero period. During the zero period and the second period, the reset potential Vrst is at the second level. During the first period, the reset potential Vrst is at the first level. During the first period, the potential of the second terminal 71b is reset to the control potential VF. During the second period, the potential of the charge accumulation unit 37 is reset to the reset potential Vrst at the second level.

[0244] The first period corresponds to the period from time t2 to t3 in Figure 20. The second period corresponds to the period from time t3 to t4 in Figure 20. The first level corresponds to the high level in Figure 20. The second level corresponds to the low level in Figure 20.

[0245] In the circuit configuration shown in Fig. 19A, the potential of the second terminal 71b and the potential of the node 47 can also be reset in addition to the reset of the potential of the charge accumulation unit 37 by control different from the control shown in Fig. 20. Fig. 22 is a timing chart for explaining another example of the operation of the transistor in the second mode of the imaging device according to the fifth embodiment.

[0246] The example shown in Fig. 22 is different from the example shown in Fig. 20 in the reset potential Vrst applied to the reset voltage line 77. Specifically, in the example shown in Fig. 22, the reset potential Vrst applied to the reset voltage line 77 is constant at a low level.

[0247] The control potential VF differs between the example shown in FIG. 22 and the example shown in FIG. 20. Specifically, in the example shown in FIG. 22, the control potential VF is at a first low level from time t0 to time t2, at a second low level from time t2 to t3, and at the first low level from time t3 onward. The second low level is lower than the first low level. In FIG. 22, the first low level is denoted as Low1, and the second low level is denoted as Low2.

[0248] 23 is a schematic diagram showing an example of the potential state of the transistor in the second mode of the imaging device according to the fifth embodiment. The state in FIG. 23 can be obtained by the control in FIG.

[0249] 23 shows a state during the period from time t2 to time t3. During this period, the control potential VF is at a relatively low second low level. The second low level is lower than the potential under the gate of the first transistor 81 in the off state. Therefore, even though the first transistor 81 is in the off state, the control potential VF is supplied from the control circuit to the node 47 and the second terminal 71b via the first source and the first drain.

[0250] 23 shows the state during the period from time t3 to time t4. During this period, the control potential VF is at a relatively high first low level. The first low level is higher than the potential under the gate of the first transistor 81 in the off state. By transitioning from state (a) to state (b), the potentials of the node 47 and the second electrode 71b are reset to the potential under the gate of the first transistor 81 in the off state.

[0251] According to the control shown in FIGS. 22 and 23, the potential of the charge storage section 37 is reset to the reset potential Vrst.

[0252] 19A, 22, and 23, during the reset period, the control circuit applies a reset potential Vrst to the charge storage unit 37. During a period included in the reset period, the control circuit temporarily shorts the first source and the first drain of the first transistor 81 in the off state by changing the level of the control potential VF in a pulsed manner. According to this example, during the reset period, the potential of the second terminal 71b can be reset in addition to the reset of the potential of the charge storage unit 37.

[0253] Specifically, the reset period includes a first period and a second period following the first period. The first period follows the zero period. During the zero, first, and second periods, the reset potential Vrst is at a level that maintains the first transistor 81 in an off state. During the zero and second periods, the control potential VF is at a third level. During the first period, the control potential VF is at a fourth level. The third level does not short-circuit the first source and first drain of the first transistor 81. The fourth level shorts the first source and first drain of the first transistor 81. The control circuit changes the control potential VF between the third and fourth levels, in other words, across the level of the potential under the gate of the first transistor 81 in the off state. This resets the potential of the second electrode 71b to the potential under the gate of the first transistor 81 in the off state. During the second period, the potential of the charge storage unit 37 is reset to the reset potential Vrst. The control potential VF after the reset period is a potential that realizes auto gamma ON.

[0254] The first period corresponds to the period from time t2 to t3 in Figure 20. The second period corresponds to the period from time t3 to t4 in Figure 20. The third level corresponds to the first low level in Figure 22. The fourth level corresponds to the second low level in Figure 22.

[0255] 19A to 23, the potential of the second terminal 71b and the potential of the node 47 can be reset in addition to resetting the potential of the charge accumulation unit 37. The potential state of the node 47 can be stabilized. Furthermore, according to this example, the potential of the second terminal 71b and the potential of the node 47 can be reset without the specific reset transistor 76 shown in FIG. 2. This is advantageous from the viewpoint of reducing the size of the pixel 11d, improving the resolution, etc.

[0256] When performing floating control, the specific circuit GSC may have a specific reset transistor 76. Fig. 19B is a schematic diagram showing another exemplary circuit configuration of the imaging device according to the fifth embodiment.

[0257] 19B, one of the source and drain of the specific reset transistor 76 is connected to the node 47. A control potential VF is applied to the other of the source and drain of the specific reset transistor 76 from the control circuit.

[0258] 19B, the potential of the second terminal 71b and the potential of the node 47 can be reset to the control potential VF by turning on the specific reset transistor 76. Therefore, the potential of the second terminal 71b and the potential of the node 47 can be reset without the timing control shown in FIGS.

[0259] (Sixth embodiment) 24 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to Embodiment 6. In a pixel 11f according to Embodiment 6, the first capacitance element 71 is a MOS capacitor.

[0260] A first terminal 71a of the first capacitance element 71 is electrically connected to the gate electrode of the amplification transistor 34, the charge accumulation unit 37, the node 44, and the photoelectric conversion unit 15. Specifically, the first terminal 71a is electrically connected to the pixel electrode 15c.

[0261] By employing the first capacitive element 71, which is a MOS capacitor, it is possible to realize the specific circuit GSC with a small number of elements, which is advantageous from the viewpoint of reducing the size of the pixel 11f, improving the resolution, etc.

[0262] In this embodiment, the first capacitive element 71, which is a MOS capacitor, is configured using a first transistor 81. One of the first terminal 71a and the second terminal 71b is electrically connected to a first source and a first drain of the first transistor 81. The other of the first terminal 71a and the second terminal 71b is electrically connected to a first gate electrode of the first transistor 81. In the example of FIG. 24 , the second terminal 71b is electrically connected to the first source and the first drain of the first transistor 81. The first terminal 71a is electrically connected to the first gate electrode of the first transistor 81.

[0263] The first source and the first drain of the first transistor 81 are electrically connected to each other. With this configuration, the first transistor 81 can be turned on when the difference between the potential of the first capacitive element 71 and the potential of the second terminal 71b reaches a certain value. The first source and the first drain of the first transistor 81 can be electrically connected by wiring or the like.

[0264] The operation of the imaging device according to this embodiment will be described below. In the following description, the term "terminal voltage of the first capacitance element 71" will be used. The terminal voltage is the difference between the potential of the first capacitance element 71 and the potential of the second terminal 71b.

[0265] A control potential VF is applied to the second terminal 71b of the first capacitance element 71. Meanwhile, the first terminal 71a is electrically connected to the charge storage section 37. Therefore, when photoelectric conversion occurs in the photoelectric conversion section 15, the potential of the first terminal 71a changes along with the potential of the charge storage section 37, and the voltage between the terminals also changes. Specifically, since the signal charge is a hole, when photoelectric conversion occurs in the photoelectric conversion section 15, the potential of the first terminal 71a increases along with the potential of the charge storage section 37. When the voltage between the terminals reaches a certain value, the first transistor 81 turns on. This causes the first capacitance element 71 to function as a capacitance that stores the charge generated by photoelectric conversion. In this way, the capacitance value of the charge storage capacitance X increases.

[0266] The control potential VF applied to the second terminal 71b may be switched. In one example, the imaging mode of the imaging device has a first mode and a second mode. In the first mode, the control potential VF applied to the second terminal 71b is a potential VFA. In the second mode, the control potential VF applied to the second terminal 71b is a potential VFB. The potentials VFA and VFB are different from each other. According to this example, a difference can be made between the first threshold potential in the first mode and the first threshold potential in the second mode.

[0267] In this embodiment, the first capacitive element 71, which is a MOS capacitor, can function as a capacitor that accumulates charge generated by photoelectric conversion. Typically, this function changes stepwise as the potential of the charge accumulation unit 37 varies across the first threshold potential. However, this function can also change continuously as the potential of the charge accumulation unit 37 varies across the first threshold potential. The expression "the specific circuit GSC changes the capacitance value of the charge accumulation capacitance X when the potential of the charge accumulation unit 37 varies across the first threshold potential" encompasses both of these modes. The expression "the specific circuit GSC changes the capacitance value of the charge accumulation capacitance X by the capacitance value of the first capacitive element 71 in response to the change in the potential of the charge accumulation unit 37" encompasses both of these modes. Furthermore, the expression "the specific circuit GSC changes the capacitance value of the charge accumulation capacitance X in response to the change in the potential of the charge accumulation unit 37" encompasses both of these modes.

[0268] (Seventh embodiment) Fig. 25 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the seventh embodiment. The circuit configuration of pixel 11g according to the seventh embodiment shown in Fig. 25 is different from the circuit configuration of pixel 11d according to the fifth embodiment shown in Fig. 19A in that the specific circuit GSC is different. Specifically, the specific circuit GSC according to the seventh embodiment shown in Fig. 25 has multiple stages of circuits corresponding to the specific circuit GSC according to the fifth embodiment shown in Fig. 19A.

[0269] Specifically, in the seventh embodiment, the specified circuit GSC has a first transistor 81, a second transistor 82, a third transistor 83, a first capacitance element 71, a second capacitance element 72, and a third capacitance element 73.

[0270] Hereinafter, the source of the second transistor 82 may be referred to as the second source. The drain of the second transistor 82 may be referred to as the second drain. The gate electrode of the second transistor 82 may be referred to as the second gate electrode. The source of the third transistor 83 may be referred to as the third source. The drain of the third transistor 83 may be referred to as the third drain. The gate electrode of the third transistor 83 may be referred to as the third gate electrode.

[0271] The second capacitive element 72 includes a first terminal 72a and a second terminal 72b, and the third capacitive element 73 includes a first terminal 73a and a second terminal 73b.

[0272] A first gate electrode of the first transistor 81 is electrically connected to the first terminal 71a of the first capacitance element 71 and the charge storage portion 37. One of the first source and the first drain of the first transistor 81 is electrically connected to the second terminal 71b of the first capacitance element 71. A first control potential VF1 is applied to the other of the first source and the first drain of the first transistor 81 from the control circuit.

[0273] A second gate electrode of the second transistor 82 is electrically connected to the first terminal 72a of the second capacitance element 72 and the charge storage portion 37. One of the second source and the second drain of the second transistor 82 is electrically connected to the second terminal 72b of the second capacitance element 72. A second control potential VF2 is applied to the other of the second source and the second drain of the second transistor 82 from the control circuit.

[0274] A third gate electrode of the third transistor 83 is electrically connected to the first terminal 73a of the third capacitance element 73 and the charge storage unit 37. One of the third source and the third drain of the third transistor 83 is electrically connected to the second terminal 73b of the third capacitance element 73. A third control potential VF3 is applied to the other of the third source and the third drain of the third transistor 83 from the control circuit.

[0275] FIG. 26 is a diagram illustrating a typical example of a change in the level of the electrical signal output from the amplifying transistor 34 with respect to a change in the amount of light incident on the photoelectric conversion unit 15 in the second mode according to the seventh embodiment. In this embodiment, when the amount of light incident on the imaging device increases beyond the first threshold light amount Qth1, the first capacitive element 71 functions as a capacitance that accumulates charge generated by photoelectric conversion. This increases the capacitance value of the charge storage capacitance X. When the amount of light incident on the imaging device increases beyond the second threshold light amount Qth2, the second capacitive element 72 functions as a capacitance that accumulates charge generated by photoelectric conversion. This increases the capacitance value of the charge storage capacitance X. When the amount of light incident on the imaging device increases beyond the third threshold light amount Qth3, the third capacitive element 73 functions as a capacitance that accumulates charge generated by photoelectric conversion. This increases the capacitance value of the charge storage capacitance X. In this context, the amount of light incident on the imaging device specifically refers to the amount of light incident on the photoelectric conversion unit 15.

[0276] Hereinafter, in the light amount-electrical signal level characteristics shown in Fig. 26, the band where the light amount is equal to or greater than the first threshold light amount Qth1 and less than the second threshold light amount Qth2 will be referred to as band (1). The band where the light amount is equal to or greater than the second threshold light amount Qth2 and less than the third threshold light amount Qth3 will be referred to as band (2). The band where the light amount is equal to or greater than the third threshold light amount Qth3 will be referred to as band (3).

[0277] The potential of the charge storage unit 37 when the light amount is the first threshold light amount Qth1 is referred to as the first threshold potential. The potential of the charge storage unit 37 when the light amount is the second threshold light amount Qth2 is referred to as the second threshold potential. The potential of the charge storage unit 37 when the light amount is the second threshold light amount Qth3 is referred to as the third threshold potential.

[0278] In this embodiment, the third control potential VF3, the second control potential VF2, and the first control potential VF1 are different from one another. In this way, the first threshold light intensity Qth1, the second threshold light intensity Qth2, and the third threshold light intensity Qth3 can be different from one another. In this context, the threshold voltage is the gate-source voltage of a transistor when the transistor turns on.

[0279] Specifically, in this embodiment, the third control potential VF3 is greater than the second control potential VF2. The second control potential VF2 is greater than the first control potential VF1. In this way, as shown in FIG. 26, the third threshold light amount Qth3 can be made greater than the second threshold light amount Qth2, and the second threshold light amount Qth2 can be made greater than the first threshold light amount Qth1.

[0280] In the modified example, the threshold voltage Vth3 of the third transistor 83, the threshold voltage Vth2 of the second transistor 82, and the threshold voltage Vth1 of the first transistor 81 are different from one another. Also in the modified example, the first threshold light amount Qth1, the second threshold light amount Qth2, and the third threshold light amount Qth3 can be different from one another.

[0281] Specifically, in the above modification, the threshold voltage Vth3 of the third transistor 83 is greater than the threshold voltage Vth2 of the second transistor 82. The threshold voltage Vth2 of the second transistor 82 is greater than the threshold voltage Vth1 of the first transistor 81. In this way, the third threshold light amount Qth3 can be made greater than the second threshold light amount Qth2, and the second threshold light amount Qth2 can be made greater than the first threshold light amount Qth1.

[0282] Both the magnitude relationship of third control potential VF3 > second control potential VF2 > first control potential VF1 and the magnitude relationship of threshold voltage Vth3 > threshold voltage Vth2 > threshold voltage Vth1 may be satisfied, or only one of these magnitude relationships may be satisfied.

[0283] In this embodiment, the capacitance value C3 of the third capacitive element 73 is larger than the capacitance value C2 of the second capacitive element 72. The capacitance value C2 of the second capacitive element 72 is larger than the capacitance value C1 of the first capacitive element 71. In this way, a pseudo-gamma characteristic having the following advantages can be obtained. These advantages are useful in a camera system. -Easy to maintain S / N ratio in low light areas -Easy to allocate rich gradation or bit depth to low light areas In areas with high light intensity, it is easy to secure the capacitance value of the charge storage capacitance X, which makes it easy to achieve a wide dynamic range and prevent overexposure. In areas with high light intensity, the potential rise of the charge storage section 37 can be suppressed, and high voltage is not applied to the charge storage section 37, transistors, etc. for a long period of time, which makes it easier to ensure the reliability of the imaging device.

[0284] In this embodiment, the specifying circuit GSC changes the capacitance value of the charge storage capacitance X when the potential of the charge storage unit 37 changes across a first threshold potential, when the potential of the charge storage unit 37 changes across a second threshold potential, and when the potential of the charge storage unit 37 changes across a third threshold potential. This configuration can contribute to realizing a gamma characteristic that is useful in a camera system.

[0285] In one example, when the potential of the charge storage unit 37 changes across a first threshold potential, the identification circuit GSC changes the capacitance value of the charge storage capacitance X in accordance with the capacitance value of the first capacitive element 71. When the potential of the charge storage unit 37 changes across a second threshold potential, the identification circuit GSC changes the capacitance value of the charge storage capacitance X in accordance with the capacitance value of the second capacitive element 72. When the potential of the charge storage unit 37 changes across a third threshold potential, the identification circuit GSC changes the capacitance value of the charge storage capacitance X in accordance with the capacitance value of the third capacitive element 73.

[0286] In one specific example, when the potential of the charge storage unit 37 changes across a first threshold potential, the identification circuit GSC changes the capacitance value of the charge storage capacitance X by the capacitance value of the first capacitance element 71. When the potential of the charge storage unit 37 changes across a second threshold potential, the identification circuit GSC changes the capacitance value of the charge storage capacitance X by the capacitance value of the second capacitance element 72. When the potential of the charge storage unit 37 changes across a third threshold potential, the identification circuit GSC changes the capacitance value of the charge storage capacitance X by the capacitance value of the third capacitance element 73.

[0287] The specifying circuit GSC of the seventh embodiment shown in Fig. 25 has multiple stages of circuits corresponding to the specifying circuit GSC of the fifth embodiment shown in Fig. 19A. However, the specifying circuit GSC may have multiple stages of circuits corresponding to the specifying circuits GSC of other embodiments. Also, although the number of stages is three in this embodiment, the number of stages may be two or four or more.

[0288] (Eighth embodiment) FIG. 27 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the eighth embodiment.

[0289] In the pixel 11h according to the eighth embodiment, unlike the pixel 11a according to the first embodiment, the photoelectric conversion unit 15 is a photodiode. Specifically, the photoelectric conversion unit 15 is a silicon photodiode. The photoelectric conversion unit 15 also serves as a charge accumulation unit 55 in which charges generated by photoelectric conversion are accumulated. The signal charges are electrons.

[0290] In this embodiment, the first gate electrode of the first transistor 81 is electrically connected to the first terminal 71a of the first capacitance element 71. One of the first source and the first drain of the first transistor 81 is electrically connected to the first terminal 71a. The other of the first source and the first drain is electrically connected to the charge accumulation unit 55. In this embodiment, a control potential is applied to the second terminal 71b of the first capacitance element 71 from the control circuit.

[0291] In this embodiment, the node 48 is electrically connected to the second terminal 71b of the first capacitance element 71. The node 47 is electrically connected to one of the first source and the first drain of the first transistor 81 and the first terminal 71a of the first capacitance element 71.

[0292] FIG. 28 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the imaging device according to the eighth embodiment.

[0293] State (a) in FIG. 28 is the state at the start of exposure. In state (a) in FIG. 28, the potential of the charge accumulation unit 55 is the reset potential Vrst. The potential of the first terminal 71a of the first capacitance element 71 is the control potential VF. The potential of the first terminal 71a of the first capacitance element 71 is higher than the potential under the gate of the first transistor 81. The potential of the charge accumulation unit 55 is higher than the potential of the first terminal 71a of the first capacitance element 71. The first transistor 81 is off.

[0294] 28(b) shows the state during exposure. Since the signal charge is electrons, the potential of the charge accumulation section 55 decreases during exposure.

[0295] As exposure progresses and the potential of the charge storage unit 55 decreases, the gate-source voltage of the first transistor 81 eventually exceeds the threshold voltage, turning on the first transistor 81. This electrically connects the charge storage unit 55 and the first terminal 71 a via the first transistor 81.

[0296] When exposure is performed and the first transistor 81 is in an on state, a situation may arise in which the potential under the gate of the first transistor 81 is lower than the potential of the first terminal 71a and the potential of the charge accumulation unit 55 is lower than the potential under the gate of the first transistor 81. In this situation, electrons are injected from the charge accumulation unit 55 to the first terminal 71a via the first transistor 81. The injection of electrons increases the potential of the charge accumulation unit 55. Accordingly, the potential under the gate of the first transistor 81 also increases. Meanwhile, the potential of the first terminal 71a decreases.

[0297] This electron injection balances the potential of the charge accumulation unit 55 and the potential of the first terminal 71a. During exposure, while this balance is maintained, the potential of the charge accumulation unit 55 and the potential of the first terminal 71a may decrease. In this situation, the voltage between the first terminal 71a and the second terminal 71b changes as signal charge is generated. In other words, the first capacitive element 71 functions as part of the charge accumulation capacitance X that accumulates charge, and the capacitance value of the charge accumulation capacitance X increases. This slows down the change in the potential of the charge accumulation unit 55.

[0298] 28 shows the state at the end of exposure. In the second mode, the potential of the charge accumulation unit 55 changes more slowly as described above, and therefore the potential of the charge accumulation unit 55 at the end of exposure is lower than in the first mode. Therefore, the differential voltage ΔV is higher in the second mode than in the first mode.

[0299] In this embodiment, both the charge accumulation unit 55 and the charge accumulation unit 37 can be considered to be "a charge accumulation unit that accumulates charges generated by photoelectric conversion." Furthermore, both the charge accumulation unit 55 and the charge accumulation unit 37 can be considered to be "a charge accumulation unit" in the expression "the specific circuit changes the capacitance value of the charge accumulation capacitance in response to a change in the potential of the charge accumulation unit."

[0300] (Ninth embodiment) FIG. 29 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the ninth embodiment.

[0301] Unlike the pixel 11h according to the eighth embodiment, the pixel 11i according to the ninth embodiment includes a transfer transistor 39. One of the source and drain of the transfer transistor 39 is electrically connected to the gate electrode of the amplification transistor 34. The other of the source and drain of the transfer transistor 39 is electrically connected to one of the first source and first drain of the first transistor 81 and the photoelectric conversion unit 15, i.e., the charge accumulation unit 55.

[0302] In this embodiment, the node 44 is electrically connected to the other of the source and drain of the transfer transistor 39, one of the first source and first drain of the first transistor 81, and the photoelectric conversion unit 15, i.e., the charge accumulation unit 55. In this embodiment, the node electrically connected to one of the source and drain of the transfer transistor 39 and the gate electrode of the amplification transistor 34 is referred to as a node 49.

[0303] In this embodiment, one of the source and drain of the transfer transistor 39 constitutes the charge accumulation unit 37. More specifically, the charge accumulation unit 37 has the function of accumulating signal charges, the function as one of the source and drain of the first reset transistor 36, and the function as one of the source and drain of the transfer transistor 39.

[0304] FIG. 30 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the imaging device according to the ninth embodiment.

[0305] State (a) in FIG. 30 is the state at the start of exposure. In state (a), no signal charge is stored in the charge storage unit 55. The potential of the first terminal 71a of the first capacitance element 71 is the control potential VF. The potential of the first terminal 71a of the first capacitance element 71 is higher than the potential under the gate of the first transistor 81. The potential of the charge storage unit 55 is higher than the potential of the first terminal 71a of the first capacitance element 71.

[0306] 30 shows a state during exposure. Since the signal charge is electrons, the potential of the photoelectric conversion unit 15 decreases during exposure. That is, the potential of the charge accumulation unit 55 decreases.

[0307] As exposure progresses and the potential of the charge storage unit 55 decreases, the gate-source voltage of the first transistor 81 eventually exceeds the threshold voltage, turning on the first transistor 81. This electrically connects the charge storage unit 55 and the first terminal 71 a via the first transistor 81.

[0308] When exposure is performed and the first transistor 81 is in an on state, a situation may arise in which the potential under the gate of the first transistor 81 is lower than the potential of the first terminal 71a and the potential of the charge accumulation unit 55 is lower than the potential under the gate of the first transistor 81. In this situation, electrons are injected from the charge accumulation unit 55 to the first terminal 71a via the first transistor 81. The injection of electrons increases the potential of the charge accumulation unit 55. Accordingly, the potential under the gate of the first transistor 81 also increases. Meanwhile, the potential of the first terminal 71a decreases.

[0309] This electron injection balances the potential of the charge accumulation unit 55 and the potential of the first terminal 71a. During exposure, while this balance is maintained, the potential of the charge accumulation unit 55 and the potential of the first terminal 71a may decrease. In this situation, the voltage between the first terminal 71a and the second terminal 71b changes as signal charge is generated. In other words, the first capacitive element 71 functions as part of the charge accumulation capacitance X that accumulates charge, and the capacitance value of the charge accumulation capacitance X increases. This slows down the change in the potential of the charge accumulation unit 55.

[0310] State (c) in Figure 30 is the state at the end of exposure. When transfer transistor 39 is turned on in this state, charge is transferred from charge storage unit 55 to charge storage unit 37. In this way, a signal is read out. This leads to state (d) in Figure 30.

[0311] In this embodiment, the transfer transistor 39 transfers charges from the charge storage unit 55 to the charge storage unit 37. This transfer can be a so-called complete transfer. Therefore, ktc noise can be suitably reduced without a noise cancellation circuit such as the feedback circuit FC in FIGS. 15 and 18.

[0312] (Tenth embodiment) FIG. 31 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to the tenth embodiment.

[0313] The circuit configuration of the pixel 11j of the tenth embodiment shown in FIG. 31 differs from the circuit configuration of the pixel 11h of the eighth embodiment shown in FIG. 27 in the specific circuit GSC.

[0314] In the tenth embodiment, the first capacitance element 71 is a MOS capacitance.

[0315] A first terminal 71a of the first capacitance element 71 is electrically connected to the gate electrode of the amplification transistor 34, the charge accumulation unit 37, the node 44, and the photoelectric conversion unit 15. The photoelectric conversion unit 15 is a photodiode. The photoelectric conversion unit 15 also serves as the charge accumulation unit 55.

[0316] In this embodiment, the first capacitive element 71, which is a MOS capacitor, is configured using a first transistor 81. One of the first terminal 71a and the second terminal 71b is electrically connected to a first source and a first drain of the first transistor 81. The other of the first terminal 71a and the second terminal 71b is electrically connected to a first gate electrode of the first transistor 81. In the example of FIG. 31 , the first terminal 71a is electrically connected to the first source and the first drain of the first transistor 81. The second terminal 71b is electrically connected to the gate electrode of the first transistor 81.

[0317] The first source and the first drain of the first transistor 81 are electrically connected to each other. With this configuration, the first transistor 81 can be turned on when the difference between the potential of the first capacitive element 71 and the potential of the second terminal 71b reaches a certain value. The first source and the first drain of the first transistor 81 can be electrically connected by wiring or the like.

[0318] The operation of the imaging device according to this embodiment will be described below. A control potential VF is applied to the second terminal 71b of the first capacitive element 71. Meanwhile, the first terminal 71a is electrically connected to the charge accumulation unit 55. Therefore, when photoelectric conversion occurs in the photoelectric conversion unit 15, i.e., the charge accumulation unit 55, the potential of the first terminal 71a changes along with the potential of the charge accumulation unit 55, and the voltage between the terminals also changes. Specifically, since the signal charge is electrons, when photoelectric conversion occurs in the photoelectric conversion unit 15, i.e., the charge accumulation unit 55, the potential of the first terminal 71a decreases along with the potential of the charge accumulation unit 55. When the difference between the potential of the first terminal 71a and the second terminal 71b reaches a certain value, the first transistor 81 turns on. This causes the first capacitive element 71 to function as a capacitance that accumulates charge generated by photoelectric conversion. In this way, the capacitance value of the charge accumulation capacitance X increases.

[0319] As in the sixth embodiment described with reference to FIG. 24, the control potential VF applied to the second terminal 71b may be switched, and the imaging mode of the imaging device may have a first mode and a second mode.

[0320] (Linearity correction according to control potential VF) FIG. 32 is a diagram schematically showing an example of a change in the output of the horizontal signal readout circuit 21 in response to an increase in the amount of exposure.

[0321] In Figure 32, the solid line L1 is a linear graph showing the change in the output of the horizontal signal readout circuit 21 with respect to the increase in the exposure amount when the control potential VF is set so that auto gamma is OFF, extended to the region with a large amount of light. The dashed lines L2 and L3 are graphs showing the change in the output of the horizontal signal readout circuit 21 with respect to the increase in the exposure amount when the control potential VF is set so that auto gamma is ON. Specifically, the dashed line L2 is a graph showing the change in the output obtained when the control potential VF is set to the potential VFA in Figure 10. The dashed line L3 shows the change in the output obtained when the control potential VF is set to the potential VFB in Figure 10. Note that in this example, the increase in the exposure amount is achieved by extending the exposure period at a constant illuminance.

[0322] The solid line L1 is a straight line. The dashed lines L2 and L3 are polygonal lines. The deviation of the dashed lines L2 and L3 from the straight line of the solid line L1 increases as the exposure dose increases.

[0323] Therefore, for example, the deviation of the output from the horizontal signal readout circuit 21 from a straight line with an increase in the exposure period may be corrected by correcting the output from the horizontal signal readout circuit 21. Figure 33 shows a schematic overview of the linearity compensation process. For example, a table may be prepared for converting the output from the horizontal signal readout circuit 21 into an appropriate digital value for each control potential VF.

[0324] In this example, three correction tables AT1 to AT3 corresponding to each control potential VF are stored in a memory 162. For example, the control circuit 160 receives, for example, an output after analog-to-digital conversion from the horizontal signal readout circuit 21 and applies a correction table according to the specific value of the control potential VF. A selector 165 in FIG. 33 is a circuit that selects which of the correction tables AT1 to AT3 to apply, or whether to apply no correction table, according to the value of the control potential VF. The corrected output is passed to an image processing circuit 164, where it is subjected to predetermined processing.

[0325] Fig. 34 shows an example of the correction table. The correction table shown in Fig. 34 describes a digital value after linearity compensation for each digital value that is output from the horizontal signal readout circuit 21. For example, when N is input as the sensor output from the horizontal signal readout circuit 21, the control circuit 160 outputs X to the image processing circuit 164. Note that, as shown in graph L1 in Fig. 32, when a potential that does not require linearity compensation is selected as the control potential VF, the sensor output from the horizontal signal readout circuit 21 is passed directly to the image processing circuit 164.

[0326] By applying such linearity compensation processing, the characteristics indicated by the broken polygonal line L2 can be corrected to those indicated by the solid straight line L1 in Fig. 32, as shown in Fig. 32. Furthermore, the characteristics indicated by the broken polygonal line L3 can be corrected to those indicated by the solid straight line L1. The linearity compensation processing may be performed by the image processing circuit 164. Note that instead of converting digital values using a table, linearity may be compensated for by having the image processing circuit 164 multiply the sensor output by an appropriate coefficient.

[0327] The above-described linearity deviation may differ for each imaging device or camera system. FIG. 35 is a diagram illustrating the difference in linearity deviation for each imaging device or camera system. In FIG. 35, dashed line M1 indicates an exemplary change in the output of the horizontal signal readout circuit 21 with respect to an increase in exposure amount for a certain imaging device or camera system, and dashed line M2 indicates an exemplary change in the output of the horizontal signal readout circuit 21 with respect to an increase in exposure amount for another imaging device or camera system. It is beneficial if the output of the horizontal signal readout circuit 21 with respect to an increase in exposure amount is consistent between these imaging devices or camera systems, for example, as indicated by line M12 in FIG. 35.

[0328] FIG. 36 shows a schematic overview of linearity compensation processing for canceling differences between image pickup devices or camera systems. For example, if there are image pickup devices of sample S1 and sample S2, data relating to the light intensity-signal level characteristics shown in FIGS. 9A and 10 are acquired in advance for each of the samples S1 and S2. Furthermore, correction values for each sample are calculated based on the acquired data, and the correction values are stored in memory 162, for example, in the form of a table. FIG. 36 shows an overview of linearity compensation processing for sample S1, for example. Correction tables AT11 to AT13 for converting the output from the horizontal signal readout circuit 21 into appropriate digital values for each control potential VF are written into memory 162 for the image pickup device of sample S1. The memory 162 is typically a nonvolatile memory.

[0329] Fig. 37 shows an example of a correction table stored in memory 162 of the image pickup device of sample S1, and Fig. 38 shows an example of a correction table stored in memory 162 of the image pickup device of sample S2. When such a correction table is applied, for example, in response to a sensor output N from the horizontal signal readout circuit 21, the control circuit 160 of the image pickup device of sample S1 outputs a digital value X, whereas the control circuit 160 of the image pickup device of sample S2 outputs a digital value Y. By applying such linearity compensation processing adapted for each image pickup device or each camera system, it is possible to cancel the effects of differences in photoelectric conversion characteristics due to individual differences between image pickup devices or camera systems, as shown in the example of Fig. 35.

[0330] As described above, the correction value calculated based on the data relating to the light intensity-signal level characteristics can be prepared for each control potential VF. However, there may be cases where exposure is performed for a time longer than expected, or the control potential VF is set to a value that was not expected.

[0331] Fig. 39 shows another example of a correction table stored in memory 162, and Fig. 40 shows plots of output values described in the correction table of Fig. 39. In Fig. 40, white circles indicate plots relating to correction values applied when control potential VF is at potential Va, white triangles indicate plots relating to correction values applied when control potential VF is at potential Vb, and white rectangles indicate plots relating to correction values applied when control potential VF is at potential Vc.

[0332] For example, if the value of P13 in the correction table of Figure 39 has not been obtained in advance, the value of P13 can be calculated by linear interpolation from, for example, correction values P11 and P12. It is also possible to calculate a correction value for when the control potential VF is set to a value that was not anticipated in advance. For example, from P22, P23, P32, and P33, a correction value can be calculated ex post when the exposure amount is between t2 and t3 and the control potential VF is set to a value between Vb and Vc.

[0333] Fig. 41 shows a schematic overview of linearity compensation processing including interpolation processing. As shown in Fig. 41, the control circuit 160 may include an interpolation processing circuit 166 that performs such linear interpolation as part thereof.

[0334] (camera system) 42 is a schematic diagram showing an example of the configuration of a camera system 600. The camera system 600 includes a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing unit 604.

[0335] The lens optical system 601 includes, for example, an autofocus lens, a zoom lens, and an aperture. The lens optical system 601 focuses light onto the imaging surface of the imaging device 602. The imaging device according to any of the first to tenth embodiments described above can be used as the imaging device 602.

[0336] The system controller 603 controls the entire camera system 600. The system controller 603 can be realized by, for example, a microcomputer.

[0337] The camera signal processing unit 604 functions as a signal processing circuit that processes an output signal from the image capturing device 602. The camera signal processing unit 604 performs processes such as color interpolation, spatial interpolation, and auto white balance. The camera signal processing unit 604 can be realized by, for example, a DSP (Digital Signal Processor).

[0338] The camera system 600 may have a control circuit. For example, the system controller 603 may correspond to the control circuit. When the system controller 603 is used as the control circuit, the control circuit may operate in the same manner as when the vertical scanning circuit 16 is used as the control circuit. For example, the control circuit controls the first threshold potential by applying a control potential VF to the specific circuit GSC. Also, for example, the control circuit switches the first threshold potential depending on the shooting mode. Furthermore, the control circuit may be configured to perform the above-mentioned linearity control. However, the camera system 600 may include an element other than the system controller 603 as the control circuit. [Industrial Applicability]

[0339] The camera system according to the present invention can be used in a variety of camera systems and sensor systems, including digital still cameras, broadcast and commercial cameras, medical cameras, surveillance cameras, in-vehicle cameras, digital single-lens reflex cameras, and digital mirrorless single-lens cameras. [Explanation of symbols]

[0340] 11a~11j pixels 15 Photoelectric conversion unit 15a Counter electrode 15b Photoelectric conversion layer 15c Pixel electrode 16 Vertical scanning circuit 17 Storage control line 18 Vertical signal line 19 Load circuit 20 Column signal processing circuit 21 Horizontal signal readout circuit 22 Power wiring 23 Horizontal common signal line 24 Inverting amplifier 24a Gain adjustment terminal 25 Feedback Line 26 Reset signal line 27,27' Constant current source 28 Feedback control line 30 Address signal line 32 Control Line 34 Amplifying transistor 36 First reset transistor 37,55 Charge storage section 38 Second reset transistor 39 Transfer transistor 40 Address transistor 41,42 Capacitor element 44, 46, 47, 48, 48a, 48b, 48c, 49 nodes 45 Capacitive circuit 50 Switching circuit 51, 51', 52, 52' Switch elements 71 First capacitance element 71a,72a,73a 1st terminal 71b,72b,73b 2nd terminal 72 Second Capacitor 73 Third Capacitor 75 Specific reset signal line 76 Specific reset transistor 77 Reset voltage line 81 First transistor 82 Second transistor 83 Third Transistor 101,201 Imaging device 160 Control circuit 162 memory 164 Image processing circuit 165 Selector 166 Interpolation processing circuit 600 Camera System 601 Lens Optical System 602 Imaging device 603 System Controller 604 Camera signal processing unit FC feedback circuit GSC specific circuit SC signal detection circuit

Claims

1. a charge storage unit that stores charges generated by photoelectric conversion; a first transistor having a first source, a first drain, and a first gate electrode; a capacitance element that holds the charge and has a first terminal; Equipped with one of the first source and the first drain is electrically connected to the first gate electrode; a first potential is supplied to the other of the first source and the first drain; the other of the first source and the first drain is always electrically connected to the first terminal of the capacitive element from the start to the end of an exposure period; Imaging device.

2. a charge storage unit that stores charges generated by photoelectric conversion; a first transistor having a first source, a first drain, and a first gate electrode; a capacitance element that holds the charge and has a first terminal and a second terminal; Equipped with one of the first source and the first drain is electrically connected to the first gate electrode; a first potential is supplied to the other of the first source and the first drain; the other of the first source and the first drain is connected to the first terminal of the capacitive element without a switch; Imaging device.

3. a charge storage unit that stores charges generated by photoelectric conversion; a first transistor having a first source, a first drain, and a first gate electrode; a capacitance element that holds the charge and has a first terminal and a second terminal; Equipped with one of the first source and the first drain is connected to the first gate electrode via the first terminal and the second terminal of the capacitance element; a first potential is supplied to the other of the first source and the first drain; Imaging device.

4. further comprising an amplifying transistor that outputs an electrical signal according to the potential of the charge storage section. The imaging device according to claim 1 .

5. a second transistor having a second source, a second drain, and a second gate electrode; the first potential is supplied to the other of the first source and the first drain via the second transistor; The imaging device according to claim 1 .

6. a second transistor having a second source, a second drain, and a second gate electrode; one of the second source and the second drain is electrically connected to the other of the first source and the first drain; the first potential is supplied to the other of the second source and the second drain; The imaging device according to claim 1 .

7. a semiconductor substrate; a photoelectric conversion unit that generates the electric charges by photoelectric conversion; Furthermore, the photoelectric conversion unit is located within the semiconductor substrate; The imaging device according to claim 1 .

8. a semiconductor substrate; a photoelectric conversion unit that generates the electric charges by photoelectric conversion; Furthermore, the photoelectric conversion unit is located on the semiconductor substrate; The imaging device according to claim 1 .

9. The capacitive element includes a metal-insulator-metal (MIM) capacitor. The imaging device according to claim 1 .

10. a charge storage unit that stores charges generated by photoelectric conversion; a node electrically connected to the charge storage unit; The circuit and Equipped with The circuit comprises: a first transistor having a first source, a first drain, and a first gate electrode; a capacitance element that holds the charge and has a first terminal; and one of the first source and the first drain is electrically connected to the first gate electrode; a first potential is supplied to the other of the first source and the first drain; the other of the first source and the first drain is always electrically connected to the first terminal of the capacitive element; Imaging device.

11. a charge storage unit that stores charges generated by photoelectric conversion; a node electrically connected to the charge storage unit; The circuit and Equipped with The circuit comprises: a first transistor having a first source, a first drain, and a first gate electrode; a capacitance element that holds the charge and has a first terminal and a second terminal; and one of the first source and the first drain is connected to the first gate electrode via the first terminal and the second terminal of the capacitance element; a first potential is supplied to the other of the first source and the first drain; Imaging device.

12. When a capacitance electrically connected to the node is defined as a charge storage capacitance, the circuit changes a capacitance value of the charge storage capacitance in response to a change in potential of the charge storage unit. The imaging device according to claim 10 or 11.

13. the circuit changes the capacitance value of the charge storage capacitor in response to a change in the potential of the charge storage unit in accordance with the capacitance value of the capacitive element; The imaging device according to claim 12.

14. the circuit changes a capacitance value of the charge storage capacitor when the potential of the charge storage unit changes across a first threshold potential; The imaging device according to claim 12 or 13.

15. Further comprising a control circuit; the control circuit controls the first threshold potential by applying a control potential to the circuit; The imaging device according to claim 14.

16. The first threshold potential is switched depending on the imaging mode.

16. The imaging device according to claim 14 or 15.

17. the first potential is a DC potential; The imaging device according to claim 1 .

18. one of the first source and the first drain is always electrically connected to the first gate electrode from the start to the end of an exposure period; 11. The imaging device according to claim 1, 2 or 10.

19. An imaging device according to any one of claims 1 to 18; A lens optical system, Equipped with the lens optical system focuses light onto an imaging surface of the imaging device; Camera system.

Images