Semiconductor Devices

Abstract

A semiconductor device (1) comprises: a semiconductor layer (40) that has a semiconductor substrate (32) on the rear surface side and is divided into three regions of a first region (A1), a second region (A2), and a third region (A3) that do not overlap one another in plan view of the semiconductor device (1); a first vertical MOS transistor (10) that is formed in the first region (A1) of the semiconductor layer (40); a second vertical MOS transistor (20) that is formed in the second region (A2) of the semiconductor layer (40); and a drain pad (151) that is connected to the semiconductor substrate (32) at a position included in the third region (A3) in plan view of the semiconductor device (1). Moreover, in plan view of the semiconductor device (1), the third region (A3) is sandwiched between the first region (A1) and the second region (A2), and the surface area of the first region (A1) is greater than the surface area of the second region (A2) in plan view of the semiconductor device (1).

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a chip-size package type semiconductor device. [Background technology]

[0002] Vertical MOS transistors are sometimes used in electrical circuits that combine two systems with different current specifications into one system. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7475569 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a demand for miniaturization of circuits using vertical MOS transistors. [Means for solving the problem]

[0005] In order to solve the above-described problems, a semiconductor device according to one aspect of the present disclosure is a chip-size package type semiconductor device that can be mounted face-down, and includes a semiconductor substrate on a back surface side, a semiconductor layer divided into three regions, a first region, a second region, and a third region, which do not overlap each other in a plan view of the semiconductor device and are not disposed in a dispersed manner, a first vertical MOS transistor entirely formed in the first region of the semiconductor layer, a second vertical MOS transistor entirely formed in the second region of the semiconductor layer, and a metal layer formed in contact with the back surface of the semiconductor layer, wherein the semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, and in the plan view, The semiconductor device is characterized in that a first source pad and a first gate pad of the first vertical MOS transistor are formed at a position included in a first region, a second source pad and a second gate pad of the second vertical MOS transistor are formed at a position included in the second region in the planar view, a drain pad connected to the common drain region is formed at a position included in the third region in the planar view, the first region and the second region are arranged on either side of the third region in the planar view of the semiconductor layer, the third region is adjacent to the first region and the second region in the planar view, and the area of the first region is larger than the area of the second region in the planar view. [Effects of the Invention]

[0006] By using the dual-configuration vertical MOS transistor described above in a circuit that merges two conduction paths with different current specifications into one, the area required by the circuit can be reduced compared to conventional circuits.

[0007] Therefore, according to the semiconductor device having the above configuration, it is possible to realize miniaturization of circuits using vertical MOS transistors. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment. [Figure 2A] FIG. 2A is a schematic plan view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 2B] FIG. 2B is a schematic plan view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to a modified example of the embodiment. [Figure 4A] FIG. 4A is a schematic plan view of a general unit configuration of a first transistor according to an embodiment. [Figure 4B] FIG. 4B is a perspective schematic view of a general unit configuration of a first transistor according to the embodiment. [Figure 5A] FIG. 5A is a schematic cross-sectional view showing a first conduction path of the semiconductor device according to the embodiment. [Figure 5B] FIG. 5B is a schematic cross-sectional view showing a second conduction path of the semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a circuit diagram showing an example of use of the semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a circuit diagram showing an example of use of a semiconductor device according to a comparative example. [Figure 8A] FIG. 8A is a schematic plan view showing an example of the structure of a transistor according to a comparative example. [Figure 8B] FIG. 8B is a schematic plan view showing an example of the structure of a transistor according to a comparative example. [Figure 9A] FIG. 9A is a schematic plan view showing an example of the structure of a transistor according to a comparative example. [Figure 9B] FIG. 9B is a schematic plan view showing an example of the structure of a transistor according to a comparative example. [Figure 10] FIG. 10 is a schematic plan view showing an example of the structure of a transistor according to a modified example of the embodiment. [Figure 11] FIG. 11 is a plan view schematically illustrating an example of the structure of a transistor according to a modified example of the embodiment. [Figure 12A] FIG. 12A is a schematic plan view showing an example of the structure of a transistor according to a modified example of the embodiment. [Figure 12B] FIG. 12B is a schematic plan view showing an example of the structure of a transistor according to a modification of the embodiment. [Figure 13] FIG. 13 is a schematic plan view showing a drain contact region of the semiconductor device according to the embodiment. [Figure 14] FIG. 14 is a graph showing the relationship between the arrangement of the drain contact region of the semiconductor device according to the embodiment and the conduction resistance of each of the first conduction path and the second conduction path. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments described below each illustrate a specific example of the present disclosure. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0010] In this disclosure, "A and B are electrically connected" includes a case where A and B are directly connected via wiring, a case where A and B are directly connected without wiring, and a case where A and B are indirectly connected via a resistance component (resistance element, resistance wiring).

[0011] (Embodiment) [1. Structure of semiconductor device] The structure of a semiconductor device according to an embodiment will be described below. The semiconductor device according to the embodiment is a chip size package (CSP) type semiconductor device that has a dual configuration in which two vertical MOS (Metal Oxide Semiconductor) transistors are formed on a semiconductor substrate and that can be mounted face down. The two vertical MOS transistors are power transistors, or so-called trench MOS field effect transistors (FETs).

[0012] Fig. 1 is a cross-sectional view showing an example of the structure of a semiconductor device 1 according to an embodiment. Figs. 2A and 2B are plan views showing an example of the structure of a semiconductor device 1 according to an embodiment. The size and shape of the semiconductor device 1 in Figs. 2A and 2B are examples. The size, shape, and arrangement of the pads and electrodes are also examples.

[0013] FIG. 1 is a cross section of the semiconductor device 1 taken along line II in FIG. 2A.

[0014] 1, the semiconductor device 1 includes a semiconductor substrate 32, a metal layer 41, and a low-concentration impurity layer 33 formed on the semiconductor substrate 32. In the present disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as a semiconductor layer 40.

[0015] The semiconductor substrate 32 is disposed on the back surface side of the semiconductor layer 40 and is made of silicon of a first conductivity type containing impurities at a first concentration. The semiconductor layer 40 has a low-concentration impurity layer 33 of the first conductivity type formed in contact with the semiconductor substrate 32 and containing impurities at a second concentration lower than the first concentration. The low-concentration impurity layer 33 is formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0016] As shown in Figures 1 and 2A, the semiconductor device 1 has a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") formed entirely within a first region A1 of the semiconductor layer 40, and a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") formed entirely within a second region A2 of the semiconductor layer 40.

[0017] A transistor 10 formed entirely within the first region A1 means that, in a planar view, all of the elements constituting the transistor 10 are contained within the first region A1 and are not contained in any region other than the first region A1. Similarly, a transistor 20 formed entirely within the second region A2 means that, in a planar view, all of the elements constituting the transistor 20 are contained within the second region A2 and are not contained in any region other than the second region A2.

[0018] As shown in FIG. 2A , the surface side of the semiconductor layer 40 is divided into a first region A1, a second region A2, and a third region A3 in a plan view. These regions do not overlap with each other and are not disposed separately. Here, the fact that the first region A1, the second region A2, and the third region A3 are not disposed separately means that the first region A1, the second region A2, and the third region A3 do not include any isolated areas. In FIG. 2A , a virtual boundary line 90 is shown as a dotted line separating the first region A1, the second region A2, and the third region A3. For ease of understanding, the dotted line indicating the boundary line 90 is shown extending to the outside of the semiconductor layer 40, but the actual boundary line 90 terminates at the outer periphery of the semiconductor layer 40 in a plan view (for convenience, the ends of the boundary line 90 are shown as P1, P2, and P3, respectively, in FIGS. 2A and 2B ). The boundary line 90 will be described later.

[0019] In FIG. 2A, the dashed lines indicating the first region A1, the second region A2, and the third region A3 do not exactly coincide with the outer periphery of the semiconductor layer 40 and the boundary line 90 for ease of understanding, but are shown with some space between them. However, the outer periphery of the first region A1, the outer periphery of the second region A2, and the outer periphery of the third region A3 essentially coincide with the outer periphery of the semiconductor layer 40 and the boundary line 90.

[0020] The metal layer 41 is formed in contact with the back surface side of the semiconductor layer 40, and may be made of, for example and not limited to, silver (Ag) or copper (Cu). Note that the metal layer 41 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material.

[0021] 1 and 2A, a first body region 18 of a second conductivity type different from the first conductivity type is formed in a first region A1 of the low-concentration impurity layer 33. A first source region 14 of the first conductivity type is formed in the first body region 18.

[0022] Also, in the first region A1, a plurality of first gate trenches 17 are formed, each extending from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a depth reaching a part of the low-concentration impurity layer 33. Furthermore, a first gate conductor 15 is formed on the first gate insulating film 16 inside the first gate trench 17. The first gate conductor 15 is a buried gate electrode buried inside the semiconductor layer 40. The first gate conductor 15 is electrically connected to a first gate electrode 19 via a first gate wiring (see FIG. 2B).

[0023] The first source electrode 11 is composed of a portion 12 and a portion 13 , and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13 .

[0024] Portion 12 of first source electrode 11 is a layer that is joined with solder during reflow soldering in face-down mounting, and may be made of a metal material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of portion 12 may be plated with gold or the like.

[0025] Portion 13 of first source electrode 11 is a layer that connects portion 12 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0026] Similarly, a second body region 28 of a second conductivity type different from the first conductivity type is formed in the second region A2 of the low-concentration impurity layer 33. A second source region 24 of the first conductivity type is formed in the second body region 28.

[0027] Also, in the second region A2, a plurality of second gate trenches 27 are formed, each extending from the upper surface of the semiconductor layer 40 through the second source region 24 and the second body region 28 to a depth reaching a part of the low-concentration impurity layer 33, and a second gate conductor 25 is formed on the second gate insulating film 26 inside the second gate trench 27. The second gate conductor 25 is a buried gate electrode buried inside the semiconductor layer 40. The second gate conductor 25 is electrically connected to a second gate electrode 29 via a second gate wiring (see FIG. 2B).

[0028] The second source electrode 21 is composed of a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23.

[0029] Portion 22 of second source electrode 21 is a layer that is joined with solder during reflow soldering in face-down mounting, and may be made of a metal material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of portion 22 may be plated with gold or the like.

[0030] Portion 23 of second source electrode 21 is a layer that connects portion 22 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0031] 2B shows the state of the semiconductor device 1 according to this embodiment immediately after forming a portion 13 of the first source electrode 11, the first gate electrode 19, the first gate wiring, a portion 23 of the second source electrode 21, the second gate electrode 29, the second gate wiring, and a portion 83 of the surface drain electrode 81 (described later) on the surface side of the semiconductor layer 40. For ease of understanding, pads that would not be visible at this point are shown by dotted lines in FIG.

[0032] 1 , the first body region 18 is covered with an interlayer insulating layer 34 having an opening, and a portion 13 of the first source electrode 11 is provided, which is connected to the first source region 14 through the opening in the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 13 of the first source electrode 11 are covered with a passivation layer 35 having an opening, and a portion 12 is provided, which is connected to the portion 13 of the first source electrode 11 through the opening in the passivation layer 35.

[0033] Similarly, the second body region 28 is covered with an interlayer insulating layer 34 having an opening, and a portion 23 of the second source electrode 21 is provided, which is connected to the second source region 24 through the opening in the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 23 of the second source electrode 21 are covered with a passivation layer 35 having an opening, and a portion 22 of the passivation layer 35 is provided, which is connected to the portion 23 of the second source electrode 21 through the opening in the passivation layer 35.

[0034] 2B, the first source pad 111 and the second source pad 121 respectively refer to regions where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, i.e., terminal portions. Similarly, the first gate pad 119 and the second gate pad 129 respectively refer to regions where the first gate electrode 19 and the second gate electrode 29 are partially exposed on the surface of the semiconductor device 1, i.e., terminal portions.

[0035] The number of first source pads 111 and second source pads 121 is not necessarily limited to the number illustrated in Fig. 2A. The shapes of the first source pads 111 and second source pads 121 are not necessarily limited to the circular shapes illustrated in Fig. 2A, and may be, for example, rectangular or elliptical. The arrangement of the first source pads 111 and second source pads 121 is not limited to the arrangement illustrated in Fig. 2A.

[0036] The number of first gate pads 119 and second gate pads 129 is not necessarily limited to the number illustrated in Fig. 2A, and may be a plurality of numbers equal to or greater than 2. Furthermore, the shapes of first gate pads 119 and second gate pads 129 are not necessarily limited to the circular shapes illustrated in Fig. 2A, and may be, for example, rectangular or elliptical.

[0037] With the above-described configuration of transistor 10 and transistor 20, the semiconductor substrate 32 and the area of the low-concentration impurity layer 33 immediately above the semiconductor substrate 32 are a common drain region that is shared by the first drain region of transistor 10 and the second drain region of transistor 20.

[0038] The metal layer 41 is a common drain electrode (hereinafter referred to as back surface drain electrode 41) in which the first drain electrode of the transistor 10 and the second drain electrode of the transistor 20 are commonized.

[0039] 1, a drain pull-up region 38 is formed in the third region A3 of the semiconductor layer 40, which pulls up current from the common drain region (semiconductor substrate 32) and the back surface drain electrode 41 to the front surface side of the semiconductor layer 40. The drain pull-up region 38 contains impurities at a concentration higher than the first concentration of the semiconductor substrate 32 and is of the first conductivity type. The drain pull-up region 38 is formed to a depth from the upper surface of the semiconductor layer 40 to a part of the semiconductor substrate 32.

[0040] On the front surface side of the semiconductor layer 40, a front surface drain electrode 81 connected to the drain pull-up region 38 is formed at a position included in the third region A3 in plan view. The modification "front surface" is intended to distinguish it from the back surface drain electrode 41, which is also a drain electrode.

[0041] The surface drain electrode 81 is composed of a portion 82 and a portion 83, and the portion 82 is connected to the low concentration impurity layer 33 and / or the drain pull-up region 38 via the portion 83.

[0042] Portion 82 of surface drain electrode 81 is a layer that is joined with solder during reflow soldering in face-down mounting, and may be made of a metal material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of portion 82 may be plated with gold or the like.

[0043] Portion 83 of surface drain electrode 81 is a layer that connects portion 82 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0044] The drain pull-up region 38 is covered with an interlayer insulating layer 34 having an opening, and a portion 83 of a surface drain electrode 81 is provided which connects to the drain pull-up region 38 through the opening in the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 83 of the surface drain electrode 81 are covered with a passivation layer 35 having an opening, and a portion 82 is provided which connects to the portion 83 of the surface drain electrode 81 through the opening in the passivation layer 35.

[0045] Therefore, as shown in FIG. 2B, the drain pad 151 refers to the region where the surface drain electrode 81 is partially exposed on the surface of the semiconductor device 1, that is, the terminal portion.

[0046] The number of drain pads 151 is not necessarily limited to the number illustrated in Fig. 2A. The shape of the drain pad 151 is not necessarily limited to the elliptical shape illustrated in Fig. 2A, and may be, for example, rectangular or circular.

[0047] In the example shown in FIG. 2A, the drain pad 151 is positioned so that its center coincides with the center of the third region A3, but even if the center of the drain pad 151 does not coincide with the center of the third region A3, there is no problem in obtaining the effects of the present disclosure.

[0048] In this disclosure, the center of a shape in a plan view is defined as follows: For circular shapes such as the first source pad 111 and the first gate pad 119 in FIG. 2A, it refers to the center. For rectangular shapes such as the third region A3, it refers to the intersection of the diagonals. For oval shapes such as the drain pad 151, it refers to the intersection of the axis of line symmetry extending in the longitudinal direction and the axis of line symmetry extending in the width direction.

[0049] The portion where the drain pull-up region 38 and the portion 83 of the surface drain electrode 81 contact each other is called the drain contact region 39. In a plan view, the drain contact region 39 is an overlapping portion between the region of the drain pull-up region 38 exposed on the surface side of the semiconductor layer 40 and the opening region of the interlayer insulating layer 34. In the example shown in FIG. 1 , the width of the drain pull-up region 38 is larger than the width of the opening of the interlayer insulating layer 34 (the area of the drain pull-up region 38 exposed on the surface side of the semiconductor layer 40 in a plan view is larger than the opening area of the interlayer insulating layer 34), so the drain contact region 39 coincides with the opening region of the interlayer insulating layer 34 in a plan view.

[0050] 3 is a schematic cross-sectional view showing a cutaway portion of a semiconductor device 1A according to Modification 1, in which only the shape of the drain pull-up region 38 is modified from that of the semiconductor device 1 according to the embodiment. As shown in Fig. 3, the width of the drain pull-up region 38 may be smaller than the opening width of the interlayer insulating layer 34. In such a case, the drain contact region 39 coincides with the region of the drain pull-up region 38 exposed on the surface side of the semiconductor layer 40 in plan view.

[0051] In either case, the drain contact region 39 may have a large area in plan view to reduce the conduction resistance. Typically, in plan view, the area where the portion 83 of the surface drain electrode 81 contacts the semiconductor layer 40 in the third region A3 (the area of the opening region of the interlayer insulating layer 34) and the area where the drain pull-up region 38 is exposed on the surface side of the semiconductor layer 40 may be approximately the same size, although there may be a difference in size.

[0052] 2A, the first region A1 and the second region A2 are disposed with the third region A3 sandwiched therebetween. In the embodiment, "the first region A1 and the second region A2 sandwich the third region A3" means that the first region A1 and the third region A3 are adjacent to each other without any other region therebetween, and the second region A2 and the third region A3 are adjacent to each other without any other region therebetween. Therefore, in a plan view of the semiconductor layer 40, the third region A3 is adjacent to both the first region A1 and the second region A2.

[0053] When viewed from above, a region is adjacent to another region, which means that the two regions face each other, and that their outer circumferences coincide with each other at the boundary line 90 between them. Hereinafter, the length of the boundary line 90 may be referred to as the facing length.

[0054] As shown in FIG. 2B, the boundary line 90 between the first region A1 and the third region A3 may be considered as a virtual line tracing the center of the gap between the portion 13 of the first source electrode 11 and the portion 83 of the surface drain electrode 81. It may also be considered as the gap itself, although it has a finite width. Even in the case of the gap, it can be recognized as a line with the naked eye or at low magnification. In the example shown in FIGS. 2A and 2B, the boundary line 90 between the first region A1 and the third region A3 is a dotted line from P1 to P4.

[0055] Similarly, the boundary line 90 between the second region A2 and the third region A3 may be considered as an imaginary line tracing the center position of the gap between the portion 23 of the second source electrode 21 and the portion 83 of the surface drain electrode 81. Alternatively, although it has a finite width, it may be considered as the gap itself. In the example shown in Figures 2A and 2B, the boundary line 90 between the second region A2 and the third region A3 is the dotted line from P2 to P4.

[0056] 2B, when the first region A1 and the second region A2 are adjacent to each other, the boundary line 90 between them may be regarded as an imaginary line tracing the center position of the gap between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Alternatively, although the width of the line is finite, it may be regarded as the gap itself. In the example shown in FIGS. 2A and 2B, the boundary line 90 between the first region A1 and the second region A2 is the dotted line from P4 to P3.

[0057] 2A and 2B, the area a1 of the first region A1 in a plan view is larger than the area a2 of the second region A2 in a plan view (a1 > a2). Similarly, the first region A1 and the second region A2 do not halve the area of the semiconductor layer 40 excluding the third region A3 in a plan view (a1 ≠ a2). Therefore, the length of the boundary line 90 between the first region A1 and the third region A3 (the facing length, the length from P1 to P4) is longer than the length of the boundary line 90 between the second region A2 and the third region A3 (the facing length, the length from P2 to P4).

[0058] 2A and 2B, in a plan view, the first region A1 is arranged so that its periphery at least partially coincides with each of the four sides of the semiconductor layer 40. In contrast, the second region A2 is arranged so that its periphery partially coincides with only two of the four sides of the rectangular periphery of the semiconductor layer 40.

[0059] 2A and 2B, in plan view, the second gate pad 129 is located closest to a corner formed by two sides of the periphery of the second region A2 that are not adjacent to the first region A1. The second gate pad 129 is located in the second region A2 farthest from the boundary line 90 with the first region A1. In the embodiment, the phrase "the pad and the corner are closest to each other" means that no other pad is located between the pad and the corner.

[0060] In addition, the first gate pad 119 is disposed at a position opposite to the second gate pad 129 with the drain pad 151 interposed therebetween in a plan view.

[0061] 4A and 4B are a plan view and a perspective view, respectively, of a general unit configuration of transistor 10 or transistor 20 repeatedly formed in the X direction and the Y direction of semiconductor device 1 according to the embodiment. For ease of understanding, semiconductor substrate 32, metal layer 41, passivation layer 35, first source electrode 11 or second source electrode 21, and interlayer insulating layer 34 are not shown in FIGS. 4A and 4B.

[0062] The Y direction is parallel to the surface of the semiconductor layer 40 and is the direction in which the first gate trench 17 extends. The X direction is parallel to the surface of the semiconductor layer 40 and is perpendicular to the Y direction. The Z direction is perpendicular to both the X direction and the Y direction and is the height direction of the semiconductor device.

[0063] 4A and 4B, the transistor 10 includes a first connection portion 18a that electrically connects the first body region 18 and the first source electrode 11. The first connection portion 18a is a region of the first body region 18 in which the first source region 14 is not formed, and has the same second conductivity type as the first body region 18. The first source regions 14 and the first connection portion 18a are alternately and periodically arranged in the Y direction. The same applies to the transistor 20.

[0064] In the semiconductor device 1 according to the present disclosure, the first conductivity type is defined as N-type and the second conductivity type is defined as P-type, with the first source region 14, the second source region 24, the drain pull-up region 38, the semiconductor substrate 32, and the low-concentration impurity layer 33 being N-type semiconductors, and the first body region 18, the first connection portion 18a, the second body region 28, and the second connection portion 28a being P-type semiconductors.

[0065] [2. Operation of the semiconductor device] 5A and 5B, the first and second conduction paths of the semiconductor device 1 and a method of driving the semiconductor device 1 will be described. 5A and 5B are cross-sectional schematic diagrams showing the conduction paths of the semiconductor device 1 according to the embodiment.

[0066] In the semiconductor device 1 according to the embodiment, it is assumed that a current flows from either the first source pad 111 in the first region A1 or the second source pad 121 in the second region A2 as an inlet, passes through the common drain region and the back surface drain electrode 41, and flows from the drain pad 151 in the third region A3 as an outlet. That is, the embodiment does not assume driving that conducts current along a path from the first source pad 111 to the second source pad 121 and / or the reverse path.

[0067] In the semiconductor device 1, a conduction path through which a current flows from the first source pad 111 in the first region A1 as an inlet to the drain pad 151 in the third region A3 as an outlet is called a first conduction path. A conduction path through which a current flows from the second source pad 121 in the second region A2 as an inlet to the drain pad 151 in the third region A3 as an outlet is called a second conduction path.

[0068] 5A, a current flows as follows: In the semiconductor device 1, a high voltage is applied to the first source electrode 11 and a low voltage is applied to the surface drain electrode 81, and a voltage equal to or greater than a threshold value is applied (ON control) to the first gate electrode 19 (first gate conductor 15) with the first source electrode 11 as a reference, thereby forming a conduction channel near the first gate insulating film 16 in the first body region 18. When the conduction channel is formed, a current flows through the path of the first source electrode 11, the first source region 14, the conduction channel formed in the first body region 18, the low-concentration impurity layer 33, the semiconductor substrate 32, the metal layer 41, the semiconductor substrate 32, the drain pull-up region 38, and the surface drain electrode 81, bringing the semiconductor device 1 into a conductive state.

[0069] When the potential of the first source electrode 11 is sufficiently high with respect to the potential of the surface drain electrode 81, it is not necessary to apply (ON control) a voltage equal to or higher than the threshold voltage to the first gate electrode 19 (first gate conductor 15). In this case, no conductive channel is formed near the first gate insulating film 16 in the first body region 18, but a current flows through the path of the first source electrode 11-first connection portion 18a-first body region 18-low-concentration impurity layer 33-semiconductor substrate 32-metal layer 41-semiconductor substrate 32-drain pull-up region 38-surface drain electrode 81, and the semiconductor device 1 becomes conductive.

[0070] Both of the above are first conduction paths. In the latter case, the conduction resistance is relatively high because a PN junction is present at the contact surface between the first body region 18 and the low-concentration impurity layer 33. In the former case, the conduction resistance is relatively low because the conduction goes through a conduction channel.

[0071] In any case, it should be noted that when the first conduction path is made conductive, the PN junction at the contact surface between the second body region 28 and the low-concentration impurity layer 33 in the transistor 20 functions as a body diode. This prevents conduction from the first source pad 111 to the second source pad 121. When only the first conduction path is used in the semiconductor device 1, it is desirable not to apply a voltage equal to or higher than the threshold voltage to the second gate electrode 29 (second gate conductor 25) of the transistor 20 (OFF control).

[0072] 5B , a current flows as follows: In the semiconductor device 1, a high voltage is applied to the second source electrode 21 and a low voltage is applied to the surface drain electrode 81, and a voltage equal to or greater than the threshold is applied (ON control) to the second gate electrode 29 (second gate conductor 25) with the second source electrode 21 as a reference, thereby forming a conduction channel near the second gate insulating film 26 in the second body region 28. When the conduction channel is formed, a current flows through the second source electrode 21, the second source region 24, the conduction channel formed in the second body region 28, the low-concentration impurity layer 33, the semiconductor substrate 32, the metal layer 41, the semiconductor substrate 32, the drain pull-up region 38, and the surface drain electrode 81, bringing the semiconductor device 1 into a conductive state.

[0073] When the potential of the second source electrode 21 is sufficiently high with respect to the potential of the surface drain electrode 81, it is not necessary to apply (ON control) a voltage equal to or higher than the threshold voltage to the second gate electrode 29 (second gate conductor 25). In this case, no conductive channel is formed near the second gate insulating film 26 in the second body region 28, but a current flows through the path of the second source electrode 21-second connection portion 28a-second body region 28-low-concentration impurity layer 33-semiconductor substrate 32-metal layer 41-semiconductor substrate 32-drain pull-up region 38-surface drain electrode 81, and the semiconductor device 1 becomes conductive.

[0074] Both of the above are second conduction paths. In the latter case, the conduction resistance is relatively high because a PN junction is present at the contact surface between the second body region 28 and the low-concentration impurity layer 33. In the former case, the conduction resistance is relatively low because the conduction goes through a conduction channel.

[0075] In any case, it should be noted that when the second conduction path is made conductive, the PN junction at the contact surface between the first body region 18 and the low-concentration impurity layer 33 in the transistor 10 functions as a body diode. This prevents conduction from the second source pad 121 to the first source pad 111. When only the second conduction path is used in the semiconductor device 1, it is desirable not to apply a voltage equal to or higher than the threshold voltage to the first gate electrode 19 (first gate conductor 15) of the transistor 10 (OFF control).

[0076] As shown in Figures 5A and 5B, in both the first conduction path and the second conduction path, most of the current flowing horizontally inside the semiconductor device 1 passes through the metal layer 41, which has low resistivity, but some of it may flow through the semiconductor substrate 32.

[0077] [3. Examples of semiconductor device usage] 6 is a circuit diagram showing a part of a power supply circuit that supplies current from a first power supply 51 and a second power supply 52, each of which is detachable, to a load 6 via a semiconductor device 1 according to an embodiment. Here, the potential of the load 6 is taken as a reference, and the potential of the first power supply 51 is assumed to be higher than the potential of the second power supply 52.

[0078] The semiconductor device 1 according to the embodiment is installed to combine two power systems, one from a first power source 51 at a high potential and the other from a second power source 52 at a lower potential, and combine them into one system toward a downstream load 6 at a low potential.

[0079] The maximum value of the current flowing due to the power supply from the first power supply 51, which has a high potential, is I1 [A], and the maximum value of the current flowing due to the power supply from the second power supply 52, which has a lower potential than the first power supply 51, is I2 [A]. I1 and I2 may be considered to be the specified maximum current values in the first conduction path and the second conduction path, respectively, which are described in the product data sheet of the semiconductor device 1 according to the embodiment.

[0080] The relationship I1>I2 exists due to the relationship between the potentials of the first power supply 51 and the second power supply 52. The first power supply 51 side, through which a relatively large current I1 flows, is connected to the first source pad 111 of the transistor 10, which has a large area in a planar view in the semiconductor device 1, and the second power supply 52 side, through which a relatively small current I2 flows, is connected to the second source pad 121 of the transistor 20, which has a small area in a planar view in the semiconductor device 1.

[0081] A switching element 7 (for example, a single-type vertical MOS transistor) is connected between the semiconductor device 1 and the load 6. A switching element 8 (for example, a single-type vertical MOS transistor) is connected between the semiconductor device 1 and the second power supply 52. A control IC 4 is connected to the switching elements 7, 8, and semiconductor device 1, and the control IC 4 individually controls the ON / OFF of the switching elements 7, 8, transistor 10, and transistor 20.

[0082] First, a state in which only the first power supply 51 is connected and the second power supply 52 is not connected (a state in FIG. 6 in which the second power supply 52 is not present) will be described. At this time, the control IC 4 controls the switching element 7 to be ON and the transistor 20 to be OFF, and power is supplied from the first power supply 51 to the load 6 via the first conduction path in the semiconductor device 1. Furthermore, if the control IC 4 controls the transistor 10 to be ON, the conduction resistance in the first conduction path can be reduced.

[0083] The first conduction path is a conduction path inside the semiconductor device 1, and as described above, is a conduction path through which current flows with the first source pad 111 of the transistor 10 as an inlet and the drain pad 151 as an outlet. When only the first conduction path is conductive, the transistor 20 is controlled to be OFF. Because the transistor 20 is controlled to be OFF, the current flowing due to power supply from the first power supply 51 can be prevented from flowing toward the second power supply 52.

[0084] Next, a state in which only the second power supply 52 is connected and the first power supply 51 is not connected (a state in FIG. 6 in which the first power supply 51 is not present) will be described. At this time, the control IC 4 controls the switching element 7 to be ON and the transistor 10 to be OFF, and power is supplied from the second power supply 52 to the load 6 via the second conduction path within the semiconductor device 1. If the control IC 4 further controls the transistor 20 to be ON, the conduction resistance in the second conduction path can be reduced.

[0085] The second conduction path is a conduction path inside the semiconductor device 1, and as described above, is a conduction path through which current flows with the second source pad 121 of the transistor 20 as an inlet and the drain pad 151 as an outlet. When only the second conduction path is conductive, the transistor 10 is controlled to be OFF. Because the transistor 10 is controlled to be OFF, the current flowing due to power supply from the second power supply 52 can be prevented from flowing toward the first power supply 51.

[0086] When both the first power supply 51 and the second power supply 52 are connected (the state shown in FIG. 6), the control IC 4 first turns off the switching element 8, creating a state in which power is supplied only from the first power supply 51. This is because the first power supply 51 has a higher potential and is therefore more advantageous in terms of power supply. Furthermore, the switching element 7 is turned on and the transistor 20 is turned off, thereby supplying power from the first power supply 51 to the load 6 via the first conduction path. If the control IC 4 turns on the transistor 10, the conduction resistance in the first conduction path can be reduced.

[0087] [4. Effects of semiconductor devices] Fig. 7 shows a comparative example in which the semiconductor device 1 according to the embodiment is not used in the power supply circuit shown in Fig. 6. In the comparative example, instead of the semiconductor device 1 according to the embodiment, for example, a single-configuration vertical MOS transistor 10B (hereinafter referred to as transistor 10B) whose example structure is shown in the schematic plan views of Figs. 8A and 8B, and a single-configuration vertical MOS transistor 20B (hereinafter referred to as transistor 20B) whose example structure is shown in the schematic plan views of Figs. 9A and 9B are used, respectively.

[0088] In the transistors 10B and 20B, components that are the same as those in the semiconductor device 1 according to the embodiment are indicated by adding the letter B to the reference numerals of the corresponding components. However, for the purpose of distinction, different reference numerals are used for the drain pads of the transistor 10B (drain pad 151B) and the transistor 20B (drain pad 152B).

[0089] 8B and 9B, similar to the plan view (FIG. 2B) of the semiconductor device 1 according to the present embodiment, show the state immediately after the source electrode portion 13B (23B), the gate electrode 19B (29B), the gate wiring, and the surface drain electrode portion 83B are formed on the surface side of the semiconductor layer 40. For ease of understanding, pads that would not be visible at this point are shown by dotted lines in FIGS.

[0090] The area in a plan view of portion 13B of the source electrode of transistor 10B is the same as the area in a plan view of portion 13 of first source electrode 11 of transistor 10 included in semiconductor device 1 according to the embodiment. Therefore, the conduction resistance of the path from first power supply 51 via transistor 10B to load 6 in Fig. 7 can be considered to be equivalent to the conduction resistance of the first conduction path of semiconductor device 1 according to the embodiment in Fig. 6.

[0091] Furthermore, the area of portion 23B of the source electrode of transistor 20B in a plan view is the same as the area of portion 23 of second source electrode 21 of transistor 20 included in semiconductor device 1 according to the embodiment in a plan view. Therefore, it is acceptable to consider that the conduction resistance of the path from second power supply 52 via transistor 20B to load 6 in Fig. 7 is equivalent to the conduction resistance of the second conduction path of semiconductor device 1 according to the embodiment in Fig. 6.

[0092] 7, when only the first power supply 51 is connected (the second power supply 52 is not present in FIG. 7), the transistor 20B is controlled to be OFF, preventing the current flowing due to the power supply from the first power supply 51 from flowing toward the second power supply 52. The transistor 10B is controlled to be ON when a voltage equal to or higher than the threshold value is applied to the gate pad 119B, and the current flowing due to the power supply from the first power supply 51 flows in from the source pad 111B of the transistor 10B and flows out from the drain pad 151B. As shown in FIGS. 8A and 8B, the area of the transistor 10B in a plan view (the area of the source electrode portion 13B) is relatively large because the current flowing due to the power supply from the first power supply 51 is relatively large.

[0093] 7, when only the second power supply 52 is connected (the first power supply 51 is not present in FIG. 7), the transistor 10B is controlled to be OFF, preventing the current flowing due to the power supply from the second power supply 52 from flowing toward the first power supply 51. The transistor 20B is controlled to be ON when a voltage equal to or higher than the threshold value is applied to the gate pad 129B, and the current flowing due to the power supply from the second power supply 52 flows in from the source pad 121B of the transistor 20B and flows out from the drain pad 152B. As shown in FIGS. 9A and 9B, the area of the transistor 20B in a plan view (the area of the source electrode portion 23B) is relatively small because the current flowing due to the power supply from the second power supply 52 is relatively small.

[0094] As described above, in the power supply circuit according to the comparative example shown in Fig. 7, the transistor 10B performs the same function as the transistor 10 provided in the semiconductor device 1 according to the embodiment in the power supply circuit of Fig. 6. Similarly, in the power supply circuit according to the comparative example shown in Fig. 7, the transistor 20B performs the same function as the transistor 20 provided in the semiconductor device 1 according to the embodiment in the power supply circuit of Fig. 6.

[0095] 7, the circuit board on which the power supply circuit according to the comparative example is mounted must ensure the areas of transistors 10B and 20B, as well as a certain installation margin between them. Furthermore, transistors 10B and 20B each have drain pads (151B, 152B) in plan view, and therefore require a certain area.

[0096] On the other hand, in a circuit board mounting the power supply circuit shown in FIG. 6, by using the semiconductor device 1 according to the embodiment, it is possible to integrate the transistor 10B and the transistor 20B according to the comparative example. This eliminates the need for a certain installation margin between the transistor 10B and the transistor 20B that was necessary in a circuit board mounting the power supply circuit according to the comparative example, and further, the drain pads (151B, 152B) that the transistors 10B and 20B each have can be shared, thereby reducing the area required for the circuit board. In the circuit board mounting the power supply circuit shown in FIG. 6, the board itself can be made smaller than in the comparative example, and other components can be mounted in the resulting surplus area.

[0097] Therefore, the semiconductor device 1 according to the embodiment is a chip-size package type semiconductor device 1 that can be mounted face-down, and has a semiconductor substrate 32 on the back surface side. The semiconductor device 1 is provided with a semiconductor layer 40 that is divided into three regions, a first region A1, a second region A2, and a third region A3, which do not overlap each other in a plan view of the semiconductor device 1 and are not disposed in a dispersed manner, a first vertical MOS transistor 10 entirely formed in the first region A1 of the semiconductor layer 40, a second vertical MOS transistor 20 entirely formed in the second region A2 of the semiconductor layer 40, and a metal layer 41 formed in contact with the back surface side of the semiconductor layer 40. The semiconductor substrate 32 is a common drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20, and in a plan view In the semiconductor device 1, a first source pad 111 and a first gate pad 119 of a first vertical MOS transistor 10 are formed at a position included in a first region A1, a second source pad 121 and a second gate pad 129 of a second vertical MOS transistor 20 are formed at a position included in a second region A2 in a plan view, a drain pad 151 connected to the common drain region is formed at a position included in a third region A3 in a plan view, the first region A1 and the second region A2 are arranged with the third region A3 in between in a plan view, the third region A3 is adjacent to the first region A1 and the second region A2 in a plan view, and the area of the first region A1 is larger than the area of the second region A2 in a plan view.

[0098] In the semiconductor device 1 according to the embodiment, the first conduction path has the first source pad 111 in the first region A1 as an inlet and the drain pad 151 in the third region A3 as an outlet. Therefore, if the first region A1 and the third region A3 are adjacent in a plan view, the first conduction path is shortened, which is advantageous because the conduction resistance can be reduced. Similarly, the second conduction path has the second source pad 121 in the second region A2 as an inlet and the drain pad 151 in the third region A3 as an outlet. Therefore, if the second region A2 and the third region A3 are adjacent in a plan view, the second conduction path is shortened, which is advantageous because the conduction resistance can be reduced.

[0099] Therefore, it is desirable that the first region A1 and the second region A2 are arranged with the third region A3 sandwiched between them in a plan view, and that the third region A3 is adjacent to the first region A1 and the second region A2.

[0100] In the semiconductor device 1 according to the embodiment, emphasis is placed on reducing the conduction resistance of the first conduction path. Therefore, as shown in Figure 2A or 2B, it is preferable that the opposing length between the first region A1 and the third region A3 is longer than the opposing length between the second region A2 and the third region A3 in a plan view. By arranging the semiconductor device 1 in the above-described plan view, the area where the current density is highest in the first conduction path can be expanded (the opposing length is increased), thereby reducing the conduction resistance.

[0101] The above-described effect can also be obtained in, for example, Modification 2 shown in Fig. 10. Fig. 10 is a schematic plan view of the semiconductor device 1 according to the embodiment, in which the ratio of the layout of the first region A1 and the second region A2 is changed.

[0102] 2A and 2B, the semiconductor layer 40 may be rectangular in plan view, and the first region A1 may be disposed so as to have an outer periphery that coincides with at least a portion of each of the four sides of the semiconductor layer 40. By arranging the semiconductor device 1 in the plan view as described above, not only can the area of the first region A1 be increased, but the first conduction path can be provided in all directions, thereby preventing localized high temperature areas from occurring due to current concentration.

[0103] The above-described effect can also be obtained in, for example, Modification 3 shown in Fig. 11. Fig. 11 is a schematic plan view in which the ratio of the layout of the first region A1 and the second region A2 is changed from that of the semiconductor device 1 according to the embodiment.

[0104] 2B, the location where the second gate electrode 29 is installed cannot contribute to conduction. For this reason, in a plan view, it is desirable to install the second gate electrode 29 as far away as possible from a location that could obstruct the second conduction path in the second region A2. Therefore, it is desirable to install the second gate electrode 29 as far away as possible from the boundary line 90 between the second region A2 and the third region A3, where the current density in the second conduction path is highest.

[0105] Therefore, in a plan view, the second gate electrode 29, i.e., the second gate pad 129, is preferably located closest to the corner formed by two sides of the periphery of the second region A2 that are not adjacent to the third region A3. In the example shown in Fig. 2B, the second gate pad 129 is located closest to the upper right corner in a plan view.

[0106] The above-described effect can also be achieved in Modification 4 shown in FIGS. 12A and 12B. FIGS. 12A and 12B are schematic plan views of Modification 2 of the semiconductor device 1 according to the embodiment, in which the positions of the first gate electrode 19, the first gate pad 119, the second gate electrode 29, and the second gate pad 129 are changed. Note that FIG. 12B shows the state immediately after the first source electrode portion 13, the second source electrode portion 23, the first gate electrode 19, the second gate electrode 29, the first gate wiring, the second gate wiring, and the surface drain electrode portion 83 are formed on the surface side of the semiconductor layer. For ease of understanding, pads that would not be visible at this point are shown with dotted lines in FIG. 12B.

[0107] 12B with the example shown in Fig. 2B, in Modification 4, the second gate pad 129 is disposed in the second region A2 so as to be closest to the boundary line 90 (the dotted line from P3 to P4) between the first region A1 and the second region A2 in plan view. This makes it possible to widely utilize the region along the boundary line 90 (the dotted line from P2 to P4) between the second region A2 and the third region A3, where the current density is highest in the second conduction path.

[0108] In addition, in the fourth modification, the second gate pad 129 is disposed so as to be closest to the corner of the outer periphery of the second region A2 that is farthest from the drain pad 151 in a plan view. This allows for the area along the boundary line 90 (dotted line from P2 to P4) between the second region A2 and the third region A3 to be widely utilized. Similarly, the first gate pad 119 is disposed so as to be closest to the corner of the outer periphery of the first region A1 that is farthest from the drain pad 151 in a plan view. This allows for the area along the boundary line 90 (dotted line from P1 to P4) between the first region A1 and the third region A3 to be widely utilized.

[0109] 6 using the semiconductor device 1 according to the embodiment. In a transistor in the ON state, the larger the area of the transistor in plan view, the larger the total gate width, and therefore the lower the on-resistance. In other words, the area of the transistor in plan view and the on-resistance are generally inversely proportional to each other.

[0110] In the semiconductor device 1, the area a1 in a plan view of the transistor 10 forming the first conduction path is larger than the area a2 in a plan view of the transistor 20 forming the second conduction path. Therefore, the first conduction path has a lower conduction resistance and is suitable for passing a relatively large current.

[0111] The conduction resistance R1 [Ω] of the first conduction path may be determined taking into account the maximum value I1 [A] of the current flowing due to the power supply from the first power supply 51. Similarly, the conduction resistance R2 [Ω] of the second conduction path may be determined taking into account the maximum value I2 [A] of the current flowing due to the power supply from the second power supply 52. Therefore, in the semiconductor device 1 according to the embodiment, it is desirable to determine the areas of the transistors 10 and 20 so that the first conduction path and the second conduction path each have an appropriate conduction resistance.

[0112] However, if the area a2 of the transistor 20 in a plan view calculated as described above is excessively small, the ESD (Electro Static Discharge) resistance of the transistor 20 decreases, and it may become impossible to maintain the ESD guarantee value for the entire semiconductor device 1. If the area a2 of the transistor 20 in a plan view is increased so as to maintain the ESD guarantee value, the conduction resistance of the second conduction path will decrease excessively, making it difficult to limit the current from the second power supply 52 to a desired magnitude.

[0113] Therefore, the inventors discovered that in the semiconductor device 1, by appropriately designing the size (area) and position of the drain contact region 39 in the third region A3 in a planar view, it is possible to control the conduction resistance in the second conduction path separately from the area a2 in a planar view of the transistor 20.

[0114] In the following description, it is assumed that the area a2 of the transistor 20 in a plan view is increased as much as necessary to maintain the ESD protection value in the semiconductor device 1 according to the embodiment. That is, it is assumed that the conduction resistance of the second conduction path is excessively reduced in the semiconductor device 1 according to the embodiment.

[0115] FIG. 13 is a schematic plan view of only the third region A3 extracted from the schematic plan view of the semiconductor device 1 shown in FIG. 2B.

[0116] 1 and 3, the drain contact region 39 is a region where the drain pull-up region 38 and the portion 83 of the surface drain electrode 81 are connected. Therefore, the drain contact region 39 is a part included in the third region A3 in plan view.

[0117] 13, both the third region A3 and the drain contact region 39 are rectangular in plan view. The direction along the short side of the rectangular third region A3 in plan view (X direction in FIG. 13) is defined as the first direction, and the direction along the long side of the third region A3 (Y direction in FIG. 13) is defined as the second direction. The first and second directions are orthogonal to each other.

[0118] In plan view, the side length of the third region A3 in the first direction is L1 [μm], and the side length of the third region A3 in the second direction is L2 [μm]. In plan view, the side length of the drain contact region 39 in the first direction is l1 [μm], and the side length of the drain contact region 39 in the second direction is l2 [μm].

[0119] With the aim of avoiding an excessive reduction in the conduction resistance in the second conduction path, the inventors set the conditions of l1≦L1 / 4 and l2≈L2 for the area of the drain contact region 39 in plan view.

[0120] 13, l2 is smaller than L2 by the installation margins at both ends in the second direction. The condition l1≦L1 / 4 is set so that the area of the drain contact region 39 is reduced to at least ¼ of the area of the third region A3, thereby enabling the position of the drain contact region 39 in a plan view to be adjusted by the distance from the second region A2.

[0121] Based on this idea, we investigated the case where a semiconductor device 1 in which the size and shape of the drain contact region 39 in a plan view are set as shown in Figure 13 is used in the circuit shown in the circuit diagram of Figure 6. Figure 14 shows a graph plotting the results of calculating the conduction resistance R1 of the first conduction path when transistor 10 is controlled to ON and transistor 20 is controlled to OFF, and the conduction resistance R2 of the second conduction path when transistor 20 is controlled to ON and transistor 10 is controlled to OFF. The conduction resistance R1 of the first conduction path is indicated by a circular marker and plotted on the left vertical axis. The conduction resistance R2 of the second conduction path is indicated by a diamond marker and plotted on the right vertical axis.

[0122] 14 represents the position along the first direction in the third region A3 in a plan view. The reference position is the left end of the third region A3 in FIG. 13, i.e., the boundary line 90 between the first region A1 and the third region A3. The horizontal axis is plotted based on the center position of the drain contact region 39.

[0123] 14 indicate, from the left, the reference position, the position L1 / 4 from the reference, the position L1 / 2 from the reference, the position 3×L1 / 4 from the reference, and the position L1 from the reference, i.e., the positions on the boundary line 90 between the third region A3 and the second region A2. In a plan view, the third region A3 is divided into four regions at the above positions so that the areas are equal, and these regions are called the fourth region, fifth region, sixth region, and seventh region from left to right in the first direction.

[0124] In calculating the results plotted in the graph of Figure 14, the semiconductor device 1 was assumed to be a square with sides of 1.5 mm in plan view, and the division of the first region A1, second region A2, and third region A3, as well as the shapes and arrangements of the pads and electrodes, were as shown in Figures 2A and 2B, respectively. The dimensions of the third region A3 in plan view were L1 = 450 μm and L2 = 1000 μm. Furthermore, l1 = 3 μm and l2 = 980 μm.

[0125] In addition, in Figure 14, the data is plotted on the horizontal axis at a certain distance from the left and right ends because, in plan view, an installation margin is added to portion 83 of the surface drain electrode 81 within the third region A3.

[0126] 14, it can be seen that when the drain contact region 39 is located near the center of the third region A3 in plan view, both R1 and R2 are minimized. Here, "near the center" refers to the fifth or sixth region. When the drain contact region 39 is located in, for example, the fourth region, this means that the center of the drain contact region 39 is located in the fourth region in plan view. This does not necessarily mean that the entire drain contact region 39 is contained within the fourth region.

[0127] 14 also shows that R2 tends to increase as the drain contact region 39 moves away from the second region A2 in plan view (moving toward the fourth region). This tendency seen in Fig. 14 becomes more pronounced as the area of the drain contact region 39 becomes smaller, and becomes less visible when the area of the drain contact region 39 increases beyond one-quarter of the area of the third region A3.

[0128] Therefore, in the semiconductor device 1 according to the embodiment, the semiconductor substrate 32 is of a first conductivity type and contains impurities of a first concentration, the semiconductor layer 40 has a low-concentration impurity layer 33 of the first conductivity type formed on and in contact with the semiconductor substrate 32 and containing impurities of a second concentration lower than the first concentration of impurities, in a planar view, a drain pull-up region 38 of the first conductivity type is formed in a third region A3 of the semiconductor layer 40, which contains impurities of a higher concentration than the first concentration of impurities and is connected to the common drain region (semiconductor substrate 32), in a planar view, a portion 83 of a surface drain electrode 81 is formed at a position included in the third region A3, in a planar view, which contacts the surface of the semiconductor layer 40 and connects to the drain pull-up region 38, and in a planar view, the area of the drain contact region 39 where the portion 83 of the surface drain electrode 81 and the drain pull-up region 38 are connected is desirably ¼ or less of the area of the third region A3.

[0129] Furthermore, the drain contact region 39 can achieve substantially the same effect as long as it has a generally rectangular shape in plan view with its longitudinal direction aligned in the second direction.

[0130] Therefore, in a planar view, the third region A3 is rectangular, and the maximum width l1 of the drain contact region 39 in a first direction parallel to the short side L1 of the third region A3 is smaller than the maximum width l2 of the drain contact region 39 in a second direction perpendicular to the first direction and parallel to the long side L2 of the third region A3 in a planar view, and it is desirable that the maximum width l1 of the drain contact region 39 in the first direction be 1 / 4 or less of the length of the short side L1 of the third region in a planar view.

[0131] 14, when the drain contact region 39 is located in the fifth region, the conduction resistance R1 of the first conduction path is almost constant and extremely small. On the other hand, the conduction resistance R2 of the second conduction path increases as the drain contact region 39 is positioned closer to the fourth region. Therefore, if the drain contact region 39 is located in the fifth region, it is possible to increase only R2 while keeping R1 reduced.

[0132] Therefore, in a planar view, the third region is divided into four equal parts, the fourth region, the fifth region, the sixth region, and the seventh region, each having the same area in the first direction, and in a planar view, the fourth region, the fifth region, the sixth region, and the seventh region are arranged in this order along the first direction from the boundary line 90 between the first region A1 and the third region A3 to the boundary line 90 between the second region A2 and the third region A3, and in a planar view, the center of the drain contact region 39 may be located in the fifth region.

[0133] More preferably, the drain contact region 39 is located in the fifth region near the boundary with the fourth region. For example, the drain contact region 39 may be located in an area including the boundary between the fourth and fifth regions. By locating the drain contact region 39 in this manner, an excessive reduction in R2 can be avoided.

[0134] As the drain contact region 39 is located in the fourth region and is positioned closer to the boundary line 90 (the reference position in the first direction) between the first region A1 and the third region A3, both R1 and R2 increase. However, R2 increases at a greater rate. This is because the drain contact region 39 is located farther away from the boundary line 90 between the second region A2 and the third region A3.

[0135] Therefore, in a planar view, the third region is divided into four equal parts, the fourth region, the fifth region, the sixth region, and the seventh region, each of which has the same area in the first direction, and in a planar view, the fourth region, the fifth region, the sixth region, and the seventh region are arranged in this order along the first direction from the boundary line 90 between the first region A1 and the third region A3 to the boundary line 90 between the second region A2 and the third region A3, and in a planar view, the center of the drain contact region 39 may be located in the fourth region.

[0136] More preferably, the closer the drain contact region 39 is to the boundary line 90 between the first region A1 and the third region A3, the greater the difference between R1 and R2 can be. By locating the drain contact region 39 in this manner, it is possible to avoid an excessive decrease in R2 due to an increase in the area of the second region A2 in a plan view.

[0137] When the drain contact region 39 is located in the sixth region, both R1 and R2 are maintained at substantially minimum values, which is convenient when it is desired to achieve low values for both R1 and R2.

[0138] Therefore, in a planar view, the third region is divided into four equal parts, the fourth region, the fifth region, the sixth region, and the seventh region, each of which has the same area in the first direction, and in a planar view, the fourth region, the fifth region, the sixth region, and the seventh region are arranged in this order along the first direction from the boundary line 90 between the first region A1 and the third region A3 to the boundary line 90 between the second region A2 and the third region A3, and in a planar view, the center of the drain contact region 39 may be located in the sixth region.

[0139] As described above, in the semiconductor device 1 according to the embodiment, after determining the planar areas of the first region A1 and the second region A2, the conduction resistance R1 of the first conduction path and the conduction resistance R2 of the second conduction path can be adjusted by adjusting the size (area) of the drain contact region 39 and its location. Even if the second region A2 is enlarged to achieve the required ESD resistance, the conduction resistance R2 of the second conduction path can be set to a desired high value, particularly in the transistor 20, which has a small area. Therefore, the current flowing through the first conduction path and the current flowing through the second conduction path can be adjusted to the desired magnitude.

[0140] Although the semiconductor device according to one aspect of the present disclosure has been described above based on the embodiment, variations 1 to 4, and a comparative example, the present disclosure is not limited to the embodiment. As long as it does not deviate from the spirit of the present disclosure, various modifications conceivable by a person skilled in the art to these embodiments, or configurations constructed by combining components of different embodiments and variations, may also be included within the scope of one or more aspects of the present disclosure. [Industrial Applicability]

[0141] A semiconductor device including a vertical MOS transistor according to the present invention can be widely used as a device for controlling the conduction state of a current path. [Explanation of symbols]

[0142] 1, 1A Semiconductor Device 4 Control IC 6 Load 7, 8 Switching elements 10, 10A, 10B Transistor (first vertical MOS transistor) 11 First source electrode 12, 13, 22, 23 parts 14 First Source Region 15 first gate conductor 16 First gate insulating film 17 First gate trench 18 First Body Region 18a First connection part 19 First gate electrode 20, 20B Transistor (Second Vertical MOS Transistor) 21 Second source electrode 24 Second Source Region 25 Second gate conductor 26 Second gate insulating film 27 Second gate trench 28 Second Body Region 28a Second connection 29 Second gate electrode 32 Semiconductor substrate 33 Low concentration impurity layer 34 Interlayer insulating layer 35 Passivation Layer 38 Drain pull-up region 40 Semiconductor layer 41 Metal layer (back surface drain electrode) 51 First Power Source 52 Second Power Source 81 Surface drain electrode 82, 83 parts 90 Borderline 111 First Source Pad 111B, 121B Sauce Pad 119 First Gate Pad 119B, 129B gate pad 121 Second Source Pad 129 Second Gate Pad 151, 151B, 152B drain pads A1 First Area A2 Second Area A3 The third area

Claims

1. A chip-size package type semiconductor device that can be mounted face-down, a semiconductor layer having a semiconductor substrate on a back surface side, the semiconductor layer being divided into three regions, a first region, a second region, and a third region, which do not overlap each other in a plan view of the semiconductor device, and which are not disposed in a dispersed manner; a first vertical MOS transistor formed entirely in the first region of the semiconductor layer; a second vertical MOS transistor formed entirely in the second region of the semiconductor layer; a metal layer formed in contact with the back surface side of the semiconductor layer, the semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; a first source pad and a first gate pad of the first vertical MOS transistor are formed at positions included in the first region in the plan view; a second source pad and a second gate pad of the second vertical MOS transistor are formed at a position included in the second region in the plan view; a drain pad connected to the common drain region is formed at a position included in the third region in the plan view; In the plan view, the first region and the second region are disposed with the third region therebetween, In the plan view, the third region is adjacent to the first region and the second region, In the plan view, an area of the first region is larger than an area of the second region, In the plan view, the semiconductor layer has a rectangular shape having a first side and a second side parallel to the first side, In the plan view, the first region is arranged to have an outer periphery that coincides with the entire first side, In the plan view, the second region is arranged to have an outer periphery that coincides with at least a part of the second side, the third region is arranged so that, in the plan view, it does not have an outer periphery that coincides with at least a portion of the first side and it does not have an outer periphery that coincides with at least a portion of the second side; In the plan view, the first region includes a region on the second side of a midline that passes through a center of the semiconductor layer and is parallel to the first side and the second side, In the plan view, the second region does not include a region on the first side of the intermediate line. Semiconductor device.

2. In the plan view, the opposing length between the first region and the third region is longer than the opposing length between the second region and the third region. The semiconductor device according to claim 1 .

3. In the plan view, the first region is disposed so as to have an outer periphery that at least a portion of each of the four sides of the semiconductor layer coincides with each other. The semiconductor device according to claim 2 .

4. In the plan view, the second gate pad is installed closest to a corner formed by two sides of the outer periphery of the second region that are not adjacent to the third region. The semiconductor device according to claim 2 .

5. In the plan view, the second gate pad is disposed closest to the corner farthest from the drain pad among the corners formed by the outer periphery of the second region. The semiconductor device according to claim 2 .

6. the semiconductor substrate is of a first conductivity type and contains impurities at a first concentration; The semiconductor layer has a low-concentration impurity layer of the first conductivity type formed on and in contact with the semiconductor substrate and containing impurities at a second concentration lower than the first concentration. In the plan view, the third region of the semiconductor layer includes a drain pull-up region of the first conductivity type, the drain pull-up region including an impurity at a concentration higher than the first concentration and connected to the common drain region; a surface drain electrode is formed in a position included in the third region in the plan view, the surface drain electrode being in contact with a surface of the semiconductor layer and connected to the drain pull-up region; In the plan view, the area of a drain contact region where the surface drain electrode and the drain pull-up region are connected is equal to or less than ¼ of the area of the third region. The semiconductor device according to claim 1 .

7. In the plan view, the third region has a rectangular shape, and a maximum width of the drain contact region in a first direction parallel to a short side of the third region is smaller than a maximum width of the drain contact region in a second direction perpendicular to the first direction and parallel to a long side of the third region, In the plan view, the maximum width of the drain contact region in the first direction is equal to or less than ¼ of the length of a short side of the third region. The semiconductor device according to claim 6.

8. In the plan view, the third region is divided into four equal regions, a fourth region, a fifth region, a sixth region, and a seventh region, each of which has an equal area in the first direction; In the plan view, the fourth region, the fifth region, the sixth region, and the seventh region are arranged in this order along the first direction from a boundary line between the first region and the third region to a boundary line between the second region and the third region, In the plan view, the center of the drain contact region is located in the fifth region. The semiconductor device according to claim 7 .

9. In the plan view, the third region is divided into four equal regions, a fourth region, a fifth region, a sixth region, and a seventh region, each of which has an equal area in the first direction; In the plan view, the fourth region, the fifth region, the sixth region, and the seventh region are arranged in this order along the first direction from a boundary line between the first region and the third region to a boundary line between the second region and the third region, In the plan view, the center of the drain contact region is located in the fourth region. The semiconductor device according to claim 7 .

10. In the plan view, the third region is divided into four equal regions, a fourth region, a fifth region, a sixth region, and a seventh region, each of which has an equal area in the first direction; In the plan view, the fourth region, the fifth region, the sixth region, and the seventh region are arranged in this order along the first direction from a boundary line between the first region and the third region to a boundary line between the second region and the third region, In the plan view, the center of the drain contact region is located in the sixth region. The semiconductor device according to claim 7 .

Images